teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file system_LPC11U6x.c
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M3 Device System Source File for
bogdanm 0:9b334a45a8ff 4 * NXP LPC11U6x Device Series
bogdanm 0:9b334a45a8ff 5 * @version V1.00
bogdanm 0:9b334a45a8ff 6 * @date 19. July 2013
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * @note
bogdanm 0:9b334a45a8ff 9 * Copyright (C) 2013 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * @par
bogdanm 0:9b334a45a8ff 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 0:9b334a45a8ff 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 14 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * @par
bogdanm 0:9b334a45a8ff 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 ******************************************************************************/
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 #include <stdint.h>
bogdanm 0:9b334a45a8ff 27 #include "LPC11U6x.h"
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 /*
bogdanm 0:9b334a45a8ff 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 0:9b334a45a8ff 31 */
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 /*- SystemCoreClock Configuration -------------------------------------------*/
bogdanm 0:9b334a45a8ff 34 // <e0> SystemCoreClock Configuration
bogdanm 0:9b334a45a8ff 35 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 36 //
bogdanm 0:9b334a45a8ff 37 // <h> System Oscillator Control (SYSOSCCTRL)
bogdanm 0:9b334a45a8ff 38 // <o.0> BYPASS: System Oscillator Bypass Enable
bogdanm 0:9b334a45a8ff 39 // <i> If enabled then PLL input (sys_osc_clk) is fed
bogdanm 0:9b334a45a8ff 40 // <i> directly from XTALIN and XTALOUT pins.
bogdanm 0:9b334a45a8ff 41 // <o.1> FREQRANGE: System Oscillator Frequency Range
bogdanm 0:9b334a45a8ff 42 // <i> Determines frequency range for Low-power oscillator.
bogdanm 0:9b334a45a8ff 43 // <0=> 1 - 20 MHz
bogdanm 0:9b334a45a8ff 44 // <1=> 15 - 25 MHz
bogdanm 0:9b334a45a8ff 45 // </h>
bogdanm 0:9b334a45a8ff 46 #define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 47 //
bogdanm 0:9b334a45a8ff 48 // <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
bogdanm 0:9b334a45a8ff 49 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 50 // <1=> Crystal Oscillator (SYSOSC)
bogdanm 0:9b334a45a8ff 51 // <3=> RTC Oscillator (32 kHz)
bogdanm 0:9b334a45a8ff 52 #define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 53 //
bogdanm 0:9b334a45a8ff 54 // <e> Clock Configuration (Manual)
bogdanm 0:9b334a45a8ff 55 #define CLOCK_SETUP_REG 1
bogdanm 0:9b334a45a8ff 56 //
bogdanm 0:9b334a45a8ff 57 // <h> WD Oscillator Setting (WDTOSCCTRL)
bogdanm 0:9b334a45a8ff 58 // <o.0..4> DIVSEL: Select Divider for Fclkana
bogdanm 0:9b334a45a8ff 59 // <i> wd_osc_clk = Fclkana / (2 × (1 + DIVSEL))
bogdanm 0:9b334a45a8ff 60 // <0-31>
bogdanm 0:9b334a45a8ff 61 // <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana)
bogdanm 0:9b334a45a8ff 62 // <1=> 0.5 MHz
bogdanm 0:9b334a45a8ff 63 // <2=> 0.8 MHz
bogdanm 0:9b334a45a8ff 64 // <3=> 1.1 MHz
bogdanm 0:9b334a45a8ff 65 // <4=> 1.4 MHz
bogdanm 0:9b334a45a8ff 66 // <5=> 1.6 MHz
bogdanm 0:9b334a45a8ff 67 // <6=> 1.8 MHz
bogdanm 0:9b334a45a8ff 68 // <7=> 2.0 MHz
bogdanm 0:9b334a45a8ff 69 // <8=> 2.2 MHz
bogdanm 0:9b334a45a8ff 70 // <9=> 2.4 MHz
bogdanm 0:9b334a45a8ff 71 // <10=> 2.6 MHz
bogdanm 0:9b334a45a8ff 72 // <11=> 2.7 MHz
bogdanm 0:9b334a45a8ff 73 // <12=> 2.9 MHz
bogdanm 0:9b334a45a8ff 74 // <13=> 3.1 MHz
bogdanm 0:9b334a45a8ff 75 // <14=> 3.2 MHz
bogdanm 0:9b334a45a8ff 76 // <15=> 3.4 MHz
bogdanm 0:9b334a45a8ff 77 // </h>
bogdanm 0:9b334a45a8ff 78 #define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0
bogdanm 0:9b334a45a8ff 79 //
bogdanm 0:9b334a45a8ff 80 // <h> System PLL Setting (SYSPLLCTRL)
bogdanm 0:9b334a45a8ff 81 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 82 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 83 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 84 // <o.0..4> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 85 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 86 // <0-31>
bogdanm 0:9b334a45a8ff 87 // <o.5..6> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 88 // <i> Post divider ratio P. Division ratio is 2 * P
bogdanm 0:9b334a45a8ff 89 // <0=> P = 1
bogdanm 0:9b334a45a8ff 90 // <1=> P = 2
bogdanm 0:9b334a45a8ff 91 // <2=> P = 4
bogdanm 0:9b334a45a8ff 92 // <3=> P = 8
bogdanm 0:9b334a45a8ff 93 // </h>
bogdanm 0:9b334a45a8ff 94 #define SYSPLLCTRL_Val 0x00000023 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 95 //
bogdanm 0:9b334a45a8ff 96 // <o.0..1> Main Clock Source Select (MAINCLKSEL)
bogdanm 0:9b334a45a8ff 97 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 98 // <1=> PLL Input
bogdanm 0:9b334a45a8ff 99 // <2=> WD Oscillator
bogdanm 0:9b334a45a8ff 100 // <3=> PLL Output
bogdanm 0:9b334a45a8ff 101 #define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 102 //
bogdanm 0:9b334a45a8ff 103 // <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
bogdanm 0:9b334a45a8ff 104 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
bogdanm 0:9b334a45a8ff 105 // <i> 0 = is disabled
bogdanm 0:9b334a45a8ff 106 // <0-255>
bogdanm 0:9b334a45a8ff 107 #define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
bogdanm 0:9b334a45a8ff 108 // </e>
bogdanm 0:9b334a45a8ff 109 //
bogdanm 0:9b334a45a8ff 110 // <e> Clock Configuration (via ROM PLL API)
bogdanm 0:9b334a45a8ff 111 #define CLOCK_SETUP_API 0
bogdanm 0:9b334a45a8ff 112 //
bogdanm 0:9b334a45a8ff 113 // <o> PLL API Mode Select
bogdanm 0:9b334a45a8ff 114 // <0=> Exact
bogdanm 0:9b334a45a8ff 115 // <1=> Less than or equal
bogdanm 0:9b334a45a8ff 116 // <2=> Greater than or equal
bogdanm 0:9b334a45a8ff 117 // <3=> As close as possible
bogdanm 0:9b334a45a8ff 118 #define PLL_API_MODE_Val 0
bogdanm 0:9b334a45a8ff 119 //
bogdanm 0:9b334a45a8ff 120 // <o> CPU Frequency [Hz] <1000000-50000000:1000>
bogdanm 0:9b334a45a8ff 121 #define PLL_API_FREQ_Val 48000000
bogdanm 0:9b334a45a8ff 122 // </e>
bogdanm 0:9b334a45a8ff 123 //
bogdanm 0:9b334a45a8ff 124 // <e> USB Clock Configuration
bogdanm 0:9b334a45a8ff 125 #define USB_CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 126 // <h> USB PLL Control (USBPLLCTRL)
bogdanm 0:9b334a45a8ff 127 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 128 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 129 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 130 // <o.0..4> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 131 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 132 // <0-31>
bogdanm 0:9b334a45a8ff 133 // <o.5..6> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 134 // <i> Post divider ratio P. Division ratio is 2 * P
bogdanm 0:9b334a45a8ff 135 // <0=> P = 1
bogdanm 0:9b334a45a8ff 136 // <1=> P = 2
bogdanm 0:9b334a45a8ff 137 // <2=> P = 4
bogdanm 0:9b334a45a8ff 138 // <3=> P = 8
bogdanm 0:9b334a45a8ff 139 // </h>
bogdanm 0:9b334a45a8ff 140 #define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 141 //
bogdanm 0:9b334a45a8ff 142 // <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
bogdanm 0:9b334a45a8ff 143 // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
bogdanm 0:9b334a45a8ff 144 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 145 // <1=> System Oscillator
bogdanm 0:9b334a45a8ff 146 #define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 147 //
bogdanm 0:9b334a45a8ff 148 // <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
bogdanm 0:9b334a45a8ff 149 // <0=> USB PLL out
bogdanm 0:9b334a45a8ff 150 // <1=> Main clock
bogdanm 0:9b334a45a8ff 151 #define USBCLKSEL_Val 0x00000000 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 152 //
bogdanm 0:9b334a45a8ff 153 // <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
bogdanm 0:9b334a45a8ff 154 // <i> Divides USB clock to 48 MHz.
bogdanm 0:9b334a45a8ff 155 // <i> 0 = is disabled
bogdanm 0:9b334a45a8ff 156 // <0-255>
bogdanm 0:9b334a45a8ff 157 #define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
bogdanm 0:9b334a45a8ff 158 // </e>
bogdanm 0:9b334a45a8ff 159 //
bogdanm 0:9b334a45a8ff 160 // </e>
bogdanm 0:9b334a45a8ff 161 //
bogdanm 0:9b334a45a8ff 162 // <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
bogdanm 0:9b334a45a8ff 163 // <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 164 //
bogdanm 0:9b334a45a8ff 165 #define XTAL_CLK_Val 12000000
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 /*
bogdanm 0:9b334a45a8ff 168 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 172 Define clocks
bogdanm 0:9b334a45a8ff 173 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 174 #define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
bogdanm 0:9b334a45a8ff 175 #define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
bogdanm 0:9b334a45a8ff 176 #define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
bogdanm 0:9b334a45a8ff 177 #define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 180 Check the register settings
bogdanm 0:9b334a45a8ff 181 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 182 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 0:9b334a45a8ff 183 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 186 #error "SYSOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 187 #endif
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
bogdanm 0:9b334a45a8ff 190 #error "WDTOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 191 #endif
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
bogdanm 0:9b334a45a8ff 194 #error "SYSPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 195 #endif
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 #if (SYSPLLCLKSEL_Val == 3) // RTC Oscillator used as PLL input
bogdanm 0:9b334a45a8ff 198 #if (CLOCK_SETUP_API == 1)
bogdanm 0:9b334a45a8ff 199 #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
bogdanm 0:9b334a45a8ff 200 #endif
bogdanm 0:9b334a45a8ff 201 #if (CLOCK_SETUP_REG == 1) && (MAINCLKSEL_Val == 3) // RTC Oscillator used as PLL input
bogdanm 0:9b334a45a8ff 202 #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
bogdanm 0:9b334a45a8ff 203 #endif
bogdanm 0:9b334a45a8ff 204 #endif
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F))
bogdanm 0:9b334a45a8ff 207 #error "SYSPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 208 #endif
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 211 #error "MAINCLKSEL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 212 #endif
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
bogdanm 0:9b334a45a8ff 215 #error "SYSAHBCLKDIV: Value out of range!"
bogdanm 0:9b334a45a8ff 216 #endif
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 #if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
bogdanm 0:9b334a45a8ff 219 #error "You must select either manual or API based Clock Configuration!"
bogdanm 0:9b334a45a8ff 220 #endif
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
bogdanm 0:9b334a45a8ff 223 #error "USBPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 224 #endif
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F))
bogdanm 0:9b334a45a8ff 227 #error "USBPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 228 #endif
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
bogdanm 0:9b334a45a8ff 231 #error "USBCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 232 #endif
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
bogdanm 0:9b334a45a8ff 235 #error "USBCLKDIV: Value out of range!"
bogdanm 0:9b334a45a8ff 236 #endif
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 #if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
bogdanm 0:9b334a45a8ff 239 #error "XTAL frequency is out of bounds"
bogdanm 0:9b334a45a8ff 240 #endif
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 #if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
bogdanm 0:9b334a45a8ff 243 #error "PLL API Mode Select not valid"
bogdanm 0:9b334a45a8ff 244 #endif
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 #if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000))
bogdanm 0:9b334a45a8ff 247 #error "CPU Frequency (API mode) not valid"
bogdanm 0:9b334a45a8ff 248 #endif
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 253 Calculate system core clock
bogdanm 0:9b334a45a8ff 254 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 255 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* sys_pllclkin calculation */
bogdanm 0:9b334a45a8ff 258 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 259 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 260 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 261 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
bogdanm 0:9b334a45a8ff 262 #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 263 #define __SYS_PLLCLKIN (__RTC_OSC_CLK)
bogdanm 0:9b334a45a8ff 264 #else
bogdanm 0:9b334a45a8ff 265 #error "Oops"
bogdanm 0:9b334a45a8ff 266 #endif
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
bogdanm 0:9b334a45a8ff 271 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 #if (__FREQSEL == 0)
bogdanm 0:9b334a45a8ff 274 #error "WDTOSCCTRL.FREQSEL undefined!"
bogdanm 0:9b334a45a8ff 275 #elif (__FREQSEL == 1)
bogdanm 0:9b334a45a8ff 276 #define __OSC_CLK ( 500000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 277 #elif (__FREQSEL == 2)
bogdanm 0:9b334a45a8ff 278 #define __OSC_CLK ( 800000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 279 #elif (__FREQSEL == 3)
bogdanm 0:9b334a45a8ff 280 #define __OSC_CLK (1100000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 281 #elif (__FREQSEL == 4)
bogdanm 0:9b334a45a8ff 282 #define __OSC_CLK (1400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 283 #elif (__FREQSEL == 5)
bogdanm 0:9b334a45a8ff 284 #define __OSC_CLK (1600000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 285 #elif (__FREQSEL == 6)
bogdanm 0:9b334a45a8ff 286 #define __OSC_CLK (1800000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 287 #elif (__FREQSEL == 7)
bogdanm 0:9b334a45a8ff 288 #define __OSC_CLK (2000000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 289 #elif (__FREQSEL == 8)
bogdanm 0:9b334a45a8ff 290 #define __OSC_CLK (2200000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 291 #elif (__FREQSEL == 9)
bogdanm 0:9b334a45a8ff 292 #define __OSC_CLK (2400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 293 #elif (__FREQSEL == 10)
bogdanm 0:9b334a45a8ff 294 #define __OSC_CLK (2600000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 295 #elif (__FREQSEL == 11)
bogdanm 0:9b334a45a8ff 296 #define __OSC_CLK (2700000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 297 #elif (__FREQSEL == 12)
bogdanm 0:9b334a45a8ff 298 #define __OSC_CLK (2900000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 299 #elif (__FREQSEL == 13)
bogdanm 0:9b334a45a8ff 300 #define __OSC_CLK (3100000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 301 #elif (__FREQSEL == 14)
bogdanm 0:9b334a45a8ff 302 #define __OSC_CLK (3200000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 303 #else
bogdanm 0:9b334a45a8ff 304 #define __OSC_CLK (3400000 / __DIVSEL)
bogdanm 0:9b334a45a8ff 305 #endif
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /* main clock calculation */
bogdanm 0:9b334a45a8ff 310 #if ((MAINCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 311 #define __MAIN_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 312 #elif ((MAINCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 313 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
bogdanm 0:9b334a45a8ff 314 #elif ((MAINCLKSEL_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 315 #define __MAIN_CLOCK (__OSC_CLK)
bogdanm 0:9b334a45a8ff 316 #elif ((MAINCLKSEL_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 317 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
bogdanm 0:9b334a45a8ff 318 #else
bogdanm 0:9b334a45a8ff 319 #error "Oops"
bogdanm 0:9b334a45a8ff 320 #endif
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
bogdanm 0:9b334a45a8ff 323 #endif /* Clock Setup via Register */
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
bogdanm 0:9b334a45a8ff 326 #define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
bogdanm 0:9b334a45a8ff 327 #endif /* Clock Setup via PLL API */
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 #else
bogdanm 0:9b334a45a8ff 330 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 331 #endif /* CLOCK_SETUP */
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 #if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
bogdanm 0:9b334a45a8ff 336 #include "power_api.h"
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 typedef struct _ROM {
bogdanm 0:9b334a45a8ff 339 const unsigned p_dev0;
bogdanm 0:9b334a45a8ff 340 const unsigned p_dev1;
bogdanm 0:9b334a45a8ff 341 const unsigned p_dev2;
bogdanm 0:9b334a45a8ff 342 const PWRD * pPWRD; /* ROM Power Management API */
bogdanm 0:9b334a45a8ff 343 const unsigned p_dev4;
bogdanm 0:9b334a45a8ff 344 const unsigned p_dev5;
bogdanm 0:9b334a45a8ff 345 const unsigned p_dev6;
bogdanm 0:9b334a45a8ff 346 const unsigned p_dev7;
bogdanm 0:9b334a45a8ff 347 } ROM;
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 350 PLL API Function
bogdanm 0:9b334a45a8ff 351 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 352 static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
bogdanm 0:9b334a45a8ff 353 {
bogdanm 0:9b334a45a8ff 354 uint32_t cmd[5], res[5];
bogdanm 0:9b334a45a8ff 355 ROM ** rom = (ROM **) 0x1FFF1FF8; /* pointer to power API calls */
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 cmd[0] = pllInFreq; /* PLL's input freq in KHz */
bogdanm 0:9b334a45a8ff 358 cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
bogdanm 0:9b334a45a8ff 359 cmd[2] = pllMode;
bogdanm 0:9b334a45a8ff 360 cmd[3] = 0; /* no timeout for PLL to lock */
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /* Execute API call */
bogdanm 0:9b334a45a8ff 363 (*rom)->pPWRD->set_pll(cmd, res); /* call API function */
bogdanm 0:9b334a45a8ff 364 if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
bogdanm 0:9b334a45a8ff 365 while(1); /* ... stay here */
bogdanm 0:9b334a45a8ff 366 }
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368 #endif
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 374 Clock Variable definitions
bogdanm 0:9b334a45a8ff 375 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 376 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 380 Clock functions
bogdanm 0:9b334a45a8ff 381 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 382 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 0:9b334a45a8ff 383 {
bogdanm 0:9b334a45a8ff 384 uint32_t oscClk = 0;
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 387 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
bogdanm 0:9b334a45a8ff 388 case 0: oscClk = 0; break;
bogdanm 0:9b334a45a8ff 389 case 1: oscClk = 500000; break;
bogdanm 0:9b334a45a8ff 390 case 2: oscClk = 800000; break;
bogdanm 0:9b334a45a8ff 391 case 3: oscClk = 1100000; break;
bogdanm 0:9b334a45a8ff 392 case 4: oscClk = 1400000; break;
bogdanm 0:9b334a45a8ff 393 case 5: oscClk = 1600000; break;
bogdanm 0:9b334a45a8ff 394 case 6: oscClk = 1800000; break;
bogdanm 0:9b334a45a8ff 395 case 7: oscClk = 2000000; break;
bogdanm 0:9b334a45a8ff 396 case 8: oscClk = 2200000; break;
bogdanm 0:9b334a45a8ff 397 case 9: oscClk = 2400000; break;
bogdanm 0:9b334a45a8ff 398 case 10: oscClk = 2600000; break;
bogdanm 0:9b334a45a8ff 399 case 11: oscClk = 2700000; break;
bogdanm 0:9b334a45a8ff 400 case 12: oscClk = 2900000; break;
bogdanm 0:9b334a45a8ff 401 case 13: oscClk = 3100000; break;
bogdanm 0:9b334a45a8ff 402 case 14: oscClk = 3200000; break;
bogdanm 0:9b334a45a8ff 403 case 15: oscClk = 3400000; break;
bogdanm 0:9b334a45a8ff 404 }
bogdanm 0:9b334a45a8ff 405 oscClk /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 408 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 409 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 410 break;
bogdanm 0:9b334a45a8ff 411 case 1: /* Input Clock to System PLL */
bogdanm 0:9b334a45a8ff 412 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 413 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 414 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 415 break;
bogdanm 0:9b334a45a8ff 416 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 417 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 0:9b334a45a8ff 418 break;
bogdanm 0:9b334a45a8ff 419 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 420 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 421 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 422 break;
bogdanm 0:9b334a45a8ff 423 }
bogdanm 0:9b334a45a8ff 424 break;
bogdanm 0:9b334a45a8ff 425 case 2: /* WDT Oscillator */
bogdanm 0:9b334a45a8ff 426 SystemCoreClock = oscClk;
bogdanm 0:9b334a45a8ff 427 break;
bogdanm 0:9b334a45a8ff 428 case 3: /* System PLL Clock Out */
bogdanm 0:9b334a45a8ff 429 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 430 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 431 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 432 break;
bogdanm 0:9b334a45a8ff 433 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 434 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 435 break;
bogdanm 0:9b334a45a8ff 436 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 437 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 438 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 439 break;
bogdanm 0:9b334a45a8ff 440 }
bogdanm 0:9b334a45a8ff 441 break;
bogdanm 0:9b334a45a8ff 442 }
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 }
bogdanm 0:9b334a45a8ff 447
bogdanm 0:9b334a45a8ff 448 #define PDRUN_VALID_BITS 0x000025FFL
bogdanm 0:9b334a45a8ff 449 #define PDRUN_RESERVED_ONE 0x0000C800L
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 static void power_down_config(uint32_t val)
bogdanm 0:9b334a45a8ff 452 {
bogdanm 0:9b334a45a8ff 453 volatile uint32_t tmp;
bogdanm 0:9b334a45a8ff 454 tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
bogdanm 0:9b334a45a8ff 455 tmp |= (val & PDRUN_VALID_BITS);
bogdanm 0:9b334a45a8ff 456 LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 static void power_up_config(uint32_t val)
bogdanm 0:9b334a45a8ff 460 {
bogdanm 0:9b334a45a8ff 461 volatile uint32_t tmp;
bogdanm 0:9b334a45a8ff 462 tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
bogdanm 0:9b334a45a8ff 463 tmp &= ~(val & PDRUN_VALID_BITS);
bogdanm 0:9b334a45a8ff 464 LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
bogdanm 0:9b334a45a8ff 465 }
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 /**
bogdanm 0:9b334a45a8ff 468 * Initialize the system
bogdanm 0:9b334a45a8ff 469 *
bogdanm 0:9b334a45a8ff 470 * @param none
bogdanm 0:9b334a45a8ff 471 * @return none
bogdanm 0:9b334a45a8ff 472 *
bogdanm 0:9b334a45a8ff 473 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 474 */
bogdanm 0:9b334a45a8ff 475 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 476 #if (CLOCK_SETUP)
bogdanm 0:9b334a45a8ff 477 volatile uint32_t i;
bogdanm 0:9b334a45a8ff 478 #endif
bogdanm 0:9b334a45a8ff 479 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
bogdanm 0:9b334a45a8ff 480 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 485 // Initialize XTALIN/XTALOUT pins
bogdanm 0:9b334a45a8ff 486 LPC_IOCON->PIO2_0 = 0x01;
bogdanm 0:9b334a45a8ff 487 LPC_IOCON->PIO2_1 = 0x01;
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 490 power_up_config(1<<5); /* Power-up sysosc */
bogdanm 0:9b334a45a8ff 491 for (i = 0; i < 2500; i++) __NOP(); /* Wait for osc to stabilize */
bogdanm 0:9b334a45a8ff 492 #endif
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 495 LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
bogdanm 0:9b334a45a8ff 496 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
bogdanm 0:9b334a45a8ff 497 #endif
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 500 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
bogdanm 0:9b334a45a8ff 501 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 0:9b334a45a8ff 502 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
bogdanm 0:9b334a45a8ff 503 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 #if (((MAINCLKSEL_Val & 0x03) == 2) )
bogdanm 0:9b334a45a8ff 508 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 509 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
bogdanm 0:9b334a45a8ff 510 for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */
bogdanm 0:9b334a45a8ff 511 #endif
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
bogdanm 0:9b334a45a8ff 514 power_down_config(1<<7); /* Power-down SYSPLL */
bogdanm 0:9b334a45a8ff 515 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 516 power_up_config(1<<7); /* Power-up SYSPLL */
bogdanm 0:9b334a45a8ff 517 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 518 #endif
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock Source */
bogdanm 0:9b334a45a8ff 521 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
bogdanm 0:9b334a45a8ff 522 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 0:9b334a45a8ff 523 LPC_SYSCON->MAINCLKUEN = 0x01;
bogdanm 0:9b334a45a8ff 524 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
bogdanm 0:9b334a45a8ff 527 #endif /* Clock Setup via Register */
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 #if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
bogdanm 0:9b334a45a8ff 530 // LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
bogdanm 0:9b334a45a8ff 531 // LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
bogdanm 0:9b334a45a8ff 532 // LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 0:9b334a45a8ff 533 // LPC_SYSCON->SYSPLLCLKUEN = 0x01;
bogdanm 0:9b334a45a8ff 534 // while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 LPC_SYSCON->MAINCLKSEL = SYSPLLCLKSEL_Val; /* Select same as SYSPLL */
bogdanm 0:9b334a45a8ff 537 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
bogdanm 0:9b334a45a8ff 538 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 0:9b334a45a8ff 539 LPC_SYSCON->MAINCLKUEN = 0x01;
bogdanm 0:9b334a45a8ff 540 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 LPC_SYSCON->SYSAHBCLKDIV = 1;
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
bogdanm 0:9b334a45a8ff 545 #endif /* Clock Setup via PLL API */
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 #if (USB_CLOCK_SETUP == 1) /* USB clock is used */
bogdanm 0:9b334a45a8ff 548 LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 #if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
bogdanm 0:9b334a45a8ff 551 LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
bogdanm 0:9b334a45a8ff 552 LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 553 LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
bogdanm 0:9b334a45a8ff 554 LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 0:9b334a45a8ff 555 LPC_SYSCON->USBPLLCLKUEN = 0x01;
bogdanm 0:9b334a45a8ff 556 while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 559 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
bogdanm 0:9b334a45a8ff 562 #endif
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
bogdanm 0:9b334a45a8ff 565 LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 #else /* USB clock is not used */
bogdanm 0:9b334a45a8ff 568 LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
bogdanm 0:9b334a45a8ff 569 LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
bogdanm 0:9b334a45a8ff 570 #endif
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 #endif /* Clock Setup */
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 }