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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
147:30b64687e01f 
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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file wdt_map.h
<> 144:ef7eb2e8f9f7 4 * @brief WDT HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3283 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup wdt
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 * <p>
<> 144:ef7eb2e8f9f7 31 * Watchdog Timer HW register map description
<> 144:ef7eb2e8f9f7 32 * </p>
<> 144:ef7eb2e8f9f7 33 *
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 37 #pragma anon_unions
<> 144:ef7eb2e8f9f7 38 #endif
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifndef WDT_MAP_H_
<> 144:ef7eb2e8f9f7 41 #define WDT_MAP_H_
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #include "architecture.h"
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #ifdef REVB
<> 144:ef7eb2e8f9f7 46 /** Watch Dog Timer Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 47 typedef struct {
<> 144:ef7eb2e8f9f7 48 __IO uint32_t LOAD; /**< Watchdog load value */
<> 144:ef7eb2e8f9f7 49 __I uint32_t VALUE; /**< Watchdog current value */
<> 144:ef7eb2e8f9f7 50 union {
<> 144:ef7eb2e8f9f7 51 struct {
<> 144:ef7eb2e8f9f7 52 __IO uint32_t INT_EN :1; /**< interrupt event : 0 = disable counter and interrupt , 1 = enable counter and interrupt */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t RESET_EN :1; /**< Watchdog reset output : 0 = disable 1 = enable */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t PAD :30; /**< Reserved, read undefined, must read as zeros. */
<> 144:ef7eb2e8f9f7 55 } BITS;
<> 144:ef7eb2e8f9f7 56 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 57 } CONTROL;
<> 144:ef7eb2e8f9f7 58 __IO uint32_t INT_CLEAR; /**< Watchdog interrupt clear */
<> 144:ef7eb2e8f9f7 59 __I uint32_t RAW_INT_STAT; /**< Raw interrupt status from the counter */
<> 144:ef7eb2e8f9f7 60 __I uint32_t MASKED_INT_STAT; /**< Enabled interrupt status from the counter */
<> 144:ef7eb2e8f9f7 61 union {
<> 144:ef7eb2e8f9f7 62 struct {
<> 144:ef7eb2e8f9f7 63 __IO uint32_t WRITE_EN :1; /**< write access to all other registers : 0 = enabled(default) , 1 = disabled */
<> 144:ef7eb2e8f9f7 64 __IO uint32_t REG_WRITE_EN :31; /**< Enable write access to all other registers by writing 0x1ACCE551. Disable it by writing any other value.*/
<> 144:ef7eb2e8f9f7 65 } BITS;
<> 144:ef7eb2e8f9f7 66 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 67 } LOCK;
<> 144:ef7eb2e8f9f7 68 __I uint32_t TEST_CTRL; /**< Integration Test Mode : 0 = disable , 1 = Enable */
<> 144:ef7eb2e8f9f7 69 union {
<> 144:ef7eb2e8f9f7 70 struct {
<> 144:ef7eb2e8f9f7 71 __IO uint32_t VAL_INT :1; /**< Value output on WDOGINT when in Integration Test Mode */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t VAL_RES :1; /**< Value output on WDOGRES when in Integration Test Mode */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t PAD:30; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 74 } BITS;
<> 144:ef7eb2e8f9f7 75 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 76 } TEST_OUT;
<> 144:ef7eb2e8f9f7 77 union {
<> 144:ef7eb2e8f9f7 78 struct {
<> 144:ef7eb2e8f9f7 79 __IO uint32_t PART_0 :8; /**< These bits read back as 0x05 */
<> 144:ef7eb2e8f9f7 80 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 81 } BITS;
<> 144:ef7eb2e8f9f7 82 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 83 } PID_REG0;
<> 144:ef7eb2e8f9f7 84 union {
<> 144:ef7eb2e8f9f7 85 struct {
<> 144:ef7eb2e8f9f7 86 __IO uint32_t PART_1 :4; /**< These bits read back as 0x08 */
<> 144:ef7eb2e8f9f7 87 __IO uint32_t DESIGNER_0 :4; /**< These bits read back as 0x01 */
<> 144:ef7eb2e8f9f7 88 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 89 } BITS;
<> 144:ef7eb2e8f9f7 90 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 91 } PID_REG1;
<> 144:ef7eb2e8f9f7 92 union {
<> 144:ef7eb2e8f9f7 93 struct {
<> 144:ef7eb2e8f9f7 94 __IO uint32_t DESIGNER_1 :4; /**< These bits read back as 0x4 */
<> 144:ef7eb2e8f9f7 95 __IO uint32_t REVISION :4; /**< These bits read back as 0x0*/
<> 144:ef7eb2e8f9f7 96 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 97 } BITS;
<> 144:ef7eb2e8f9f7 98 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 99 } PID_REG2;
<> 144:ef7eb2e8f9f7 100 union {
<> 144:ef7eb2e8f9f7 101 struct {
<> 144:ef7eb2e8f9f7 102 __IO uint32_t CONFIG :8; /**< These bits read back as 0x00 */
<> 144:ef7eb2e8f9f7 103 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 104 } BITS;
<> 144:ef7eb2e8f9f7 105 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 106 } PID_REG3;
<> 144:ef7eb2e8f9f7 107 union {
<> 144:ef7eb2e8f9f7 108 struct {
<> 144:ef7eb2e8f9f7 109 __IO uint32_t ID0 :8; /**< These bits read back as 0x0D */
<> 144:ef7eb2e8f9f7 110 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 111 } BITS;
<> 144:ef7eb2e8f9f7 112 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 113 } PCELL_ID0;
<> 144:ef7eb2e8f9f7 114 union {
<> 144:ef7eb2e8f9f7 115 struct {
<> 144:ef7eb2e8f9f7 116 __IO uint32_t ID :8; /**< These bits read back as 0xF0*/
<> 144:ef7eb2e8f9f7 117 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 118 } BITS;
<> 144:ef7eb2e8f9f7 119 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 120 } PCELL_ID1;
<> 144:ef7eb2e8f9f7 121 union {
<> 144:ef7eb2e8f9f7 122 struct {
<> 144:ef7eb2e8f9f7 123 __IO uint32_t ID :8; /**< These bits read back as 0x05*/
<> 144:ef7eb2e8f9f7 124 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 125 } BITS;
<> 144:ef7eb2e8f9f7 126 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 127 } PCELL_ID2;
<> 144:ef7eb2e8f9f7 128 union {
<> 144:ef7eb2e8f9f7 129 struct {
<> 144:ef7eb2e8f9f7 130 __IO uint32_t ID :8; /**< These bits read back as 0xB1*/
<> 144:ef7eb2e8f9f7 131 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 132 } BITS;
<> 144:ef7eb2e8f9f7 133 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 134 } PCELL_ID3;
<> 144:ef7eb2e8f9f7 135 } WdtReg_t, *WdtReg_pt;
<> 144:ef7eb2e8f9f7 136 #endif /* REVB */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifdef REVD
<> 144:ef7eb2e8f9f7 139 typedef struct {
<> 144:ef7eb2e8f9f7 140 __IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
<> 144:ef7eb2e8f9f7 141 __I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
<> 144:ef7eb2e8f9f7 142 union {
<> 144:ef7eb2e8f9f7 143 struct {
<> 144:ef7eb2e8f9f7 144 __IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
<> 144:ef7eb2e8f9f7 145 } BITS;
<> 144:ef7eb2e8f9f7 146 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 147 } CONTROL; /* 0x4000A008 */
<> 144:ef7eb2e8f9f7 148 __O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
<> 144:ef7eb2e8f9f7 149 __O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
<> 144:ef7eb2e8f9f7 150 union {
<> 144:ef7eb2e8f9f7 151 struct {
<> 144:ef7eb2e8f9f7 152 __I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
<> 144:ef7eb2e8f9f7 153 __I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
<> 144:ef7eb2e8f9f7 154 __I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
<> 144:ef7eb2e8f9f7 155 __IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
<> 144:ef7eb2e8f9f7 156 } BITS;
<> 144:ef7eb2e8f9f7 157 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 158 } STATUS; /* 0x4000A014 */
<> 144:ef7eb2e8f9f7 159 } WdtReg_t, *WdtReg_pt;
<> 144:ef7eb2e8f9f7 160 #endif /* REVD */
<> 144:ef7eb2e8f9f7 161 #endif /* WDT_MAP_H_ */