teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
147:30b64687e01f 
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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file uart_16c550.h
<> 144:ef7eb2e8f9f7 4 * @brief Definitions and API for the 16c550 driver.
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 2607 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2013-12-06 18:02:43 +0530 (Fri, 06 Dec 2013) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup uart_16c550
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 * The driver for the 16c550 UART is a character driver (see char_driver.h).
<> 144:ef7eb2e8f9f7 31 * The driver can be accessed via the uart_16c550_driver variable.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 * This file defines the options structure to be passed to the driver when
<> 144:ef7eb2e8f9f7 34 * opening a device. The structure depends on the generic uart_options_t
<> 144:ef7eb2e8f9f7 35 * options structure for any UART implementation (see uart.h).
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 * Any application that uses this driver must define an interrupt handler
<> 144:ef7eb2e8f9f7 38 * for the 16C550 interrupt and call the fUart16C550Handler() function from
<> 144:ef7eb2e8f9f7 39 * that ISR.
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifndef UART_16C550_H_
<> 144:ef7eb2e8f9f7 43 #define UART_16C550_H_
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #include "architecture.h"
<> 144:ef7eb2e8f9f7 46 #include "uart.h"
<> 144:ef7eb2e8f9f7 47 #include "uart_16c550_map.h"
<> 144:ef7eb2e8f9f7 48 #include "memory_map.h"
<> 144:ef7eb2e8f9f7 49 #include "crossbar.h"
<> 144:ef7eb2e8f9f7 50 #include "types.h"
<> 144:ef7eb2e8f9f7 51 #include "clock.h"
<> 144:ef7eb2e8f9f7 52 #include "pad.h"
<> 144:ef7eb2e8f9f7 53 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** A set of options to be passed when opening a 16C550 UART device. */
<> 144:ef7eb2e8f9f7 56 typedef struct uart_16c550_options {
<> 144:ef7eb2e8f9f7 57 uart_options_t uartOptions; /**< The generic UART options. */
<> 144:ef7eb2e8f9f7 58 Uart16C550Reg_pt membase; /**< The memory base for the device's registers. */
<> 144:ef7eb2e8f9f7 59 uint8_t irq; /**< The IRQ number of the IRQ associated to the device. */
<> 144:ef7eb2e8f9f7 60 } uart_16c550_options_t, *uart_16c550_options_pt;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 #define UART_NUM 2
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 #define CTS_ASSERT 1
<> 144:ef7eb2e8f9f7 65 #define CTS_UNASSERT 0
<> 144:ef7eb2e8f9f7 66 #define RTS_ASSERT 1
<> 144:ef7eb2e8f9f7 67 #define RTS_UNASSERT 0
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #define UART_ERROR_INSUFFICIENT_SPACE ((uint8_t)0xF0)
<> 144:ef7eb2e8f9f7 70 #define UART_ERROR_TOO_BIG ((uint8_t)0xF1)
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** The depth of the hardware FIFOs. */
<> 144:ef7eb2e8f9f7 73 #define UART_HW_FIFO_DEPTH 16
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /** The length of the receive buffer in software. */
<> 144:ef7eb2e8f9f7 76 #define UART_RX_BUFFER_LENGTH (1<<8)
<> 144:ef7eb2e8f9f7 77 #define UART_TX_BUFFER_LENGTH (1<<8)
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 #define STATUS_INVALID_PARAMETER 0x1
<> 144:ef7eb2e8f9f7 80 #define STATUS_SUCCESS 0x1
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 #define UART_LCR_DATALEN_BIT_POS 0
<> 144:ef7eb2e8f9f7 83 #define UART_LCR_STPBIT_BIT_POS 2
<> 144:ef7eb2e8f9f7 84 #define UART_LCR_PARITY_BIT_POS 3
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #define UART_FCS_RX_FIFO_RST_BIT_POS 1
<> 144:ef7eb2e8f9f7 87 #define UART_FCS_TX_FIFO_RST_BIT_POS 2
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #define UART_RX_IRQ 0x0
<> 144:ef7eb2e8f9f7 90 #define UART_TX_IRQ 0x1
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #define UART_RX_BUFFER_LEN_MAX 16
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #define UART_LSR_TX_EMPTY_MASK 0x40
<> 144:ef7eb2e8f9f7 95 #define UART_LSR_RX_DATA_READY_MASK 0x01
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #define UART_IER_TX_EMPTY_MASK 0x02
<> 144:ef7eb2e8f9f7 98 #define UART_IER_RX_DATA_READY_MASK 0x01
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 #define UART_DEFAULT_BAUD 9600
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** Interrupt handler for 16C550 UART devices; to be called from an actual ISR.
<> 144:ef7eb2e8f9f7 103 * @param membase The memory base for the device that corresponds to the IRQ.
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 void fUart16C550Handler(Uart16C550Reg_pt membase);
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** An externally accessible instance of the UART driver implementation. */
<> 144:ef7eb2e8f9f7 108 //extern char_driver_t uart_16c550_driver;
<> 144:ef7eb2e8f9f7 109 typedef void (*fUartCallBack)(void);
<> 144:ef7eb2e8f9f7 110 //void serial_init(serial_t *obj, PinName tx, PinName rx);
<> 144:ef7eb2e8f9f7 111 //extern void fSerialInit(Uart16C550Reg_pt UartRegBase, flow_control_t FlowControl);
<> 144:ef7eb2e8f9f7 112 extern void fSerialFree(void);
<> 144:ef7eb2e8f9f7 113 extern void fSerialBaud(Uart16C550Reg_pt UartRegBase, uint32_t BaudRate);
<> 144:ef7eb2e8f9f7 114 extern void fSerialFormat(Uart16C550Reg_pt UartRegBase, uint8_t DataLen, uint8_t Parity, uint8_t StopBit);
<> 144:ef7eb2e8f9f7 115 extern void fSerialIrqSet(Uart16C550Reg_pt UartRegBase, fUartCallBack PtrUartCallBack, uint8_t IrqType, boolean Enable);
<> 144:ef7eb2e8f9f7 116 extern uint8_t fSerialGetc(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 117 extern void fSerialPutc(Uart16C550Reg_pt UartRegBase, uint8_t c);
<> 144:ef7eb2e8f9f7 118 extern boolean fSerialReadable(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 119 extern boolean fSerialWritable(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 120 extern void fSerialClear(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 121 extern void fSerialBreakSet(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 122 extern void fSerialBreakClear(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 123 extern void fSerialPinoutTx(uint8_t PinNo);
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 extern void Uart1_Irq(void);
<> 144:ef7eb2e8f9f7 126 extern void Uart2_Irq(void);
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #endif /* UART_16C550_H_ */