teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
147:30b64687e01f 
backup

Who changed what in which revision?

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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file spi_api.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a sleep functionality
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 0.1 $
<> 144:ef7eb2e8f9f7 8 * $Date: 02-05-2016 $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup spi_api
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 * SPI implementation
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33 #if DEVICE_SPI
<> 144:ef7eb2e8f9f7 34 #include "spi.h"
<> 144:ef7eb2e8f9f7 35 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 36 #include "objects.h"
<> 144:ef7eb2e8f9f7 37 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 38 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 39 #include "memory_map.h"
<> 144:ef7eb2e8f9f7 40 #include "spi_ipc7207_map.h"
<> 144:ef7eb2e8f9f7 41 #include "crossbar.h"
<> 144:ef7eb2e8f9f7 42 #include "clock.h"
<> 144:ef7eb2e8f9f7 43 #include "cmsis_nvic.h"
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #define SPI_FREQ_MAX 4000000
<> 144:ef7eb2e8f9f7 47 #define SPI_ENDIAN_LSB_FIRST 0
<> 144:ef7eb2e8f9f7 48 #define SPI_MASTER_MODE 1
<> 144:ef7eb2e8f9f7 49 #define SPI_SLAVE_MODE 0
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 144:ef7eb2e8f9f7 52 {
<> 144:ef7eb2e8f9f7 53 fSpiInit(obj, mosi, miso, sclk, ssel);
<> 144:ef7eb2e8f9f7 54 }
<> 144:ef7eb2e8f9f7 55 void spi_free(spi_t *obj)
<> 144:ef7eb2e8f9f7 56 {
<> 144:ef7eb2e8f9f7 57 fSpiClose(obj);
<> 144:ef7eb2e8f9f7 58 }
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 if(slave) {
<> 144:ef7eb2e8f9f7 63 /* Slave mode */
<> 144:ef7eb2e8f9f7 64 obj->membase->CONTROL.BITS.MODE = SPI_SLAVE_MODE;
<> 144:ef7eb2e8f9f7 65 } else {
<> 144:ef7eb2e8f9f7 66 /* Master mode */
<> 144:ef7eb2e8f9f7 67 obj->membase->CONTROL.BITS.MODE = SPI_MASTER_MODE;
<> 144:ef7eb2e8f9f7 68 }
<> 144:ef7eb2e8f9f7 69 obj->membase->CONTROL.BITS.WORD_WIDTH = bits >> 0x4; /* word width */
<> 144:ef7eb2e8f9f7 70 obj->membase->CONTROL.BITS.CPOL = mode >> 0x1; /* CPOL */
<> 144:ef7eb2e8f9f7 71 obj->membase->CONTROL.BITS.CPHA = mode & 0x1; /* CPHA */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 obj->membase->CONTROL.BITS.ENDIAN = SPI_ENDIAN_LSB_FIRST; /* Endian */
<> 144:ef7eb2e8f9f7 74 }
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 void spi_frequency(spi_t *obj, int hz)
<> 144:ef7eb2e8f9f7 77 {
<> 144:ef7eb2e8f9f7 78 /* If the frequency is outside the allowable range, set it to the max */
<> 144:ef7eb2e8f9f7 79 if(hz > SPI_FREQ_MAX) {
<> 144:ef7eb2e8f9f7 80 hz = SPI_FREQ_MAX;
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82 obj->membase->FDIV = ((fClockGetPeriphClockfrequency() / hz) >> 1) - 1;
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 int spi_master_write(spi_t *obj, int value)
<> 144:ef7eb2e8f9f7 86 {
<> 144:ef7eb2e8f9f7 87 return(fSpiWriteB(obj, value));
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 int spi_busy(spi_t *obj)
<> 144:ef7eb2e8f9f7 91 {
<> 144:ef7eb2e8f9f7 92 return(obj->membase->STATUS.BITS.XFER_IP);
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint8_t spi_get_module(spi_t *obj)
<> 144:ef7eb2e8f9f7 96 {
<> 144:ef7eb2e8f9f7 97 if(obj->membase == SPI1REG) {
<> 144:ef7eb2e8f9f7 98 return 0; /* UART #1 */
<> 144:ef7eb2e8f9f7 99 } else if(obj->membase == SPI2REG) {
<> 144:ef7eb2e8f9f7 100 return 1; /* UART #2 */
<> 144:ef7eb2e8f9f7 101 } else {
<> 144:ef7eb2e8f9f7 102 return 2; /* Invalid address */
<> 144:ef7eb2e8f9f7 103 }
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #if DEVICE_SPI_ASYNCH /* TODO Not implemented yet */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
<> 144:ef7eb2e8f9f7 109 {
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 uint32_t i;
<> 144:ef7eb2e8f9f7 112 int ndata = 0;
<> 144:ef7eb2e8f9f7 113 uint16_t *tx_ptr = (uint16_t *) tx;
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 if(obj->spi->CONTROL.BITS.WORD_WIDTH == 0) {
<> 144:ef7eb2e8f9f7 116 /* Word size 8 bits */
<> 144:ef7eb2e8f9f7 117 WORD_WIDTH_MASK = 0xFF;
<> 144:ef7eb2e8f9f7 118 } else if(obj->spi->CONTROL.BITS.WORD_WIDTH == 1) {
<> 144:ef7eb2e8f9f7 119 /* Word size 16 bits */
<> 144:ef7eb2e8f9f7 120 WORD_WIDTH_MASK = 0xFFFF;
<> 144:ef7eb2e8f9f7 121 } else {
<> 144:ef7eb2e8f9f7 122 /* Word size 32 bits */
<> 144:ef7eb2e8f9f7 123 WORD_WIDTH_MASK = 0xFFFFFFFF;
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 //frame size
<> 144:ef7eb2e8f9f7 127 if(tx_length == 0) {
<> 144:ef7eb2e8f9f7 128 tx_length = rx_length;
<> 144:ef7eb2e8f9f7 129 tx = (void*) 0;
<> 144:ef7eb2e8f9f7 130 }
<> 144:ef7eb2e8f9f7 131 //set tx rx buffer
<> 144:ef7eb2e8f9f7 132 obj->tx_buff.buffer = (void *)tx;
<> 144:ef7eb2e8f9f7 133 obj->rx_buff.buffer = rx;
<> 144:ef7eb2e8f9f7 134 obj->tx_buff.length = tx_length;
<> 144:ef7eb2e8f9f7 135 obj->rx_buff.length = rx_length;
<> 144:ef7eb2e8f9f7 136 obj->tx_buff.pos = 0;
<> 144:ef7eb2e8f9f7 137 obj->rx_buff.pos = 0;
<> 144:ef7eb2e8f9f7 138 obj->tx_buff.width = bit_width;
<> 144:ef7eb2e8f9f7 139 obj->rx_buff.width = bit_width;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 if((obj->spi.bits == 9) && (tx != 0)) {
<> 144:ef7eb2e8f9f7 143 // Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation
<> 144:ef7eb2e8f9f7 144 for(i = 0; i < (tx_length / 2); i++) {
<> 144:ef7eb2e8f9f7 145 tx_ptr[i] &= 0x1FF;
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 // enable events
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 obj->spi.event |= event;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 // set sleep_level
<> 144:ef7eb2e8f9f7 156 enable irq
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 //write async
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 if ( && ) {
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 }
<> 144:ef7eb2e8f9f7 163 while ((obj->tx_buff.pos < obj->tx_buff.length) &&
<> 144:ef7eb2e8f9f7 164 (obj->spi->STATUS.BITS.TX_FULL == False) &&
<> 144:ef7eb2e8f9f7 165 (obj->spi->STATUS.BITS.RX_FULL == False)) {
<> 144:ef7eb2e8f9f7 166 // spi_buffer_tx_write(obj);
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 if (obj->tx_buff.buffer == (void *)0) {
<> 144:ef7eb2e8f9f7 169 data = SPI_FILL_WORD;
<> 144:ef7eb2e8f9f7 170 } else {
<> 144:ef7eb2e8f9f7 171 uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
<> 144:ef7eb2e8f9f7 172 data = tx[obj->tx_buff.pos] & 0xFF;
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174 obj->spi->TX_DATA = data;
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 ndata++;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179 return ndata;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 uint8_t spi_active(spi_t *obj)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 void spi_abort_asynch(spi_t *obj)
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 #endif /* DEVICE_SPI_ASYNCH */
<> 144:ef7eb2e8f9f7 196 #endif /* DEVICE_SPI */