teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/sleep.c@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
147:30b64687e01f 
backup

Who changed what in which revision?

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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file sleep.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of an sleep functionality
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 0.1 $
<> 144:ef7eb2e8f9f7 8 * $Date: 01-21-2016 $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup sleep
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 * Sleep implementation
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33 #if DEVICE_SLEEP
<> 144:ef7eb2e8f9f7 34 #include "sleep.h"
<> 144:ef7eb2e8f9f7 35 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 36 #include "cmsis_nvic.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #define ENABLE (uint8_t)0x01
<> 144:ef7eb2e8f9f7 39 #define DISABLE (uint8_t)0x00
<> 144:ef7eb2e8f9f7 40 #define MAC_LUT_SIZE (uint8_t)96
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
<> 144:ef7eb2e8f9f7 43 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
<> 144:ef7eb2e8f9f7 44 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
<> 144:ef7eb2e8f9f7 45 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 void sleep(void)
<> 144:ef7eb2e8f9f7 48 {
<> 144:ef7eb2e8f9f7 49 /** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */
<> 144:ef7eb2e8f9f7 50 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 51 PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /* Enter into sleep mode */
<> 144:ef7eb2e8f9f7 54 __ISB();
<> 144:ef7eb2e8f9f7 55 __WFI();
<> 144:ef7eb2e8f9f7 56 }
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 void deepsleep(void)
<> 144:ef7eb2e8f9f7 59 {
<> 144:ef7eb2e8f9f7 60 /** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */
<> 144:ef7eb2e8f9f7 61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 62 PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /** Enter into deep sleep mode */
<> 144:ef7eb2e8f9f7 65 __ISB();
<> 144:ef7eb2e8f9f7 66 __WFI();
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /** Wait for the external 32MHz to be power-ed up & running
<> 144:ef7eb2e8f9f7 69 * Re-power down the 32MHz internal osc
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71 while (!CLOCKREG->CSR.BITS.XTAL32M);
<> 144:ef7eb2e8f9f7 72 PMUREG->CONTROL.BITS.INT32M = 1;
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 void coma(void)
<> 144:ef7eb2e8f9f7 76 {
<> 144:ef7eb2e8f9f7 77 /** Set SLEEPDEEP (SCR) and set COMA to select coma mode */
<> 144:ef7eb2e8f9f7 78 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 79 PMUREG->CONTROL.BITS.ENCOMA = ENABLE;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* TODO Wait till MAC is idle */
<> 144:ef7eb2e8f9f7 82 // while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /* TODO Back up MAC_LUT *
<> 144:ef7eb2e8f9f7 85 uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE];
<> 144:ef7eb2e8f9f7 86 fMacBackupFrameStoreLUT(MAC_LUT_BackUp); */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Disable UART 1 & 2 FIFO during coma*/
<> 144:ef7eb2e8f9f7 89 UART1REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
<> 144:ef7eb2e8f9f7 90 UART2REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /** Enter into coma mode */
<> 144:ef7eb2e8f9f7 93 __ISB();
<> 144:ef7eb2e8f9f7 94 __WFI();
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** Wait for the external 32MHz to be power-ed up & running
<> 144:ef7eb2e8f9f7 97 * Re-power down the 32MHz internal osc
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 while (!CLOCKREG->CSR.BITS.XTAL32M);
<> 144:ef7eb2e8f9f7 100 PMUREG->CONTROL.BITS.INT32M = 1;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** Trim the oscillators */
<> 144:ef7eb2e8f9f7 103 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 144:ef7eb2e8f9f7 104 CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
<> 144:ef7eb2e8f9f7 105 }
<> 144:ef7eb2e8f9f7 106 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 144:ef7eb2e8f9f7 107 CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
<> 144:ef7eb2e8f9f7 108 }
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* Enable UART 1 & 2 FIFO */
<> 144:ef7eb2e8f9f7 111 UART1REG->FCR.WORD |= FCR_FIFO_ENABLE;
<> 144:ef7eb2e8f9f7 112 UART2REG->FCR.WORD |= FCR_FIFO_ENABLE;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* TODO Restore MAC_LUT *
<> 144:ef7eb2e8f9f7 115 fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #endif /* DEVICE_SLEEP */