teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
147:30b64687e01f 
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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file Serial.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a 16C550 UART driver
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 0.1 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-11-04 05:30:00 +0530 (Wed, 04 Nov 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup uart_16c550
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #if DEVICE_SERIAL
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 35 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 36 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 39 #include <string.h>
<> 144:ef7eb2e8f9f7 40 #include "uart_16c550.h"
<> 144:ef7eb2e8f9f7 41 #include "cmsis_nvic.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 static IRQn_Type Irq;
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 uint32_t stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 46 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 static uint32_t serial_irq_ids[UART_NUM] = {0};
<> 144:ef7eb2e8f9f7 49 static uart_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 50 static inline void uart_irq(uint8_t status, uint32_t index);
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** Opens UART device.
<> 144:ef7eb2e8f9f7 54 * @details
<> 144:ef7eb2e8f9f7 55 * Sets the necessary registers. Set to default Baud rate 115200, 8 bit, parity None and stop bit 1.
<> 144:ef7eb2e8f9f7 56 * The UART interrupt is enabled.
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * @note The UART transmit interrupt is not enabled, because sending is controlled
<> 144:ef7eb2e8f9f7 59 * by the task.
<> 144:ef7eb2e8f9f7 60 *
<> 144:ef7eb2e8f9f7 61 * @param UartNum A UART device instance.
<> 144:ef7eb2e8f9f7 62 * @param options The options parameter containing the baud rate.
<> 144:ef7eb2e8f9f7 63 * @return True if opening was successful.
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint16_t clockDivisor;
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 CrossbReg_t *CbRegOffSet;
<> 144:ef7eb2e8f9f7 71 PadReg_t *PadRegOffset;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 //find which peripheral is associated with the rx and tx pins
<> 144:ef7eb2e8f9f7 74 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 75 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 76 //check if the peripherals for each pin are the same or not
<> 144:ef7eb2e8f9f7 77 //returns the enum associated with the peripheral
<> 144:ef7eb2e8f9f7 78 //in the case of this target, the enum is the base address of the peripheral
<> 144:ef7eb2e8f9f7 79 obj->UARTREG = (Uart16C550Reg_pt) pinmap_merge(uart_tx, uart_rx);
<> 144:ef7eb2e8f9f7 80 MBED_ASSERT(obj->UARTREG != (Uart16C550Reg_pt) NC);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 83 pinmap_pinout(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /*TODO: Mac Lobdell - we should recommend using the instance method and not using base addresses as index */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 if (obj->UARTREG == (Uart16C550Reg_pt)STDIO_UART) {
<> 144:ef7eb2e8f9f7 88 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 89 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 90 }
<> 144:ef7eb2e8f9f7 91 /*TODO: determine if pullups are needed/recommended */
<> 144:ef7eb2e8f9f7 92 /* if (tx != NC) {
<> 144:ef7eb2e8f9f7 93 pin_mode(tx, PullUp);
<> 144:ef7eb2e8f9f7 94 }
<> 144:ef7eb2e8f9f7 95 if (rx != NC) {
<> 144:ef7eb2e8f9f7 96 pin_mode(rx, PullUp);
<> 144:ef7eb2e8f9f7 97 }
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 /* Configure IOs to UART using cross bar, pad and GPIO settings */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 if(obj->UARTREG == UART2REG) {
<> 144:ef7eb2e8f9f7 102 /* UART 2 */
<> 144:ef7eb2e8f9f7 103 CLOCK_ENABLE(CLOCK_UART2);
<> 144:ef7eb2e8f9f7 104 Irq = Uart2_IRQn;
<> 144:ef7eb2e8f9f7 105 } else if(obj->UARTREG == UART1REG) {
<> 144:ef7eb2e8f9f7 106 /* UART 1 */
<> 144:ef7eb2e8f9f7 107 CLOCK_ENABLE(CLOCK_UART1);
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 Irq = Uart1_IRQn;
<> 144:ef7eb2e8f9f7 110 } else {
<> 144:ef7eb2e8f9f7 111 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 115 CLOCK_ENABLE(CLOCK_CROSSB);
<> 144:ef7eb2e8f9f7 116 CLOCK_ENABLE(CLOCK_PAD);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /*TODO: determine if tx and rx are used correctly in this case - this depends on the pin enum matching the position in the crossbar*/
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Configure tx pin as UART */
<> 144:ef7eb2e8f9f7 121 CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (tx * CROSS_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 122 CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* tx pin as UART */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* Configure rx pin as UART */
<> 144:ef7eb2e8f9f7 125 CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (rx * CROSS_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 126 CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* rx pin as UART */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /** - Set pad parameters, output drive strength, pull piece control, output drive type */
<> 144:ef7eb2e8f9f7 129 PadRegOffset = (PadReg_t*)(PADREG_BASE + (tx * PAD_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 130 PadRegOffset->PADIO0.WORD = PAD_UART_TX; /* Pad setting for UART Tx */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 133 PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 GPIOREG->W_OUT |= (True << tx); /* tx as OUT direction */
<> 144:ef7eb2e8f9f7 136 GPIOREG->W_IN |= (True << rx); /* rx as IN directon */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 CLOCK_DISABLE(CLOCK_PAD);
<> 144:ef7eb2e8f9f7 139 CLOCK_DISABLE(CLOCK_CROSSB);
<> 144:ef7eb2e8f9f7 140 CLOCK_DISABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
<> 144:ef7eb2e8f9f7 143 * The right-shift of 4 is a division of 16, representing the oversampling rate. */
<> 144:ef7eb2e8f9f7 144 clockDivisor = (fClockGetPeriphClockfrequency() / UART_DEFAULT_BAUD) >> 4;
<> 144:ef7eb2e8f9f7 145 obj->UARTREG->LCR.WORD = 0x80;
<> 144:ef7eb2e8f9f7 146 obj->UARTREG->DLL = clockDivisor & 0xFF;
<> 144:ef7eb2e8f9f7 147 obj->UARTREG->DLM = clockDivisor >> 8;
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Set the character width to 8 data bits, no parity, 1 stop bit. Write the entire line control register,
<> 144:ef7eb2e8f9f7 150 * effectively disabling the divisor latch. */
<> 144:ef7eb2e8f9f7 151 obj->UARTREG->LCR.WORD = 0x03;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Enable the FIFOs, reset the Tx and Rx FIFOs, set the Rx FIFO trigger level to 8 bytes, and set DMA Mode
<> 144:ef7eb2e8f9f7 154 to 1. */
<> 144:ef7eb2e8f9f7 155 obj->UARTREG->FCR.WORD = (FCR_RXFIFOTRIGGERLEVEL_8 | FCR_DMA_MODE_1 |
<> 144:ef7eb2e8f9f7 156 FCR_TXFIFO_RESET | FCR_RXFIFO_RESET | FCR_FIFO_ENABLE);
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Make a copy of the current MSR to the SCR register. This is used from task space to determine the
<> 144:ef7eb2e8f9f7 159 * flow control state. */
<> 144:ef7eb2e8f9f7 160 obj->UARTREG->SCR = obj->UARTREG->MSR.WORD;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 if((int)obj->UARTREG == STDIO_UART) {
<> 144:ef7eb2e8f9f7 163 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 164 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 NVIC_ClearPendingIRQ(Irq);
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 return;
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /** Closes a UART device.
<> 144:ef7eb2e8f9f7 173 * @details
<> 144:ef7eb2e8f9f7 174 * Disables the UART interrupt.
<> 144:ef7eb2e8f9f7 175 *
<> 144:ef7eb2e8f9f7 176 * @param device The UART device to close.
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 void serial_free(serial_t *obj)
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 NVIC_DisableIRQ(obj->IRQType);
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 void serial_baud(serial_t *obj, int baudrate)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
<> 144:ef7eb2e8f9f7 186 * The right-shift of 4 is a division of 16, representing the oversampling rate. */
<> 144:ef7eb2e8f9f7 187 uint16_t clockDivisor = (fClockGetPeriphClockfrequency() / baudrate) >> 4;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 obj->UARTREG->LCR.BITS.DLAB = True;
<> 144:ef7eb2e8f9f7 190 obj->UARTREG->DLL = clockDivisor & 0xFF;
<> 144:ef7eb2e8f9f7 191 obj->UARTREG->DLM = clockDivisor >> 8;
<> 144:ef7eb2e8f9f7 192 obj->UARTREG->LCR.BITS.DLAB = False;
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /*
<> 144:ef7eb2e8f9f7 196 Parity XX0 – Parity disabled; 001 – Odd Parity; 011 – Even Parity; 101 – Stick Parity, checked as 1; 111 – Stick Parity, checked as 0.
<> 144:ef7eb2e8f9f7 197 StopBit 0 – 1 stop bit; 1 – 2 stop bits.
<> 144:ef7eb2e8f9f7 198 DataLen 00 – 5 bits; 01 – 6 bits; 10 – 7 bits; 11 – 8 bits
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 if(data_bits >= 5 && data_bits <= 8 && parity <= 7 && stop_bits >= 1 && stop_bits <= 2) {
<> 144:ef7eb2e8f9f7 203 if(parity == (SerialParity)0) {
<> 144:ef7eb2e8f9f7 204 parity = (SerialParity)0;
<> 144:ef7eb2e8f9f7 205 } else {
<> 144:ef7eb2e8f9f7 206 parity = (SerialParity)(parity + parity - 1) ;
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 obj->UARTREG->LCR.WORD |= ((((data_bits - 5) << UART_LCR_DATALEN_BIT_POS) |
<> 144:ef7eb2e8f9f7 210 (parity << UART_LCR_PARITY_BIT_POS) |
<> 144:ef7eb2e8f9f7 211 ((stop_bits - 1) << UART_LCR_STPBIT_BIT_POS)) & 0x3F);
<> 144:ef7eb2e8f9f7 212 } else {
<> 144:ef7eb2e8f9f7 213 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 218 {
<> 144:ef7eb2e8f9f7 219 irq_handler = handler;
<> 144:ef7eb2e8f9f7 220 serial_irq_ids[obj->index] = id;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /******************************************************
<> 144:ef7eb2e8f9f7 224 ************* Internal IRQ functions ******************
<> 144:ef7eb2e8f9f7 225 *******************************************************/
<> 144:ef7eb2e8f9f7 226 void Uart1_Irq()
<> 144:ef7eb2e8f9f7 227 {
<> 144:ef7eb2e8f9f7 228 uint8_t active_irq = (uint8_t)(UART1REG->LSR.WORD) & 0xFF;
<> 144:ef7eb2e8f9f7 229 uint8_t irq_mask = 0;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 if(UART1REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
<> 144:ef7eb2e8f9f7 232 irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 if(UART1REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
<> 144:ef7eb2e8f9f7 236 irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 //uart_irq((uint8_t)(UART1REG->LSR.WORD & 0xFF), 0);
<> 144:ef7eb2e8f9f7 240 uart_irq(active_irq & irq_mask, 0);
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 void Uart2_Irq()
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 uint8_t active_irq = (uint8_t)(UART2REG->LSR.WORD) & 0xFF;
<> 144:ef7eb2e8f9f7 246 uint8_t irq_mask = 0;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 if(UART2REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
<> 144:ef7eb2e8f9f7 249 irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 if(UART2REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
<> 144:ef7eb2e8f9f7 253 irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 //uart_irq((uint8_t)(UART2REG->LSR.WORD & 0xFF), 1);
<> 144:ef7eb2e8f9f7 257 uart_irq(active_irq & irq_mask, 1);
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 }
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 static inline void uart_irq(uint8_t status, uint32_t index)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 if (serial_irq_ids[index] != 0) {
<> 144:ef7eb2e8f9f7 264 if (status & UART_LSR_TX_EMPTY_MASK) {
<> 144:ef7eb2e8f9f7 265 irq_handler(serial_irq_ids[index], TxIrq);
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267 if (status & UART_LSR_RX_DATA_READY_MASK) {
<> 144:ef7eb2e8f9f7 268 irq_handler(serial_irq_ids[index], RxIrq);
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272 /******************************************************/
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 IRQn_Type irq_n = (IRQn_Type)0;
<> 144:ef7eb2e8f9f7 277 uint32_t Vector = 0;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Check UART number & assign irq handler */
<> 144:ef7eb2e8f9f7 280 if(obj->UARTREG == UART1REG) {
<> 144:ef7eb2e8f9f7 281 /* UART 2 */
<> 144:ef7eb2e8f9f7 282 Vector = (uint32_t)&Uart1_Irq;
<> 144:ef7eb2e8f9f7 283 irq_n = Uart1_IRQn;
<> 144:ef7eb2e8f9f7 284 } else if(obj->UARTREG == UART2REG) {
<> 144:ef7eb2e8f9f7 285 /* UART 1 */
<> 144:ef7eb2e8f9f7 286 Vector = (uint32_t)&Uart2_Irq;
<> 144:ef7eb2e8f9f7 287 irq_n = Uart2_IRQn;
<> 144:ef7eb2e8f9f7 288 } else {
<> 144:ef7eb2e8f9f7 289 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Check IRQ type & enable/disable accordingly */
<> 144:ef7eb2e8f9f7 293 if(enable) {
<> 144:ef7eb2e8f9f7 294 /* Enable */
<> 144:ef7eb2e8f9f7 295 if(irq == RxIrq) {
<> 144:ef7eb2e8f9f7 296 /* Rx IRQ */
<> 144:ef7eb2e8f9f7 297 obj->UARTREG->FCR.BITS.RX_FIFO_TRIG = 0x0;
<> 144:ef7eb2e8f9f7 298 obj->UARTREG->IER.BITS.RX_DATA_INT = True;
<> 144:ef7eb2e8f9f7 299 } else if(irq == TxIrq) {
<> 144:ef7eb2e8f9f7 300 /* Tx IRQ */
<> 144:ef7eb2e8f9f7 301 obj->UARTREG->IER.BITS.TX_HOLD_INT = True;
<> 144:ef7eb2e8f9f7 302 } else {
<> 144:ef7eb2e8f9f7 303 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305 NVIC_SetVector(irq_n, Vector);
<> 144:ef7eb2e8f9f7 306 NVIC_EnableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 307 } else {
<> 144:ef7eb2e8f9f7 308 /* Disable */
<> 144:ef7eb2e8f9f7 309 NVIC_DisableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 310 if(irq == RxIrq) {
<> 144:ef7eb2e8f9f7 311 /* Rx IRQ */
<> 144:ef7eb2e8f9f7 312 obj->UARTREG->IER.BITS.RX_DATA_INT = False;
<> 144:ef7eb2e8f9f7 313 } else if(irq == TxIrq) {
<> 144:ef7eb2e8f9f7 314 /* Tx IRQ */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 obj->UARTREG->IER.BITS.TX_HOLD_INT = False;
<> 144:ef7eb2e8f9f7 317 } else {
<> 144:ef7eb2e8f9f7 318 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 int serial_getc(serial_t *obj)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 uint8_t c;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */
<> 144:ef7eb2e8f9f7 328 c = obj->UARTREG->RBR & 0xFF; /* Get received character */
<> 144:ef7eb2e8f9f7 329 return c;
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 void serial_putc(serial_t *obj, int c)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 while(!obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY);/* Wait till THR is empty */
<> 144:ef7eb2e8f9f7 336 obj->UARTREG->THR = c; /* Transmit byte */
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 int serial_readable(serial_t *obj)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 return obj->UARTREG->LSR.BITS.READY;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 int serial_writable(serial_t *obj)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 return obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 void serial_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 351 {
<> 144:ef7eb2e8f9f7 352 /* Reset TX & RX FIFO */
<> 144:ef7eb2e8f9f7 353 obj->UARTREG->FCR.WORD |= ((True << UART_FCS_TX_FIFO_RST_BIT_POS) |
<> 144:ef7eb2e8f9f7 354 (True << UART_FCS_RX_FIFO_RST_BIT_POS));
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 void serial_break_set(serial_t *obj)
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 obj->UARTREG->LCR.BITS.BREAK = True;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 void serial_break_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 363 {
<> 144:ef7eb2e8f9f7 364 obj->UARTREG->LCR.BITS.BREAK = False;
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 void serial_pinout_tx(PinName tx)
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 /* COnfigure PinNo to drive strength of 1, Push pull and pull none */
<> 144:ef7eb2e8f9f7 370 fPadIOCtrl(tx, 1, 0, 1);
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /** Configure the serial for the flow control. It sets flow control in the hardware
<> 144:ef7eb2e8f9f7 374 * if a serial peripheral supports it, otherwise software emulation is used.
<> 144:ef7eb2e8f9f7 375 *
<> 144:ef7eb2e8f9f7 376 * @param obj The serial object
<> 144:ef7eb2e8f9f7 377 * @param type The type of the flow control. Look at the available FlowControl types.
<> 144:ef7eb2e8f9f7 378 * @param rxflow The TX pin name
<> 144:ef7eb2e8f9f7 379 * @param txflow The RX pin name
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 144:ef7eb2e8f9f7 382 {
<> 144:ef7eb2e8f9f7 383 /* TODO: This is an empty implementation for now.*/
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 #endif /* DEVICE_SERIAL */