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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
147:30b64687e01f 
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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file rtc_map.h
<> 144:ef7eb2e8f9f7 4 * @brief Real Time Clock HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor.
<> 144:ef7eb2e8f9f7 7 * $Rev: 3008 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup rtc
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 * <p>
<> 144:ef7eb2e8f9f7 31 * Teal Time Clock HW register map description
<> 144:ef7eb2e8f9f7 32 * </p>
<> 144:ef7eb2e8f9f7 33 *
<> 144:ef7eb2e8f9f7 34 * <h1> Reference document(s) </h1>
<> 144:ef7eb2e8f9f7 35 * <p>
<> 144:ef7eb2e8f9f7 36 * <a HOURef="../pdf/IPC7206_RTC_APB_DS_v1P0.pdf" target="_blank">
<> 144:ef7eb2e8f9f7 37 * IPC7206 APB RTC Design Specification v1.0 </a>
<> 144:ef7eb2e8f9f7 38 * </p>
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #ifndef RTC_MAP_H_
<> 144:ef7eb2e8f9f7 42 #define RTC_MAP_H_
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #include "architecture.h"
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** Real Time Clock Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 47 typedef struct {
<> 144:ef7eb2e8f9f7 48 #ifdef REVB
<> 144:ef7eb2e8f9f7 49 /*REVD REPLACE COMPLETE MAP WITH DATA FROM DIG DESIGN SPEC */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t SECOND;/**<SECOND Counter */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t MINUTE;/**<DAY Counter */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t HOUR;/**< HOUR Counter */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t DAY;/**< DAY Counter */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t MONTH;/**< MONTH Counter */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t YEAR;/**< YEAR Counter */
<> 144:ef7eb2e8f9f7 56 union {
<> 144:ef7eb2e8f9f7 57 struct {
<> 144:ef7eb2e8f9f7 58 __IO uint32_t PAD1 :1;/**<Reserved; Writes have no effect. Read as 0 */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t TEST_MINUTE :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 60 __IO uint32_t TEST_HOUR :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t TEST_DAY :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 62 __IO uint32_t TEST_MONTH :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 63 __IO uint32_t TEST_YEAR :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 64 __IO uint32_t PAD2 :1;/**<Reserved; Writes have no effect. Read as 0 */
<> 144:ef7eb2e8f9f7 65 __IO uint32_t RESET :1;/**< 0 = counters are incrementing , 1 = counters are in reset */
<> 144:ef7eb2e8f9f7 66 } BITS;
<> 144:ef7eb2e8f9f7 67 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 68 } CONTROL;
<> 144:ef7eb2e8f9f7 69 __IO uint32_t DIVISOR;/**<Clock Divisor value */
<> 144:ef7eb2e8f9f7 70 __IO uint32_t ALARM_SECOND;/**<SECOND Alarm's BCD value */
<> 144:ef7eb2e8f9f7 71 __IO uint32_t ALARM_MINUTE;/**<MINUTE Alarm's BCD value */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t ALARM_HOUR;/**<HOUR Alarm's BCD value*/
<> 144:ef7eb2e8f9f7 73 __IO uint32_t ALARM_DAY;/**<DAY Alarm's BCD value */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t ALARM_MONTH;/**<MONTH Alarm's BCD value */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t ALARM_YEAR;/**<YEAR Alarm's BCD value */
<> 144:ef7eb2e8f9f7 76 union {
<> 144:ef7eb2e8f9f7 77 struct {
<> 144:ef7eb2e8f9f7 78 __IO uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 80 __IO uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t DAY :1;/**<DAY Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 82 __IO uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 83 __IO uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 84 __IO uint32_t PAD :2 ;/**<Writes have no effect; Read as 2’b00 */
<> 144:ef7eb2e8f9f7 85 } BITS;
<> 144:ef7eb2e8f9f7 86 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 87 } INT_EN_CONTROL;
<> 144:ef7eb2e8f9f7 88 union {
<> 144:ef7eb2e8f9f7 89 struct {
<> 144:ef7eb2e8f9f7 90 __I uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 91 __I uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 92 __I uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 93 __I uint32_t DAY :1;/**<DAY Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 94 __I uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 95 __I uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 96 __I uint32_t PAD :2; /**<Read as 00 */
<> 144:ef7eb2e8f9f7 97 } BITS;
<> 144:ef7eb2e8f9f7 98 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 99 } INT_STATUS;
<> 144:ef7eb2e8f9f7 100 union {
<> 144:ef7eb2e8f9f7 101 struct {
<> 144:ef7eb2e8f9f7 102 __O uint32_t SECOND :1;/**<Write 1 to clear the SECOND Alarm interrupt.*/
<> 144:ef7eb2e8f9f7 103 __O uint32_t MINUTE :1;/**<Write 1 to clear the MINUTE Alarm interrupt*/
<> 144:ef7eb2e8f9f7 104 __O uint32_t HOUR :1;/**<Write 1 to clear the HOUR Alarm interrupt*/
<> 144:ef7eb2e8f9f7 105 __O uint32_t DAY :1;/**< Write 1 to clear the DAY Alarm interrupt*/
<> 144:ef7eb2e8f9f7 106 __O uint32_t MONTH :1;/**<Write 1 to clear the MONTH Alarm interrupt */
<> 144:ef7eb2e8f9f7 107 __O uint32_t YEAR :1;/**< Write 1 to clear the YEAR Alarm interrupt*/
<> 144:ef7eb2e8f9f7 108 __O uint32_t PAD :2 ;/**< Writes have no effect. */
<> 144:ef7eb2e8f9f7 109 } BITS;
<> 144:ef7eb2e8f9f7 110 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 111 } INT_CLEAR;
<> 144:ef7eb2e8f9f7 112 #endif /* REVB */
<> 144:ef7eb2e8f9f7 113 #ifdef REVD
<> 144:ef7eb2e8f9f7 114 __IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
<> 144:ef7eb2e8f9f7 115 __IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
<> 144:ef7eb2e8f9f7 116 __IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
<> 144:ef7eb2e8f9f7 117 __IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
<> 144:ef7eb2e8f9f7 118 union {
<> 144:ef7eb2e8f9f7 119 struct {
<> 144:ef7eb2e8f9f7 120 __IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
<> 144:ef7eb2e8f9f7 121 __IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
<> 144:ef7eb2e8f9f7 122 __IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
<> 144:ef7eb2e8f9f7 123 __IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
<> 144:ef7eb2e8f9f7 124 } BITS;
<> 144:ef7eb2e8f9f7 125 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 126 } CONTROL; /* 0x4000F010 */
<> 144:ef7eb2e8f9f7 127 union {
<> 144:ef7eb2e8f9f7 128 struct {
<> 144:ef7eb2e8f9f7 129 /**<Any write to the status register will clear the error bit. */
<> 144:ef7eb2e8f9f7 130 __IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
<> 144:ef7eb2e8f9f7 131 __IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
<> 144:ef7eb2e8f9f7 132 __IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
<> 144:ef7eb2e8f9f7 133 __IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
<> 144:ef7eb2e8f9f7 134 __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
<> 144:ef7eb2e8f9f7 135 __IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
<> 144:ef7eb2e8f9f7 136 __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
<> 144:ef7eb2e8f9f7 137 __IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
<> 144:ef7eb2e8f9f7 138 __IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
<> 144:ef7eb2e8f9f7 139 __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
<> 144:ef7eb2e8f9f7 140 __IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
<> 144:ef7eb2e8f9f7 141 } BITS;
<> 144:ef7eb2e8f9f7 142 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 143 } STATUS; /* 0x4000F014 */
<> 144:ef7eb2e8f9f7 144 union {
<> 144:ef7eb2e8f9f7 145 struct {
<> 144:ef7eb2e8f9f7 146 __O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
<> 144:ef7eb2e8f9f7 147 __O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
<> 144:ef7eb2e8f9f7 148 } BITS;
<> 144:ef7eb2e8f9f7 149 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 150 } INT_CLEAR; /* 0x4000F018 */
<> 144:ef7eb2e8f9f7 151 #endif /* REVD */
<> 144:ef7eb2e8f9f7 152 } RtcReg_t, *RtcReg_pt;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 #endif /* RTC_MAP_H_ */