teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
147:30b64687e01f 
backup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file macHw_map.h
<> 144:ef7eb2e8f9f7 4 * @brief MACHW hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3390 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-05-13 17:21:05 +0530 (Wed, 13 May 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup macHw
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 */
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 #ifndef MACHW_MAP_H_
<> 144:ef7eb2e8f9f7 33 #define MACHW_MAP_H_
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 36 * *
<> 144:ef7eb2e8f9f7 37 * Header files *
<> 144:ef7eb2e8f9f7 38 * *
<> 144:ef7eb2e8f9f7 39 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include "architecture.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 44 * *
<> 144:ef7eb2e8f9f7 45 * Type definitions *
<> 144:ef7eb2e8f9f7 46 * *
<> 144:ef7eb2e8f9f7 47 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** macHw register map (phy, mac and agc parts) */
<> 144:ef7eb2e8f9f7 50 typedef struct {
<> 144:ef7eb2e8f9f7 51 __O uint32_t SEQUENCER; /**< 0x40014000 */
<> 144:ef7eb2e8f9f7 52 union {
<> 144:ef7eb2e8f9f7 53 struct {
<> 144:ef7eb2e8f9f7 54 __IO uint32_t MODE:2;
<> 144:ef7eb2e8f9f7 55 __IO uint32_t NOACK:1;
<> 144:ef7eb2e8f9f7 56 __IO uint32_t FT:1;
<> 144:ef7eb2e8f9f7 57 __IO uint32_t PAD0:3;
<> 144:ef7eb2e8f9f7 58 __IO uint32_t AUTO:1;
<> 144:ef7eb2e8f9f7 59 __IO uint32_t PAD1:1;
<> 144:ef7eb2e8f9f7 60 __IO uint32_t NOW:1;
<> 144:ef7eb2e8f9f7 61 __IO uint32_t PAD2:1;
<> 144:ef7eb2e8f9f7 62 __IO uint32_t PRM:1;
<> 144:ef7eb2e8f9f7 63 __IO uint32_t NFCS:1;
<> 144:ef7eb2e8f9f7 64 __IO uint32_t PAN:1;
<> 144:ef7eb2e8f9f7 65 __IO uint32_t RSTT:1;
<> 144:ef7eb2e8f9f7 66 __IO uint32_t RSTR:1;
<> 144:ef7eb2e8f9f7 67 __IO uint32_t ACK_ENABLE:1;
<> 144:ef7eb2e8f9f7 68 __IO uint32_t BEA_ENABLE:1;
<> 144:ef7eb2e8f9f7 69 __IO uint32_t CMD_ENABLE:1;
<> 144:ef7eb2e8f9f7 70 __IO uint32_t DATA_ENABLE:1;
<> 144:ef7eb2e8f9f7 71 __IO uint32_t RES_ENABLE:1;
<> 144:ef7eb2e8f9f7 72 } BITS;
<> 144:ef7eb2e8f9f7 73 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 74 } SEQ_OPTIONS; /**< 0x40014004 */
<> 144:ef7eb2e8f9f7 75 union {
<> 144:ef7eb2e8f9f7 76 struct {
<> 144:ef7eb2e8f9f7 77 __IO uint32_t SRST:1;
<> 144:ef7eb2e8f9f7 78 __IO uint32_t ON:1;
<> 144:ef7eb2e8f9f7 79 __IO uint32_t CLKDIV:1;
<> 144:ef7eb2e8f9f7 80 } BITS;
<> 144:ef7eb2e8f9f7 81 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 82 } CONTROL; /**< 0x40014008 */
<> 144:ef7eb2e8f9f7 83 __O uint32_t PAD0; /**< 0x4001400C */
<> 144:ef7eb2e8f9f7 84 union {
<> 144:ef7eb2e8f9f7 85 struct {
<> 144:ef7eb2e8f9f7 86 __I uint32_t CODE:4;
<> 144:ef7eb2e8f9f7 87 __I uint32_t PAD0:8;
<> 144:ef7eb2e8f9f7 88 __I uint32_t MSO:1;
<> 144:ef7eb2e8f9f7 89 __I uint32_t CB:1;
<> 144:ef7eb2e8f9f7 90 __I uint32_t PAD1:1;
<> 144:ef7eb2e8f9f7 91 __I uint32_t MST:1;
<> 144:ef7eb2e8f9f7 92 } BITS;
<> 144:ef7eb2e8f9f7 93 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 94 } STATUS; /**< 0x40014010 */
<> 144:ef7eb2e8f9f7 95 union {
<> 144:ef7eb2e8f9f7 96 struct {
<> 144:ef7eb2e8f9f7 97 __IO uint32_t TFP:1;
<> 144:ef7eb2e8f9f7 98 __IO uint32_t SDC:1;
<> 144:ef7eb2e8f9f7 99 __IO uint32_t IC:1;
<> 144:ef7eb2e8f9f7 100 __IO uint32_t SDB:1;
<> 144:ef7eb2e8f9f7 101 __IO uint32_t SSP:1;
<> 144:ef7eb2e8f9f7 102 __IO uint32_t TFPO:1;
<> 144:ef7eb2e8f9f7 103 } BITS;
<> 144:ef7eb2e8f9f7 104 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 105 } OPTIONS; /**< 0x40014014 */
<> 144:ef7eb2e8f9f7 106 __IO uint32_t PANID; /**< 0x40014018 */
<> 144:ef7eb2e8f9f7 107 __IO uint32_t SHORT_ADDRESS; /**< 0x4001401C */
<> 144:ef7eb2e8f9f7 108 __IO uint32_t LONG_ADDRESS_HIGH; /**< 0x40014020 */
<> 144:ef7eb2e8f9f7 109 __IO uint32_t LONG_ADDRESS_LOW; /**< 0x40014024 */
<> 144:ef7eb2e8f9f7 110 union {
<> 144:ef7eb2e8f9f7 111 struct {
<> 144:ef7eb2e8f9f7 112 __IO uint32_t BIT_CLOCK_DIVIDER:8;
<> 144:ef7eb2e8f9f7 113 __IO uint32_t SYSTEM_CLOCK_DIVIDER:8;
<> 144:ef7eb2e8f9f7 114 __IO uint32_t CHIP_CLOCK_DIVIDER:8;
<> 144:ef7eb2e8f9f7 115 } BITS;
<> 144:ef7eb2e8f9f7 116 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 117 } DIVIDER; /**< 0x40014028 */
<> 144:ef7eb2e8f9f7 118 union {
<> 144:ef7eb2e8f9f7 119 struct {
<> 144:ef7eb2e8f9f7 120 __IO uint32_t RECEIVE_WARMPUP:12;
<> 144:ef7eb2e8f9f7 121 __IO uint32_t PAD0:4;
<> 144:ef7eb2e8f9f7 122 __IO uint32_t TRANSMIT_WARMPUP:12;
<> 144:ef7eb2e8f9f7 123 } BITS;
<> 144:ef7eb2e8f9f7 124 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 125 } RX_TX_WARMPUPS; /**< 0x4001402c */
<> 144:ef7eb2e8f9f7 126 union {
<> 144:ef7eb2e8f9f7 127 struct {
<> 144:ef7eb2e8f9f7 128 __O uint32_t EC:1;
<> 144:ef7eb2e8f9f7 129 __O uint32_t ES:1;
<> 144:ef7eb2e8f9f7 130 __O uint32_t DATA:1;
<> 144:ef7eb2e8f9f7 131 __O uint32_t FS:1;
<> 144:ef7eb2e8f9f7 132 __O uint32_t FP:1;
<> 144:ef7eb2e8f9f7 133 __O uint32_t FMD:1;
<> 144:ef7eb2e8f9f7 134 #ifdef REVD
<> 144:ef7eb2e8f9f7 135 __I uint32_t PC:1;
<> 144:ef7eb2e8f9f7 136 #endif /* REVD */
<> 144:ef7eb2e8f9f7 137 } BITS;
<> 144:ef7eb2e8f9f7 138 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 139 } CLEAR_IRQ; /**< 0x40014030 */
<> 144:ef7eb2e8f9f7 140 union {
<> 144:ef7eb2e8f9f7 141 struct {
<> 144:ef7eb2e8f9f7 142 __IO uint32_t EC:1;
<> 144:ef7eb2e8f9f7 143 __IO uint32_t ES:1;
<> 144:ef7eb2e8f9f7 144 __IO uint32_t DATA:1;
<> 144:ef7eb2e8f9f7 145 __IO uint32_t FS:1;
<> 144:ef7eb2e8f9f7 146 __IO uint32_t FP:1;
<> 144:ef7eb2e8f9f7 147 __IO uint32_t FM:1;
<> 144:ef7eb2e8f9f7 148 #ifdef REVD
<> 144:ef7eb2e8f9f7 149 __I uint32_t PC:1;
<> 144:ef7eb2e8f9f7 150 #endif /* REVD */
<> 144:ef7eb2e8f9f7 151 } BITS;
<> 144:ef7eb2e8f9f7 152 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 153 } MASK_IRQ; /**< 0x40014034 */
<> 144:ef7eb2e8f9f7 154 union {
<> 144:ef7eb2e8f9f7 155 struct {
<> 144:ef7eb2e8f9f7 156 __I uint32_t EC:1;
<> 144:ef7eb2e8f9f7 157 __I uint32_t ES:1;
<> 144:ef7eb2e8f9f7 158 __I uint32_t DATA:1;
<> 144:ef7eb2e8f9f7 159 __I uint32_t FS:1;
<> 144:ef7eb2e8f9f7 160 __I uint32_t FP:1;
<> 144:ef7eb2e8f9f7 161 __I uint32_t FM:1;
<> 144:ef7eb2e8f9f7 162 #ifdef REVD
<> 144:ef7eb2e8f9f7 163 __I uint32_t PC:1;
<> 144:ef7eb2e8f9f7 164 #endif /* REVD */
<> 144:ef7eb2e8f9f7 165 } BITS;
<> 144:ef7eb2e8f9f7 166 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 167 } IRQ_STATUS; /**< 0x40014038 */
<> 144:ef7eb2e8f9f7 168 __O uint32_t PAD1; /**< 0x4001403C */
<> 144:ef7eb2e8f9f7 169 union {
<> 144:ef7eb2e8f9f7 170 struct {
<> 144:ef7eb2e8f9f7 171 __IO uint32_t START:1;
<> 144:ef7eb2e8f9f7 172 __IO uint32_t STOP:1;
<> 144:ef7eb2e8f9f7 173 } BITS;
<> 144:ef7eb2e8f9f7 174 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 175 } TIMER_ENABLE; /**< 0x40014040 */
<> 144:ef7eb2e8f9f7 176 union {
<> 144:ef7eb2e8f9f7 177 struct {
<> 144:ef7eb2e8f9f7 178 __IO uint32_t START:1;
<> 144:ef7eb2e8f9f7 179 __IO uint32_t STOP:1;
<> 144:ef7eb2e8f9f7 180 } BITS;
<> 144:ef7eb2e8f9f7 181 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 182 } TIMER_DISABLE; /**< 0x40014044 */
<> 144:ef7eb2e8f9f7 183 __IO uint32_t TIMER; /**< 0x40014048 */
<> 144:ef7eb2e8f9f7 184 __IO uint32_t START_TIME; /**< 0x4001404C */
<> 144:ef7eb2e8f9f7 185 __IO uint32_t STOP_TIME; /**< 0x40014050 */
<> 144:ef7eb2e8f9f7 186 union {
<> 144:ef7eb2e8f9f7 187 struct {
<> 144:ef7eb2e8f9f7 188 __I uint32_t START:1;
<> 144:ef7eb2e8f9f7 189 __I uint32_t STOP:1;
<> 144:ef7eb2e8f9f7 190 } BITS;
<> 144:ef7eb2e8f9f7 191 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 192 } TIMER_STATUS; /**< 0x40014054 */
<> 144:ef7eb2e8f9f7 193 __I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */
<> 144:ef7eb2e8f9f7 194 __O uint32_t PAD4; /**< 0x4001405C */
<> 144:ef7eb2e8f9f7 195 __I uint32_t FINISH_TIME; /**< 0x40014060 */
<> 144:ef7eb2e8f9f7 196 union {
<> 144:ef7eb2e8f9f7 197 struct {
<> 144:ef7eb2e8f9f7 198 __IO uint32_t TX_SLOT_OFFSET:12;
<> 144:ef7eb2e8f9f7 199 __IO uint32_t PAD0:4;
<> 144:ef7eb2e8f9f7 200 __IO uint32_t RX_SLOT_OFFSET:12;
<> 144:ef7eb2e8f9f7 201 } BITS;
<> 144:ef7eb2e8f9f7 202 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 203 } SLOT_OFFSET; /**< 0x40014064 */
<> 144:ef7eb2e8f9f7 204 __I uint32_t TIME_STAMP; /**< 0x40014068 */
<> 144:ef7eb2e8f9f7 205 #ifdef REVB
<> 144:ef7eb2e8f9f7 206 __O uint32_t PAD5; /**< 0x4001406C */
<> 144:ef7eb2e8f9f7 207 #endif /* REVB */
<> 144:ef7eb2e8f9f7 208 union {
<> 144:ef7eb2e8f9f7 209 struct {
<> 144:ef7eb2e8f9f7 210 __IO uint32_t CRD_SHORT_ADDRESS:16;
<> 144:ef7eb2e8f9f7 211 __IO uint32_t PAD0:13;
<> 144:ef7eb2e8f9f7 212 __IO uint32_t ASSOC_PAN_COORD:1;
<> 144:ef7eb2e8f9f7 213 __IO uint32_t PAN_COORD_ADDR_L:1;
<> 144:ef7eb2e8f9f7 214 __IO uint32_t PAN_COORD_ADDR_S:1;
<> 144:ef7eb2e8f9f7 215 } BITS;
<> 144:ef7eb2e8f9f7 216 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 217 #ifdef REVB
<> 144:ef7eb2e8f9f7 218 } CRD_SHORT_ADDR; /**< 0x40014070 */
<> 144:ef7eb2e8f9f7 219 __IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014074 */
<> 144:ef7eb2e8f9f7 220 __IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014078 */
<> 144:ef7eb2e8f9f7 221 #endif /* REVB */
<> 144:ef7eb2e8f9f7 222 #ifdef REVD
<> 144:ef7eb2e8f9f7 223 } CRD_SHORT_ADDR; /**< 0x4001406C */
<> 144:ef7eb2e8f9f7 224 __IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */
<> 144:ef7eb2e8f9f7 225 __IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */
<> 144:ef7eb2e8f9f7 226 __O uint32_t PAD5; /**< 0x40014078 */
<> 144:ef7eb2e8f9f7 227 #endif /* REVD */
<> 144:ef7eb2e8f9f7 228 __O uint32_t PAD9; /**< 0x4001407C */
<> 144:ef7eb2e8f9f7 229 __O uint32_t PAD10; /**< 0x40014080 */
<> 144:ef7eb2e8f9f7 230 __O uint32_t PAD11; /**< 0x40014084 */
<> 144:ef7eb2e8f9f7 231 __IO uint32_t RX_LENGTH; /**< 0x40014088 */
<> 144:ef7eb2e8f9f7 232 union {
<> 144:ef7eb2e8f9f7 233 struct {
<> 144:ef7eb2e8f9f7 234 __IO uint32_t TXLENGTH:7;
<> 144:ef7eb2e8f9f7 235 __O uint32_t PAD0:1;
<> 144:ef7eb2e8f9f7 236 __IO uint32_t TX_PRE_CHIPS:4;
<> 144:ef7eb2e8f9f7 237 } BITS;
<> 144:ef7eb2e8f9f7 238 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 239 } TX_LENGTH; /**< 0x4001408C */
<> 144:ef7eb2e8f9f7 240 __IO uint32_t TX_SEQ_NUMBER; /**< 0x40014090 */
<> 144:ef7eb2e8f9f7 241 __IO uint32_t TX_ACK_DELAY; /**< 0x40014094 */
<> 144:ef7eb2e8f9f7 242 union {
<> 144:ef7eb2e8f9f7 243 struct {
<> 144:ef7eb2e8f9f7 244 __IO uint32_t RXACKDELAY:12;
<> 144:ef7eb2e8f9f7 245 __IO uint32_t PAD0:4;
<> 144:ef7eb2e8f9f7 246 __IO uint32_t RXAUTODELAY:12;
<> 144:ef7eb2e8f9f7 247 } BITS;
<> 144:ef7eb2e8f9f7 248 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 249 } RX_ACK_DELAY; /**< 0x40014098 */
<> 144:ef7eb2e8f9f7 250 __IO uint32_t TX_FLUSH; /**< 0x4001409C */
<> 144:ef7eb2e8f9f7 251 union {
<> 144:ef7eb2e8f9f7 252 struct {
<> 144:ef7eb2e8f9f7 253 __IO uint32_t CCA_DELAY:12;
<> 144:ef7eb2e8f9f7 254 __IO uint32_t PAD0:4;
<> 144:ef7eb2e8f9f7 255 __IO uint32_t CCA_LENGTH:12;
<> 144:ef7eb2e8f9f7 256 } BITS;
<> 144:ef7eb2e8f9f7 257 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 258 } CCA; /**< 0x400140A0 */
<> 144:ef7eb2e8f9f7 259 union {
<> 144:ef7eb2e8f9f7 260 struct {
<> 144:ef7eb2e8f9f7 261 __IO uint32_t RXACK_END:12;
<> 144:ef7eb2e8f9f7 262 __IO uint32_t PAD0:4;
<> 144:ef7eb2e8f9f7 263 __IO uint32_t RXSLOTTED_END:12;
<> 144:ef7eb2e8f9f7 264 } BITS;
<> 144:ef7eb2e8f9f7 265 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 266 } ACK_STOP; /**< 0x400140A4 */
<> 144:ef7eb2e8f9f7 267 __IO uint32_t TXCCA; /**< 0x400140A8 */
<> 144:ef7eb2e8f9f7 268 __IO uint32_t ADDR_L_LOC; /**< 0x400140AC */
<> 144:ef7eb2e8f9f7 269 __IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */
<> 144:ef7eb2e8f9f7 270 __IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */
<> 144:ef7eb2e8f9f7 271 __IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */
<> 144:ef7eb2e8f9f7 272 __IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */
<> 144:ef7eb2e8f9f7 273 union {
<> 144:ef7eb2e8f9f7 274 struct {
<> 144:ef7eb2e8f9f7 275 __IO uint32_t AA:1;
<> 144:ef7eb2e8f9f7 276 __IO uint32_t AFA:1;
<> 144:ef7eb2e8f9f7 277 __IO uint32_t PRE:1;
<> 144:ef7eb2e8f9f7 278 __IO uint32_t PAD0:25;
<> 144:ef7eb2e8f9f7 279 __IO uint32_t GAIN_START:4;
<> 144:ef7eb2e8f9f7 280 } BITS;
<> 144:ef7eb2e8f9f7 281 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 282 } AGC_CONTROL; /**< 0x400140C0 */
<> 144:ef7eb2e8f9f7 283 union {
<> 144:ef7eb2e8f9f7 284 struct {
<> 144:ef7eb2e8f9f7 285 __IO uint32_t SETTLE_DELAY:8;
<> 144:ef7eb2e8f9f7 286 __IO uint32_t MEASURE_DELAY:8;
<> 144:ef7eb2e8f9f7 287 __IO uint32_t DIVIDER:8;
<> 144:ef7eb2e8f9f7 288 __IO uint32_t HIGH_THRESHOLD:4;
<> 144:ef7eb2e8f9f7 289 __IO uint32_t LOW_THRESHOLD:4;
<> 144:ef7eb2e8f9f7 290 } BITS;
<> 144:ef7eb2e8f9f7 291 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 292 } AGC_SETTINGS; /**< 0x400140C4 */
<> 144:ef7eb2e8f9f7 293 union {
<> 144:ef7eb2e8f9f7 294 struct {
<> 144:ef7eb2e8f9f7 295 __IO uint32_t GC1:3;
<> 144:ef7eb2e8f9f7 296 __IO uint32_t GC2:3;
<> 144:ef7eb2e8f9f7 297 __IO uint32_t GC3:1;
<> 144:ef7eb2e8f9f7 298 __IO uint32_t PAD:1;
<> 144:ef7eb2e8f9f7 299 __IO uint32_t AGC_STATE:4;
<> 144:ef7eb2e8f9f7 300 } BITS;
<> 144:ef7eb2e8f9f7 301 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 302 } AGC_STATUS; /**< 0x400140C8 */
<> 144:ef7eb2e8f9f7 303 union {
<> 144:ef7eb2e8f9f7 304 struct {
<> 144:ef7eb2e8f9f7 305 __IO uint32_t GAIN3:7;
<> 144:ef7eb2e8f9f7 306 __IO uint32_t PAD0:1;
<> 144:ef7eb2e8f9f7 307 __IO uint32_t GAIN2:7;
<> 144:ef7eb2e8f9f7 308 __IO uint32_t PAD1:1;
<> 144:ef7eb2e8f9f7 309 __IO uint32_t GAIN1:7;
<> 144:ef7eb2e8f9f7 310 __IO uint32_t PAD2:1;
<> 144:ef7eb2e8f9f7 311 __IO uint32_t GAIN0:7;
<> 144:ef7eb2e8f9f7 312 __IO uint32_t PAD3:1;
<> 144:ef7eb2e8f9f7 313 } BITS;
<> 144:ef7eb2e8f9f7 314 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 315 } AGC_GAIN_TABLE0; /**< 0x400140CC */
<> 144:ef7eb2e8f9f7 316 union {
<> 144:ef7eb2e8f9f7 317 struct {
<> 144:ef7eb2e8f9f7 318 __IO uint32_t GAIN7:7;
<> 144:ef7eb2e8f9f7 319 __IO uint32_t PAD0:1;
<> 144:ef7eb2e8f9f7 320 __IO uint32_t GAIN6:7;
<> 144:ef7eb2e8f9f7 321 __IO uint32_t PAD1:1;
<> 144:ef7eb2e8f9f7 322 __IO uint32_t GAIN5:7;
<> 144:ef7eb2e8f9f7 323 __IO uint32_t PAD2:1;
<> 144:ef7eb2e8f9f7 324 __IO uint32_t GAIN4:7;
<> 144:ef7eb2e8f9f7 325 __IO uint32_t PAD3:1;
<> 144:ef7eb2e8f9f7 326 } BITS;
<> 144:ef7eb2e8f9f7 327 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 328 } AGC_GAIN_TABLE1; /**< 0x400140D0 */
<> 144:ef7eb2e8f9f7 329 union {
<> 144:ef7eb2e8f9f7 330 struct {
<> 144:ef7eb2e8f9f7 331 __IO uint32_t GAIN11:7;
<> 144:ef7eb2e8f9f7 332 __IO uint32_t PAD0:1;
<> 144:ef7eb2e8f9f7 333 __IO uint32_t GAIN10:7;
<> 144:ef7eb2e8f9f7 334 __IO uint32_t PAD1:1;
<> 144:ef7eb2e8f9f7 335 __IO uint32_t GAIN9:7;
<> 144:ef7eb2e8f9f7 336 __IO uint32_t PAD2:1;
<> 144:ef7eb2e8f9f7 337 __IO uint32_t GAIN8:7;
<> 144:ef7eb2e8f9f7 338 __IO uint32_t PAD3:1;
<> 144:ef7eb2e8f9f7 339 } BITS;
<> 144:ef7eb2e8f9f7 340 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 341 } AGC_GAIN_TABLE2; /**< 0x400140D4 */
<> 144:ef7eb2e8f9f7 342 union {
<> 144:ef7eb2e8f9f7 343 struct {
<> 144:ef7eb2e8f9f7 344 __IO uint32_t GAIN15:7;
<> 144:ef7eb2e8f9f7 345 __IO uint32_t PAD0:1;
<> 144:ef7eb2e8f9f7 346 __IO uint32_t GAIN14:7;
<> 144:ef7eb2e8f9f7 347 __IO uint32_t PAD1:1;
<> 144:ef7eb2e8f9f7 348 __IO uint32_t GAIN13:7;
<> 144:ef7eb2e8f9f7 349 __IO uint32_t PAD2:1;
<> 144:ef7eb2e8f9f7 350 __IO uint32_t GAIN12:7;
<> 144:ef7eb2e8f9f7 351 __IO uint32_t PAD3:1;
<> 144:ef7eb2e8f9f7 352 } BITS;
<> 144:ef7eb2e8f9f7 353 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 354 } AGC_GAIN_TABLE3; /**< 0x400140D8 */
<> 144:ef7eb2e8f9f7 355 } MacHwReg_t, *MacHwReg_pt;
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /** macHw register map (demodulator part) */
<> 144:ef7eb2e8f9f7 358 typedef struct {
<> 144:ef7eb2e8f9f7 359 union {
<> 144:ef7eb2e8f9f7 360 struct {
<> 144:ef7eb2e8f9f7 361 __IO uint32_t DRC:1; /**< Reserved */
<> 144:ef7eb2e8f9f7 362 __IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */
<> 144:ef7eb2e8f9f7 363 __IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */
<> 144:ef7eb2e8f9f7 364 __IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */
<> 144:ef7eb2e8f9f7 365 __IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */
<> 144:ef7eb2e8f9f7 366 __IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */
<> 144:ef7eb2e8f9f7 367 __IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */
<> 144:ef7eb2e8f9f7 368 __IO uint32_t PAD1:9;
<> 144:ef7eb2e8f9f7 369 __IO uint32_t DFR:16; /**<Selectively enables individual frequency offsets used during preamble search. Each of the 15 bits in this field corresponds to one of 15 different frequency offsets. A bit value of 0 removes a specific frequency offset from the search, while a bit value of 1 includes the frequency offset in the search. */
<> 144:ef7eb2e8f9f7 370 } BITS;
<> 144:ef7eb2e8f9f7 371 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 372 } DMD_CONTROL0; /**< 0x40014100 */
<> 144:ef7eb2e8f9f7 373 union {
<> 144:ef7eb2e8f9f7 374 struct {
<> 144:ef7eb2e8f9f7 375 __IO uint32_t DST:4; /**< This value specifies the SFD search period in symbols. After preamble detection, the demodulator begins symbol recovery and searches for the start-of-frame delimiter (SFD). If the SFD is not found within the number of symbols specified, the preamble detection flag is cleared and a new preamble search is initiated. The default value of 8 symbols should be sufficient for 802.15.4 compliant applications. Default 8 */
<> 144:ef7eb2e8f9f7 376 __IO uint32_t PAD0:4;
<> 144:ef7eb2e8f9f7 377 __IO uint32_t DPT:6; /**< The similarity criteria used for preamble detection includes a rule that all time index values must occupy a span equal to or less than this value. The default span of 0011 means that the correlation peaks must span a range of 3Ts, where Ts is the sample period = 0.25 µs. This value is recommended for typical multipath conditions. Very long-range applications may benefit from a higher value. Default 3 */
<> 144:ef7eb2e8f9f7 378 __IO uint32_t PAD1:2;
<> 144:ef7eb2e8f9f7 379 __IO uint32_t DPF:4; /**< The similarity criteria used for preamble detection includes a rule that all frequency index values must occupy a span equal to or less than this value. The default span of 0001 means that the difference between largest frequency index and smallest frequency index must be less than or equal to 1. Default 1 */
<> 144:ef7eb2e8f9f7 380 __IO uint32_t PAD2:4;
<> 144:ef7eb2e8f9f7 381 __IO uint32_t DCT:4; /**< In order for preamble detection to be declared, the correlation peaks must exceed a threshold. The threshold is computed dynamically and includes a programmable scale factor: 1 + bit[27]/2 + bit[26]/4 + bit[25]/8 + bit[24]/16 The default value of 1.5 is recommended for manual-antenna selection, while a value of 1.75 is recommended for automatic antenna selection. */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 } BITS;
<> 144:ef7eb2e8f9f7 384 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 385 } DMD_CONTROL1; /**< 0x40014104 */
<> 144:ef7eb2e8f9f7 386 union {
<> 144:ef7eb2e8f9f7 387 struct {
<> 144:ef7eb2e8f9f7 388 __IO uint32_t RSSI_THRESHOLD:8; /**< Threshold value used to determine clear channel assessment (CCA) result. The channel is declared busy if RSSI > threshold. Default 0xFF */
<> 144:ef7eb2e8f9f7 389 __IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */
<> 144:ef7eb2e8f9f7 390 } BITS;
<> 144:ef7eb2e8f9f7 391 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 392 } DMD_CONTROL2; /**< 0x40014108 */
<> 144:ef7eb2e8f9f7 393 union {
<> 144:ef7eb2e8f9f7 394 struct {
<> 144:ef7eb2e8f9f7 395 __I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */
<> 144:ef7eb2e8f9f7 396 __I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
<> 144:ef7eb2e8f9f7 397 __I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
<> 144:ef7eb2e8f9f7 398 __I uint32_t PAD0:3;
<> 144:ef7eb2e8f9f7 399 __I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */
<> 144:ef7eb2e8f9f7 400 } BITS;
<> 144:ef7eb2e8f9f7 401 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 402 } DMD_STATUS; /**< 0x4001410C */
<> 144:ef7eb2e8f9f7 403 } DmdReg_t, *DmdReg_pt;
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 #endif /* MACHW_MAP_H_ */