teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
147:30b64687e01f 
backup

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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file dma_map.h
<> 144:ef7eb2e8f9f7 4 * @brief DMA hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3415 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup dma
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 */
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 #ifndef DMA_MAP_H_
<> 144:ef7eb2e8f9f7 33 #define DMA_MAP_H_
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 36 * *
<> 144:ef7eb2e8f9f7 37 * Header files *
<> 144:ef7eb2e8f9f7 38 * *
<> 144:ef7eb2e8f9f7 39 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include "architecture.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 44 * *
<> 144:ef7eb2e8f9f7 45 * Type definitions *
<> 144:ef7eb2e8f9f7 46 * *
<> 144:ef7eb2e8f9f7 47 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** DMA control HW registers structure overlay */
<> 144:ef7eb2e8f9f7 50 #ifdef REVB
<> 144:ef7eb2e8f9f7 51 typedef struct {
<> 144:ef7eb2e8f9f7 52 __IO uint32_t CONTROL; /**< Write 1 to enable DMA, write 0 to disable */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t STATUS; /**< To be debined */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t INT_ENABLE; /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t INT_CLEAR_ENABLE; /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
<> 144:ef7eb2e8f9f7 59 __I uint32_t INT_STATUS; /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
<> 144:ef7eb2e8f9f7 60 } DmaReg_t, *DmaReg_pt;
<> 144:ef7eb2e8f9f7 61 #endif /* REVB */
<> 144:ef7eb2e8f9f7 62 #ifdef REVD
<> 144:ef7eb2e8f9f7 63 typedef struct {
<> 144:ef7eb2e8f9f7 64 union {
<> 144:ef7eb2e8f9f7 65 struct {
<> 144:ef7eb2e8f9f7 66 __IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
<> 144:ef7eb2e8f9f7 68 } BITS;
<> 144:ef7eb2e8f9f7 69 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 70 } CONTROL; /**< Control register */
<> 144:ef7eb2e8f9f7 71 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
<> 144:ef7eb2e8f9f7 74 union {
<> 144:ef7eb2e8f9f7 75 struct {
<> 144:ef7eb2e8f9f7 76 __I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
<> 144:ef7eb2e8f9f7 77 __I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
<> 144:ef7eb2e8f9f7 78 __I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
<> 144:ef7eb2e8f9f7 79 } BITS;
<> 144:ef7eb2e8f9f7 80 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 81 } STATUS; /**< Status register */
<> 144:ef7eb2e8f9f7 82 union {
<> 144:ef7eb2e8f9f7 83 struct {
<> 144:ef7eb2e8f9f7 84 __IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
<> 144:ef7eb2e8f9f7 85 __IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
<> 144:ef7eb2e8f9f7 86 __IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
<> 144:ef7eb2e8f9f7 87 } BITS;
<> 144:ef7eb2e8f9f7 88 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 89 } INT_ENABLE; /**< Interrupt enable */
<> 144:ef7eb2e8f9f7 90 union {
<> 144:ef7eb2e8f9f7 91 struct {
<> 144:ef7eb2e8f9f7 92 __IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
<> 144:ef7eb2e8f9f7 93 __IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
<> 144:ef7eb2e8f9f7 94 __IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
<> 144:ef7eb2e8f9f7 95 } BITS;
<> 144:ef7eb2e8f9f7 96 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 97 } INT_CLEAR; /**< Interrupt clear */
<> 144:ef7eb2e8f9f7 98 union {
<> 144:ef7eb2e8f9f7 99 struct {
<> 144:ef7eb2e8f9f7 100 __I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
<> 144:ef7eb2e8f9f7 101 __I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
<> 144:ef7eb2e8f9f7 102 __I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
<> 144:ef7eb2e8f9f7 103 } BITS;
<> 144:ef7eb2e8f9f7 104 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 105 } INT_STATUS; /**< Interrupt status */
<> 144:ef7eb2e8f9f7 106 } DmaReg_t, *DmaReg_pt;
<> 144:ef7eb2e8f9f7 107 #endif /* REVD */
<> 144:ef7eb2e8f9f7 108 #endif /* DMA_MAP_H_ */