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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h@148:4802eb17e82b, 2016-10-17 (annotated)
- Committer:
- rodriguise
- Date:
- Mon Oct 17 18:47:01 2016 +0000
- Revision:
- 148:4802eb17e82b
- Parent:
- 147:30b64687e01f
backup
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file adc_sar_map.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @brief ADC HW register map |
<> | 144:ef7eb2e8f9f7 | 5 | * @internal |
<> | 144:ef7eb2e8f9f7 | 6 | * @author ON Semiconductor |
<> | 144:ef7eb2e8f9f7 | 7 | * $Rev: 3422 $ |
<> | 144:ef7eb2e8f9f7 | 8 | * $Date: 2015-06-09 11:01:43 +0530 (Tue, 09 Jun 2015) $ |
<> | 144:ef7eb2e8f9f7 | 9 | ****************************************************************************** |
<> | 147:30b64687e01f | 10 | * Copyright 2016 Semiconductor Components Industries LLC (d/b/a ON Semiconductor). |
<> | 147:30b64687e01f | 11 | * All rights reserved. This software and/or documentation is licensed by ON Semiconductor |
<> | 147:30b64687e01f | 12 | * under limited terms and conditions. The terms and conditions pertaining to the software |
<> | 147:30b64687e01f | 13 | * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf |
<> | 147:30b64687e01f | 14 | * (ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software) and |
<> | 147:30b64687e01f | 15 | * if applicable the software license agreement. Do not use this software and/or |
<> | 147:30b64687e01f | 16 | * documentation unless you have carefully read and you agree to the limited terms and |
<> | 147:30b64687e01f | 17 | * conditions. By using this software and/or documentation, you agree to the limited |
<> | 147:30b64687e01f | 18 | * terms and conditions. |
<> | 144:ef7eb2e8f9f7 | 19 | * |
<> | 144:ef7eb2e8f9f7 | 20 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
<> | 144:ef7eb2e8f9f7 | 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
<> | 144:ef7eb2e8f9f7 | 23 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
<> | 144:ef7eb2e8f9f7 | 24 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
<> | 144:ef7eb2e8f9f7 | 25 | * @endinternal |
<> | 144:ef7eb2e8f9f7 | 26 | * |
<> | 144:ef7eb2e8f9f7 | 27 | * @ingroup adc_sar |
<> | 144:ef7eb2e8f9f7 | 28 | * |
<> | 144:ef7eb2e8f9f7 | 29 | * @details |
<> | 144:ef7eb2e8f9f7 | 30 | * <p> |
<> | 144:ef7eb2e8f9f7 | 31 | * ADC HW register map description |
<> | 144:ef7eb2e8f9f7 | 32 | * </p> |
<> | 144:ef7eb2e8f9f7 | 33 | * |
<> | 144:ef7eb2e8f9f7 | 34 | */ |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | #ifndef ADC_MAP_H_ |
<> | 144:ef7eb2e8f9f7 | 37 | #define ADC_MAP_H_ |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | #include "architecture.h" |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | /* ADC Control HW Structure Overlay */ |
<> | 144:ef7eb2e8f9f7 | 43 | typedef struct { |
<> | 144:ef7eb2e8f9f7 | 44 | union { |
<> | 144:ef7eb2e8f9f7 | 45 | struct { |
<> | 144:ef7eb2e8f9f7 | 46 | __IO uint32_t MODE :1; /** 1= Continuous Conversion 0= Single Shot */ |
<> | 144:ef7eb2e8f9f7 | 47 | __IO uint32_t START_CONV :1; /** 1= Start Conversion 0= No effect*/ |
<> | 144:ef7eb2e8f9f7 | 48 | __IO uint32_t ABORT :1; /** 1= Aborts the Continuous Conversion mode 0=No effect */ |
<> | 144:ef7eb2e8f9f7 | 49 | __IO uint32_t MEASUREMENT_TYPE :1; /** 1= Absolute 0= Differential */ |
<> | 144:ef7eb2e8f9f7 | 50 | __IO uint32_t INPUT_SCALE :3; /** 000 1.0 001 0.6923 010 0.5294 011 0.4286 100 0.3600 101 0.3103 110 0.2728 111 0.2432 */ |
<> | 144:ef7eb2e8f9f7 | 51 | __I uint32_t BIT7:1; /** NA Always read backs 0*/ |
<> | 144:ef7eb2e8f9f7 | 52 | __IO uint32_t CONV_CH :3; /** Selects 1 or 8 channels to do a conversion on. 000 A[0] 000 A[1] 010 A[2] 011 A[3] 100 N/A 101 N/A 110 Temperature sensor 111 Battery */ |
<> | 144:ef7eb2e8f9f7 | 53 | __I uint32_t NA :1; /** NA */ |
<> | 144:ef7eb2e8f9f7 | 54 | __IO uint32_t REF_CH :3; /** Selects 1 to 8 channels for reference channel 000 A[0] 000 A[1] 010 A[2] 011 A[3] 100 N/A 101 N/A 110 Temperature sensor 111 Battery */ |
<> | 144:ef7eb2e8f9f7 | 55 | } BITS; |
<> | 144:ef7eb2e8f9f7 | 56 | __IO uint32_t WORD; |
<> | 144:ef7eb2e8f9f7 | 57 | } CONTROL; |
<> | 144:ef7eb2e8f9f7 | 58 | union { |
<> | 144:ef7eb2e8f9f7 | 59 | struct { |
<> | 144:ef7eb2e8f9f7 | 60 | __IO uint32_t SAMPLE_RATE :16; /** Sets the sample rate in units of PCLKperiod * (Prescale + 1). */ |
<> | 144:ef7eb2e8f9f7 | 61 | __IO uint32_t WARMUP_TIME :8; /** Sets the warm-up time in units of PCLKperiod * (Prescale + 1) */ |
<> | 144:ef7eb2e8f9f7 | 62 | __IO uint32_t SAMPLE_TIME :8; /** Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/ |
<> | 144:ef7eb2e8f9f7 | 63 | } BITS; |
<> | 144:ef7eb2e8f9f7 | 64 | __IO uint32_t WORD; |
<> | 144:ef7eb2e8f9f7 | 65 | } DELAY; |
<> | 144:ef7eb2e8f9f7 | 66 | __I uint32_t DATA; |
<> | 144:ef7eb2e8f9f7 | 67 | __IO uint32_t IR; |
<> | 144:ef7eb2e8f9f7 | 68 | union { |
<> | 144:ef7eb2e8f9f7 | 69 | struct { |
<> | 144:ef7eb2e8f9f7 | 70 | __IO uint32_t PRESC_VAL :8; /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */ |
<> | 144:ef7eb2e8f9f7 | 71 | __IO uint32_t PRESC_EN :1; /** 1= enables PreScalar 0= Disable Prescalar */ |
<> | 144:ef7eb2e8f9f7 | 72 | // __IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */ |
<> | 144:ef7eb2e8f9f7 | 73 | } BITS; |
<> | 144:ef7eb2e8f9f7 | 74 | __IO uint32_t WORD; |
<> | 144:ef7eb2e8f9f7 | 75 | } PRESCALE; |
<> | 144:ef7eb2e8f9f7 | 76 | __I uint32_t STATUS; |
<> | 144:ef7eb2e8f9f7 | 77 | } ADCReg_t,*AdcReg_pt; |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | #endif /* ADC_MAP_H_ */ |