teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/startup_LPC8xx.S@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************
<> 144:ef7eb2e8f9f7 2 *
<> 144:ef7eb2e8f9f7 3 * Part one of the system initialization code, contains low-level
<> 144:ef7eb2e8f9f7 4 * initialization, plain thumb variant.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Copyright 2011 IAR Systems. All rights reserved.
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * $Revision: 47876 $
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 **************************************************/
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 ;
<> 144:ef7eb2e8f9f7 13 ; The modules in this file are included in the libraries, and may be replaced
<> 144:ef7eb2e8f9f7 14 ; by any user-defined modules that define the PUBLIC symbol _program_start or
<> 144:ef7eb2e8f9f7 15 ; a user defined start symbol.
<> 144:ef7eb2e8f9f7 16 ; To override the cstartup defined in the library, simply add your modified
<> 144:ef7eb2e8f9f7 17 ; version to the workbench project.
<> 144:ef7eb2e8f9f7 18 ;
<> 144:ef7eb2e8f9f7 19 ; The vector table is normally located at address 0.
<> 144:ef7eb2e8f9f7 20 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
<> 144:ef7eb2e8f9f7 21 ; The name "__vector_table" has special meaning for C-SPY:
<> 144:ef7eb2e8f9f7 22 ; it is where the SP start value is found, and the NVIC vector
<> 144:ef7eb2e8f9f7 23 ; table register (VTOR) is initialized to this address if != 0.
<> 144:ef7eb2e8f9f7 24 ;
<> 144:ef7eb2e8f9f7 25 ; Cortex-M version
<> 144:ef7eb2e8f9f7 26 ;
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 MODULE ?cstartup
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 ;; Forward declaration of sections.
<> 144:ef7eb2e8f9f7 32 SECTION CSTACK:DATA:NOROOT(3)
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 SECTION .intvec:CODE:NOROOT(2)
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 EXTERN __iar_program_start
<> 144:ef7eb2e8f9f7 37 EXTERN SystemInit
<> 144:ef7eb2e8f9f7 38 PUBLIC __vector_table
<> 144:ef7eb2e8f9f7 39 PUBLIC __vector_table_0x1c
<> 144:ef7eb2e8f9f7 40 PUBLIC __Vectors
<> 144:ef7eb2e8f9f7 41 PUBLIC __Vectors_End
<> 144:ef7eb2e8f9f7 42 PUBLIC __Vectors_Size
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 DATA
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 __vector_table
<> 144:ef7eb2e8f9f7 47 DCD sfe(CSTACK)
<> 144:ef7eb2e8f9f7 48 DCD Reset_Handler
<> 144:ef7eb2e8f9f7 49 DCD NMI_Handler
<> 144:ef7eb2e8f9f7 50 DCD HardFault_Handler
<> 144:ef7eb2e8f9f7 51 DCD 0
<> 144:ef7eb2e8f9f7 52 DCD 0
<> 144:ef7eb2e8f9f7 53 DCD 0
<> 144:ef7eb2e8f9f7 54 __vector_table_0x1c
<> 144:ef7eb2e8f9f7 55 DCD 0
<> 144:ef7eb2e8f9f7 56 DCD 0
<> 144:ef7eb2e8f9f7 57 DCD 0
<> 144:ef7eb2e8f9f7 58 DCD 0
<> 144:ef7eb2e8f9f7 59 DCD SVC_Handler
<> 144:ef7eb2e8f9f7 60 DCD 0
<> 144:ef7eb2e8f9f7 61 DCD 0
<> 144:ef7eb2e8f9f7 62 DCD PendSV_Handler
<> 144:ef7eb2e8f9f7 63 DCD SysTick_Handler
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 ; External Interrupts
<> 144:ef7eb2e8f9f7 66 DCD SPI0_IRQHandler ; SPI0 controller
<> 144:ef7eb2e8f9f7 67 DCD SPI1_IRQHandler ; SPI1 controller
<> 144:ef7eb2e8f9f7 68 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 69 DCD UART0_IRQHandler ; UART0
<> 144:ef7eb2e8f9f7 70 DCD UART1_IRQHandler ; UART1
<> 144:ef7eb2e8f9f7 71 DCD UART2_IRQHandler ; UART2
<> 144:ef7eb2e8f9f7 72 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 73 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 74 DCD I2C_IRQHandler ; I2C controller
<> 144:ef7eb2e8f9f7 75 DCD SCT_IRQHandler ; Smart Counter Timer
<> 144:ef7eb2e8f9f7 76 DCD MRT_IRQHandler ; Multi-Rate Timer
<> 144:ef7eb2e8f9f7 77 DCD CMP_IRQHandler ; Comparator
<> 144:ef7eb2e8f9f7 78 DCD WDT_IRQHandler ; PIO1 (0:11)
<> 144:ef7eb2e8f9f7 79 DCD BOD_IRQHandler ; Brown Out Detect
<> 144:ef7eb2e8f9f7 80 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 81 DCD WKT_IRQHandler ; Wakeup timer
<> 144:ef7eb2e8f9f7 82 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 83 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 84 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 85 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 86 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 87 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 90 DCD PININT0_IRQHandler ; PIO INT0
<> 144:ef7eb2e8f9f7 91 DCD PININT1_IRQHandler ; PIO INT1
<> 144:ef7eb2e8f9f7 92 DCD PININT2_IRQHandler ; PIO INT2
<> 144:ef7eb2e8f9f7 93 DCD PININT3_IRQHandler ; PIO INT3
<> 144:ef7eb2e8f9f7 94 DCD PININT4_IRQHandler ; PIO INT4
<> 144:ef7eb2e8f9f7 95 DCD PININT5_IRQHandler ; PIO INT5
<> 144:ef7eb2e8f9f7 96 DCD PININT6_IRQHandler ; PIO INT6
<> 144:ef7eb2e8f9f7 97 DCD PININT7_IRQHandler ; PIO INT7
<> 144:ef7eb2e8f9f7 98 __Vectors_End
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 __Vectors EQU __vector_table
<> 144:ef7eb2e8f9f7 101 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 104 ;;
<> 144:ef7eb2e8f9f7 105 ;; Default interrupt handlers.
<> 144:ef7eb2e8f9f7 106 ;;
<> 144:ef7eb2e8f9f7 107 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 THUMB
<> 144:ef7eb2e8f9f7 110 PUBWEAK Reset_Handler
<> 144:ef7eb2e8f9f7 111 SECTION .text:CODE:NOROOT:REORDER(2)
<> 144:ef7eb2e8f9f7 112 Reset_Handler
<> 144:ef7eb2e8f9f7 113 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 114 BLX R0
<> 144:ef7eb2e8f9f7 115 LDR R0, =__iar_program_start
<> 144:ef7eb2e8f9f7 116 BX R0
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 PUBWEAK NMI_Handler
<> 144:ef7eb2e8f9f7 119 PUBWEAK HardFault_Handler
<> 144:ef7eb2e8f9f7 120 PUBWEAK SVC_Handler
<> 144:ef7eb2e8f9f7 121 PUBWEAK PendSV_Handler
<> 144:ef7eb2e8f9f7 122 PUBWEAK SysTick_Handler
<> 144:ef7eb2e8f9f7 123 PUBWEAK SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 124 PUBWEAK SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 125 PUBWEAK UART0_IRQHandler
<> 144:ef7eb2e8f9f7 126 PUBWEAK UART1_IRQHandler
<> 144:ef7eb2e8f9f7 127 PUBWEAK UART2_IRQHandler
<> 144:ef7eb2e8f9f7 128 PUBWEAK I2C_IRQHandler
<> 144:ef7eb2e8f9f7 129 PUBWEAK SCT_IRQHandler
<> 144:ef7eb2e8f9f7 130 PUBWEAK MRT_IRQHandler
<> 144:ef7eb2e8f9f7 131 PUBWEAK CMP_IRQHandler
<> 144:ef7eb2e8f9f7 132 PUBWEAK WDT_IRQHandler
<> 144:ef7eb2e8f9f7 133 PUBWEAK BOD_IRQHandler
<> 144:ef7eb2e8f9f7 134 PUBWEAK WKT_IRQHandler
<> 144:ef7eb2e8f9f7 135 PUBWEAK PININT0_IRQHandler
<> 144:ef7eb2e8f9f7 136 PUBWEAK PININT1_IRQHandler
<> 144:ef7eb2e8f9f7 137 PUBWEAK PININT2_IRQHandler
<> 144:ef7eb2e8f9f7 138 PUBWEAK PININT3_IRQHandler
<> 144:ef7eb2e8f9f7 139 PUBWEAK PININT4_IRQHandler
<> 144:ef7eb2e8f9f7 140 PUBWEAK PININT5_IRQHandler
<> 144:ef7eb2e8f9f7 141 PUBWEAK PININT6_IRQHandler
<> 144:ef7eb2e8f9f7 142 PUBWEAK PININT7_IRQHandler
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 SECTION .text:CODE:REORDER:NOROOT(1)
<> 144:ef7eb2e8f9f7 145 THUMB
<> 144:ef7eb2e8f9f7 146 NMI_Handler
<> 144:ef7eb2e8f9f7 147 HardFault_Handler
<> 144:ef7eb2e8f9f7 148 SVC_Handler
<> 144:ef7eb2e8f9f7 149 PendSV_Handler
<> 144:ef7eb2e8f9f7 150 SysTick_Handler
<> 144:ef7eb2e8f9f7 151 SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 152 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 153 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 154 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 155 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 156 I2C_IRQHandler
<> 144:ef7eb2e8f9f7 157 SCT_IRQHandler
<> 144:ef7eb2e8f9f7 158 MRT_IRQHandler
<> 144:ef7eb2e8f9f7 159 CMP_IRQHandler
<> 144:ef7eb2e8f9f7 160 WDT_IRQHandler
<> 144:ef7eb2e8f9f7 161 BOD_IRQHandler
<> 144:ef7eb2e8f9f7 162 WKT_IRQHandler
<> 144:ef7eb2e8f9f7 163 PININT0_IRQHandler
<> 144:ef7eb2e8f9f7 164 PININT1_IRQHandler
<> 144:ef7eb2e8f9f7 165 PININT2_IRQHandler
<> 144:ef7eb2e8f9f7 166 PININT3_IRQHandler
<> 144:ef7eb2e8f9f7 167 PININT4_IRQHandler
<> 144:ef7eb2e8f9f7 168 PININT5_IRQHandler
<> 144:ef7eb2e8f9f7 169 PININT6_IRQHandler
<> 144:ef7eb2e8f9f7 170 PININT7_IRQHandler
<> 144:ef7eb2e8f9f7 171 Default_IRQHandler
<> 144:ef7eb2e8f9f7 172 B Default_IRQHandler
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 SECTION .crp:CODE:ROOT(2)
<> 144:ef7eb2e8f9f7 175 DATA
<> 144:ef7eb2e8f9f7 176 /* Code Read Protection
<> 144:ef7eb2e8f9f7 177 NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
<> 144:ef7eb2e8f9f7 178 CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
<> 144:ef7eb2e8f9f7 179 - Copy RAM to flash command can not write to Sector 0.
<> 144:ef7eb2e8f9f7 180 - Erase command can erase Sector 0 only when all sectors
<> 144:ef7eb2e8f9f7 181 are selected for erase.
<> 144:ef7eb2e8f9f7 182 - Compare command is disabled.
<> 144:ef7eb2e8f9f7 183 - Read Memory command is disabled.
<> 144:ef7eb2e8f9f7 184 CRP2 0x87654321 - Read Memory is disabled.
<> 144:ef7eb2e8f9f7 185 - Write to RAM is disabled.
<> 144:ef7eb2e8f9f7 186 - "Go" command is disabled.
<> 144:ef7eb2e8f9f7 187 - Copy RAM to flash is disabled.
<> 144:ef7eb2e8f9f7 188 - Compare is disabled.
<> 144:ef7eb2e8f9f7 189 CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
<> 144:ef7eb2e8f9f7 190 by pulling PIO0_1 LOW is disabled if a valid user code is
<> 144:ef7eb2e8f9f7 191 present in flash sector 0.
<> 144:ef7eb2e8f9f7 192 Caution: If CRP3 is selected, no future factory testing can be
<> 144:ef7eb2e8f9f7 193 performed on the device.
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 END