mbed library sources. Supersedes mbed-src.
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targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.S@148:4802eb17e82b, 2016-10-17 (annotated)
- Committer:
- rodriguise
- Date:
- Mon Oct 17 18:47:01 2016 +0000
- Revision:
- 148:4802eb17e82b
- Parent:
- 144:ef7eb2e8f9f7
backup
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* File: startup_ARMCM3.s |
<> | 144:ef7eb2e8f9f7 | 2 | * Purpose: startup file for Cortex-M3/M4 devices. Should use with |
<> | 144:ef7eb2e8f9f7 | 3 | * GNU Tools for ARM Embedded Processors |
<> | 144:ef7eb2e8f9f7 | 4 | * Version: V1.1 |
<> | 144:ef7eb2e8f9f7 | 5 | * Date: 17 June 2011 |
<> | 144:ef7eb2e8f9f7 | 6 | * |
<> | 144:ef7eb2e8f9f7 | 7 | * Copyright (C) 2011 ARM Limited. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 8 | * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 |
<> | 144:ef7eb2e8f9f7 | 9 | * processor based microcontrollers. This file can be freely distributed |
<> | 144:ef7eb2e8f9f7 | 10 | * within development tools that are supporting such ARM based processors. |
<> | 144:ef7eb2e8f9f7 | 11 | * |
<> | 144:ef7eb2e8f9f7 | 12 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
<> | 144:ef7eb2e8f9f7 | 13 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
<> | 144:ef7eb2e8f9f7 | 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
<> | 144:ef7eb2e8f9f7 | 15 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
<> | 144:ef7eb2e8f9f7 | 16 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
<> | 144:ef7eb2e8f9f7 | 17 | */ |
<> | 144:ef7eb2e8f9f7 | 18 | .syntax unified |
<> | 144:ef7eb2e8f9f7 | 19 | .arch armv7-m |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | /* Memory Model |
<> | 144:ef7eb2e8f9f7 | 22 | The HEAP starts at the end of the DATA section and grows upward. |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | The STACK starts at the end of the RAM and grows downward. |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | The HEAP and stack STACK are only checked at compile time: |
<> | 144:ef7eb2e8f9f7 | 27 | (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | This is just a check for the bare minimum for the Heap+Stack area before |
<> | 144:ef7eb2e8f9f7 | 30 | aborting compilation, it is not the run time limit: |
<> | 144:ef7eb2e8f9f7 | 31 | Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 |
<> | 144:ef7eb2e8f9f7 | 32 | */ |
<> | 144:ef7eb2e8f9f7 | 33 | .section .stack |
<> | 144:ef7eb2e8f9f7 | 34 | .align 3 |
<> | 144:ef7eb2e8f9f7 | 35 | #ifdef __STACK_SIZE |
<> | 144:ef7eb2e8f9f7 | 36 | .equ Stack_Size, __STACK_SIZE |
<> | 144:ef7eb2e8f9f7 | 37 | #else |
<> | 144:ef7eb2e8f9f7 | 38 | .equ Stack_Size, 0xc00 |
<> | 144:ef7eb2e8f9f7 | 39 | #endif |
<> | 144:ef7eb2e8f9f7 | 40 | .globl __StackTop |
<> | 144:ef7eb2e8f9f7 | 41 | .globl __StackLimit |
<> | 144:ef7eb2e8f9f7 | 42 | __StackLimit: |
<> | 144:ef7eb2e8f9f7 | 43 | .space Stack_Size |
<> | 144:ef7eb2e8f9f7 | 44 | .size __StackLimit, . - __StackLimit |
<> | 144:ef7eb2e8f9f7 | 45 | __StackTop: |
<> | 144:ef7eb2e8f9f7 | 46 | .size __StackTop, . - __StackTop |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | .section .heap |
<> | 144:ef7eb2e8f9f7 | 49 | .align 3 |
<> | 144:ef7eb2e8f9f7 | 50 | #ifdef __HEAP_SIZE |
<> | 144:ef7eb2e8f9f7 | 51 | .equ Heap_Size, __HEAP_SIZE |
<> | 144:ef7eb2e8f9f7 | 52 | #else |
<> | 144:ef7eb2e8f9f7 | 53 | .equ Heap_Size, 0x800 |
<> | 144:ef7eb2e8f9f7 | 54 | #endif |
<> | 144:ef7eb2e8f9f7 | 55 | .globl __HeapBase |
<> | 144:ef7eb2e8f9f7 | 56 | .globl __HeapLimit |
<> | 144:ef7eb2e8f9f7 | 57 | __HeapBase: |
<> | 144:ef7eb2e8f9f7 | 58 | .space Heap_Size |
<> | 144:ef7eb2e8f9f7 | 59 | .size __HeapBase, . - __HeapBase |
<> | 144:ef7eb2e8f9f7 | 60 | __HeapLimit: |
<> | 144:ef7eb2e8f9f7 | 61 | .size __HeapLimit, . - __HeapLimit |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | .section .isr_vector |
<> | 144:ef7eb2e8f9f7 | 64 | .align 2 |
<> | 144:ef7eb2e8f9f7 | 65 | .globl __isr_vector |
<> | 144:ef7eb2e8f9f7 | 66 | __isr_vector: |
<> | 144:ef7eb2e8f9f7 | 67 | .long __StackTop /* Top of Stack */ |
<> | 144:ef7eb2e8f9f7 | 68 | .long Reset_Handler /* Reset Handler */ |
<> | 144:ef7eb2e8f9f7 | 69 | .long NMI_Handler /* NMI Handler */ |
<> | 144:ef7eb2e8f9f7 | 70 | .long HardFault_Handler /* Hard Fault Handler */ |
<> | 144:ef7eb2e8f9f7 | 71 | .long MemManage_Handler /* MPU Fault Handler */ |
<> | 144:ef7eb2e8f9f7 | 72 | .long BusFault_Handler /* Bus Fault Handler */ |
<> | 144:ef7eb2e8f9f7 | 73 | .long UsageFault_Handler /* Usage Fault Handler */ |
<> | 144:ef7eb2e8f9f7 | 74 | .long 0 /* Reserved */ |
<> | 144:ef7eb2e8f9f7 | 75 | .long 0 /* Reserved */ |
<> | 144:ef7eb2e8f9f7 | 76 | .long 0 /* Reserved */ |
<> | 144:ef7eb2e8f9f7 | 77 | .long 0 /* Reserved */ |
<> | 144:ef7eb2e8f9f7 | 78 | .long SVC_Handler /* SVCall Handler */ |
<> | 144:ef7eb2e8f9f7 | 79 | .long DebugMon_Handler /* Debug Monitor Handler */ |
<> | 144:ef7eb2e8f9f7 | 80 | .long 0 /* Reserved */ |
<> | 144:ef7eb2e8f9f7 | 81 | .long PendSV_Handler /* PendSV Handler */ |
<> | 144:ef7eb2e8f9f7 | 82 | .long SysTick_Handler /* SysTick Handler */ |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 144:ef7eb2e8f9f7 | 84 | /* External interrupts */ |
<> | 144:ef7eb2e8f9f7 | 85 | .long WDT_IRQHandler /* 16: Watchdog Timer */ |
<> | 144:ef7eb2e8f9f7 | 86 | .long TIMER0_IRQHandler /* 17: Timer0 */ |
<> | 144:ef7eb2e8f9f7 | 87 | .long TIMER1_IRQHandler /* 18: Timer1 */ |
<> | 144:ef7eb2e8f9f7 | 88 | .long TIMER2_IRQHandler /* 19: Timer2 */ |
<> | 144:ef7eb2e8f9f7 | 89 | .long TIMER3_IRQHandler /* 20: Timer3 */ |
<> | 144:ef7eb2e8f9f7 | 90 | .long UART0_IRQHandler /* 21: UART0 */ |
<> | 144:ef7eb2e8f9f7 | 91 | .long UART1_IRQHandler /* 22: UART1 */ |
<> | 144:ef7eb2e8f9f7 | 92 | .long UART2_IRQHandler /* 23: UART2 */ |
<> | 144:ef7eb2e8f9f7 | 93 | .long UART3_IRQHandler /* 24: UART3 */ |
<> | 144:ef7eb2e8f9f7 | 94 | .long PWM1_IRQHandler /* 25: PWM1 */ |
<> | 144:ef7eb2e8f9f7 | 95 | .long I2C0_IRQHandler /* 26: I2C0 */ |
<> | 144:ef7eb2e8f9f7 | 96 | .long I2C1_IRQHandler /* 27: I2C1 */ |
<> | 144:ef7eb2e8f9f7 | 97 | .long I2C2_IRQHandler /* 28: I2C2 */ |
<> | 144:ef7eb2e8f9f7 | 98 | .long SPI_IRQHandler /* 29: SPI */ |
<> | 144:ef7eb2e8f9f7 | 99 | .long SSP0_IRQHandler /* 30: SSP0 */ |
<> | 144:ef7eb2e8f9f7 | 100 | .long SSP1_IRQHandler /* 31: SSP1 */ |
<> | 144:ef7eb2e8f9f7 | 101 | .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */ |
<> | 144:ef7eb2e8f9f7 | 102 | .long RTC_IRQHandler /* 33: Real Time Clock */ |
<> | 144:ef7eb2e8f9f7 | 103 | .long EINT0_IRQHandler /* 34: External Interrupt 0 */ |
<> | 144:ef7eb2e8f9f7 | 104 | .long EINT1_IRQHandler /* 35: External Interrupt 1 */ |
<> | 144:ef7eb2e8f9f7 | 105 | .long EINT2_IRQHandler /* 36: External Interrupt 2 */ |
<> | 144:ef7eb2e8f9f7 | 106 | .long EINT3_IRQHandler /* 37: External Interrupt 3 */ |
<> | 144:ef7eb2e8f9f7 | 107 | .long ADC_IRQHandler /* 38: A/D Converter */ |
<> | 144:ef7eb2e8f9f7 | 108 | .long BOD_IRQHandler /* 39: Brown-Out Detect */ |
<> | 144:ef7eb2e8f9f7 | 109 | .long USB_IRQHandler /* 40: USB */ |
<> | 144:ef7eb2e8f9f7 | 110 | .long CAN_IRQHandler /* 41: CAN */ |
<> | 144:ef7eb2e8f9f7 | 111 | .long DMA_IRQHandler /* 42: General Purpose DMA */ |
<> | 144:ef7eb2e8f9f7 | 112 | .long I2S_IRQHandler /* 43: I2S */ |
<> | 144:ef7eb2e8f9f7 | 113 | .long ENET_IRQHandler /* 44: Ethernet */ |
<> | 144:ef7eb2e8f9f7 | 114 | .long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */ |
<> | 144:ef7eb2e8f9f7 | 115 | .long MCPWM_IRQHandler /* 46: Motor Control PWM */ |
<> | 144:ef7eb2e8f9f7 | 116 | .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */ |
<> | 144:ef7eb2e8f9f7 | 117 | .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */ |
<> | 144:ef7eb2e8f9f7 | 118 | .long USBActivity_IRQHandler /* 49: USB Activity */ |
<> | 144:ef7eb2e8f9f7 | 119 | .long CANActivity_IRQHandler /* 50: CAN Activity */ |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | .size __isr_vector, . - __isr_vector |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | .text |
<> | 144:ef7eb2e8f9f7 | 124 | .thumb |
<> | 144:ef7eb2e8f9f7 | 125 | .thumb_func |
<> | 144:ef7eb2e8f9f7 | 126 | .align 2 |
<> | 144:ef7eb2e8f9f7 | 127 | .globl Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 128 | .type Reset_Handler, %function |
<> | 144:ef7eb2e8f9f7 | 129 | Reset_Handler: |
<> | 144:ef7eb2e8f9f7 | 130 | /* Loop to copy data from read only memory to RAM. The ranges |
<> | 144:ef7eb2e8f9f7 | 131 | * of copy from/to are specified by following symbols evaluated in |
<> | 144:ef7eb2e8f9f7 | 132 | * linker script. |
<> | 144:ef7eb2e8f9f7 | 133 | * _etext: End of code section, i.e., begin of data sections to copy from. |
<> | 144:ef7eb2e8f9f7 | 134 | * __data_start__/__data_end__: RAM address range that data should be |
<> | 144:ef7eb2e8f9f7 | 135 | * copied to. Both must be aligned to 4 bytes boundary. */ |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | ldr r1, =__etext |
<> | 144:ef7eb2e8f9f7 | 138 | ldr r2, =__data_start__ |
<> | 144:ef7eb2e8f9f7 | 139 | ldr r3, =__data_end__ |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | .Lflash_to_ram_loop: |
<> | 144:ef7eb2e8f9f7 | 142 | cmp r2, r3 |
<> | 144:ef7eb2e8f9f7 | 143 | ittt lt |
<> | 144:ef7eb2e8f9f7 | 144 | ldrlt r0, [r1], #4 |
<> | 144:ef7eb2e8f9f7 | 145 | strlt r0, [r2], #4 |
<> | 144:ef7eb2e8f9f7 | 146 | blt .Lflash_to_ram_loop |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | ldr r0, =SystemInit |
<> | 144:ef7eb2e8f9f7 | 149 | blx r0 |
<> | 144:ef7eb2e8f9f7 | 150 | ldr r0, =_start |
<> | 144:ef7eb2e8f9f7 | 151 | bx r0 |
<> | 144:ef7eb2e8f9f7 | 152 | .pool |
<> | 144:ef7eb2e8f9f7 | 153 | .size Reset_Handler, . - Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | .text |
<> | 144:ef7eb2e8f9f7 | 156 | /* Macro to define default handlers. Default handler |
<> | 144:ef7eb2e8f9f7 | 157 | * will be weak symbol and just dead loops. They can be |
<> | 144:ef7eb2e8f9f7 | 158 | * overwritten by other handlers */ |
<> | 144:ef7eb2e8f9f7 | 159 | .macro def_default_handler handler_name |
<> | 144:ef7eb2e8f9f7 | 160 | .align 1 |
<> | 144:ef7eb2e8f9f7 | 161 | .thumb_func |
<> | 144:ef7eb2e8f9f7 | 162 | .weak \handler_name |
<> | 144:ef7eb2e8f9f7 | 163 | .type \handler_name, %function |
<> | 144:ef7eb2e8f9f7 | 164 | \handler_name : |
<> | 144:ef7eb2e8f9f7 | 165 | b . |
<> | 144:ef7eb2e8f9f7 | 166 | .size \handler_name, . - \handler_name |
<> | 144:ef7eb2e8f9f7 | 167 | .endm |
<> | 144:ef7eb2e8f9f7 | 168 | |
<> | 144:ef7eb2e8f9f7 | 169 | def_default_handler NMI_Handler |
<> | 144:ef7eb2e8f9f7 | 170 | def_default_handler HardFault_Handler |
<> | 144:ef7eb2e8f9f7 | 171 | def_default_handler MemManage_Handler |
<> | 144:ef7eb2e8f9f7 | 172 | def_default_handler BusFault_Handler |
<> | 144:ef7eb2e8f9f7 | 173 | def_default_handler UsageFault_Handler |
<> | 144:ef7eb2e8f9f7 | 174 | def_default_handler SVC_Handler |
<> | 144:ef7eb2e8f9f7 | 175 | def_default_handler DebugMon_Handler |
<> | 144:ef7eb2e8f9f7 | 176 | def_default_handler PendSV_Handler |
<> | 144:ef7eb2e8f9f7 | 177 | def_default_handler SysTick_Handler |
<> | 144:ef7eb2e8f9f7 | 178 | def_default_handler Default_Handler |
<> | 144:ef7eb2e8f9f7 | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | .macro def_irq_default_handler handler_name |
<> | 144:ef7eb2e8f9f7 | 181 | .weak \handler_name |
<> | 144:ef7eb2e8f9f7 | 182 | .set \handler_name, Default_Handler |
<> | 144:ef7eb2e8f9f7 | 183 | .endm |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | def_irq_default_handler WDT_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 186 | def_irq_default_handler TIMER0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 187 | def_irq_default_handler TIMER1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 188 | def_irq_default_handler TIMER2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 189 | def_irq_default_handler TIMER3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 190 | def_irq_default_handler UART0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 191 | def_irq_default_handler UART1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 192 | def_irq_default_handler UART2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 193 | def_irq_default_handler UART3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 194 | def_irq_default_handler PWM1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 195 | def_irq_default_handler I2C0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 196 | def_irq_default_handler I2C1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 197 | def_irq_default_handler I2C2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 198 | def_irq_default_handler SPI_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 199 | def_irq_default_handler SSP0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 200 | def_irq_default_handler SSP1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 201 | def_irq_default_handler PLL0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 202 | def_irq_default_handler RTC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 203 | def_irq_default_handler EINT0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 204 | def_irq_default_handler EINT1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 205 | def_irq_default_handler EINT2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 206 | def_irq_default_handler EINT3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 207 | def_irq_default_handler ADC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 208 | def_irq_default_handler BOD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 209 | def_irq_default_handler USB_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 210 | def_irq_default_handler CAN_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 211 | def_irq_default_handler DMA_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 212 | def_irq_default_handler I2S_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 213 | def_irq_default_handler ENET_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 214 | def_irq_default_handler RIT_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 215 | def_irq_default_handler MCPWM_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 216 | def_irq_default_handler QEI_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 217 | def_irq_default_handler PLL1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 218 | def_irq_default_handler USBActivity_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 219 | def_irq_default_handler CANActivity_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 220 | def_irq_default_handler DEF_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | .end |
<> | 144:ef7eb2e8f9f7 | 223 |