teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/*****************************************************************************
<> 144:ef7eb2e8f9f7 2 ; * @file: startup_LPC17xx.s
<> 144:ef7eb2e8f9f7 3 ; * @purpose: CMSIS Cortex-M3 Core Device Startup File
<> 144:ef7eb2e8f9f7 4 ; * for the NXP LPC17xx Device Series
<> 144:ef7eb2e8f9f7 5 ; * @version: V1.02, modified for mbed
<> 144:ef7eb2e8f9f7 6 ; * @date: 27. July 2009, modified 3rd Aug 2009
<> 144:ef7eb2e8f9f7 7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 8 ; *
<> 144:ef7eb2e8f9f7 9 ; * Copyright (C) 2009 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
<> 144:ef7eb2e8f9f7 11 ; * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 12 ; * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 13 ; *
<> 144:ef7eb2e8f9f7 14 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 ; *
<> 144:ef7eb2e8f9f7 20 ; *****************************************************************************/
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 Stack_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 25 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 28 __initial_sp EQU 0x10008000 ; Top of RAM from LPC1768
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 Heap_Size EQU 0x00000000
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 34 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 35 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 __heap_base
<> 144:ef7eb2e8f9f7 38 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 39 __heap_limit
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 PRESERVE8
<> 144:ef7eb2e8f9f7 42 THUMB
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 47 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 50 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 51 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 52 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 53 DCD MemManage_Handler ; MPU Fault Handler
<> 144:ef7eb2e8f9f7 54 DCD BusFault_Handler ; Bus Fault Handler
<> 144:ef7eb2e8f9f7 55 DCD UsageFault_Handler ; Usage Fault Handler
<> 144:ef7eb2e8f9f7 56 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 57 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 58 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 59 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 60 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 61 DCD DebugMon_Handler ; Debug Monitor Handler
<> 144:ef7eb2e8f9f7 62 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 63 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 64 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 ; External Interrupts
<> 144:ef7eb2e8f9f7 67 DCD WDT_IRQHandler ; 16: Watchdog Timer
<> 144:ef7eb2e8f9f7 68 DCD TIMER0_IRQHandler ; 17: Timer0
<> 144:ef7eb2e8f9f7 69 DCD TIMER1_IRQHandler ; 18: Timer1
<> 144:ef7eb2e8f9f7 70 DCD TIMER2_IRQHandler ; 19: Timer2
<> 144:ef7eb2e8f9f7 71 DCD TIMER3_IRQHandler ; 20: Timer3
<> 144:ef7eb2e8f9f7 72 DCD UART0_IRQHandler ; 21: UART0
<> 144:ef7eb2e8f9f7 73 DCD UART1_IRQHandler ; 22: UART1
<> 144:ef7eb2e8f9f7 74 DCD UART2_IRQHandler ; 23: UART2
<> 144:ef7eb2e8f9f7 75 DCD UART3_IRQHandler ; 24: UART3
<> 144:ef7eb2e8f9f7 76 DCD PWM1_IRQHandler ; 25: PWM1
<> 144:ef7eb2e8f9f7 77 DCD I2C0_IRQHandler ; 26: I2C0
<> 144:ef7eb2e8f9f7 78 DCD I2C1_IRQHandler ; 27: I2C1
<> 144:ef7eb2e8f9f7 79 DCD I2C2_IRQHandler ; 28: I2C2
<> 144:ef7eb2e8f9f7 80 DCD SPI_IRQHandler ; 29: SPI
<> 144:ef7eb2e8f9f7 81 DCD SSP0_IRQHandler ; 30: SSP0
<> 144:ef7eb2e8f9f7 82 DCD SSP1_IRQHandler ; 31: SSP1
<> 144:ef7eb2e8f9f7 83 DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
<> 144:ef7eb2e8f9f7 84 DCD RTC_IRQHandler ; 33: Real Time Clock
<> 144:ef7eb2e8f9f7 85 DCD EINT0_IRQHandler ; 34: External Interrupt 0
<> 144:ef7eb2e8f9f7 86 DCD EINT1_IRQHandler ; 35: External Interrupt 1
<> 144:ef7eb2e8f9f7 87 DCD EINT2_IRQHandler ; 36: External Interrupt 2
<> 144:ef7eb2e8f9f7 88 DCD EINT3_IRQHandler ; 37: External Interrupt 3
<> 144:ef7eb2e8f9f7 89 DCD ADC_IRQHandler ; 38: A/D Converter
<> 144:ef7eb2e8f9f7 90 DCD BOD_IRQHandler ; 39: Brown-Out Detect
<> 144:ef7eb2e8f9f7 91 DCD USB_IRQHandler ; 40: USB
<> 144:ef7eb2e8f9f7 92 DCD CAN_IRQHandler ; 41: CAN
<> 144:ef7eb2e8f9f7 93 DCD DMA_IRQHandler ; 42: General Purpose DMA
<> 144:ef7eb2e8f9f7 94 DCD I2S_IRQHandler ; 43: I2S
<> 144:ef7eb2e8f9f7 95 DCD ENET_IRQHandler ; 44: Ethernet
<> 144:ef7eb2e8f9f7 96 DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
<> 144:ef7eb2e8f9f7 97 DCD MCPWM_IRQHandler ; 46: Motor Control PWM
<> 144:ef7eb2e8f9f7 98 DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
<> 144:ef7eb2e8f9f7 99 DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 IF :LNOT::DEF:NO_CRP
<> 144:ef7eb2e8f9f7 103 AREA |.ARM.__at_0x02FC|, CODE, READONLY
<> 144:ef7eb2e8f9f7 104 CRP_Key DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 105 ENDIF
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 ; Reset Handler
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 114 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 115 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 116 IMPORT __main
<> 144:ef7eb2e8f9f7 117 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 118 BLX R0
<> 144:ef7eb2e8f9f7 119 LDR R0, =__main
<> 144:ef7eb2e8f9f7 120 BX R0
<> 144:ef7eb2e8f9f7 121 ENDP
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 127 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 128 B .
<> 144:ef7eb2e8f9f7 129 ENDP
<> 144:ef7eb2e8f9f7 130 HardFault_Handler\
<> 144:ef7eb2e8f9f7 131 PROC
<> 144:ef7eb2e8f9f7 132 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 133 B .
<> 144:ef7eb2e8f9f7 134 ENDP
<> 144:ef7eb2e8f9f7 135 MemManage_Handler\
<> 144:ef7eb2e8f9f7 136 PROC
<> 144:ef7eb2e8f9f7 137 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 138 B .
<> 144:ef7eb2e8f9f7 139 ENDP
<> 144:ef7eb2e8f9f7 140 BusFault_Handler\
<> 144:ef7eb2e8f9f7 141 PROC
<> 144:ef7eb2e8f9f7 142 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 143 B .
<> 144:ef7eb2e8f9f7 144 ENDP
<> 144:ef7eb2e8f9f7 145 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 146 PROC
<> 144:ef7eb2e8f9f7 147 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 148 B .
<> 144:ef7eb2e8f9f7 149 ENDP
<> 144:ef7eb2e8f9f7 150 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 151 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 152 B .
<> 144:ef7eb2e8f9f7 153 ENDP
<> 144:ef7eb2e8f9f7 154 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 155 PROC
<> 144:ef7eb2e8f9f7 156 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 157 B .
<> 144:ef7eb2e8f9f7 158 ENDP
<> 144:ef7eb2e8f9f7 159 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 160 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 161 B .
<> 144:ef7eb2e8f9f7 162 ENDP
<> 144:ef7eb2e8f9f7 163 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 164 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 165 B .
<> 144:ef7eb2e8f9f7 166 ENDP
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 Default_Handler PROC
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 EXPORT WDT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 171 EXPORT TIMER0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 172 EXPORT TIMER1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 173 EXPORT TIMER2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 174 EXPORT TIMER3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 175 EXPORT UART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT UART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT UART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 178 EXPORT UART3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 179 EXPORT PWM1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 180 EXPORT I2C0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 181 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 182 EXPORT I2C2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 183 EXPORT SPI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 184 EXPORT SSP0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 185 EXPORT SSP1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 186 EXPORT PLL0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 187 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 188 EXPORT EINT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 189 EXPORT EINT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 190 EXPORT EINT2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 191 EXPORT EINT3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 192 EXPORT ADC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 193 EXPORT BOD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 194 EXPORT USB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 195 EXPORT CAN_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 196 EXPORT DMA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 197 EXPORT I2S_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 198 EXPORT ENET_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 199 EXPORT RIT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 200 EXPORT MCPWM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 201 EXPORT QEI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 202 EXPORT PLL1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 WDT_IRQHandler
<> 144:ef7eb2e8f9f7 205 TIMER0_IRQHandler
<> 144:ef7eb2e8f9f7 206 TIMER1_IRQHandler
<> 144:ef7eb2e8f9f7 207 TIMER2_IRQHandler
<> 144:ef7eb2e8f9f7 208 TIMER3_IRQHandler
<> 144:ef7eb2e8f9f7 209 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 210 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 211 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 212 UART3_IRQHandler
<> 144:ef7eb2e8f9f7 213 PWM1_IRQHandler
<> 144:ef7eb2e8f9f7 214 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 215 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 216 I2C2_IRQHandler
<> 144:ef7eb2e8f9f7 217 SPI_IRQHandler
<> 144:ef7eb2e8f9f7 218 SSP0_IRQHandler
<> 144:ef7eb2e8f9f7 219 SSP1_IRQHandler
<> 144:ef7eb2e8f9f7 220 PLL0_IRQHandler
<> 144:ef7eb2e8f9f7 221 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 222 EINT0_IRQHandler
<> 144:ef7eb2e8f9f7 223 EINT1_IRQHandler
<> 144:ef7eb2e8f9f7 224 EINT2_IRQHandler
<> 144:ef7eb2e8f9f7 225 EINT3_IRQHandler
<> 144:ef7eb2e8f9f7 226 ADC_IRQHandler
<> 144:ef7eb2e8f9f7 227 BOD_IRQHandler
<> 144:ef7eb2e8f9f7 228 USB_IRQHandler
<> 144:ef7eb2e8f9f7 229 CAN_IRQHandler
<> 144:ef7eb2e8f9f7 230 DMA_IRQHandler
<> 144:ef7eb2e8f9f7 231 I2S_IRQHandler
<> 144:ef7eb2e8f9f7 232 ENET_IRQHandler
<> 144:ef7eb2e8f9f7 233 RIT_IRQHandler
<> 144:ef7eb2e8f9f7 234 MCPWM_IRQHandler
<> 144:ef7eb2e8f9f7 235 QEI_IRQHandler
<> 144:ef7eb2e8f9f7 236 PLL1_IRQHandler
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 B .
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 ENDP
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 ALIGN
<> 144:ef7eb2e8f9f7 243 END