teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.S@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 ; * @file startup_LPC11U6x.s
<> 144:ef7eb2e8f9f7 3 ; * @brief CMSIS Cortex-M0+ Core Device Startup File for
<> 144:ef7eb2e8f9f7 4 ; * NXP LPC11U6x Device Series
<> 144:ef7eb2e8f9f7 5 ; * @version V1.00
<> 144:ef7eb2e8f9f7 6 ; * @date 22. October 2013
<> 144:ef7eb2e8f9f7 7 ; *
<> 144:ef7eb2e8f9f7 8 ; * @note
<> 144:ef7eb2e8f9f7 9 ; * Copyright (C) 2013 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 10 ; *
<> 144:ef7eb2e8f9f7 11 ; * @par
<> 144:ef7eb2e8f9f7 12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 144:ef7eb2e8f9f7 13 ; * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 14 ; * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 15 ; *
<> 144:ef7eb2e8f9f7 16 ; * @par
<> 144:ef7eb2e8f9f7 17 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 22 ; *
<> 144:ef7eb2e8f9f7 23 ; ******************************************************************************/
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 28 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 29 ; </h>
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 32 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 __initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 38 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 39 ; </h>
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 Heap_Size EQU 0x00000000
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 44 __heap_base
<> 144:ef7eb2e8f9f7 45 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 46 __heap_limit
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 PRESERVE8
<> 144:ef7eb2e8f9f7 50 THUMB
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 56 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 59 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 60 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 61 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 62 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 63 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 64 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 65 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 66 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 67 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 68 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 69 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 70 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 71 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 72 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 73 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 ; External Interrupts
<> 144:ef7eb2e8f9f7 76 DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
<> 144:ef7eb2e8f9f7 77 DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
<> 144:ef7eb2e8f9f7 78 DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
<> 144:ef7eb2e8f9f7 79 DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
<> 144:ef7eb2e8f9f7 80 DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
<> 144:ef7eb2e8f9f7 81 DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
<> 144:ef7eb2e8f9f7 82 DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
<> 144:ef7eb2e8f9f7 83 DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
<> 144:ef7eb2e8f9f7 84 DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
<> 144:ef7eb2e8f9f7 85 DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
<> 144:ef7eb2e8f9f7 86 DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
<> 144:ef7eb2e8f9f7 87 DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
<> 144:ef7eb2e8f9f7 88 DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
<> 144:ef7eb2e8f9f7 89 DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
<> 144:ef7eb2e8f9f7 90 DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
<> 144:ef7eb2e8f9f7 91 DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
<> 144:ef7eb2e8f9f7 92 DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
<> 144:ef7eb2e8f9f7 93 DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
<> 144:ef7eb2e8f9f7 94 DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
<> 144:ef7eb2e8f9f7 95 DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
<> 144:ef7eb2e8f9f7 96 DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
<> 144:ef7eb2e8f9f7 97 DCD USART0_IRQHandler ; 16+21 USART0 interrupt
<> 144:ef7eb2e8f9f7 98 DCD USB_IRQHandler ; 16+22 USB interrupt
<> 144:ef7eb2e8f9f7 99 DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
<> 144:ef7eb2e8f9f7 100 DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
<> 144:ef7eb2e8f9f7 101 DCD RTC_IRQHandler ; 16+25 RTC interrupt
<> 144:ef7eb2e8f9f7 102 DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
<> 144:ef7eb2e8f9f7 103 DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
<> 144:ef7eb2e8f9f7 104 DCD DMA_IRQHandler ; 16+28 DMA interrupt
<> 144:ef7eb2e8f9f7 105 DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
<> 144:ef7eb2e8f9f7 106 DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
<> 144:ef7eb2e8f9f7 107 DCD 0 ; 16+31 Reserved
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 ; <h> Code Read Protection
<> 144:ef7eb2e8f9f7 110 ; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
<> 144:ef7eb2e8f9f7 111 ; <0x12345678=>CRP Level 1
<> 144:ef7eb2e8f9f7 112 ; <0x87654321=>CRP Level 2
<> 144:ef7eb2e8f9f7 113 ; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
<> 144:ef7eb2e8f9f7 114 ; <0x4E697370=>NO ISP (ARE YOU SURE?)
<> 144:ef7eb2e8f9f7 115 ; </h>
<> 144:ef7eb2e8f9f7 116 IF :LNOT::DEF:NO_CRP
<> 144:ef7eb2e8f9f7 117 AREA |.ARM.__at_0x02FC|, CODE, READONLY
<> 144:ef7eb2e8f9f7 118 DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 119 ENDIF
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 ; Reset Handler
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 127 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 128 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 129 IMPORT __main
<> 144:ef7eb2e8f9f7 130 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 131 BLX R0
<> 144:ef7eb2e8f9f7 132 LDR R0, =__main
<> 144:ef7eb2e8f9f7 133 BX R0
<> 144:ef7eb2e8f9f7 134 ENDP
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 140 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 141 B .
<> 144:ef7eb2e8f9f7 142 ENDP
<> 144:ef7eb2e8f9f7 143 HardFault_Handler\
<> 144:ef7eb2e8f9f7 144 PROC
<> 144:ef7eb2e8f9f7 145 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 146 B .
<> 144:ef7eb2e8f9f7 147 ENDP
<> 144:ef7eb2e8f9f7 148 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 149 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 150 B .
<> 144:ef7eb2e8f9f7 151 ENDP
<> 144:ef7eb2e8f9f7 152 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 153 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 154 B .
<> 144:ef7eb2e8f9f7 155 ENDP
<> 144:ef7eb2e8f9f7 156 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 157 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 158 B .
<> 144:ef7eb2e8f9f7 159 ENDP
<> 144:ef7eb2e8f9f7 160 Reserved_IRQHandler PROC
<> 144:ef7eb2e8f9f7 161 EXPORT Reserved_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 B .
<> 144:ef7eb2e8f9f7 163 ENDP
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 Default_Handler PROC
<> 144:ef7eb2e8f9f7 166 EXPORT PIN_INT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 167 EXPORT PIN_INT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 168 EXPORT PIN_INT2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 169 EXPORT PIN_INT3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 170 EXPORT PIN_INT4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 171 EXPORT PIN_INT5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 172 EXPORT PIN_INT6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 173 EXPORT PIN_INT7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 174 EXPORT GINT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 175 EXPORT GINT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT USART1_4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 178 EXPORT USART2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 179 EXPORT SCT0_1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 180 EXPORT SSP1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 181 EXPORT I2C0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 182 EXPORT CT16B0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 183 EXPORT CT16B1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 184 EXPORT CT32B0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 185 EXPORT CT32B1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 186 EXPORT SSP0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 187 EXPORT USART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 188 EXPORT USB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 189 EXPORT USB_FIQ_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 190 EXPORT ADC_A_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 191 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 192 EXPORT BOD_WDT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 193 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 194 EXPORT DMA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 195 EXPORT ADC_B_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 196 EXPORT USBWAKEUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 PIN_INT0_IRQHandler
<> 144:ef7eb2e8f9f7 199 PIN_INT1_IRQHandler
<> 144:ef7eb2e8f9f7 200 PIN_INT2_IRQHandler
<> 144:ef7eb2e8f9f7 201 PIN_INT3_IRQHandler
<> 144:ef7eb2e8f9f7 202 PIN_INT4_IRQHandler
<> 144:ef7eb2e8f9f7 203 PIN_INT5_IRQHandler
<> 144:ef7eb2e8f9f7 204 PIN_INT6_IRQHandler
<> 144:ef7eb2e8f9f7 205 PIN_INT7_IRQHandler
<> 144:ef7eb2e8f9f7 206 GINT0_IRQHandler
<> 144:ef7eb2e8f9f7 207 GINT1_IRQHandler
<> 144:ef7eb2e8f9f7 208 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 209 USART1_4_IRQHandler
<> 144:ef7eb2e8f9f7 210 USART2_3_IRQHandler
<> 144:ef7eb2e8f9f7 211 SCT0_1_IRQHandler
<> 144:ef7eb2e8f9f7 212 SSP1_IRQHandler
<> 144:ef7eb2e8f9f7 213 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 214 CT16B0_IRQHandler
<> 144:ef7eb2e8f9f7 215 CT16B1_IRQHandler
<> 144:ef7eb2e8f9f7 216 CT32B0_IRQHandler
<> 144:ef7eb2e8f9f7 217 CT32B1_IRQHandler
<> 144:ef7eb2e8f9f7 218 SSP0_IRQHandler
<> 144:ef7eb2e8f9f7 219 USART0_IRQHandler
<> 144:ef7eb2e8f9f7 220 USB_IRQHandler
<> 144:ef7eb2e8f9f7 221 USB_FIQ_IRQHandler
<> 144:ef7eb2e8f9f7 222 ADC_A_IRQHandler
<> 144:ef7eb2e8f9f7 223 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 224 BOD_WDT_IRQHandler
<> 144:ef7eb2e8f9f7 225 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 226 DMA_IRQHandler
<> 144:ef7eb2e8f9f7 227 ADC_B_IRQHandler
<> 144:ef7eb2e8f9f7 228 USBWAKEUP_IRQHandler
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 B .
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 ENDP
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 ALIGN
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 ; User Initial Stack & Heap
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 241 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 242 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 END