teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ; mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 ; Copyright (c) 2013 Nordic Semiconductor.
<> 144:ef7eb2e8f9f7 3 ;Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 4 ;you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 5 ;You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 6 ;http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 7 ;Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 8 ;distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 9 ;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 10 ;See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 11 ;limitations under the License.
<> 144:ef7eb2e8f9f7 12
<> 144:ef7eb2e8f9f7 13 ; Description message
<> 144:ef7eb2e8f9f7 14
<> 144:ef7eb2e8f9f7 15 __initial_sp EQU 0x20008000
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 PRESERVE8
<> 144:ef7eb2e8f9f7 19 THUMB
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 24 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 25 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 26 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 29 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 30 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 31 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 32 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 33 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 34 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 35 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 36 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 37 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 38 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 39 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 40 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 41 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 42 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 43 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 ; External Interrupts
<> 144:ef7eb2e8f9f7 46 DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
<> 144:ef7eb2e8f9f7 47 DCD RADIO_IRQHandler ;RADIO
<> 144:ef7eb2e8f9f7 48 DCD UART0_IRQHandler ;UART0
<> 144:ef7eb2e8f9f7 49 DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
<> 144:ef7eb2e8f9f7 50 DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
<> 144:ef7eb2e8f9f7 51 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 52 DCD GPIOTE_IRQHandler ;GPIOTE
<> 144:ef7eb2e8f9f7 53 DCD ADC_IRQHandler ;ADC
<> 144:ef7eb2e8f9f7 54 DCD TIMER0_IRQHandler ;TIMER0
<> 144:ef7eb2e8f9f7 55 DCD TIMER1_IRQHandler ;TIMER1
<> 144:ef7eb2e8f9f7 56 DCD TIMER2_IRQHandler ;TIMER2
<> 144:ef7eb2e8f9f7 57 DCD RTC0_IRQHandler ;RTC0
<> 144:ef7eb2e8f9f7 58 DCD TEMP_IRQHandler ;TEMP
<> 144:ef7eb2e8f9f7 59 DCD RNG_IRQHandler ;RNG
<> 144:ef7eb2e8f9f7 60 DCD ECB_IRQHandler ;ECB
<> 144:ef7eb2e8f9f7 61 DCD CCM_AAR_IRQHandler ;CCM_AAR
<> 144:ef7eb2e8f9f7 62 DCD WDT_IRQHandler ;WDT
<> 144:ef7eb2e8f9f7 63 DCD RTC1_IRQHandler ;RTC1
<> 144:ef7eb2e8f9f7 64 DCD QDEC_IRQHandler ;QDEC
<> 144:ef7eb2e8f9f7 65 DCD LPCOMP_IRQHandler ;LPCOMP
<> 144:ef7eb2e8f9f7 66 DCD SWI0_IRQHandler ;SWI0
<> 144:ef7eb2e8f9f7 67 DCD SWI1_IRQHandler ;SWI1
<> 144:ef7eb2e8f9f7 68 DCD SWI2_IRQHandler ;SWI2
<> 144:ef7eb2e8f9f7 69 DCD SWI3_IRQHandler ;SWI3
<> 144:ef7eb2e8f9f7 70 DCD SWI4_IRQHandler ;SWI4
<> 144:ef7eb2e8f9f7 71 DCD SWI5_IRQHandler ;SWI5
<> 144:ef7eb2e8f9f7 72 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 73 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 74 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 75 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 76 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 77 DCD 0 ;Reserved
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 __Vectors_End
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 ; Reset Handler
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
<> 144:ef7eb2e8f9f7 89 NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address
<> 144:ef7eb2e8f9f7 90 NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 93 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 94 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 95 IMPORT __main
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 LDR R0, =NRF_POWER_RAMON_ADDRESS
<> 144:ef7eb2e8f9f7 100 LDR R2, [R0]
<> 144:ef7eb2e8f9f7 101 ORRS R2, R2, R1
<> 144:ef7eb2e8f9f7 102 STR R2, [R0]
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 LDR R0, =NRF_POWER_RAMONB_ADDRESS
<> 144:ef7eb2e8f9f7 105 LDR R2, [R0]
<> 144:ef7eb2e8f9f7 106 ORRS R2, R2, R1
<> 144:ef7eb2e8f9f7 107 STR R2, [R0]
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 110 BLX R0
<> 144:ef7eb2e8f9f7 111 LDR R0, =__main
<> 144:ef7eb2e8f9f7 112 BX R0
<> 144:ef7eb2e8f9f7 113 ENDP
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 118 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 119 B .
<> 144:ef7eb2e8f9f7 120 ENDP
<> 144:ef7eb2e8f9f7 121 HardFault_Handler\
<> 144:ef7eb2e8f9f7 122 PROC
<> 144:ef7eb2e8f9f7 123 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 124 B .
<> 144:ef7eb2e8f9f7 125 ENDP
<> 144:ef7eb2e8f9f7 126 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 127 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 128 B .
<> 144:ef7eb2e8f9f7 129 ENDP
<> 144:ef7eb2e8f9f7 130 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 131 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 132 B .
<> 144:ef7eb2e8f9f7 133 ENDP
<> 144:ef7eb2e8f9f7 134 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 135 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 136 B .
<> 144:ef7eb2e8f9f7 137 ENDP
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 Default_Handler PROC
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 EXPORT POWER_CLOCK_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 142 EXPORT RADIO_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 143 EXPORT UART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 144 EXPORT SPI0_TWI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 145 EXPORT SPI1_TWI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 146 EXPORT GPIOTE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 147 EXPORT ADC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 148 EXPORT TIMER0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 149 EXPORT TIMER1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 150 EXPORT TIMER2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 151 EXPORT RTC0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 152 EXPORT TEMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 153 EXPORT RNG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 154 EXPORT ECB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 155 EXPORT CCM_AAR_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 156 EXPORT WDT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 157 EXPORT RTC1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 158 EXPORT QDEC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 159 EXPORT LPCOMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 160 EXPORT SWI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 161 EXPORT SWI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 EXPORT SWI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 163 EXPORT SWI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 164 EXPORT SWI4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 165 EXPORT SWI5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 166 POWER_CLOCK_IRQHandler
<> 144:ef7eb2e8f9f7 167 RADIO_IRQHandler
<> 144:ef7eb2e8f9f7 168 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 169 SPI0_TWI0_IRQHandler
<> 144:ef7eb2e8f9f7 170 SPI1_TWI1_IRQHandler
<> 144:ef7eb2e8f9f7 171 GPIOTE_IRQHandler
<> 144:ef7eb2e8f9f7 172 ADC_IRQHandler
<> 144:ef7eb2e8f9f7 173 TIMER0_IRQHandler
<> 144:ef7eb2e8f9f7 174 TIMER1_IRQHandler
<> 144:ef7eb2e8f9f7 175 TIMER2_IRQHandler
<> 144:ef7eb2e8f9f7 176 RTC0_IRQHandler
<> 144:ef7eb2e8f9f7 177 TEMP_IRQHandler
<> 144:ef7eb2e8f9f7 178 RNG_IRQHandler
<> 144:ef7eb2e8f9f7 179 ECB_IRQHandler
<> 144:ef7eb2e8f9f7 180 CCM_AAR_IRQHandler
<> 144:ef7eb2e8f9f7 181 WDT_IRQHandler
<> 144:ef7eb2e8f9f7 182 RTC1_IRQHandler
<> 144:ef7eb2e8f9f7 183 QDEC_IRQHandler
<> 144:ef7eb2e8f9f7 184 LPCOMP_IRQHandler
<> 144:ef7eb2e8f9f7 185 SWI0_IRQHandler
<> 144:ef7eb2e8f9f7 186 SWI1_IRQHandler
<> 144:ef7eb2e8f9f7 187 SWI2_IRQHandler
<> 144:ef7eb2e8f9f7 188 SWI3_IRQHandler
<> 144:ef7eb2e8f9f7 189 SWI4_IRQHandler
<> 144:ef7eb2e8f9f7 190 SWI5_IRQHandler
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 B .
<> 144:ef7eb2e8f9f7 193 ENDP
<> 144:ef7eb2e8f9f7 194 ALIGN
<> 144:ef7eb2e8f9f7 195 END
<> 144:ef7eb2e8f9f7 196