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targets/cmsis/TARGET_Maxim/TARGET_MAX32620/wdt_regs.h@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

Who changed what in which revision?

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<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_WDT_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_WDT_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*
<> 144:ef7eb2e8f9f7 44 If types are not defined elsewhere (CMSIS) define them here
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 #ifndef __IO
<> 144:ef7eb2e8f9f7 47 #define __IO volatile
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 #ifndef __I
<> 144:ef7eb2e8f9f7 50 #define __I volatile const
<> 144:ef7eb2e8f9f7 51 #endif
<> 144:ef7eb2e8f9f7 52 #ifndef __O
<> 144:ef7eb2e8f9f7 53 #define __O volatile
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*
<> 144:ef7eb2e8f9f7 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 144:ef7eb2e8f9f7 59 access to each register in module.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Offset Register Description
<> 144:ef7eb2e8f9f7 63 ============= ============================================================================ */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t clear; /* 0x0004 Watchdog Timer Clear Register (Feed Dog) */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t flags; /* 0x0008 Watchdog Timer Interrupt and Reset Flags */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t enable; /* 0x000C Watchdog Timer Interrupt/Reset Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 69 __I uint32_t rsv010; /* 0x0010 */
<> 144:ef7eb2e8f9f7 70 __IO uint32_t lock_ctrl; /* 0x0014 Watchdog Timer Register Setting Lock for Control Register */
<> 144:ef7eb2e8f9f7 71 } mxc_wdt_regs_t;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /*
<> 144:ef7eb2e8f9f7 75 Register offsets for module WDT.
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 #define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 79 #define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 80 #define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 81 #define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 82 #define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /*
<> 144:ef7eb2e8f9f7 86 Field positions and masks for module WDT.
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0
<> 144:ef7eb2e8f9f7 90 #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 91 #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4
<> 144:ef7eb2e8f9f7 92 #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 93 #define MXC_F_WDT_CTRL_EN_TIMER_POS 8
<> 144:ef7eb2e8f9f7 94 #define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
<> 144:ef7eb2e8f9f7 95 #define MXC_F_WDT_CTRL_EN_CLOCK_POS 9
<> 144:ef7eb2e8f9f7 96 #define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
<> 144:ef7eb2e8f9f7 97 #define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12
<> 144:ef7eb2e8f9f7 98 #define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 #define MXC_F_WDT_FLAGS_TIMEOUT_POS 0
<> 144:ef7eb2e8f9f7 101 #define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 102 #define MXC_F_WDT_FLAGS_PRE_WIN_POS 1
<> 144:ef7eb2e8f9f7 103 #define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
<> 144:ef7eb2e8f9f7 104 #define MXC_F_WDT_FLAGS_RESET_OUT_POS 2
<> 144:ef7eb2e8f9f7 105 #define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define MXC_F_WDT_ENABLE_TIMEOUT_POS 0
<> 144:ef7eb2e8f9f7 108 #define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 109 #define MXC_F_WDT_ENABLE_PRE_WIN_POS 1
<> 144:ef7eb2e8f9f7 110 #define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
<> 144:ef7eb2e8f9f7 111 #define MXC_F_WDT_ENABLE_RESET_OUT_POS 2
<> 144:ef7eb2e8f9f7 112 #define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0
<> 144:ef7eb2e8f9f7 115 #define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /*
<> 144:ef7eb2e8f9f7 120 Field values and shifted values for module WDT.
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 #define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 124 #define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 125 #define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 126 #define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 127 #define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 128 #define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 129 #define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL))
<> 144:ef7eb2e8f9f7 130 #define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL))
<> 144:ef7eb2e8f9f7 131 #define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL))
<> 144:ef7eb2e8f9f7 132 #define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL))
<> 144:ef7eb2e8f9f7 133 #define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL))
<> 144:ef7eb2e8f9f7 134 #define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL))
<> 144:ef7eb2e8f9f7 135 #define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL))
<> 144:ef7eb2e8f9f7 136 #define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL))
<> 144:ef7eb2e8f9f7 137 #define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL))
<> 144:ef7eb2e8f9f7 138 #define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL))
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 141 #define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 142 #define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 143 #define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 144 #define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 145 #define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 146 #define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 147 #define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 148 #define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 149 #define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 150 #define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 151 #define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 152 #define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 153 #define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 154 #define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 155 #define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 158 #define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 159 #define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 160 #define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 161 #define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 162 #define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 163 #define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL))
<> 144:ef7eb2e8f9f7 164 #define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL))
<> 144:ef7eb2e8f9f7 165 #define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL))
<> 144:ef7eb2e8f9f7 166 #define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL))
<> 144:ef7eb2e8f9f7 167 #define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL))
<> 144:ef7eb2e8f9f7 168 #define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL))
<> 144:ef7eb2e8f9f7 169 #define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL))
<> 144:ef7eb2e8f9f7 170 #define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL))
<> 144:ef7eb2e8f9f7 171 #define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL))
<> 144:ef7eb2e8f9f7 172 #define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL))
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 175 #define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 176 #define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 177 #define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 178 #define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 179 #define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 180 #define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 181 #define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 182 #define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 183 #define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 184 #define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 185 #define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 186 #define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 187 #define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 188 #define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 189 #define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 192 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 193 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 194 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 195 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 196 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 197 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL))
<> 144:ef7eb2e8f9f7 198 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL))
<> 144:ef7eb2e8f9f7 199 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL))
<> 144:ef7eb2e8f9f7 200 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL))
<> 144:ef7eb2e8f9f7 201 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL))
<> 144:ef7eb2e8f9f7 202 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL))
<> 144:ef7eb2e8f9f7 203 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL))
<> 144:ef7eb2e8f9f7 204 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL))
<> 144:ef7eb2e8f9f7 205 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL))
<> 144:ef7eb2e8f9f7 206 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL))
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 209 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 210 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 211 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 212 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 213 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 214 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 215 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 216 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 217 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 218 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 219 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 220 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 221 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 222 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 223 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 #define MXC_V_WDT_LOCK_KEY 0x24
<> 144:ef7eb2e8f9f7 227 #define MXC_V_WDT_UNLOCK_KEY 0x42
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 #define MXC_V_WDT_RESET_KEY_0 0xA5
<> 144:ef7eb2e8f9f7 230 #define MXC_V_WDT_RESET_KEY_1 0x5A
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 #endif
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #endif /* _MXC_WDT_REGS_H_ */
<> 144:ef7eb2e8f9f7 238