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targets/cmsis/TARGET_Maxim/TARGET_MAX32620/rtc_regs.h@148:4802eb17e82b, 2016-10-17 (annotated)

Committer:
rodriguise
Date:
Mon Oct 17 18:47:01 2016 +0000
Revision:
148:4802eb17e82b
Parent:
144:ef7eb2e8f9f7 
backup

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UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_RTC_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_RTC_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*
<> 144:ef7eb2e8f9f7 44 If types are not defined elsewhere (CMSIS) define them here
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 #ifndef __IO
<> 144:ef7eb2e8f9f7 47 #define __IO volatile
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 #ifndef __I
<> 144:ef7eb2e8f9f7 50 #define __I volatile const
<> 144:ef7eb2e8f9f7 51 #endif
<> 144:ef7eb2e8f9f7 52 #ifndef __O
<> 144:ef7eb2e8f9f7 53 #define __O volatile
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*
<> 144:ef7eb2e8f9f7 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 144:ef7eb2e8f9f7 59 access to each register in module.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Offset Register Description
<> 144:ef7eb2e8f9f7 63 ============= ============================================================================ */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t comp[2]; /* 0x0008-0x000C RTC Time of Day Alarm [0..1] Compare Register */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t snz_val; /* 0x0014 RTC Timer Alarm Snooze Value */
<> 144:ef7eb2e8f9f7 70 __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */
<> 144:ef7eb2e8f9f7 71 __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */
<> 144:ef7eb2e8f9f7 72 __I uint32_t rsv020; /* 0x0020 */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */
<> 144:ef7eb2e8f9f7 76 } mxc_rtctmr_regs_t;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Offset Register Description
<> 144:ef7eb2e8f9f7 80 ============= ============================================================================ */
<> 144:ef7eb2e8f9f7 81 typedef struct {
<> 144:ef7eb2e8f9f7 82 __IO uint32_t nano_cntr; /* 0x0000 Nano Oscillator Counter Read Register */
<> 144:ef7eb2e8f9f7 83 __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */
<> 144:ef7eb2e8f9f7 84 __I uint32_t rsv008; /* 0x0008 */
<> 144:ef7eb2e8f9f7 85 __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */
<> 144:ef7eb2e8f9f7 86 } mxc_rtccfg_regs_t;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /*
<> 144:ef7eb2e8f9f7 90 Register offsets for module RTC.
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 94 #define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 95 #define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 96 #define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 97 #define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 98 #define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 99 #define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 100 #define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 101 #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 102 #define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL)
<> 144:ef7eb2e8f9f7 103 #define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL)
<> 144:ef7eb2e8f9f7 104 #define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 105 #define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 106 #define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /*
<> 144:ef7eb2e8f9f7 110 Field positions and masks for module RTC.
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #define MXC_F_RTC_CTRL_ENABLE_POS 0
<> 144:ef7eb2e8f9f7 114 #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
<> 144:ef7eb2e8f9f7 115 #define MXC_F_RTC_CTRL_CLEAR_POS 1
<> 144:ef7eb2e8f9f7 116 #define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
<> 144:ef7eb2e8f9f7 117 #define MXC_F_RTC_CTRL_PENDING_POS 2
<> 144:ef7eb2e8f9f7 118 #define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
<> 144:ef7eb2e8f9f7 119 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3
<> 144:ef7eb2e8f9f7 120 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
<> 144:ef7eb2e8f9f7 121 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4
<> 144:ef7eb2e8f9f7 122 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
<> 144:ef7eb2e8f9f7 123 #define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5
<> 144:ef7eb2e8f9f7 124 #define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS))
<> 144:ef7eb2e8f9f7 125 #define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6
<> 144:ef7eb2e8f9f7 126 #define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS))
<> 144:ef7eb2e8f9f7 127 #define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16
<> 144:ef7eb2e8f9f7 128 #define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 129 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17
<> 144:ef7eb2e8f9f7 130 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 131 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18
<> 144:ef7eb2e8f9f7 132 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 133 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19
<> 144:ef7eb2e8f9f7 134 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 135 #define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20
<> 144:ef7eb2e8f9f7 136 #define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 137 #define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21
<> 144:ef7eb2e8f9f7 138 #define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 139 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22
<> 144:ef7eb2e8f9f7 140 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 141 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23
<> 144:ef7eb2e8f9f7 142 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 143 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24
<> 144:ef7eb2e8f9f7 144 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 145 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25
<> 144:ef7eb2e8f9f7 146 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 147 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26
<> 144:ef7eb2e8f9f7 148 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 149 #define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27
<> 144:ef7eb2e8f9f7 150 #define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 151 #define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28
<> 144:ef7eb2e8f9f7 152 #define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 153 #define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29
<> 144:ef7eb2e8f9f7 154 #define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 155 #define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30
<> 144:ef7eb2e8f9f7 156 #define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS))
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 #define MXC_F_RTC_FLAGS_COMP0_POS 0
<> 144:ef7eb2e8f9f7 159 #define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
<> 144:ef7eb2e8f9f7 160 #define MXC_F_RTC_FLAGS_COMP1_POS 1
<> 144:ef7eb2e8f9f7 161 #define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
<> 144:ef7eb2e8f9f7 162 #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2
<> 144:ef7eb2e8f9f7 163 #define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
<> 144:ef7eb2e8f9f7 164 #define MXC_F_RTC_FLAGS_OVERFLOW_POS 3
<> 144:ef7eb2e8f9f7 165 #define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
<> 144:ef7eb2e8f9f7 166 #define MXC_F_RTC_FLAGS_TRIM_POS 4
<> 144:ef7eb2e8f9f7 167 #define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
<> 144:ef7eb2e8f9f7 168 #define MXC_F_RTC_FLAGS_SNOOZE_POS 5
<> 144:ef7eb2e8f9f7 169 #define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS))
<> 144:ef7eb2e8f9f7 170 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8
<> 144:ef7eb2e8f9f7 171 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 172 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9
<> 144:ef7eb2e8f9f7 173 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 174 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10
<> 144:ef7eb2e8f9f7 175 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 176 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11
<> 144:ef7eb2e8f9f7 177 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 178 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12
<> 144:ef7eb2e8f9f7 179 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 180 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31
<> 144:ef7eb2e8f9f7 181 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #define MXC_F_RTC_SNZ_VAL_VALUE_POS 0
<> 144:ef7eb2e8f9f7 184 #define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS))
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #define MXC_F_RTC_INTEN_COMP0_POS 0
<> 144:ef7eb2e8f9f7 187 #define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
<> 144:ef7eb2e8f9f7 188 #define MXC_F_RTC_INTEN_COMP1_POS 1
<> 144:ef7eb2e8f9f7 189 #define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
<> 144:ef7eb2e8f9f7 190 #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2
<> 144:ef7eb2e8f9f7 191 #define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
<> 144:ef7eb2e8f9f7 192 #define MXC_F_RTC_INTEN_OVERFLOW_POS 3
<> 144:ef7eb2e8f9f7 193 #define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
<> 144:ef7eb2e8f9f7 194 #define MXC_F_RTC_INTEN_TRIM_POS 4
<> 144:ef7eb2e8f9f7 195 #define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 #define MXC_F_RTC_PRESCALE_PRESCALE_POS 0
<> 144:ef7eb2e8f9f7 198 #define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS))
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 #define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0
<> 144:ef7eb2e8f9f7 201 #define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS))
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0
<> 144:ef7eb2e8f9f7 204 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
<> 144:ef7eb2e8f9f7 205 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1
<> 144:ef7eb2e8f9f7 206 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
<> 144:ef7eb2e8f9f7 207 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2
<> 144:ef7eb2e8f9f7 208 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0
<> 144:ef7eb2e8f9f7 211 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
<> 144:ef7eb2e8f9f7 212 #define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18
<> 144:ef7eb2e8f9f7 213 #define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS))
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0
<> 144:ef7eb2e8f9f7 216 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0
<> 144:ef7eb2e8f9f7 219 #define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
<> 144:ef7eb2e8f9f7 220 #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1
<> 144:ef7eb2e8f9f7 221 #define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
<> 144:ef7eb2e8f9f7 222 #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2
<> 144:ef7eb2e8f9f7 223 #define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0
<> 144:ef7eb2e8f9f7 226 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
<> 144:ef7eb2e8f9f7 227 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1
<> 144:ef7eb2e8f9f7 228 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
<> 144:ef7eb2e8f9f7 229 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2
<> 144:ef7eb2e8f9f7 230 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
<> 144:ef7eb2e8f9f7 231 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3
<> 144:ef7eb2e8f9f7 232 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238 #endif
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 #endif /* _MXC_RTC_REGS_H_ */
<> 144:ef7eb2e8f9f7 241