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targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c@119:3921aeca8633, 2016-04-29 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Apr 29 01:15:11 2016 +0100
- Revision:
- 119:3921aeca8633
Synchronized with git revision fe9720f24b1adc71ab6962506ec51290f6afd270
Full URL: https://github.com/mbedmicro/mbed/commit/fe9720f24b1adc71ab6962506ec51290f6afd270/
[Renesas RZ/A1H] Enable asynchronous communications
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 119:3921aeca8633 | 1 | /* mbed Microcontroller Library |
mbed_official | 119:3921aeca8633 | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 119:3921aeca8633 | 3 | * |
mbed_official | 119:3921aeca8633 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 119:3921aeca8633 | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 119:3921aeca8633 | 6 | * You may obtain a copy of the License at |
mbed_official | 119:3921aeca8633 | 7 | * |
mbed_official | 119:3921aeca8633 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 119:3921aeca8633 | 9 | * |
mbed_official | 119:3921aeca8633 | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 119:3921aeca8633 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 119:3921aeca8633 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 119:3921aeca8633 | 13 | * See the License for the specific language governing permissions and |
mbed_official | 119:3921aeca8633 | 14 | * limitations under the License. |
mbed_official | 119:3921aeca8633 | 15 | */ |
mbed_official | 119:3921aeca8633 | 16 | #include "mbed_assert.h" |
mbed_official | 119:3921aeca8633 | 17 | #include <math.h> |
mbed_official | 119:3921aeca8633 | 18 | |
mbed_official | 119:3921aeca8633 | 19 | #include "spi_api.h" |
mbed_official | 119:3921aeca8633 | 20 | #include "cmsis.h" |
mbed_official | 119:3921aeca8633 | 21 | #include "pinmap.h" |
mbed_official | 119:3921aeca8633 | 22 | #include "mbed_error.h" |
mbed_official | 119:3921aeca8633 | 23 | #include "RZ_A1_Init.h" |
mbed_official | 119:3921aeca8633 | 24 | |
mbed_official | 119:3921aeca8633 | 25 | |
mbed_official | 119:3921aeca8633 | 26 | #ifdef MAX_PERI |
mbed_official | 119:3921aeca8633 | 27 | static const PinMap PinMap_SPI_SCLK[] = { |
mbed_official | 119:3921aeca8633 | 28 | {P2_12 , SPI_0, 2}, |
mbed_official | 119:3921aeca8633 | 29 | {P7_15 , SPI_0, 2}, |
mbed_official | 119:3921aeca8633 | 30 | {P4_4 , SPI_1, 2}, |
mbed_official | 119:3921aeca8633 | 31 | {P6_4 , SPI_1, 7}, |
mbed_official | 119:3921aeca8633 | 32 | {P8_3 , SPI_2, 3}, |
mbed_official | 119:3921aeca8633 | 33 | {P8_14 , SPI_2, 5}, |
mbed_official | 119:3921aeca8633 | 34 | {P3_0 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 35 | {P5_0 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 36 | {P2_8 , SPI_4, 8}, |
mbed_official | 119:3921aeca8633 | 37 | {P4_0 , SPI_4, 7}, |
mbed_official | 119:3921aeca8633 | 38 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 39 | }; |
mbed_official | 119:3921aeca8633 | 40 | |
mbed_official | 119:3921aeca8633 | 41 | static const PinMap PinMap_SPI_SSEL[] = { |
mbed_official | 119:3921aeca8633 | 42 | {P2_13 , SPI_0, 2}, |
mbed_official | 119:3921aeca8633 | 43 | {P8_0 , SPI_0, 2}, |
mbed_official | 119:3921aeca8633 | 44 | {P4_5 , SPI_1, 2}, |
mbed_official | 119:3921aeca8633 | 45 | {P6_5 , SPI_1, 7}, |
mbed_official | 119:3921aeca8633 | 46 | {P8_4 , SPI_2, 3}, |
mbed_official | 119:3921aeca8633 | 47 | {P8_15 , SPI_2, 5}, |
mbed_official | 119:3921aeca8633 | 48 | {P3_1 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 49 | {P5_1 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 50 | {P2_9 , SPI_4, 8}, |
mbed_official | 119:3921aeca8633 | 51 | {P4_1 , SPI_4, 7}, |
mbed_official | 119:3921aeca8633 | 52 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 53 | }; |
mbed_official | 119:3921aeca8633 | 54 | |
mbed_official | 119:3921aeca8633 | 55 | static const PinMap PinMap_SPI_MOSI[] = { |
mbed_official | 119:3921aeca8633 | 56 | {P2_14 , SPI_0, 2}, |
mbed_official | 119:3921aeca8633 | 57 | {P8_1 , SPI_0, 2}, |
mbed_official | 119:3921aeca8633 | 58 | {P4_6 , SPI_1, 2}, |
mbed_official | 119:3921aeca8633 | 59 | {P6_6 , SPI_1, 7}, |
mbed_official | 119:3921aeca8633 | 60 | {P8_5 , SPI_2, 3}, |
mbed_official | 119:3921aeca8633 | 61 | {P9_0 , SPI_2, 5}, |
mbed_official | 119:3921aeca8633 | 62 | {P3_2 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 63 | {P5_2 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 64 | {P2_10 , SPI_4, 8}, |
mbed_official | 119:3921aeca8633 | 65 | {P4_2 , SPI_4, 7}, |
mbed_official | 119:3921aeca8633 | 66 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 67 | }; |
mbed_official | 119:3921aeca8633 | 68 | |
mbed_official | 119:3921aeca8633 | 69 | static const PinMap PinMap_SPI_MISO[] = { |
mbed_official | 119:3921aeca8633 | 70 | {P2_15 , SPI_0, 2}, |
mbed_official | 119:3921aeca8633 | 71 | {P8_2 , SPI_0, 2}, |
mbed_official | 119:3921aeca8633 | 72 | {P4_7 , SPI_1, 2}, |
mbed_official | 119:3921aeca8633 | 73 | {P6_7 , SPI_1, 7}, |
mbed_official | 119:3921aeca8633 | 74 | {P8_6 , SPI_2, 3}, |
mbed_official | 119:3921aeca8633 | 75 | {P9_1 , SPI_2, 5}, |
mbed_official | 119:3921aeca8633 | 76 | {P3_3 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 77 | {P5_3 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 78 | {P2_11 , SPI_4, 8}, |
mbed_official | 119:3921aeca8633 | 79 | {P4_3 , SPI_4, 7}, |
mbed_official | 119:3921aeca8633 | 80 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 81 | }; |
mbed_official | 119:3921aeca8633 | 82 | #else |
mbed_official | 119:3921aeca8633 | 83 | static const PinMap PinMap_SPI_SCLK[] = { |
mbed_official | 119:3921aeca8633 | 84 | {P4_4 , SPI_1, 2}, |
mbed_official | 119:3921aeca8633 | 85 | {P8_14 , SPI_2, 5}, |
mbed_official | 119:3921aeca8633 | 86 | {P5_0 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 87 | {P4_0 , SPI_4, 7}, |
mbed_official | 119:3921aeca8633 | 88 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 89 | }; |
mbed_official | 119:3921aeca8633 | 90 | |
mbed_official | 119:3921aeca8633 | 91 | static const PinMap PinMap_SPI_SSEL[] = { |
mbed_official | 119:3921aeca8633 | 92 | {P4_5 , SPI_1, 2}, |
mbed_official | 119:3921aeca8633 | 93 | {P8_15 , SPI_2, 5}, |
mbed_official | 119:3921aeca8633 | 94 | {P5_1 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 95 | {P4_1 , SPI_4, 7}, |
mbed_official | 119:3921aeca8633 | 96 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 97 | }; |
mbed_official | 119:3921aeca8633 | 98 | |
mbed_official | 119:3921aeca8633 | 99 | static const PinMap PinMap_SPI_MOSI[] = { |
mbed_official | 119:3921aeca8633 | 100 | {P4_6 , SPI_1, 2}, |
mbed_official | 119:3921aeca8633 | 101 | {P9_0 , SPI_2, 5}, |
mbed_official | 119:3921aeca8633 | 102 | {P5_2 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 103 | {P4_2 , SPI_4, 7}, |
mbed_official | 119:3921aeca8633 | 104 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 105 | }; |
mbed_official | 119:3921aeca8633 | 106 | |
mbed_official | 119:3921aeca8633 | 107 | static const PinMap PinMap_SPI_MISO[] = { |
mbed_official | 119:3921aeca8633 | 108 | {P4_7 , SPI_1, 2}, |
mbed_official | 119:3921aeca8633 | 109 | {P9_1 , SPI_2, 5}, |
mbed_official | 119:3921aeca8633 | 110 | {P5_3 , SPI_3, 8}, |
mbed_official | 119:3921aeca8633 | 111 | {P4_3 , SPI_4, 7}, |
mbed_official | 119:3921aeca8633 | 112 | {NC , NC , 0} |
mbed_official | 119:3921aeca8633 | 113 | }; |
mbed_official | 119:3921aeca8633 | 114 | #endif |
mbed_official | 119:3921aeca8633 | 115 | |
mbed_official | 119:3921aeca8633 | 116 | |
mbed_official | 119:3921aeca8633 | 117 | static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST; |
mbed_official | 119:3921aeca8633 | 118 | |
mbed_official | 119:3921aeca8633 | 119 | static inline void spi_disable(spi_t *obj); |
mbed_official | 119:3921aeca8633 | 120 | static inline void spi_enable(spi_t *obj); |
mbed_official | 119:3921aeca8633 | 121 | static inline int spi_readable(spi_t *obj); |
mbed_official | 119:3921aeca8633 | 122 | static inline void spi_write(spi_t *obj, int value); |
mbed_official | 119:3921aeca8633 | 123 | static inline int spi_read(spi_t *obj); |
mbed_official | 119:3921aeca8633 | 124 | |
mbed_official | 119:3921aeca8633 | 125 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { |
mbed_official | 119:3921aeca8633 | 126 | // determine the SPI to use |
mbed_official | 119:3921aeca8633 | 127 | volatile uint8_t dummy; |
mbed_official | 119:3921aeca8633 | 128 | uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
mbed_official | 119:3921aeca8633 | 129 | uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); |
mbed_official | 119:3921aeca8633 | 130 | uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
mbed_official | 119:3921aeca8633 | 131 | uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
mbed_official | 119:3921aeca8633 | 132 | uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); |
mbed_official | 119:3921aeca8633 | 133 | uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); |
mbed_official | 119:3921aeca8633 | 134 | uint32_t spi = pinmap_merge(spi_data, spi_cntl); |
mbed_official | 119:3921aeca8633 | 135 | |
mbed_official | 119:3921aeca8633 | 136 | MBED_ASSERT((int)spi != NC); |
mbed_official | 119:3921aeca8633 | 137 | |
mbed_official | 119:3921aeca8633 | 138 | obj->spi = (struct st_rspi *)RSPI[spi]; |
mbed_official | 119:3921aeca8633 | 139 | |
mbed_official | 119:3921aeca8633 | 140 | // enable power and clocking |
mbed_official | 119:3921aeca8633 | 141 | switch (spi) { |
mbed_official | 119:3921aeca8633 | 142 | case SPI_1: CPGSTBCR10 &= ~(0x40); break; |
mbed_official | 119:3921aeca8633 | 143 | case SPI_2: CPGSTBCR10 &= ~(0x20); break; |
mbed_official | 119:3921aeca8633 | 144 | case SPI_3: CPGSTBCR10 &= ~(0x10); break; |
mbed_official | 119:3921aeca8633 | 145 | case SPI_4: CPGSTBCR10 &= ~(0x08); break; |
mbed_official | 119:3921aeca8633 | 146 | } |
mbed_official | 119:3921aeca8633 | 147 | dummy = CPGSTBCR10; |
mbed_official | 119:3921aeca8633 | 148 | |
mbed_official | 119:3921aeca8633 | 149 | obj->spi->SPCR = 0x00; // CTRL to 0 |
mbed_official | 119:3921aeca8633 | 150 | obj->spi->SPSCR = 0x00; // no sequential operation |
mbed_official | 119:3921aeca8633 | 151 | obj->spi->SSLP = 0x00; // SSL 'L' active |
mbed_official | 119:3921aeca8633 | 152 | obj->spi->SPDCR = 0x20; // byte access |
mbed_official | 119:3921aeca8633 | 153 | obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK |
mbed_official | 119:3921aeca8633 | 154 | obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK |
mbed_official | 119:3921aeca8633 | 155 | obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK |
mbed_official | 119:3921aeca8633 | 156 | obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0 |
mbed_official | 119:3921aeca8633 | 157 | obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1 |
mbed_official | 119:3921aeca8633 | 158 | obj->spi->SPBFCR = 0x30; // and reset buffer |
mbed_official | 119:3921aeca8633 | 159 | |
mbed_official | 119:3921aeca8633 | 160 | // pin out the spi pins |
mbed_official | 119:3921aeca8633 | 161 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
mbed_official | 119:3921aeca8633 | 162 | pinmap_pinout(miso, PinMap_SPI_MISO); |
mbed_official | 119:3921aeca8633 | 163 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
mbed_official | 119:3921aeca8633 | 164 | if ((int)ssel != NC) { |
mbed_official | 119:3921aeca8633 | 165 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
mbed_official | 119:3921aeca8633 | 166 | } |
mbed_official | 119:3921aeca8633 | 167 | } |
mbed_official | 119:3921aeca8633 | 168 | |
mbed_official | 119:3921aeca8633 | 169 | void spi_free(spi_t *obj) {} |
mbed_official | 119:3921aeca8633 | 170 | |
mbed_official | 119:3921aeca8633 | 171 | void spi_format(spi_t *obj, int bits, int mode, int slave) { |
mbed_official | 119:3921aeca8633 | 172 | int DSS; // DSS (data select size) |
mbed_official | 119:3921aeca8633 | 173 | int polarity = (mode & 0x2) ? 1 : 0; |
mbed_official | 119:3921aeca8633 | 174 | int phase = (mode & 0x1) ? 1 : 0; |
mbed_official | 119:3921aeca8633 | 175 | uint16_t tmp = 0; |
mbed_official | 119:3921aeca8633 | 176 | uint16_t mask = 0xf03; |
mbed_official | 119:3921aeca8633 | 177 | uint16_t wk_spcmd0; |
mbed_official | 119:3921aeca8633 | 178 | uint8_t splw; |
mbed_official | 119:3921aeca8633 | 179 | |
mbed_official | 119:3921aeca8633 | 180 | switch (mode) { |
mbed_official | 119:3921aeca8633 | 181 | case 0: |
mbed_official | 119:3921aeca8633 | 182 | case 1: |
mbed_official | 119:3921aeca8633 | 183 | case 2: |
mbed_official | 119:3921aeca8633 | 184 | case 3: |
mbed_official | 119:3921aeca8633 | 185 | // Do Nothing |
mbed_official | 119:3921aeca8633 | 186 | break; |
mbed_official | 119:3921aeca8633 | 187 | default: |
mbed_official | 119:3921aeca8633 | 188 | error("SPI format error"); |
mbed_official | 119:3921aeca8633 | 189 | return; |
mbed_official | 119:3921aeca8633 | 190 | } |
mbed_official | 119:3921aeca8633 | 191 | |
mbed_official | 119:3921aeca8633 | 192 | switch (bits) { |
mbed_official | 119:3921aeca8633 | 193 | case 8: |
mbed_official | 119:3921aeca8633 | 194 | DSS = 0x7; |
mbed_official | 119:3921aeca8633 | 195 | splw = 0x20; |
mbed_official | 119:3921aeca8633 | 196 | break; |
mbed_official | 119:3921aeca8633 | 197 | case 16: |
mbed_official | 119:3921aeca8633 | 198 | DSS = 0xf; |
mbed_official | 119:3921aeca8633 | 199 | splw = 0x40; |
mbed_official | 119:3921aeca8633 | 200 | break; |
mbed_official | 119:3921aeca8633 | 201 | case 32: |
mbed_official | 119:3921aeca8633 | 202 | DSS = 0x2; |
mbed_official | 119:3921aeca8633 | 203 | splw = 0x60; |
mbed_official | 119:3921aeca8633 | 204 | break; |
mbed_official | 119:3921aeca8633 | 205 | default: |
mbed_official | 119:3921aeca8633 | 206 | error("SPI module don't support other than 8/16/32bits"); |
mbed_official | 119:3921aeca8633 | 207 | return; |
mbed_official | 119:3921aeca8633 | 208 | } |
mbed_official | 119:3921aeca8633 | 209 | tmp |= phase; |
mbed_official | 119:3921aeca8633 | 210 | tmp |= (polarity << 1); |
mbed_official | 119:3921aeca8633 | 211 | tmp |= (DSS << 8); |
mbed_official | 119:3921aeca8633 | 212 | obj->bits = bits; |
mbed_official | 119:3921aeca8633 | 213 | |
mbed_official | 119:3921aeca8633 | 214 | spi_disable(obj); |
mbed_official | 119:3921aeca8633 | 215 | wk_spcmd0 = obj->spi->SPCMD0; |
mbed_official | 119:3921aeca8633 | 216 | wk_spcmd0 &= ~mask; |
mbed_official | 119:3921aeca8633 | 217 | wk_spcmd0 |= (mask & tmp); |
mbed_official | 119:3921aeca8633 | 218 | obj->spi->SPCMD0 = wk_spcmd0; |
mbed_official | 119:3921aeca8633 | 219 | obj->spi->SPDCR = splw; |
mbed_official | 119:3921aeca8633 | 220 | if (slave) { |
mbed_official | 119:3921aeca8633 | 221 | obj->spi->SPCR &=~(1 << 3); // MSTR to 0 |
mbed_official | 119:3921aeca8633 | 222 | } else { |
mbed_official | 119:3921aeca8633 | 223 | obj->spi->SPCR |= (1 << 3); // MSTR to 1 |
mbed_official | 119:3921aeca8633 | 224 | } |
mbed_official | 119:3921aeca8633 | 225 | spi_enable(obj); |
mbed_official | 119:3921aeca8633 | 226 | } |
mbed_official | 119:3921aeca8633 | 227 | |
mbed_official | 119:3921aeca8633 | 228 | void spi_frequency(spi_t *obj, int hz) { |
mbed_official | 119:3921aeca8633 | 229 | uint32_t pclk_base; |
mbed_official | 119:3921aeca8633 | 230 | uint32_t div; |
mbed_official | 119:3921aeca8633 | 231 | uint32_t brdv = 0; |
mbed_official | 119:3921aeca8633 | 232 | uint32_t hz_max; |
mbed_official | 119:3921aeca8633 | 233 | uint32_t hz_min; |
mbed_official | 119:3921aeca8633 | 234 | uint16_t mask = 0x000c; |
mbed_official | 119:3921aeca8633 | 235 | uint16_t wk_spcmd0; |
mbed_official | 119:3921aeca8633 | 236 | |
mbed_official | 119:3921aeca8633 | 237 | /* set PCLK */ |
mbed_official | 119:3921aeca8633 | 238 | if (RZ_A1_IsClockMode0() == false) { |
mbed_official | 119:3921aeca8633 | 239 | pclk_base = CM1_RENESAS_RZ_A1_P1_CLK; |
mbed_official | 119:3921aeca8633 | 240 | } else { |
mbed_official | 119:3921aeca8633 | 241 | pclk_base = CM0_RENESAS_RZ_A1_P1_CLK; |
mbed_official | 119:3921aeca8633 | 242 | } |
mbed_official | 119:3921aeca8633 | 243 | |
mbed_official | 119:3921aeca8633 | 244 | hz_min = pclk_base / 2 / 256 / 8; |
mbed_official | 119:3921aeca8633 | 245 | hz_max = pclk_base / 2; |
mbed_official | 119:3921aeca8633 | 246 | if ((hz < hz_min) || (hz > hz_max)) { |
mbed_official | 119:3921aeca8633 | 247 | error("Couldn't setup requested SPI frequency"); |
mbed_official | 119:3921aeca8633 | 248 | return; |
mbed_official | 119:3921aeca8633 | 249 | } |
mbed_official | 119:3921aeca8633 | 250 | |
mbed_official | 119:3921aeca8633 | 251 | div = (pclk_base / hz / 2); |
mbed_official | 119:3921aeca8633 | 252 | while (div > 256) { |
mbed_official | 119:3921aeca8633 | 253 | div >>= 1; |
mbed_official | 119:3921aeca8633 | 254 | brdv++; |
mbed_official | 119:3921aeca8633 | 255 | } |
mbed_official | 119:3921aeca8633 | 256 | div -= 1; |
mbed_official | 119:3921aeca8633 | 257 | brdv = (brdv << 2); |
mbed_official | 119:3921aeca8633 | 258 | |
mbed_official | 119:3921aeca8633 | 259 | spi_disable(obj); |
mbed_official | 119:3921aeca8633 | 260 | obj->spi->SPBR = div; |
mbed_official | 119:3921aeca8633 | 261 | wk_spcmd0 = obj->spi->SPCMD0; |
mbed_official | 119:3921aeca8633 | 262 | wk_spcmd0 &= ~mask; |
mbed_official | 119:3921aeca8633 | 263 | wk_spcmd0 |= (mask & brdv); |
mbed_official | 119:3921aeca8633 | 264 | obj->spi->SPCMD0 = wk_spcmd0; |
mbed_official | 119:3921aeca8633 | 265 | spi_enable(obj); |
mbed_official | 119:3921aeca8633 | 266 | } |
mbed_official | 119:3921aeca8633 | 267 | |
mbed_official | 119:3921aeca8633 | 268 | static inline void spi_disable(spi_t *obj) { |
mbed_official | 119:3921aeca8633 | 269 | obj->spi->SPCR &= ~(1 << 6); // SPE to 0 |
mbed_official | 119:3921aeca8633 | 270 | } |
mbed_official | 119:3921aeca8633 | 271 | |
mbed_official | 119:3921aeca8633 | 272 | static inline void spi_enable(spi_t *obj) { |
mbed_official | 119:3921aeca8633 | 273 | obj->spi->SPCR |= (1 << 6); // SPE to 1 |
mbed_official | 119:3921aeca8633 | 274 | } |
mbed_official | 119:3921aeca8633 | 275 | |
mbed_official | 119:3921aeca8633 | 276 | static inline int spi_readable(spi_t *obj) { |
mbed_official | 119:3921aeca8633 | 277 | return obj->spi->SPSR & (1 << 7); // SPRF |
mbed_official | 119:3921aeca8633 | 278 | } |
mbed_official | 119:3921aeca8633 | 279 | |
mbed_official | 119:3921aeca8633 | 280 | static inline int spi_tend(spi_t *obj) { |
mbed_official | 119:3921aeca8633 | 281 | return obj->spi->SPSR & (1 << 6); // TEND |
mbed_official | 119:3921aeca8633 | 282 | } |
mbed_official | 119:3921aeca8633 | 283 | |
mbed_official | 119:3921aeca8633 | 284 | static inline void spi_write(spi_t *obj, int value) { |
mbed_official | 119:3921aeca8633 | 285 | if (obj->bits == 8) { |
mbed_official | 119:3921aeca8633 | 286 | obj->spi->SPDR.UINT8[0] = (uint8_t)value; |
mbed_official | 119:3921aeca8633 | 287 | } else if (obj->bits == 16) { |
mbed_official | 119:3921aeca8633 | 288 | obj->spi->SPDR.UINT16[0] = (uint16_t)value; |
mbed_official | 119:3921aeca8633 | 289 | } else { |
mbed_official | 119:3921aeca8633 | 290 | obj->spi->SPDR.UINT32 = (uint32_t)value; |
mbed_official | 119:3921aeca8633 | 291 | } |
mbed_official | 119:3921aeca8633 | 292 | } |
mbed_official | 119:3921aeca8633 | 293 | |
mbed_official | 119:3921aeca8633 | 294 | static inline int spi_read(spi_t *obj) { |
mbed_official | 119:3921aeca8633 | 295 | int read_data; |
mbed_official | 119:3921aeca8633 | 296 | |
mbed_official | 119:3921aeca8633 | 297 | if (obj->bits == 8) { |
mbed_official | 119:3921aeca8633 | 298 | read_data = obj->spi->SPDR.UINT8[0]; |
mbed_official | 119:3921aeca8633 | 299 | } else if (obj->bits == 16) { |
mbed_official | 119:3921aeca8633 | 300 | read_data = obj->spi->SPDR.UINT16[0]; |
mbed_official | 119:3921aeca8633 | 301 | } else { |
mbed_official | 119:3921aeca8633 | 302 | read_data = obj->spi->SPDR.UINT32; |
mbed_official | 119:3921aeca8633 | 303 | } |
mbed_official | 119:3921aeca8633 | 304 | |
mbed_official | 119:3921aeca8633 | 305 | return read_data; |
mbed_official | 119:3921aeca8633 | 306 | } |
mbed_official | 119:3921aeca8633 | 307 | |
mbed_official | 119:3921aeca8633 | 308 | int spi_master_write(spi_t *obj, int value) { |
mbed_official | 119:3921aeca8633 | 309 | spi_write(obj, value); |
mbed_official | 119:3921aeca8633 | 310 | while(!spi_tend(obj)); |
mbed_official | 119:3921aeca8633 | 311 | return spi_read(obj); |
mbed_official | 119:3921aeca8633 | 312 | } |
mbed_official | 119:3921aeca8633 | 313 | |
mbed_official | 119:3921aeca8633 | 314 | int spi_slave_receive(spi_t *obj) { |
mbed_official | 119:3921aeca8633 | 315 | return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0); |
mbed_official | 119:3921aeca8633 | 316 | } |
mbed_official | 119:3921aeca8633 | 317 | |
mbed_official | 119:3921aeca8633 | 318 | int spi_slave_read(spi_t *obj) { |
mbed_official | 119:3921aeca8633 | 319 | return spi_read(obj); |
mbed_official | 119:3921aeca8633 | 320 | } |
mbed_official | 119:3921aeca8633 | 321 | |
mbed_official | 119:3921aeca8633 | 322 | void spi_slave_write(spi_t *obj, int value) { |
mbed_official | 119:3921aeca8633 | 323 | spi_write(obj, value); |
mbed_official | 119:3921aeca8633 | 324 | } |
mbed_official | 119:3921aeca8633 | 325 | |
mbed_official | 119:3921aeca8633 | 326 | int spi_busy(spi_t *obj) { |
mbed_official | 119:3921aeca8633 | 327 | return 0; |
mbed_official | 119:3921aeca8633 | 328 | } |