teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c@147:30b64687e01f, 2016-09-16 (annotated)

Committer:
<>
Date:
Fri Sep 16 16:24:25 2016 +0100
Revision:
147:30b64687e01f
Parent:
144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v126

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file us_ticker_api.h
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a Timer driver
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-11-15 $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup timer
<> 144:ef7eb2e8f9f7 28 */
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 #include <stddef.h>
<> 144:ef7eb2e8f9f7 31 #include "timer.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #define US_TIMER TIMER0
<> 144:ef7eb2e8f9f7 34 #define US_TICKER TIMER1
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 static int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 static void us_timer_init(void);
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 static uint32_t us_ticker_int_counter = 0;
<> 144:ef7eb2e8f9f7 41 static volatile uint32_t msb_counter = 0;
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 void us_ticker_init(void)
<> 144:ef7eb2e8f9f7 44 {
<> 144:ef7eb2e8f9f7 45 if (!us_ticker_inited) {
<> 144:ef7eb2e8f9f7 46 us_timer_init();
<> 144:ef7eb2e8f9f7 47 }
<> 144:ef7eb2e8f9f7 48 }
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /*******************************************************************************
<> 144:ef7eb2e8f9f7 51 * Timer for us timing reference
<> 144:ef7eb2e8f9f7 52 *
<> 144:ef7eb2e8f9f7 53 * Uptime counter for scheduling reference. It uses TIMER0.
<> 144:ef7eb2e8f9f7 54 * The NCS36510 does not have a 32 bit timer nor the option to chain timers,
<> 144:ef7eb2e8f9f7 55 * which is why a software timer is required to get 32-bit word length.
<> 144:ef7eb2e8f9f7 56 ******************************************************************************/
<> 144:ef7eb2e8f9f7 57 /* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */
<> 144:ef7eb2e8f9f7 58 /* TODO - Add msb_counter rollover protection at 16 bits count? */
<> 144:ef7eb2e8f9f7 59 /* TODO - How is overflow handled? */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Timer 0 for free running time */
<> 144:ef7eb2e8f9f7 62 extern void us_timer_isr(void)
<> 144:ef7eb2e8f9f7 63 {
<> 144:ef7eb2e8f9f7 64 TIM0REG->CLEAR = 0;
<> 144:ef7eb2e8f9f7 65 msb_counter++;
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /* Initializing TIMER 0(TImer) and TIMER 1(Ticker) */
<> 144:ef7eb2e8f9f7 69 static void us_timer_init(void)
<> 144:ef7eb2e8f9f7 70 {
<> 144:ef7eb2e8f9f7 71 /* Enable the timer0 periphery clock */
<> 144:ef7eb2e8f9f7 72 CLOCK_ENABLE(CLOCK_TIMER0);
<> 144:ef7eb2e8f9f7 73 /* Enable the timer0 periphery clock */
<> 144:ef7eb2e8f9f7 74 CLOCK_ENABLE(CLOCK_TIMER1);
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /* Timer init */
<> 144:ef7eb2e8f9f7 77 /* load timer value */
<> 144:ef7eb2e8f9f7 78 TIM0REG->LOAD = 0xFFFF;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* set timer prescale 32 (1 us), mode & enable */
<> 144:ef7eb2e8f9f7 81 TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
<> 144:ef7eb2e8f9f7 82 (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) |
<> 144:ef7eb2e8f9f7 83 (TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS));
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* Ticker init */
<> 144:ef7eb2e8f9f7 86 /* load timer value */
<> 144:ef7eb2e8f9f7 87 TIM1REG->LOAD = 0xFFFF;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /* set timer prescale 32 (1 us), mode & enable */
<> 144:ef7eb2e8f9f7 90 TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
<> 144:ef7eb2e8f9f7 91 (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS));
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* Register & enable interrupt associated with the timer */
<> 144:ef7eb2e8f9f7 94 NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr);
<> 144:ef7eb2e8f9f7 95 NVIC_SetVector(Tim1_IRQn,(uint32_t)us_ticker_isr);
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Clear pending irqs */
<> 144:ef7eb2e8f9f7 98 NVIC_ClearPendingIRQ(Tim0_IRQn);
<> 144:ef7eb2e8f9f7 99 NVIC_ClearPendingIRQ(Tim1_IRQn);
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* Setup NVIC for timer */
<> 144:ef7eb2e8f9f7 102 NVIC_EnableIRQ(Tim0_IRQn);
<> 144:ef7eb2e8f9f7 103 NVIC_EnableIRQ(Tim1_IRQn);
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* Reads 32 bit timer's current value (16 bit s/w timer | 16 bit h/w timer) */
<> 144:ef7eb2e8f9f7 109 uint32_t us_ticker_read()
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 uint32_t retval, tim0cval;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 if (!us_ticker_inited) {
<> 144:ef7eb2e8f9f7 114 us_timer_init();
<> 144:ef7eb2e8f9f7 115 }
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Get the current tick from the hw and sw timers */
<> 144:ef7eb2e8f9f7 118 tim0cval = TIM0REG->VALUE; /* read current time */
<> 144:ef7eb2e8f9f7 119 retval = (0xFFFF - tim0cval); /* subtract down count */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 NVIC_DisableIRQ(Tim0_IRQn);
<> 144:ef7eb2e8f9f7 122 if (TIM0REG->CONTROL.BITS.INT) {
<> 144:ef7eb2e8f9f7 123 TIM0REG->CLEAR = 0;
<> 144:ef7eb2e8f9f7 124 msb_counter++;
<> 144:ef7eb2e8f9f7 125 tim0cval = TIM0REG->VALUE; /* read current time again after interrupt */
<> 144:ef7eb2e8f9f7 126 retval = (0xFFFF - tim0cval);
<> 144:ef7eb2e8f9f7 127 }
<> 144:ef7eb2e8f9f7 128 retval |= msb_counter << 16; /* add software bits */
<> 144:ef7eb2e8f9f7 129 NVIC_EnableIRQ(Tim0_IRQn);
<> 144:ef7eb2e8f9f7 130 return retval;
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /*******************************************************************************
<> 144:ef7eb2e8f9f7 134 * Event Timer
<> 144:ef7eb2e8f9f7 135 *
<> 144:ef7eb2e8f9f7 136 * Schedules interrupts at given (32bit)us interval of time. It uses TIMER1.
<> 144:ef7eb2e8f9f7 137 * The NCS36510 does not have a 32 bit timer nor the option to chain timers,
<> 144:ef7eb2e8f9f7 138 * which is why a software timer is required to get 32-bit word length.
<> 144:ef7eb2e8f9f7 139 *******************************************************************************/
<> 144:ef7eb2e8f9f7 140 /* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* TImer 1 disbale interrupt */
<> 144:ef7eb2e8f9f7 143 void us_ticker_disable_interrupt(void)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 /* Disable the TIMER1 interrupt */
<> 144:ef7eb2e8f9f7 146 TIM1REG->CONTROL.BITS.ENABLE = 0x0;
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* TImer 1 clear interrupt */
<> 144:ef7eb2e8f9f7 150 void us_ticker_clear_interrupt(void)
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 /* Clear the Ticker (TIMER1) interrupt */
<> 144:ef7eb2e8f9f7 153 TIM1REG->CLEAR = 0;
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Setting TImer 1 (ticker) */
<> 144:ef7eb2e8f9f7 157 inline static void ticker_set(uint32_t count)
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 /* Disable TIMER1, load the new value, and re-enable */
<> 144:ef7eb2e8f9f7 160 TIM1REG->CONTROL.BITS.ENABLE = 0;
<> 144:ef7eb2e8f9f7 161 TIM1REG->LOAD = count;
<> 144:ef7eb2e8f9f7 162 TIM1REG->CONTROL.BITS.ENABLE = 1;
<> 144:ef7eb2e8f9f7 163 }
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* TImer 1 - ticker ISR */
<> 144:ef7eb2e8f9f7 166 extern void us_ticker_isr(void)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 /* Clear IRQ flag */
<> 144:ef7eb2e8f9f7 169 TIM1REG->CLEAR = 0;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* If this is a longer timer it will take multiple full hw counter cycles */
<> 144:ef7eb2e8f9f7 172 if (us_ticker_int_counter > 0) {
<> 144:ef7eb2e8f9f7 173 ticker_set(0xFFFF);
<> 144:ef7eb2e8f9f7 174 us_ticker_int_counter--;
<> 144:ef7eb2e8f9f7 175 } else {
<> 144:ef7eb2e8f9f7 176 TIM1REG->CONTROL.BITS.ENABLE = False;
<> 144:ef7eb2e8f9f7 177 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Set timer 1 ticker interrupt */
<> 144:ef7eb2e8f9f7 182 void us_ticker_set_interrupt(timestamp_t timestamp)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 int32_t delta = (uint32_t)timestamp - us_ticker_read();
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 if (delta <= 0) {
<> 144:ef7eb2e8f9f7 187 /* This event was in the past */
<> 144:ef7eb2e8f9f7 188 //us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 189 // This event was in the past.
<> 144:ef7eb2e8f9f7 190 // Set the interrupt as pending, but don't process it here.
<> 144:ef7eb2e8f9f7 191 // This prevents a recurive loop under heavy load
<> 144:ef7eb2e8f9f7 192 // which can lead to a stack overflow.
<> 144:ef7eb2e8f9f7 193 NVIC_SetPendingIRQ(Tim1_IRQn);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 return;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Calculate how much delta falls outside the 16-bit counter range. */
<> 144:ef7eb2e8f9f7 199 /* You will have to perform a full timer overflow for each bit above */
<> 144:ef7eb2e8f9f7 200 /* that range. */
<> 144:ef7eb2e8f9f7 201 us_ticker_int_counter = (uint32_t)(delta >> 16);
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 ticker_set(delta);
<> 144:ef7eb2e8f9f7 204 }