teralytic / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed by teralytic

targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c@76:2aa1c040b668, 2016-02-29 (annotated)

Committer:
mbed_official
Date:
Mon Feb 29 07:15:09 2016 +0000
Revision:
76:2aa1c040b668
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 08f4e17d695dae8bf945bcb506d81399fc42b732



Full URL: https://github.com/mbedmicro/mbed/commit/08f4e17d695dae8bf945bcb506d81399fc42b732/



[LPC15XX] Fix Clock Configuration

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file system_LPC15xx.c
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M3 Device System Source File for
bogdanm 0:9b334a45a8ff 4 * NXP LPC15xx Device Series
bogdanm 0:9b334a45a8ff 5 * @version V1.00
bogdanm 0:9b334a45a8ff 6 * @date 19. July 2013
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * @note
bogdanm 0:9b334a45a8ff 9 * Copyright (C) 2013 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * @par
bogdanm 0:9b334a45a8ff 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 0:9b334a45a8ff 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 14 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * @par
bogdanm 0:9b334a45a8ff 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 ******************************************************************************/
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 #include <stdint.h>
bogdanm 0:9b334a45a8ff 27 #include "LPC15xx.h"
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 /*
bogdanm 0:9b334a45a8ff 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 0:9b334a45a8ff 31 */
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 /*- SystemCoreClock Configuration -------------------------------------------*/
bogdanm 0:9b334a45a8ff 34 // <e0> SystemCoreClock Configuration
bogdanm 0:9b334a45a8ff 35 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 36 //
bogdanm 0:9b334a45a8ff 37 // <h> System Oscillator Control (SYSOSCCTRL)
bogdanm 0:9b334a45a8ff 38 // <o.0> BYPASS: System Oscillator Bypass Enable
bogdanm 0:9b334a45a8ff 39 // <i> If enabled then PLL input (sys_osc_clk) is fed
bogdanm 0:9b334a45a8ff 40 // <i> directly from XTALIN and XTALOUT pins.
bogdanm 0:9b334a45a8ff 41 // <o.1> FREQRANGE: System Oscillator Frequency Range
bogdanm 0:9b334a45a8ff 42 // <i> Determines frequency range for Low-power oscillator.
bogdanm 0:9b334a45a8ff 43 // <0=> 1 - 20 MHz
bogdanm 0:9b334a45a8ff 44 // <1=> 15 - 25 MHz
bogdanm 0:9b334a45a8ff 45 // </h>
bogdanm 0:9b334a45a8ff 46 #define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 47 //
bogdanm 0:9b334a45a8ff 48 // <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
bogdanm 0:9b334a45a8ff 49 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 50 // <1=> Crystal Oscillator (SYSOSC)
bogdanm 0:9b334a45a8ff 51 #define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 52 //
bogdanm 0:9b334a45a8ff 53 // <e> Clock Configuration (Manual)
bogdanm 0:9b334a45a8ff 54 #define CLOCK_SETUP_REG 1
bogdanm 0:9b334a45a8ff 55 //
bogdanm 0:9b334a45a8ff 56 // <o.0..1> Main Clock Source Select A (MAINCLKSELA)
bogdanm 0:9b334a45a8ff 57 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 58 // <1=> System Oscillator
bogdanm 0:9b334a45a8ff 59 // <2=> WD Oscillator
bogdanm 0:9b334a45a8ff 60 #define MAINCLKSELA_Val 0x00000001 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 61 //
bogdanm 0:9b334a45a8ff 62 // <o.0..1> Main Clock Source Select B (MAINCLKSELB)
bogdanm 0:9b334a45a8ff 63 // <0=> MAINCLKSELA
bogdanm 0:9b334a45a8ff 64 // <1=> System PLL Input
bogdanm 0:9b334a45a8ff 65 // <2=> System PLL Output
bogdanm 0:9b334a45a8ff 66 // <3=> RTC Oscillator
bogdanm 0:9b334a45a8ff 67 #define MAINCLKSELB_Val 0x00000002 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 68 //
bogdanm 0:9b334a45a8ff 69 // <h> System PLL Setting (SYSPLLCTRL)
bogdanm 0:9b334a45a8ff 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 73 // <o.0..5> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 74 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 75 // <0-31>
mbed_official 76:2aa1c040b668 76 // <o.6..7> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 77 // <i> Post divider ratio P. Division ratio is 2 * P
bogdanm 0:9b334a45a8ff 78 // <0=> P = 1
bogdanm 0:9b334a45a8ff 79 // <1=> P = 2
bogdanm 0:9b334a45a8ff 80 // <2=> P = 4
bogdanm 0:9b334a45a8ff 81 // <3=> P = 8
bogdanm 0:9b334a45a8ff 82 // </h>
mbed_official 76:2aa1c040b668 83 #define SYSPLLCTRL_Val 0x00000045 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 84 //
bogdanm 0:9b334a45a8ff 85 // <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
bogdanm 0:9b334a45a8ff 86 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
bogdanm 0:9b334a45a8ff 87 // <i> 0 = is disabled
bogdanm 0:9b334a45a8ff 88 // <0-255>
bogdanm 0:9b334a45a8ff 89 #define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
bogdanm 0:9b334a45a8ff 90 // </e>
bogdanm 0:9b334a45a8ff 91 //
bogdanm 0:9b334a45a8ff 92 // <e> Clock Configuration (via ROM PLL API)
bogdanm 0:9b334a45a8ff 93 #define CLOCK_SETUP_API 0
bogdanm 0:9b334a45a8ff 94 //
bogdanm 0:9b334a45a8ff 95 // <o> PLL API Mode Select
bogdanm 0:9b334a45a8ff 96 // <0=> Exact
bogdanm 0:9b334a45a8ff 97 // <1=> Less than or equal
bogdanm 0:9b334a45a8ff 98 // <2=> Greater than or equal
bogdanm 0:9b334a45a8ff 99 // <3=> As close as possible
bogdanm 0:9b334a45a8ff 100 #define PLL_API_MODE_Val 0
bogdanm 0:9b334a45a8ff 101 //
bogdanm 0:9b334a45a8ff 102 // <o> CPU Frequency [Hz] <1000000-72000000:1000>
bogdanm 0:9b334a45a8ff 103 #define PLL_API_FREQ_Val 72000000
bogdanm 0:9b334a45a8ff 104 // </e>
bogdanm 0:9b334a45a8ff 105 //
bogdanm 0:9b334a45a8ff 106 // <e> USB Clock Configuration
bogdanm 0:9b334a45a8ff 107 #define USB_CLOCK_SETUP 0
bogdanm 0:9b334a45a8ff 108 // <h> USB PLL Control (USBPLLCTRL)
bogdanm 0:9b334a45a8ff 109 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 110 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 111 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 112 // <o.0..5> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 113 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 114 // <0-31>
bogdanm 0:9b334a45a8ff 115 // <o.7..6> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 116 // <i> Post divider ratio P. Division ratio is 2 * P
bogdanm 0:9b334a45a8ff 117 // <0=> P = 1
bogdanm 0:9b334a45a8ff 118 // <1=> P = 2
bogdanm 0:9b334a45a8ff 119 // <2=> P = 4
bogdanm 0:9b334a45a8ff 120 // <3=> P = 8
bogdanm 0:9b334a45a8ff 121 // </h>
bogdanm 0:9b334a45a8ff 122 #define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 123 //
bogdanm 0:9b334a45a8ff 124 // <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
bogdanm 0:9b334a45a8ff 125 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 126 // <1=> System Oscillator
bogdanm 0:9b334a45a8ff 127 #define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 128 //
bogdanm 0:9b334a45a8ff 129 // <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
bogdanm 0:9b334a45a8ff 130 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 131 // <1=> System Oscillator
bogdanm 0:9b334a45a8ff 132 // <2=> USB PLL out
bogdanm 0:9b334a45a8ff 133 // <3=> Main clock
bogdanm 0:9b334a45a8ff 134 #define USBCLKSEL_Val 0x00000002 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 135 //
bogdanm 0:9b334a45a8ff 136 // <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
bogdanm 0:9b334a45a8ff 137 // <i> Divides USB clock to 48 MHz.
bogdanm 0:9b334a45a8ff 138 // <i> 0 = is disabled
bogdanm 0:9b334a45a8ff 139 // <0-255>
bogdanm 0:9b334a45a8ff 140 #define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
bogdanm 0:9b334a45a8ff 141 // </e>
bogdanm 0:9b334a45a8ff 142 //
bogdanm 0:9b334a45a8ff 143 // <e> SCT Clock Configuration
bogdanm 0:9b334a45a8ff 144 #define SCT_CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 145 // <h> SCT PLL Control (SCTPLLCTRL)
bogdanm 0:9b334a45a8ff 146 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 0:9b334a45a8ff 147 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 148 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 0:9b334a45a8ff 149 // <o.0..5> MSEL: Feedback Divider Selection
bogdanm 0:9b334a45a8ff 150 // <i> M = MSEL + 1
bogdanm 0:9b334a45a8ff 151 // <0-31>
bogdanm 0:9b334a45a8ff 152 // <o.7..6> PSEL: Post Divider Selection
bogdanm 0:9b334a45a8ff 153 // <i> Post divider ratio P. Division ratio is 2 * P
bogdanm 0:9b334a45a8ff 154 // <0=> P = 1
bogdanm 0:9b334a45a8ff 155 // <1=> P = 2
bogdanm 0:9b334a45a8ff 156 // <2=> P = 4
bogdanm 0:9b334a45a8ff 157 // <3=> P = 8
bogdanm 0:9b334a45a8ff 158 // </h>
mbed_official 76:2aa1c040b668 159 #define SCTPLLCTRL_Val 0x00000045 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 160 //
bogdanm 0:9b334a45a8ff 161 // <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
bogdanm 0:9b334a45a8ff 162 // <0=> IRC Oscillator
bogdanm 0:9b334a45a8ff 163 // <1=> System Oscillator
bogdanm 0:9b334a45a8ff 164 #define SCTPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
bogdanm 0:9b334a45a8ff 165 // </e>
bogdanm 0:9b334a45a8ff 166 //
bogdanm 0:9b334a45a8ff 167 // </e>
bogdanm 0:9b334a45a8ff 168 //
bogdanm 0:9b334a45a8ff 169 // <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
bogdanm 0:9b334a45a8ff 170 // <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
bogdanm 0:9b334a45a8ff 171 //
bogdanm 0:9b334a45a8ff 172 #define XTAL_CLK_Val 12000000
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /*
bogdanm 0:9b334a45a8ff 175 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 0:9b334a45a8ff 176 */
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 179 Define clocks
bogdanm 0:9b334a45a8ff 180 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 181 #define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
bogdanm 0:9b334a45a8ff 182 #define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
bogdanm 0:9b334a45a8ff 183 #define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
bogdanm 0:9b334a45a8ff 184 #define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
bogdanm 0:9b334a45a8ff 185 #define __WDT_OSC_CLK ( 503000UL) /* WDT oscillator freq */
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 188 Check the register settings
bogdanm 0:9b334a45a8ff 189 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 190 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 0:9b334a45a8ff 191 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 #if (CHECK_RANGE((SYSOSCCTRL_Val), 0, 1))
bogdanm 0:9b334a45a8ff 194 #error "SYSOSCCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 195 #endif
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
bogdanm 0:9b334a45a8ff 198 #error "SYSPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 199 #endif
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000000FF))
bogdanm 0:9b334a45a8ff 202 #error "SYSPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 203 #endif
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 #if (CHECK_RANGE((MAINCLKSELA_Val), 0, 2))
bogdanm 0:9b334a45a8ff 206 #error "MAINCLKSELA: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 207 #endif
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 #if (CHECK_RSVD((MAINCLKSELB_Val), ~0x00000003))
bogdanm 0:9b334a45a8ff 210 #error "MAINCLKSELB: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 211 #endif
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
bogdanm 0:9b334a45a8ff 214 #error "SYSAHBCLKDIV: Value out of range!"
bogdanm 0:9b334a45a8ff 215 #endif
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 #if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
bogdanm 0:9b334a45a8ff 218 #error "You must select either manual or API based Clock Configuration!"
bogdanm 0:9b334a45a8ff 219 #endif
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
bogdanm 0:9b334a45a8ff 222 #error "USBPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 223 #endif
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x00000FF))
bogdanm 0:9b334a45a8ff 226 #error "USBPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 227 #endif
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 3))
bogdanm 0:9b334a45a8ff 230 #error "USBCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 231 #endif
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
bogdanm 0:9b334a45a8ff 234 #error "USBCLKDIV: Value out of range!"
bogdanm 0:9b334a45a8ff 235 #endif
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 #if (CHECK_RANGE((SCTPLLCLKSEL_Val), 0, 1))
bogdanm 0:9b334a45a8ff 238 #error "SCTPLLCLKSEL: Value out of range!"
bogdanm 0:9b334a45a8ff 239 #endif
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 #if (CHECK_RSVD((SCTPLLCTRL_Val), ~0x00000FF))
bogdanm 0:9b334a45a8ff 242 #error "SCTPLLCTRL: Invalid values of reserved bits!"
bogdanm 0:9b334a45a8ff 243 #endif
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 #if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
bogdanm 0:9b334a45a8ff 246 #error "XTAL frequency is out of bounds"
bogdanm 0:9b334a45a8ff 247 #endif
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 #if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
bogdanm 0:9b334a45a8ff 250 #error "PLL API Mode Select not valid"
bogdanm 0:9b334a45a8ff 251 #endif
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 #if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 72000000))
bogdanm 0:9b334a45a8ff 254 #error "CPU Frequency (API mode) not valid"
bogdanm 0:9b334a45a8ff 255 #endif
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 260 Calculate system core clock
bogdanm 0:9b334a45a8ff 261 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 262 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 /* sys_pllclkin calculation */
bogdanm 0:9b334a45a8ff 265 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 266 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 267 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 268 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
bogdanm 0:9b334a45a8ff 269 #else
bogdanm 0:9b334a45a8ff 270 #error "Oops"
bogdanm 0:9b334a45a8ff 271 #endif
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 #if ((MAINCLKSELA_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 276 #define __MAINA_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 277 #elif ((MAINCLKSELA_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 278 #define __MAINA_CLOCK (__SYS_OSC_CLK)
bogdanm 0:9b334a45a8ff 279 #elif ((MAINCLKSELA_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 280 #define __MAINA_CLOCK (__WDT_OSC_CLK)
bogdanm 0:9b334a45a8ff 281 #else
bogdanm 0:9b334a45a8ff 282 #error "Oops"
bogdanm 0:9b334a45a8ff 283 #endif
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /* main clock calculation */
bogdanm 0:9b334a45a8ff 288 #if ((MAINCLKSELB_Val & 0x03) == 0)
bogdanm 0:9b334a45a8ff 289 #define __MAINB_CLOCK (__MAINA_CLOCK)
bogdanm 0:9b334a45a8ff 290 #elif ((MAINCLKSELB_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 291 #define __MAINB_CLOCK (__SYS_PLLCLKIN)
bogdanm 0:9b334a45a8ff 292 #elif ((MAINCLKSELB_Val & 0x03) == 2)
bogdanm 0:9b334a45a8ff 293 #define __MAINB_CLOCK (__SYS_PLLCLKOUT)
bogdanm 0:9b334a45a8ff 294 #elif ((MAINCLKSELB_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 295 #define __MAINB_CLOCK (__RTC_OSC_CLK)
bogdanm 0:9b334a45a8ff 296 #else
bogdanm 0:9b334a45a8ff 297 #error "Oops"
bogdanm 0:9b334a45a8ff 298 #endif
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 #define __SYSTEM_CLOCK (__MAINB_CLOCK / SYSAHBCLKDIV_Val)
bogdanm 0:9b334a45a8ff 301 #endif /* Clock Setup via Register */
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
bogdanm 0:9b334a45a8ff 304 #define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
bogdanm 0:9b334a45a8ff 305 #endif /* Clock Setup via PLL API */
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 #else
bogdanm 0:9b334a45a8ff 308 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
bogdanm 0:9b334a45a8ff 309 #endif /* CLOCK_SETUP */
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 #if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
bogdanm 0:9b334a45a8ff 314 #include "power_api.h"
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 typedef struct _ROM {
bogdanm 0:9b334a45a8ff 317 const unsigned p_dev0;
bogdanm 0:9b334a45a8ff 318 const unsigned p_dev1;
bogdanm 0:9b334a45a8ff 319 const unsigned p_dev2;
bogdanm 0:9b334a45a8ff 320 const PWRD * pPWRD; /* ROM Power Management API */
bogdanm 0:9b334a45a8ff 321 const unsigned p_dev4;
bogdanm 0:9b334a45a8ff 322 const unsigned p_dev5;
bogdanm 0:9b334a45a8ff 323 const unsigned p_dev6;
bogdanm 0:9b334a45a8ff 324 const unsigned p_dev7;
bogdanm 0:9b334a45a8ff 325 } ROM;
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 328 PLL API Function
bogdanm 0:9b334a45a8ff 329 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 330 static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
bogdanm 0:9b334a45a8ff 331 {
bogdanm 0:9b334a45a8ff 332 uint32_t cmd[5], res[5];
bogdanm 0:9b334a45a8ff 333 ROM ** rom = (ROM **) 0x03000200; /* pointer to power API calls */
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 cmd[0] = pllInFreq; /* PLL's input freq in KHz */
bogdanm 0:9b334a45a8ff 336 cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
bogdanm 0:9b334a45a8ff 337 cmd[2] = pllMode;
bogdanm 0:9b334a45a8ff 338 cmd[3] = 0; /* no timeout for PLL to lock */
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /* Execute API call */
bogdanm 0:9b334a45a8ff 341 (*rom)->pPWRD->set_pll(cmd, res); /* call API function */
bogdanm 0:9b334a45a8ff 342 if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
bogdanm 0:9b334a45a8ff 343 while(1); /* ... stay here */
bogdanm 0:9b334a45a8ff 344 }
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346 #endif
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 352 Clock Variable definitions
bogdanm 0:9b334a45a8ff 353 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 354 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 358 Clock functions
bogdanm 0:9b334a45a8ff 359 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 360 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 0:9b334a45a8ff 361 {
bogdanm 0:9b334a45a8ff 362 /* Determine clock frequency according to clock register values */
bogdanm 0:9b334a45a8ff 363 switch (LPC_SYSCON->MAINCLKSELB & 0x03) {
bogdanm 0:9b334a45a8ff 364 case 0: /* MAINCLKSELA clock sel */
bogdanm 0:9b334a45a8ff 365 switch (LPC_SYSCON->MAINCLKSELA & 0x03) {
bogdanm 0:9b334a45a8ff 366 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 367 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 368 break;
bogdanm 0:9b334a45a8ff 369 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 370 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 0:9b334a45a8ff 371 break;
bogdanm 0:9b334a45a8ff 372 case 2: /* Watchdog oscillator */
bogdanm 0:9b334a45a8ff 373 SystemCoreClock = __WDT_OSC_CLK;
bogdanm 0:9b334a45a8ff 374 break;
bogdanm 0:9b334a45a8ff 375 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 376 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 377 break;
bogdanm 0:9b334a45a8ff 378 }
bogdanm 0:9b334a45a8ff 379 break;
bogdanm 0:9b334a45a8ff 380 case 1: /* Input Clock to System PLL */
bogdanm 0:9b334a45a8ff 381 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 382 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 383 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 0:9b334a45a8ff 384 break;
bogdanm 0:9b334a45a8ff 385 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 386 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 0:9b334a45a8ff 387 break;
bogdanm 0:9b334a45a8ff 388 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 389 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 390 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 391 break;
bogdanm 0:9b334a45a8ff 392 }
bogdanm 0:9b334a45a8ff 393 break;
bogdanm 0:9b334a45a8ff 394 case 2: /* System PLL Clock Out */
bogdanm 0:9b334a45a8ff 395 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 0:9b334a45a8ff 396 case 0: /* Internal RC oscillator */
bogdanm 0:9b334a45a8ff 397 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 398 break;
bogdanm 0:9b334a45a8ff 399 case 1: /* System oscillator */
bogdanm 0:9b334a45a8ff 400 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 0:9b334a45a8ff 401 break;
bogdanm 0:9b334a45a8ff 402 case 2: /* Reserved */
bogdanm 0:9b334a45a8ff 403 case 3: /* Reserved */
bogdanm 0:9b334a45a8ff 404 SystemCoreClock = 0;
bogdanm 0:9b334a45a8ff 405 break;
bogdanm 0:9b334a45a8ff 406 }
bogdanm 0:9b334a45a8ff 407 break;
bogdanm 0:9b334a45a8ff 408 case 3: /* WDT Oscillator */
bogdanm 0:9b334a45a8ff 409 SystemCoreClock = __WDT_OSC_CLK;
bogdanm 0:9b334a45a8ff 410 break;
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 }
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /**
bogdanm 0:9b334a45a8ff 418 * Initialize the system
bogdanm 0:9b334a45a8ff 419 *
bogdanm 0:9b334a45a8ff 420 * @param none
bogdanm 0:9b334a45a8ff 421 * @return none
bogdanm 0:9b334a45a8ff 422 *
bogdanm 0:9b334a45a8ff 423 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 424 */
bogdanm 0:9b334a45a8ff 425 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 426 #if (CLOCK_SETUP)
bogdanm 0:9b334a45a8ff 427 volatile uint32_t i;
bogdanm 0:9b334a45a8ff 428 #endif
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 0:9b334a45a8ff 433 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 434 LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
bogdanm 0:9b334a45a8ff 435 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
bogdanm 0:9b334a45a8ff 436 #endif
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 #if (((MAINCLKSELA_Val & 0x03) == 1) )
bogdanm 0:9b334a45a8ff 443 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 0:9b334a45a8ff 444 LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
bogdanm 0:9b334a45a8ff 445 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
bogdanm 0:9b334a45a8ff 446 #endif
bogdanm 0:9b334a45a8ff 447
bogdanm 0:9b334a45a8ff 448 #if (((MAINCLKSELA_Val & 0x03) == 2) )
bogdanm 0:9b334a45a8ff 449 LPC_SYSCON->PDRUNCFG &= ~(1 << 20); /* Power-up WDT Clock */
bogdanm 0:9b334a45a8ff 450 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
bogdanm 0:9b334a45a8ff 451 #endif
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 #if ((MAINCLKSELB_Val & 0x03) == 3)
bogdanm 0:9b334a45a8ff 454 LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
bogdanm 0:9b334a45a8ff 455 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
bogdanm 0:9b334a45a8ff 456 #endif
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 LPC_SYSCON->MAINCLKSELA = MAINCLKSELA_Val; /* select MAINCLKA clock */
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 #if ((MAINCLKSELB_Val & 0x03) == 2) /* Main Clock is PLL Out */
bogdanm 0:9b334a45a8ff 461 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 462 LPC_SYSCON->PDRUNCFG &= ~(1 << 22); /* Power-up SYSPLL */
bogdanm 0:9b334a45a8ff 463 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 464 #endif
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 LPC_SYSCON->MAINCLKSELB = MAINCLKSELB_Val; /* select Main clock */
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
bogdanm 0:9b334a45a8ff 469 #endif /* Clock Setup via Register */
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 #if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
bogdanm 0:9b334a45a8ff 472 // LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 LPC_SYSCON->MAINCLKSELB = (1 << 2); /* Select System PLL output */
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 LPC_SYSCON->SYSAHBCLKDIV = 1;
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
bogdanm 0:9b334a45a8ff 479 #endif /* Clock Setup via PLL API */
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 #if (USB_CLOCK_SETUP == 1) /* USB clock is used */
bogdanm 0:9b334a45a8ff 482 LPC_SYSCON->PDRUNCFG &= ~(1 << 9); /* Power-up USB PHY */
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 #if ((USBCLKSEL_Val & 0x003) == 2) /* USB clock is USB PLL out */
bogdanm 0:9b334a45a8ff 485 LPC_SYSCON->PDRUNCFG &= ~(1 << 23); /* Power-up USB PLL */
bogdanm 0:9b334a45a8ff 486 LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 489 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 LPC_SYSCON->USBCLKSEL = 0x02; /* Select USB PLL */
bogdanm 0:9b334a45a8ff 492 #endif
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
bogdanm 0:9b334a45a8ff 495 LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 #else /* USB clock is not used */
bogdanm 0:9b334a45a8ff 498 LPC_SYSCON->PDRUNCFG |= (1 << 9); /* Power-down USB PHY */
bogdanm 0:9b334a45a8ff 499 LPC_SYSCON->PDRUNCFG |= (1 << 23); /* Power-down USB PLL */
bogdanm 0:9b334a45a8ff 500 #endif
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 #if (SCT_CLOCK_SETUP == 1) /* SCT clock is used */
bogdanm 0:9b334a45a8ff 503 LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */
bogdanm 0:9b334a45a8ff 504 LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 LPC_SYSCON->SCTPLLCTRL = SCTPLLCTRL_Val;
bogdanm 0:9b334a45a8ff 507 while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 0:9b334a45a8ff 508 #else /* SCT clock is not used */
bogdanm 0:9b334a45a8ff 509 LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */
bogdanm 0:9b334a45a8ff 510 #endif
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 #endif /* Clock Setup */
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << 12); /* enable clock for SWM */
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 }