Pokitto Community Team / Pokitto_

PokittoLib with changes to lcd refresh etc.

Dependents:   Pokittris

Fork of Pokitto by Pokitto Community Team

This is a fork by user @Spinal, and is used in Pokittris for testing. Do not import this to your own program.

mbed-pokitto/targets/cmsis/core_caFunc.h@5:7e5c566b1760, 2017-10-07 (annotated)

Committer:
Pokitto
Date:
Sat Oct 07 21:31:12 2017 +0000
Revision:
5:7e5c566b1760
mbed-pokitto integrated

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pokitto 5:7e5c566b1760 1 /**************************************************************************//**
Pokitto 5:7e5c566b1760 2 * @file core_caFunc.h
Pokitto 5:7e5c566b1760 3 * @brief CMSIS Cortex-A Core Function Access Header File
Pokitto 5:7e5c566b1760 4 * @version V3.10
Pokitto 5:7e5c566b1760 5 * @date 30 Oct 2013
Pokitto 5:7e5c566b1760 6 *
Pokitto 5:7e5c566b1760 7 * @note
Pokitto 5:7e5c566b1760 8 *
Pokitto 5:7e5c566b1760 9 ******************************************************************************/
Pokitto 5:7e5c566b1760 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Pokitto 5:7e5c566b1760 11
Pokitto 5:7e5c566b1760 12 All rights reserved.
Pokitto 5:7e5c566b1760 13 Redistribution and use in source and binary forms, with or without
Pokitto 5:7e5c566b1760 14 modification, are permitted provided that the following conditions are met:
Pokitto 5:7e5c566b1760 15 - Redistributions of source code must retain the above copyright
Pokitto 5:7e5c566b1760 16 notice, this list of conditions and the following disclaimer.
Pokitto 5:7e5c566b1760 17 - Redistributions in binary form must reproduce the above copyright
Pokitto 5:7e5c566b1760 18 notice, this list of conditions and the following disclaimer in the
Pokitto 5:7e5c566b1760 19 documentation and/or other materials provided with the distribution.
Pokitto 5:7e5c566b1760 20 - Neither the name of ARM nor the names of its contributors may be used
Pokitto 5:7e5c566b1760 21 to endorse or promote products derived from this software without
Pokitto 5:7e5c566b1760 22 specific prior written permission.
Pokitto 5:7e5c566b1760 23 *
Pokitto 5:7e5c566b1760 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Pokitto 5:7e5c566b1760 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Pokitto 5:7e5c566b1760 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Pokitto 5:7e5c566b1760 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Pokitto 5:7e5c566b1760 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Pokitto 5:7e5c566b1760 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Pokitto 5:7e5c566b1760 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Pokitto 5:7e5c566b1760 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Pokitto 5:7e5c566b1760 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Pokitto 5:7e5c566b1760 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Pokitto 5:7e5c566b1760 34 POSSIBILITY OF SUCH DAMAGE.
Pokitto 5:7e5c566b1760 35 ---------------------------------------------------------------------------*/
Pokitto 5:7e5c566b1760 36
Pokitto 5:7e5c566b1760 37
Pokitto 5:7e5c566b1760 38 #ifndef __CORE_CAFUNC_H__
Pokitto 5:7e5c566b1760 39 #define __CORE_CAFUNC_H__
Pokitto 5:7e5c566b1760 40
Pokitto 5:7e5c566b1760 41
Pokitto 5:7e5c566b1760 42 /* ########################### Core Function Access ########################### */
Pokitto 5:7e5c566b1760 43 /** \ingroup CMSIS_Core_FunctionInterface
Pokitto 5:7e5c566b1760 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Pokitto 5:7e5c566b1760 45 @{
Pokitto 5:7e5c566b1760 46 */
Pokitto 5:7e5c566b1760 47
Pokitto 5:7e5c566b1760 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Pokitto 5:7e5c566b1760 49 /* ARM armcc specific functions */
Pokitto 5:7e5c566b1760 50
Pokitto 5:7e5c566b1760 51 #if (__ARMCC_VERSION < 400677)
Pokitto 5:7e5c566b1760 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Pokitto 5:7e5c566b1760 53 #endif
Pokitto 5:7e5c566b1760 54
Pokitto 5:7e5c566b1760 55 #define MODE_USR 0x10
Pokitto 5:7e5c566b1760 56 #define MODE_FIQ 0x11
Pokitto 5:7e5c566b1760 57 #define MODE_IRQ 0x12
Pokitto 5:7e5c566b1760 58 #define MODE_SVC 0x13
Pokitto 5:7e5c566b1760 59 #define MODE_MON 0x16
Pokitto 5:7e5c566b1760 60 #define MODE_ABT 0x17
Pokitto 5:7e5c566b1760 61 #define MODE_HYP 0x1A
Pokitto 5:7e5c566b1760 62 #define MODE_UND 0x1B
Pokitto 5:7e5c566b1760 63 #define MODE_SYS 0x1F
Pokitto 5:7e5c566b1760 64
Pokitto 5:7e5c566b1760 65 /** \brief Get APSR Register
Pokitto 5:7e5c566b1760 66
Pokitto 5:7e5c566b1760 67 This function returns the content of the APSR Register.
Pokitto 5:7e5c566b1760 68
Pokitto 5:7e5c566b1760 69 \return APSR Register value
Pokitto 5:7e5c566b1760 70 */
Pokitto 5:7e5c566b1760 71 __STATIC_INLINE uint32_t __get_APSR(void)
Pokitto 5:7e5c566b1760 72 {
Pokitto 5:7e5c566b1760 73 register uint32_t __regAPSR __ASM("apsr");
Pokitto 5:7e5c566b1760 74 return(__regAPSR);
Pokitto 5:7e5c566b1760 75 }
Pokitto 5:7e5c566b1760 76
Pokitto 5:7e5c566b1760 77
Pokitto 5:7e5c566b1760 78 /** \brief Get CPSR Register
Pokitto 5:7e5c566b1760 79
Pokitto 5:7e5c566b1760 80 This function returns the content of the CPSR Register.
Pokitto 5:7e5c566b1760 81
Pokitto 5:7e5c566b1760 82 \return CPSR Register value
Pokitto 5:7e5c566b1760 83 */
Pokitto 5:7e5c566b1760 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Pokitto 5:7e5c566b1760 85 {
Pokitto 5:7e5c566b1760 86 register uint32_t __regCPSR __ASM("cpsr");
Pokitto 5:7e5c566b1760 87 return(__regCPSR);
Pokitto 5:7e5c566b1760 88 }
Pokitto 5:7e5c566b1760 89
Pokitto 5:7e5c566b1760 90 /** \brief Set Stack Pointer
Pokitto 5:7e5c566b1760 91
Pokitto 5:7e5c566b1760 92 This function assigns the given value to the current stack pointer.
Pokitto 5:7e5c566b1760 93
Pokitto 5:7e5c566b1760 94 \param [in] topOfStack Stack Pointer value to set
Pokitto 5:7e5c566b1760 95 */
Pokitto 5:7e5c566b1760 96 register uint32_t __regSP __ASM("sp");
Pokitto 5:7e5c566b1760 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Pokitto 5:7e5c566b1760 98 {
Pokitto 5:7e5c566b1760 99 __regSP = topOfStack;
Pokitto 5:7e5c566b1760 100 }
Pokitto 5:7e5c566b1760 101
Pokitto 5:7e5c566b1760 102
Pokitto 5:7e5c566b1760 103 /** \brief Get link register
Pokitto 5:7e5c566b1760 104
Pokitto 5:7e5c566b1760 105 This function returns the value of the link register
Pokitto 5:7e5c566b1760 106
Pokitto 5:7e5c566b1760 107 \return Value of link register
Pokitto 5:7e5c566b1760 108 */
Pokitto 5:7e5c566b1760 109 register uint32_t __reglr __ASM("lr");
Pokitto 5:7e5c566b1760 110 __STATIC_INLINE uint32_t __get_LR(void)
Pokitto 5:7e5c566b1760 111 {
Pokitto 5:7e5c566b1760 112 return(__reglr);
Pokitto 5:7e5c566b1760 113 }
Pokitto 5:7e5c566b1760 114
Pokitto 5:7e5c566b1760 115 /** \brief Set link register
Pokitto 5:7e5c566b1760 116
Pokitto 5:7e5c566b1760 117 This function sets the value of the link register
Pokitto 5:7e5c566b1760 118
Pokitto 5:7e5c566b1760 119 \param [in] lr LR value to set
Pokitto 5:7e5c566b1760 120 */
Pokitto 5:7e5c566b1760 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Pokitto 5:7e5c566b1760 122 {
Pokitto 5:7e5c566b1760 123 __reglr = lr;
Pokitto 5:7e5c566b1760 124 }
Pokitto 5:7e5c566b1760 125
Pokitto 5:7e5c566b1760 126 /** \brief Set Process Stack Pointer
Pokitto 5:7e5c566b1760 127
Pokitto 5:7e5c566b1760 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Pokitto 5:7e5c566b1760 129
Pokitto 5:7e5c566b1760 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Pokitto 5:7e5c566b1760 131 */
Pokitto 5:7e5c566b1760 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Pokitto 5:7e5c566b1760 133 {
Pokitto 5:7e5c566b1760 134 ARM
Pokitto 5:7e5c566b1760 135 PRESERVE8
Pokitto 5:7e5c566b1760 136
Pokitto 5:7e5c566b1760 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Pokitto 5:7e5c566b1760 138 MRS R1, CPSR
Pokitto 5:7e5c566b1760 139 CPS #MODE_SYS ;no effect in USR mode
Pokitto 5:7e5c566b1760 140 MOV SP, R0
Pokitto 5:7e5c566b1760 141 MSR CPSR_c, R1 ;no effect in USR mode
Pokitto 5:7e5c566b1760 142 ISB
Pokitto 5:7e5c566b1760 143 BX LR
Pokitto 5:7e5c566b1760 144
Pokitto 5:7e5c566b1760 145 }
Pokitto 5:7e5c566b1760 146
Pokitto 5:7e5c566b1760 147 /** \brief Set User Mode
Pokitto 5:7e5c566b1760 148
Pokitto 5:7e5c566b1760 149 This function changes the processor state to User Mode
Pokitto 5:7e5c566b1760 150 */
Pokitto 5:7e5c566b1760 151 __STATIC_ASM void __set_CPS_USR(void)
Pokitto 5:7e5c566b1760 152 {
Pokitto 5:7e5c566b1760 153 ARM
Pokitto 5:7e5c566b1760 154
Pokitto 5:7e5c566b1760 155 CPS #MODE_USR
Pokitto 5:7e5c566b1760 156 BX LR
Pokitto 5:7e5c566b1760 157 }
Pokitto 5:7e5c566b1760 158
Pokitto 5:7e5c566b1760 159
Pokitto 5:7e5c566b1760 160 /** \brief Enable FIQ
Pokitto 5:7e5c566b1760 161
Pokitto 5:7e5c566b1760 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Pokitto 5:7e5c566b1760 163 Can only be executed in Privileged modes.
Pokitto 5:7e5c566b1760 164 */
Pokitto 5:7e5c566b1760 165 #define __enable_fault_irq __enable_fiq
Pokitto 5:7e5c566b1760 166
Pokitto 5:7e5c566b1760 167
Pokitto 5:7e5c566b1760 168 /** \brief Disable FIQ
Pokitto 5:7e5c566b1760 169
Pokitto 5:7e5c566b1760 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Pokitto 5:7e5c566b1760 171 Can only be executed in Privileged modes.
Pokitto 5:7e5c566b1760 172 */
Pokitto 5:7e5c566b1760 173 #define __disable_fault_irq __disable_fiq
Pokitto 5:7e5c566b1760 174
Pokitto 5:7e5c566b1760 175
Pokitto 5:7e5c566b1760 176 /** \brief Get FPSCR
Pokitto 5:7e5c566b1760 177
Pokitto 5:7e5c566b1760 178 This function returns the current value of the Floating Point Status/Control register.
Pokitto 5:7e5c566b1760 179
Pokitto 5:7e5c566b1760 180 \return Floating Point Status/Control register value
Pokitto 5:7e5c566b1760 181 */
Pokitto 5:7e5c566b1760 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Pokitto 5:7e5c566b1760 183 {
Pokitto 5:7e5c566b1760 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Pokitto 5:7e5c566b1760 185 register uint32_t __regfpscr __ASM("fpscr");
Pokitto 5:7e5c566b1760 186 return(__regfpscr);
Pokitto 5:7e5c566b1760 187 #else
Pokitto 5:7e5c566b1760 188 return(0);
Pokitto 5:7e5c566b1760 189 #endif
Pokitto 5:7e5c566b1760 190 }
Pokitto 5:7e5c566b1760 191
Pokitto 5:7e5c566b1760 192
Pokitto 5:7e5c566b1760 193 /** \brief Set FPSCR
Pokitto 5:7e5c566b1760 194
Pokitto 5:7e5c566b1760 195 This function assigns the given value to the Floating Point Status/Control register.
Pokitto 5:7e5c566b1760 196
Pokitto 5:7e5c566b1760 197 \param [in] fpscr Floating Point Status/Control value to set
Pokitto 5:7e5c566b1760 198 */
Pokitto 5:7e5c566b1760 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Pokitto 5:7e5c566b1760 200 {
Pokitto 5:7e5c566b1760 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Pokitto 5:7e5c566b1760 202 register uint32_t __regfpscr __ASM("fpscr");
Pokitto 5:7e5c566b1760 203 __regfpscr = (fpscr);
Pokitto 5:7e5c566b1760 204 #endif
Pokitto 5:7e5c566b1760 205 }
Pokitto 5:7e5c566b1760 206
Pokitto 5:7e5c566b1760 207 /** \brief Get FPEXC
Pokitto 5:7e5c566b1760 208
Pokitto 5:7e5c566b1760 209 This function returns the current value of the Floating Point Exception Control register.
Pokitto 5:7e5c566b1760 210
Pokitto 5:7e5c566b1760 211 \return Floating Point Exception Control register value
Pokitto 5:7e5c566b1760 212 */
Pokitto 5:7e5c566b1760 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Pokitto 5:7e5c566b1760 214 {
Pokitto 5:7e5c566b1760 215 #if (__FPU_PRESENT == 1)
Pokitto 5:7e5c566b1760 216 register uint32_t __regfpexc __ASM("fpexc");
Pokitto 5:7e5c566b1760 217 return(__regfpexc);
Pokitto 5:7e5c566b1760 218 #else
Pokitto 5:7e5c566b1760 219 return(0);
Pokitto 5:7e5c566b1760 220 #endif
Pokitto 5:7e5c566b1760 221 }
Pokitto 5:7e5c566b1760 222
Pokitto 5:7e5c566b1760 223
Pokitto 5:7e5c566b1760 224 /** \brief Set FPEXC
Pokitto 5:7e5c566b1760 225
Pokitto 5:7e5c566b1760 226 This function assigns the given value to the Floating Point Exception Control register.
Pokitto 5:7e5c566b1760 227
Pokitto 5:7e5c566b1760 228 \param [in] fpscr Floating Point Exception Control value to set
Pokitto 5:7e5c566b1760 229 */
Pokitto 5:7e5c566b1760 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Pokitto 5:7e5c566b1760 231 {
Pokitto 5:7e5c566b1760 232 #if (__FPU_PRESENT == 1)
Pokitto 5:7e5c566b1760 233 register uint32_t __regfpexc __ASM("fpexc");
Pokitto 5:7e5c566b1760 234 __regfpexc = (fpexc);
Pokitto 5:7e5c566b1760 235 #endif
Pokitto 5:7e5c566b1760 236 }
Pokitto 5:7e5c566b1760 237
Pokitto 5:7e5c566b1760 238 /** \brief Get CPACR
Pokitto 5:7e5c566b1760 239
Pokitto 5:7e5c566b1760 240 This function returns the current value of the Coprocessor Access Control register.
Pokitto 5:7e5c566b1760 241
Pokitto 5:7e5c566b1760 242 \return Coprocessor Access Control register value
Pokitto 5:7e5c566b1760 243 */
Pokitto 5:7e5c566b1760 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Pokitto 5:7e5c566b1760 245 {
Pokitto 5:7e5c566b1760 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Pokitto 5:7e5c566b1760 247 return __regCPACR;
Pokitto 5:7e5c566b1760 248 }
Pokitto 5:7e5c566b1760 249
Pokitto 5:7e5c566b1760 250 /** \brief Set CPACR
Pokitto 5:7e5c566b1760 251
Pokitto 5:7e5c566b1760 252 This function assigns the given value to the Coprocessor Access Control register.
Pokitto 5:7e5c566b1760 253
Pokitto 5:7e5c566b1760 254 \param [in] cpacr Coprocessor Acccess Control value to set
Pokitto 5:7e5c566b1760 255 */
Pokitto 5:7e5c566b1760 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Pokitto 5:7e5c566b1760 257 {
Pokitto 5:7e5c566b1760 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Pokitto 5:7e5c566b1760 259 __regCPACR = cpacr;
Pokitto 5:7e5c566b1760 260 __ISB();
Pokitto 5:7e5c566b1760 261 }
Pokitto 5:7e5c566b1760 262
Pokitto 5:7e5c566b1760 263 /** \brief Get CBAR
Pokitto 5:7e5c566b1760 264
Pokitto 5:7e5c566b1760 265 This function returns the value of the Configuration Base Address register.
Pokitto 5:7e5c566b1760 266
Pokitto 5:7e5c566b1760 267 \return Configuration Base Address register value
Pokitto 5:7e5c566b1760 268 */
Pokitto 5:7e5c566b1760 269 __STATIC_INLINE uint32_t __get_CBAR() {
Pokitto 5:7e5c566b1760 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Pokitto 5:7e5c566b1760 271 return(__regCBAR);
Pokitto 5:7e5c566b1760 272 }
Pokitto 5:7e5c566b1760 273
Pokitto 5:7e5c566b1760 274 /** \brief Get TTBR0
Pokitto 5:7e5c566b1760 275
Pokitto 5:7e5c566b1760 276 This function returns the value of the Translation Table Base Register 0.
Pokitto 5:7e5c566b1760 277
Pokitto 5:7e5c566b1760 278 \return Translation Table Base Register 0 value
Pokitto 5:7e5c566b1760 279 */
Pokitto 5:7e5c566b1760 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Pokitto 5:7e5c566b1760 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Pokitto 5:7e5c566b1760 282 return(__regTTBR0);
Pokitto 5:7e5c566b1760 283 }
Pokitto 5:7e5c566b1760 284
Pokitto 5:7e5c566b1760 285 /** \brief Set TTBR0
Pokitto 5:7e5c566b1760 286
Pokitto 5:7e5c566b1760 287 This function assigns the given value to the Translation Table Base Register 0.
Pokitto 5:7e5c566b1760 288
Pokitto 5:7e5c566b1760 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Pokitto 5:7e5c566b1760 290 */
Pokitto 5:7e5c566b1760 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Pokitto 5:7e5c566b1760 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Pokitto 5:7e5c566b1760 293 __regTTBR0 = ttbr0;
Pokitto 5:7e5c566b1760 294 __ISB();
Pokitto 5:7e5c566b1760 295 }
Pokitto 5:7e5c566b1760 296
Pokitto 5:7e5c566b1760 297 /** \brief Get DACR
Pokitto 5:7e5c566b1760 298
Pokitto 5:7e5c566b1760 299 This function returns the value of the Domain Access Control Register.
Pokitto 5:7e5c566b1760 300
Pokitto 5:7e5c566b1760 301 \return Domain Access Control Register value
Pokitto 5:7e5c566b1760 302 */
Pokitto 5:7e5c566b1760 303 __STATIC_INLINE uint32_t __get_DACR() {
Pokitto 5:7e5c566b1760 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Pokitto 5:7e5c566b1760 305 return(__regDACR);
Pokitto 5:7e5c566b1760 306 }
Pokitto 5:7e5c566b1760 307
Pokitto 5:7e5c566b1760 308 /** \brief Set DACR
Pokitto 5:7e5c566b1760 309
Pokitto 5:7e5c566b1760 310 This function assigns the given value to the Domain Access Control Register.
Pokitto 5:7e5c566b1760 311
Pokitto 5:7e5c566b1760 312 \param [in] dacr Domain Access Control Register value to set
Pokitto 5:7e5c566b1760 313 */
Pokitto 5:7e5c566b1760 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Pokitto 5:7e5c566b1760 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Pokitto 5:7e5c566b1760 316 __regDACR = dacr;
Pokitto 5:7e5c566b1760 317 __ISB();
Pokitto 5:7e5c566b1760 318 }
Pokitto 5:7e5c566b1760 319
Pokitto 5:7e5c566b1760 320 /******************************** Cache and BTAC enable ****************************************************/
Pokitto 5:7e5c566b1760 321
Pokitto 5:7e5c566b1760 322 /** \brief Set SCTLR
Pokitto 5:7e5c566b1760 323
Pokitto 5:7e5c566b1760 324 This function assigns the given value to the System Control Register.
Pokitto 5:7e5c566b1760 325
Pokitto 5:7e5c566b1760 326 \param [in] sctlr System Control Register value to set
Pokitto 5:7e5c566b1760 327 */
Pokitto 5:7e5c566b1760 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Pokitto 5:7e5c566b1760 329 {
Pokitto 5:7e5c566b1760 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Pokitto 5:7e5c566b1760 331 __regSCTLR = sctlr;
Pokitto 5:7e5c566b1760 332 }
Pokitto 5:7e5c566b1760 333
Pokitto 5:7e5c566b1760 334 /** \brief Get SCTLR
Pokitto 5:7e5c566b1760 335
Pokitto 5:7e5c566b1760 336 This function returns the value of the System Control Register.
Pokitto 5:7e5c566b1760 337
Pokitto 5:7e5c566b1760 338 \return System Control Register value
Pokitto 5:7e5c566b1760 339 */
Pokitto 5:7e5c566b1760 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Pokitto 5:7e5c566b1760 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Pokitto 5:7e5c566b1760 342 return(__regSCTLR);
Pokitto 5:7e5c566b1760 343 }
Pokitto 5:7e5c566b1760 344
Pokitto 5:7e5c566b1760 345 /** \brief Enable Caches
Pokitto 5:7e5c566b1760 346
Pokitto 5:7e5c566b1760 347 Enable Caches
Pokitto 5:7e5c566b1760 348 */
Pokitto 5:7e5c566b1760 349 __STATIC_INLINE void __enable_caches(void) {
Pokitto 5:7e5c566b1760 350 // Set I bit 12 to enable I Cache
Pokitto 5:7e5c566b1760 351 // Set C bit 2 to enable D Cache
Pokitto 5:7e5c566b1760 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Pokitto 5:7e5c566b1760 353 }
Pokitto 5:7e5c566b1760 354
Pokitto 5:7e5c566b1760 355 /** \brief Disable Caches
Pokitto 5:7e5c566b1760 356
Pokitto 5:7e5c566b1760 357 Disable Caches
Pokitto 5:7e5c566b1760 358 */
Pokitto 5:7e5c566b1760 359 __STATIC_INLINE void __disable_caches(void) {
Pokitto 5:7e5c566b1760 360 // Clear I bit 12 to disable I Cache
Pokitto 5:7e5c566b1760 361 // Clear C bit 2 to disable D Cache
Pokitto 5:7e5c566b1760 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Pokitto 5:7e5c566b1760 363 __ISB();
Pokitto 5:7e5c566b1760 364 }
Pokitto 5:7e5c566b1760 365
Pokitto 5:7e5c566b1760 366 /** \brief Enable BTAC
Pokitto 5:7e5c566b1760 367
Pokitto 5:7e5c566b1760 368 Enable BTAC
Pokitto 5:7e5c566b1760 369 */
Pokitto 5:7e5c566b1760 370 __STATIC_INLINE void __enable_btac(void) {
Pokitto 5:7e5c566b1760 371 // Set Z bit 11 to enable branch prediction
Pokitto 5:7e5c566b1760 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Pokitto 5:7e5c566b1760 373 __ISB();
Pokitto 5:7e5c566b1760 374 }
Pokitto 5:7e5c566b1760 375
Pokitto 5:7e5c566b1760 376 /** \brief Disable BTAC
Pokitto 5:7e5c566b1760 377
Pokitto 5:7e5c566b1760 378 Disable BTAC
Pokitto 5:7e5c566b1760 379 */
Pokitto 5:7e5c566b1760 380 __STATIC_INLINE void __disable_btac(void) {
Pokitto 5:7e5c566b1760 381 // Clear Z bit 11 to disable branch prediction
Pokitto 5:7e5c566b1760 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Pokitto 5:7e5c566b1760 383 }
Pokitto 5:7e5c566b1760 384
Pokitto 5:7e5c566b1760 385
Pokitto 5:7e5c566b1760 386 /** \brief Enable MMU
Pokitto 5:7e5c566b1760 387
Pokitto 5:7e5c566b1760 388 Enable MMU
Pokitto 5:7e5c566b1760 389 */
Pokitto 5:7e5c566b1760 390 __STATIC_INLINE void __enable_mmu(void) {
Pokitto 5:7e5c566b1760 391 // Set M bit 0 to enable the MMU
Pokitto 5:7e5c566b1760 392 // Set AFE bit to enable simplified access permissions model
Pokitto 5:7e5c566b1760 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Pokitto 5:7e5c566b1760 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Pokitto 5:7e5c566b1760 395 __ISB();
Pokitto 5:7e5c566b1760 396 }
Pokitto 5:7e5c566b1760 397
Pokitto 5:7e5c566b1760 398 /** \brief Disable MMU
Pokitto 5:7e5c566b1760 399
Pokitto 5:7e5c566b1760 400 Disable MMU
Pokitto 5:7e5c566b1760 401 */
Pokitto 5:7e5c566b1760 402 __STATIC_INLINE void __disable_mmu(void) {
Pokitto 5:7e5c566b1760 403 // Clear M bit 0 to disable the MMU
Pokitto 5:7e5c566b1760 404 __set_SCTLR( __get_SCTLR() & ~1);
Pokitto 5:7e5c566b1760 405 __ISB();
Pokitto 5:7e5c566b1760 406 }
Pokitto 5:7e5c566b1760 407
Pokitto 5:7e5c566b1760 408 /******************************** TLB maintenance operations ************************************************/
Pokitto 5:7e5c566b1760 409 /** \brief Invalidate the whole tlb
Pokitto 5:7e5c566b1760 410
Pokitto 5:7e5c566b1760 411 TLBIALL. Invalidate the whole tlb
Pokitto 5:7e5c566b1760 412 */
Pokitto 5:7e5c566b1760 413
Pokitto 5:7e5c566b1760 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Pokitto 5:7e5c566b1760 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Pokitto 5:7e5c566b1760 416 __TLBIALL = 0;
Pokitto 5:7e5c566b1760 417 __DSB();
Pokitto 5:7e5c566b1760 418 __ISB();
Pokitto 5:7e5c566b1760 419 }
Pokitto 5:7e5c566b1760 420
Pokitto 5:7e5c566b1760 421 /******************************** BTB maintenance operations ************************************************/
Pokitto 5:7e5c566b1760 422 /** \brief Invalidate entire branch predictor array
Pokitto 5:7e5c566b1760 423
Pokitto 5:7e5c566b1760 424 BPIALL. Branch Predictor Invalidate All.
Pokitto 5:7e5c566b1760 425 */
Pokitto 5:7e5c566b1760 426
Pokitto 5:7e5c566b1760 427 __STATIC_INLINE void __v7_inv_btac(void) {
Pokitto 5:7e5c566b1760 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Pokitto 5:7e5c566b1760 429 __BPIALL = 0;
Pokitto 5:7e5c566b1760 430 __DSB(); //ensure completion of the invalidation
Pokitto 5:7e5c566b1760 431 __ISB(); //ensure instruction fetch path sees new state
Pokitto 5:7e5c566b1760 432 }
Pokitto 5:7e5c566b1760 433
Pokitto 5:7e5c566b1760 434
Pokitto 5:7e5c566b1760 435 /******************************** L1 cache operations ******************************************************/
Pokitto 5:7e5c566b1760 436
Pokitto 5:7e5c566b1760 437 /** \brief Invalidate the whole I$
Pokitto 5:7e5c566b1760 438
Pokitto 5:7e5c566b1760 439 ICIALLU. Instruction Cache Invalidate All to PoU
Pokitto 5:7e5c566b1760 440 */
Pokitto 5:7e5c566b1760 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Pokitto 5:7e5c566b1760 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Pokitto 5:7e5c566b1760 443 __ICIALLU = 0;
Pokitto 5:7e5c566b1760 444 __DSB(); //ensure completion of the invalidation
Pokitto 5:7e5c566b1760 445 __ISB(); //ensure instruction fetch path sees new I cache state
Pokitto 5:7e5c566b1760 446 }
Pokitto 5:7e5c566b1760 447
Pokitto 5:7e5c566b1760 448 /** \brief Clean D$ by MVA
Pokitto 5:7e5c566b1760 449
Pokitto 5:7e5c566b1760 450 DCCMVAC. Data cache clean by MVA to PoC
Pokitto 5:7e5c566b1760 451 */
Pokitto 5:7e5c566b1760 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Pokitto 5:7e5c566b1760 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Pokitto 5:7e5c566b1760 454 __DCCMVAC = (uint32_t)va;
Pokitto 5:7e5c566b1760 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:7e5c566b1760 456 }
Pokitto 5:7e5c566b1760 457
Pokitto 5:7e5c566b1760 458 /** \brief Invalidate D$ by MVA
Pokitto 5:7e5c566b1760 459
Pokitto 5:7e5c566b1760 460 DCIMVAC. Data cache invalidate by MVA to PoC
Pokitto 5:7e5c566b1760 461 */
Pokitto 5:7e5c566b1760 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Pokitto 5:7e5c566b1760 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Pokitto 5:7e5c566b1760 464 __DCIMVAC = (uint32_t)va;
Pokitto 5:7e5c566b1760 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:7e5c566b1760 466 }
Pokitto 5:7e5c566b1760 467
Pokitto 5:7e5c566b1760 468 /** \brief Clean and Invalidate D$ by MVA
Pokitto 5:7e5c566b1760 469
Pokitto 5:7e5c566b1760 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Pokitto 5:7e5c566b1760 471 */
Pokitto 5:7e5c566b1760 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Pokitto 5:7e5c566b1760 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Pokitto 5:7e5c566b1760 474 __DCCIMVAC = (uint32_t)va;
Pokitto 5:7e5c566b1760 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:7e5c566b1760 476 }
Pokitto 5:7e5c566b1760 477
Pokitto 5:7e5c566b1760 478 /** \brief Clean and Invalidate the entire data or unified cache
Pokitto 5:7e5c566b1760 479
Pokitto 5:7e5c566b1760 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Pokitto 5:7e5c566b1760 481 */
Pokitto 5:7e5c566b1760 482 #pragma push
Pokitto 5:7e5c566b1760 483 #pragma arm
Pokitto 5:7e5c566b1760 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Pokitto 5:7e5c566b1760 485 ARM
Pokitto 5:7e5c566b1760 486
Pokitto 5:7e5c566b1760 487 PUSH {R4-R11}
Pokitto 5:7e5c566b1760 488
Pokitto 5:7e5c566b1760 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Pokitto 5:7e5c566b1760 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Pokitto 5:7e5c566b1760 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Pokitto 5:7e5c566b1760 492 BEQ Finished // If 0, no need to clean
Pokitto 5:7e5c566b1760 493
Pokitto 5:7e5c566b1760 494 MOV R10, #0 // R10 holds current cache level << 1
Pokitto 5:7e5c566b1760 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Pokitto 5:7e5c566b1760 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Pokitto 5:7e5c566b1760 497 AND R1, R1, #7 // Isolate those lower 3 bits
Pokitto 5:7e5c566b1760 498 CMP R1, #2
Pokitto 5:7e5c566b1760 499 BLT Skip // No cache or only instruction cache at this level
Pokitto 5:7e5c566b1760 500
Pokitto 5:7e5c566b1760 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Pokitto 5:7e5c566b1760 502 ISB // ISB to sync the change to the CacheSizeID reg
Pokitto 5:7e5c566b1760 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Pokitto 5:7e5c566b1760 504 AND R2, R1, #7 // Extract the line length field
Pokitto 5:7e5c566b1760 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Pokitto 5:7e5c566b1760 506 LDR R4, =0x3FF
Pokitto 5:7e5c566b1760 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Pokitto 5:7e5c566b1760 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Pokitto 5:7e5c566b1760 509 LDR R7, =0x7FFF
Pokitto 5:7e5c566b1760 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Pokitto 5:7e5c566b1760 511
Pokitto 5:7e5c566b1760 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Pokitto 5:7e5c566b1760 513
Pokitto 5:7e5c566b1760 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Pokitto 5:7e5c566b1760 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Pokitto 5:7e5c566b1760 516 CMP R0, #0
Pokitto 5:7e5c566b1760 517 BNE Dccsw
Pokitto 5:7e5c566b1760 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Pokitto 5:7e5c566b1760 519 B cont
Pokitto 5:7e5c566b1760 520 Dccsw CMP R0, #1
Pokitto 5:7e5c566b1760 521 BNE Dccisw
Pokitto 5:7e5c566b1760 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Pokitto 5:7e5c566b1760 523 B cont
Pokitto 5:7e5c566b1760 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Pokitto 5:7e5c566b1760 525 cont SUBS R9, R9, #1 // Decrement the Way number
Pokitto 5:7e5c566b1760 526 BGE Loop3
Pokitto 5:7e5c566b1760 527 SUBS R7, R7, #1 // Decrement the Set number
Pokitto 5:7e5c566b1760 528 BGE Loop2
Pokitto 5:7e5c566b1760 529 Skip ADD R10, R10, #2 // Increment the cache number
Pokitto 5:7e5c566b1760 530 CMP R3, R10
Pokitto 5:7e5c566b1760 531 BGT Loop1
Pokitto 5:7e5c566b1760 532
Pokitto 5:7e5c566b1760 533 Finished
Pokitto 5:7e5c566b1760 534 DSB
Pokitto 5:7e5c566b1760 535 POP {R4-R11}
Pokitto 5:7e5c566b1760 536 BX lr
Pokitto 5:7e5c566b1760 537
Pokitto 5:7e5c566b1760 538 }
Pokitto 5:7e5c566b1760 539 #pragma pop
Pokitto 5:7e5c566b1760 540
Pokitto 5:7e5c566b1760 541
Pokitto 5:7e5c566b1760 542 /** \brief Invalidate the whole D$
Pokitto 5:7e5c566b1760 543
Pokitto 5:7e5c566b1760 544 DCISW. Invalidate by Set/Way
Pokitto 5:7e5c566b1760 545 */
Pokitto 5:7e5c566b1760 546
Pokitto 5:7e5c566b1760 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Pokitto 5:7e5c566b1760 548 __v7_all_cache(0);
Pokitto 5:7e5c566b1760 549 }
Pokitto 5:7e5c566b1760 550
Pokitto 5:7e5c566b1760 551 /** \brief Clean the whole D$
Pokitto 5:7e5c566b1760 552
Pokitto 5:7e5c566b1760 553 DCCSW. Clean by Set/Way
Pokitto 5:7e5c566b1760 554 */
Pokitto 5:7e5c566b1760 555
Pokitto 5:7e5c566b1760 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Pokitto 5:7e5c566b1760 557 __v7_all_cache(1);
Pokitto 5:7e5c566b1760 558 }
Pokitto 5:7e5c566b1760 559
Pokitto 5:7e5c566b1760 560 /** \brief Clean and invalidate the whole D$
Pokitto 5:7e5c566b1760 561
Pokitto 5:7e5c566b1760 562 DCCISW. Clean and Invalidate by Set/Way
Pokitto 5:7e5c566b1760 563 */
Pokitto 5:7e5c566b1760 564
Pokitto 5:7e5c566b1760 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Pokitto 5:7e5c566b1760 566 __v7_all_cache(2);
Pokitto 5:7e5c566b1760 567 }
Pokitto 5:7e5c566b1760 568
Pokitto 5:7e5c566b1760 569 #include "core_ca_mmu.h"
Pokitto 5:7e5c566b1760 570
Pokitto 5:7e5c566b1760 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Pokitto 5:7e5c566b1760 572
Pokitto 5:7e5c566b1760 573 #error IAR Compiler support not implemented for Cortex-A
Pokitto 5:7e5c566b1760 574
Pokitto 5:7e5c566b1760 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Pokitto 5:7e5c566b1760 576 /* GNU gcc specific functions */
Pokitto 5:7e5c566b1760 577
Pokitto 5:7e5c566b1760 578 #define MODE_USR 0x10
Pokitto 5:7e5c566b1760 579 #define MODE_FIQ 0x11
Pokitto 5:7e5c566b1760 580 #define MODE_IRQ 0x12
Pokitto 5:7e5c566b1760 581 #define MODE_SVC 0x13
Pokitto 5:7e5c566b1760 582 #define MODE_MON 0x16
Pokitto 5:7e5c566b1760 583 #define MODE_ABT 0x17
Pokitto 5:7e5c566b1760 584 #define MODE_HYP 0x1A
Pokitto 5:7e5c566b1760 585 #define MODE_UND 0x1B
Pokitto 5:7e5c566b1760 586 #define MODE_SYS 0x1F
Pokitto 5:7e5c566b1760 587
Pokitto 5:7e5c566b1760 588
Pokitto 5:7e5c566b1760 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Pokitto 5:7e5c566b1760 590 {
Pokitto 5:7e5c566b1760 591 __ASM volatile ("cpsie i");
Pokitto 5:7e5c566b1760 592 }
Pokitto 5:7e5c566b1760 593
Pokitto 5:7e5c566b1760 594 /** \brief Disable IRQ Interrupts
Pokitto 5:7e5c566b1760 595
Pokitto 5:7e5c566b1760 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Pokitto 5:7e5c566b1760 597 Can only be executed in Privileged modes.
Pokitto 5:7e5c566b1760 598 */
Pokitto 5:7e5c566b1760 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Pokitto 5:7e5c566b1760 600 {
Pokitto 5:7e5c566b1760 601 uint32_t result;
Pokitto 5:7e5c566b1760 602
Pokitto 5:7e5c566b1760 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Pokitto 5:7e5c566b1760 604 __ASM volatile ("cpsid i");
Pokitto 5:7e5c566b1760 605 return(result & 0x80);
Pokitto 5:7e5c566b1760 606 }
Pokitto 5:7e5c566b1760 607
Pokitto 5:7e5c566b1760 608
Pokitto 5:7e5c566b1760 609 /** \brief Get APSR Register
Pokitto 5:7e5c566b1760 610
Pokitto 5:7e5c566b1760 611 This function returns the content of the APSR Register.
Pokitto 5:7e5c566b1760 612
Pokitto 5:7e5c566b1760 613 \return APSR Register value
Pokitto 5:7e5c566b1760 614 */
Pokitto 5:7e5c566b1760 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Pokitto 5:7e5c566b1760 616 {
Pokitto 5:7e5c566b1760 617 #if 1
Pokitto 5:7e5c566b1760 618 register uint32_t __regAPSR;
Pokitto 5:7e5c566b1760 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Pokitto 5:7e5c566b1760 620 #else
Pokitto 5:7e5c566b1760 621 register uint32_t __regAPSR __ASM("apsr");
Pokitto 5:7e5c566b1760 622 #endif
Pokitto 5:7e5c566b1760 623 return(__regAPSR);
Pokitto 5:7e5c566b1760 624 }
Pokitto 5:7e5c566b1760 625
Pokitto 5:7e5c566b1760 626
Pokitto 5:7e5c566b1760 627 /** \brief Get CPSR Register
Pokitto 5:7e5c566b1760 628
Pokitto 5:7e5c566b1760 629 This function returns the content of the CPSR Register.
Pokitto 5:7e5c566b1760 630
Pokitto 5:7e5c566b1760 631 \return CPSR Register value
Pokitto 5:7e5c566b1760 632 */
Pokitto 5:7e5c566b1760 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Pokitto 5:7e5c566b1760 634 {
Pokitto 5:7e5c566b1760 635 #if 1
Pokitto 5:7e5c566b1760 636 register uint32_t __regCPSR;
Pokitto 5:7e5c566b1760 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Pokitto 5:7e5c566b1760 638 #else
Pokitto 5:7e5c566b1760 639 register uint32_t __regCPSR __ASM("cpsr");
Pokitto 5:7e5c566b1760 640 #endif
Pokitto 5:7e5c566b1760 641 return(__regCPSR);
Pokitto 5:7e5c566b1760 642 }
Pokitto 5:7e5c566b1760 643
Pokitto 5:7e5c566b1760 644 #if 0
Pokitto 5:7e5c566b1760 645 /** \brief Set Stack Pointer
Pokitto 5:7e5c566b1760 646
Pokitto 5:7e5c566b1760 647 This function assigns the given value to the current stack pointer.
Pokitto 5:7e5c566b1760 648
Pokitto 5:7e5c566b1760 649 \param [in] topOfStack Stack Pointer value to set
Pokitto 5:7e5c566b1760 650 */
Pokitto 5:7e5c566b1760 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Pokitto 5:7e5c566b1760 652 {
Pokitto 5:7e5c566b1760 653 register uint32_t __regSP __ASM("sp");
Pokitto 5:7e5c566b1760 654 __regSP = topOfStack;
Pokitto 5:7e5c566b1760 655 }
Pokitto 5:7e5c566b1760 656 #endif
Pokitto 5:7e5c566b1760 657
Pokitto 5:7e5c566b1760 658 /** \brief Get link register
Pokitto 5:7e5c566b1760 659
Pokitto 5:7e5c566b1760 660 This function returns the value of the link register
Pokitto 5:7e5c566b1760 661
Pokitto 5:7e5c566b1760 662 \return Value of link register
Pokitto 5:7e5c566b1760 663 */
Pokitto 5:7e5c566b1760 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Pokitto 5:7e5c566b1760 665 {
Pokitto 5:7e5c566b1760 666 register uint32_t __reglr __ASM("lr");
Pokitto 5:7e5c566b1760 667 return(__reglr);
Pokitto 5:7e5c566b1760 668 }
Pokitto 5:7e5c566b1760 669
Pokitto 5:7e5c566b1760 670 #if 0
Pokitto 5:7e5c566b1760 671 /** \brief Set link register
Pokitto 5:7e5c566b1760 672
Pokitto 5:7e5c566b1760 673 This function sets the value of the link register
Pokitto 5:7e5c566b1760 674
Pokitto 5:7e5c566b1760 675 \param [in] lr LR value to set
Pokitto 5:7e5c566b1760 676 */
Pokitto 5:7e5c566b1760 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Pokitto 5:7e5c566b1760 678 {
Pokitto 5:7e5c566b1760 679 register uint32_t __reglr __ASM("lr");
Pokitto 5:7e5c566b1760 680 __reglr = lr;
Pokitto 5:7e5c566b1760 681 }
Pokitto 5:7e5c566b1760 682 #endif
Pokitto 5:7e5c566b1760 683
Pokitto 5:7e5c566b1760 684 /** \brief Set Process Stack Pointer
Pokitto 5:7e5c566b1760 685
Pokitto 5:7e5c566b1760 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Pokitto 5:7e5c566b1760 687
Pokitto 5:7e5c566b1760 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Pokitto 5:7e5c566b1760 689 */
Pokitto 5:7e5c566b1760 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Pokitto 5:7e5c566b1760 691 {
Pokitto 5:7e5c566b1760 692 __asm__ volatile (
Pokitto 5:7e5c566b1760 693 ".ARM;"
Pokitto 5:7e5c566b1760 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Pokitto 5:7e5c566b1760 695
Pokitto 5:7e5c566b1760 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Pokitto 5:7e5c566b1760 697 "MRS R1, CPSR;"
Pokitto 5:7e5c566b1760 698 "CPS %0;" /* ;no effect in USR mode */
Pokitto 5:7e5c566b1760 699 "MOV SP, R0;"
Pokitto 5:7e5c566b1760 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Pokitto 5:7e5c566b1760 701 "ISB;"
Pokitto 5:7e5c566b1760 702 //"BX LR;"
Pokitto 5:7e5c566b1760 703 :
Pokitto 5:7e5c566b1760 704 : "i"(MODE_SYS)
Pokitto 5:7e5c566b1760 705 : "r0", "r1");
Pokitto 5:7e5c566b1760 706 return;
Pokitto 5:7e5c566b1760 707 }
Pokitto 5:7e5c566b1760 708
Pokitto 5:7e5c566b1760 709 /** \brief Set User Mode
Pokitto 5:7e5c566b1760 710
Pokitto 5:7e5c566b1760 711 This function changes the processor state to User Mode
Pokitto 5:7e5c566b1760 712 */
Pokitto 5:7e5c566b1760 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Pokitto 5:7e5c566b1760 714 {
Pokitto 5:7e5c566b1760 715 __asm__ volatile (
Pokitto 5:7e5c566b1760 716 ".ARM;"
Pokitto 5:7e5c566b1760 717
Pokitto 5:7e5c566b1760 718 "CPS %0;"
Pokitto 5:7e5c566b1760 719 //"BX LR;"
Pokitto 5:7e5c566b1760 720 :
Pokitto 5:7e5c566b1760 721 : "i"(MODE_USR)
Pokitto 5:7e5c566b1760 722 : );
Pokitto 5:7e5c566b1760 723 return;
Pokitto 5:7e5c566b1760 724 }
Pokitto 5:7e5c566b1760 725
Pokitto 5:7e5c566b1760 726
Pokitto 5:7e5c566b1760 727 /** \brief Enable FIQ
Pokitto 5:7e5c566b1760 728
Pokitto 5:7e5c566b1760 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Pokitto 5:7e5c566b1760 730 Can only be executed in Privileged modes.
Pokitto 5:7e5c566b1760 731 */
Pokitto 5:7e5c566b1760 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Pokitto 5:7e5c566b1760 733
Pokitto 5:7e5c566b1760 734
Pokitto 5:7e5c566b1760 735 /** \brief Disable FIQ
Pokitto 5:7e5c566b1760 736
Pokitto 5:7e5c566b1760 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Pokitto 5:7e5c566b1760 738 Can only be executed in Privileged modes.
Pokitto 5:7e5c566b1760 739 */
Pokitto 5:7e5c566b1760 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Pokitto 5:7e5c566b1760 741
Pokitto 5:7e5c566b1760 742
Pokitto 5:7e5c566b1760 743 /** \brief Get FPSCR
Pokitto 5:7e5c566b1760 744
Pokitto 5:7e5c566b1760 745 This function returns the current value of the Floating Point Status/Control register.
Pokitto 5:7e5c566b1760 746
Pokitto 5:7e5c566b1760 747 \return Floating Point Status/Control register value
Pokitto 5:7e5c566b1760 748 */
Pokitto 5:7e5c566b1760 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Pokitto 5:7e5c566b1760 750 {
Pokitto 5:7e5c566b1760 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Pokitto 5:7e5c566b1760 752 #if 1
Pokitto 5:7e5c566b1760 753 uint32_t result;
Pokitto 5:7e5c566b1760 754
Pokitto 5:7e5c566b1760 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Pokitto 5:7e5c566b1760 756 return (result);
Pokitto 5:7e5c566b1760 757 #else
Pokitto 5:7e5c566b1760 758 register uint32_t __regfpscr __ASM("fpscr");
Pokitto 5:7e5c566b1760 759 return(__regfpscr);
Pokitto 5:7e5c566b1760 760 #endif
Pokitto 5:7e5c566b1760 761 #else
Pokitto 5:7e5c566b1760 762 return(0);
Pokitto 5:7e5c566b1760 763 #endif
Pokitto 5:7e5c566b1760 764 }
Pokitto 5:7e5c566b1760 765
Pokitto 5:7e5c566b1760 766
Pokitto 5:7e5c566b1760 767 /** \brief Set FPSCR
Pokitto 5:7e5c566b1760 768
Pokitto 5:7e5c566b1760 769 This function assigns the given value to the Floating Point Status/Control register.
Pokitto 5:7e5c566b1760 770
Pokitto 5:7e5c566b1760 771 \param [in] fpscr Floating Point Status/Control value to set
Pokitto 5:7e5c566b1760 772 */
Pokitto 5:7e5c566b1760 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Pokitto 5:7e5c566b1760 774 {
Pokitto 5:7e5c566b1760 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Pokitto 5:7e5c566b1760 776 #if 1
Pokitto 5:7e5c566b1760 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Pokitto 5:7e5c566b1760 778 #else
Pokitto 5:7e5c566b1760 779 register uint32_t __regfpscr __ASM("fpscr");
Pokitto 5:7e5c566b1760 780 __regfpscr = (fpscr);
Pokitto 5:7e5c566b1760 781 #endif
Pokitto 5:7e5c566b1760 782 #endif
Pokitto 5:7e5c566b1760 783 }
Pokitto 5:7e5c566b1760 784
Pokitto 5:7e5c566b1760 785 /** \brief Get FPEXC
Pokitto 5:7e5c566b1760 786
Pokitto 5:7e5c566b1760 787 This function returns the current value of the Floating Point Exception Control register.
Pokitto 5:7e5c566b1760 788
Pokitto 5:7e5c566b1760 789 \return Floating Point Exception Control register value
Pokitto 5:7e5c566b1760 790 */
Pokitto 5:7e5c566b1760 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Pokitto 5:7e5c566b1760 792 {
Pokitto 5:7e5c566b1760 793 #if (__FPU_PRESENT == 1)
Pokitto 5:7e5c566b1760 794 #if 1
Pokitto 5:7e5c566b1760 795 uint32_t result;
Pokitto 5:7e5c566b1760 796
Pokitto 5:7e5c566b1760 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Pokitto 5:7e5c566b1760 798 return (result);
Pokitto 5:7e5c566b1760 799 #else
Pokitto 5:7e5c566b1760 800 register uint32_t __regfpexc __ASM("fpexc");
Pokitto 5:7e5c566b1760 801 return(__regfpexc);
Pokitto 5:7e5c566b1760 802 #endif
Pokitto 5:7e5c566b1760 803 #else
Pokitto 5:7e5c566b1760 804 return(0);
Pokitto 5:7e5c566b1760 805 #endif
Pokitto 5:7e5c566b1760 806 }
Pokitto 5:7e5c566b1760 807
Pokitto 5:7e5c566b1760 808
Pokitto 5:7e5c566b1760 809 /** \brief Set FPEXC
Pokitto 5:7e5c566b1760 810
Pokitto 5:7e5c566b1760 811 This function assigns the given value to the Floating Point Exception Control register.
Pokitto 5:7e5c566b1760 812
Pokitto 5:7e5c566b1760 813 \param [in] fpscr Floating Point Exception Control value to set
Pokitto 5:7e5c566b1760 814 */
Pokitto 5:7e5c566b1760 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Pokitto 5:7e5c566b1760 816 {
Pokitto 5:7e5c566b1760 817 #if (__FPU_PRESENT == 1)
Pokitto 5:7e5c566b1760 818 #if 1
Pokitto 5:7e5c566b1760 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Pokitto 5:7e5c566b1760 820 #else
Pokitto 5:7e5c566b1760 821 register uint32_t __regfpexc __ASM("fpexc");
Pokitto 5:7e5c566b1760 822 __regfpexc = (fpexc);
Pokitto 5:7e5c566b1760 823 #endif
Pokitto 5:7e5c566b1760 824 #endif
Pokitto 5:7e5c566b1760 825 }
Pokitto 5:7e5c566b1760 826
Pokitto 5:7e5c566b1760 827 /** \brief Get CPACR
Pokitto 5:7e5c566b1760 828
Pokitto 5:7e5c566b1760 829 This function returns the current value of the Coprocessor Access Control register.
Pokitto 5:7e5c566b1760 830
Pokitto 5:7e5c566b1760 831 \return Coprocessor Access Control register value
Pokitto 5:7e5c566b1760 832 */
Pokitto 5:7e5c566b1760 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Pokitto 5:7e5c566b1760 834 {
Pokitto 5:7e5c566b1760 835 #if 1
Pokitto 5:7e5c566b1760 836 register uint32_t __regCPACR;
Pokitto 5:7e5c566b1760 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Pokitto 5:7e5c566b1760 838 #else
Pokitto 5:7e5c566b1760 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Pokitto 5:7e5c566b1760 840 #endif
Pokitto 5:7e5c566b1760 841 return __regCPACR;
Pokitto 5:7e5c566b1760 842 }
Pokitto 5:7e5c566b1760 843
Pokitto 5:7e5c566b1760 844 /** \brief Set CPACR
Pokitto 5:7e5c566b1760 845
Pokitto 5:7e5c566b1760 846 This function assigns the given value to the Coprocessor Access Control register.
Pokitto 5:7e5c566b1760 847
Pokitto 5:7e5c566b1760 848 \param [in] cpacr Coprocessor Acccess Control value to set
Pokitto 5:7e5c566b1760 849 */
Pokitto 5:7e5c566b1760 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Pokitto 5:7e5c566b1760 851 {
Pokitto 5:7e5c566b1760 852 #if 1
Pokitto 5:7e5c566b1760 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Pokitto 5:7e5c566b1760 854 #else
Pokitto 5:7e5c566b1760 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Pokitto 5:7e5c566b1760 856 __regCPACR = cpacr;
Pokitto 5:7e5c566b1760 857 #endif
Pokitto 5:7e5c566b1760 858 __ISB();
Pokitto 5:7e5c566b1760 859 }
Pokitto 5:7e5c566b1760 860
Pokitto 5:7e5c566b1760 861 /** \brief Get CBAR
Pokitto 5:7e5c566b1760 862
Pokitto 5:7e5c566b1760 863 This function returns the value of the Configuration Base Address register.
Pokitto 5:7e5c566b1760 864
Pokitto 5:7e5c566b1760 865 \return Configuration Base Address register value
Pokitto 5:7e5c566b1760 866 */
Pokitto 5:7e5c566b1760 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Pokitto 5:7e5c566b1760 868 #if 1
Pokitto 5:7e5c566b1760 869 register uint32_t __regCBAR;
Pokitto 5:7e5c566b1760 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Pokitto 5:7e5c566b1760 871 #else
Pokitto 5:7e5c566b1760 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Pokitto 5:7e5c566b1760 873 #endif
Pokitto 5:7e5c566b1760 874 return(__regCBAR);
Pokitto 5:7e5c566b1760 875 }
Pokitto 5:7e5c566b1760 876
Pokitto 5:7e5c566b1760 877 /** \brief Get TTBR0
Pokitto 5:7e5c566b1760 878
Pokitto 5:7e5c566b1760 879 This function returns the value of the Translation Table Base Register 0.
Pokitto 5:7e5c566b1760 880
Pokitto 5:7e5c566b1760 881 \return Translation Table Base Register 0 value
Pokitto 5:7e5c566b1760 882 */
Pokitto 5:7e5c566b1760 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Pokitto 5:7e5c566b1760 884 #if 1
Pokitto 5:7e5c566b1760 885 register uint32_t __regTTBR0;
Pokitto 5:7e5c566b1760 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Pokitto 5:7e5c566b1760 887 #else
Pokitto 5:7e5c566b1760 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Pokitto 5:7e5c566b1760 889 #endif
Pokitto 5:7e5c566b1760 890 return(__regTTBR0);
Pokitto 5:7e5c566b1760 891 }
Pokitto 5:7e5c566b1760 892
Pokitto 5:7e5c566b1760 893 /** \brief Set TTBR0
Pokitto 5:7e5c566b1760 894
Pokitto 5:7e5c566b1760 895 This function assigns the given value to the Translation Table Base Register 0.
Pokitto 5:7e5c566b1760 896
Pokitto 5:7e5c566b1760 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Pokitto 5:7e5c566b1760 898 */
Pokitto 5:7e5c566b1760 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Pokitto 5:7e5c566b1760 900 #if 1
Pokitto 5:7e5c566b1760 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Pokitto 5:7e5c566b1760 902 #else
Pokitto 5:7e5c566b1760 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Pokitto 5:7e5c566b1760 904 __regTTBR0 = ttbr0;
Pokitto 5:7e5c566b1760 905 #endif
Pokitto 5:7e5c566b1760 906 __ISB();
Pokitto 5:7e5c566b1760 907 }
Pokitto 5:7e5c566b1760 908
Pokitto 5:7e5c566b1760 909 /** \brief Get DACR
Pokitto 5:7e5c566b1760 910
Pokitto 5:7e5c566b1760 911 This function returns the value of the Domain Access Control Register.
Pokitto 5:7e5c566b1760 912
Pokitto 5:7e5c566b1760 913 \return Domain Access Control Register value
Pokitto 5:7e5c566b1760 914 */
Pokitto 5:7e5c566b1760 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Pokitto 5:7e5c566b1760 916 #if 1
Pokitto 5:7e5c566b1760 917 register uint32_t __regDACR;
Pokitto 5:7e5c566b1760 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Pokitto 5:7e5c566b1760 919 #else
Pokitto 5:7e5c566b1760 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Pokitto 5:7e5c566b1760 921 #endif
Pokitto 5:7e5c566b1760 922 return(__regDACR);
Pokitto 5:7e5c566b1760 923 }
Pokitto 5:7e5c566b1760 924
Pokitto 5:7e5c566b1760 925 /** \brief Set DACR
Pokitto 5:7e5c566b1760 926
Pokitto 5:7e5c566b1760 927 This function assigns the given value to the Domain Access Control Register.
Pokitto 5:7e5c566b1760 928
Pokitto 5:7e5c566b1760 929 \param [in] dacr Domain Access Control Register value to set
Pokitto 5:7e5c566b1760 930 */
Pokitto 5:7e5c566b1760 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Pokitto 5:7e5c566b1760 932 #if 1
Pokitto 5:7e5c566b1760 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Pokitto 5:7e5c566b1760 934 #else
Pokitto 5:7e5c566b1760 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Pokitto 5:7e5c566b1760 936 __regDACR = dacr;
Pokitto 5:7e5c566b1760 937 #endif
Pokitto 5:7e5c566b1760 938 __ISB();
Pokitto 5:7e5c566b1760 939 }
Pokitto 5:7e5c566b1760 940
Pokitto 5:7e5c566b1760 941 /******************************** Cache and BTAC enable ****************************************************/
Pokitto 5:7e5c566b1760 942
Pokitto 5:7e5c566b1760 943 /** \brief Set SCTLR
Pokitto 5:7e5c566b1760 944
Pokitto 5:7e5c566b1760 945 This function assigns the given value to the System Control Register.
Pokitto 5:7e5c566b1760 946
Pokitto 5:7e5c566b1760 947 \param [in] sctlr System Control Register value to set
Pokitto 5:7e5c566b1760 948 */
Pokitto 5:7e5c566b1760 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Pokitto 5:7e5c566b1760 950 {
Pokitto 5:7e5c566b1760 951 #if 1
Pokitto 5:7e5c566b1760 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Pokitto 5:7e5c566b1760 953 #else
Pokitto 5:7e5c566b1760 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Pokitto 5:7e5c566b1760 955 __regSCTLR = sctlr;
Pokitto 5:7e5c566b1760 956 #endif
Pokitto 5:7e5c566b1760 957 }
Pokitto 5:7e5c566b1760 958
Pokitto 5:7e5c566b1760 959 /** \brief Get SCTLR
Pokitto 5:7e5c566b1760 960
Pokitto 5:7e5c566b1760 961 This function returns the value of the System Control Register.
Pokitto 5:7e5c566b1760 962
Pokitto 5:7e5c566b1760 963 \return System Control Register value
Pokitto 5:7e5c566b1760 964 */
Pokitto 5:7e5c566b1760 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Pokitto 5:7e5c566b1760 966 #if 1
Pokitto 5:7e5c566b1760 967 register uint32_t __regSCTLR;
Pokitto 5:7e5c566b1760 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Pokitto 5:7e5c566b1760 969 #else
Pokitto 5:7e5c566b1760 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Pokitto 5:7e5c566b1760 971 #endif
Pokitto 5:7e5c566b1760 972 return(__regSCTLR);
Pokitto 5:7e5c566b1760 973 }
Pokitto 5:7e5c566b1760 974
Pokitto 5:7e5c566b1760 975 /** \brief Enable Caches
Pokitto 5:7e5c566b1760 976
Pokitto 5:7e5c566b1760 977 Enable Caches
Pokitto 5:7e5c566b1760 978 */
Pokitto 5:7e5c566b1760 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Pokitto 5:7e5c566b1760 980 // Set I bit 12 to enable I Cache
Pokitto 5:7e5c566b1760 981 // Set C bit 2 to enable D Cache
Pokitto 5:7e5c566b1760 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Pokitto 5:7e5c566b1760 983 }
Pokitto 5:7e5c566b1760 984
Pokitto 5:7e5c566b1760 985 /** \brief Disable Caches
Pokitto 5:7e5c566b1760 986
Pokitto 5:7e5c566b1760 987 Disable Caches
Pokitto 5:7e5c566b1760 988 */
Pokitto 5:7e5c566b1760 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Pokitto 5:7e5c566b1760 990 // Clear I bit 12 to disable I Cache
Pokitto 5:7e5c566b1760 991 // Clear C bit 2 to disable D Cache
Pokitto 5:7e5c566b1760 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Pokitto 5:7e5c566b1760 993 __ISB();
Pokitto 5:7e5c566b1760 994 }
Pokitto 5:7e5c566b1760 995
Pokitto 5:7e5c566b1760 996 /** \brief Enable BTAC
Pokitto 5:7e5c566b1760 997
Pokitto 5:7e5c566b1760 998 Enable BTAC
Pokitto 5:7e5c566b1760 999 */
Pokitto 5:7e5c566b1760 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Pokitto 5:7e5c566b1760 1001 // Set Z bit 11 to enable branch prediction
Pokitto 5:7e5c566b1760 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Pokitto 5:7e5c566b1760 1003 __ISB();
Pokitto 5:7e5c566b1760 1004 }
Pokitto 5:7e5c566b1760 1005
Pokitto 5:7e5c566b1760 1006 /** \brief Disable BTAC
Pokitto 5:7e5c566b1760 1007
Pokitto 5:7e5c566b1760 1008 Disable BTAC
Pokitto 5:7e5c566b1760 1009 */
Pokitto 5:7e5c566b1760 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Pokitto 5:7e5c566b1760 1011 // Clear Z bit 11 to disable branch prediction
Pokitto 5:7e5c566b1760 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Pokitto 5:7e5c566b1760 1013 }
Pokitto 5:7e5c566b1760 1014
Pokitto 5:7e5c566b1760 1015
Pokitto 5:7e5c566b1760 1016 /** \brief Enable MMU
Pokitto 5:7e5c566b1760 1017
Pokitto 5:7e5c566b1760 1018 Enable MMU
Pokitto 5:7e5c566b1760 1019 */
Pokitto 5:7e5c566b1760 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Pokitto 5:7e5c566b1760 1021 // Set M bit 0 to enable the MMU
Pokitto 5:7e5c566b1760 1022 // Set AFE bit to enable simplified access permissions model
Pokitto 5:7e5c566b1760 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Pokitto 5:7e5c566b1760 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Pokitto 5:7e5c566b1760 1025 __ISB();
Pokitto 5:7e5c566b1760 1026 }
Pokitto 5:7e5c566b1760 1027
Pokitto 5:7e5c566b1760 1028 /** \brief Disable MMU
Pokitto 5:7e5c566b1760 1029
Pokitto 5:7e5c566b1760 1030 Disable MMU
Pokitto 5:7e5c566b1760 1031 */
Pokitto 5:7e5c566b1760 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Pokitto 5:7e5c566b1760 1033 // Clear M bit 0 to disable the MMU
Pokitto 5:7e5c566b1760 1034 __set_SCTLR( __get_SCTLR() & ~1);
Pokitto 5:7e5c566b1760 1035 __ISB();
Pokitto 5:7e5c566b1760 1036 }
Pokitto 5:7e5c566b1760 1037
Pokitto 5:7e5c566b1760 1038 /******************************** TLB maintenance operations ************************************************/
Pokitto 5:7e5c566b1760 1039 /** \brief Invalidate the whole tlb
Pokitto 5:7e5c566b1760 1040
Pokitto 5:7e5c566b1760 1041 TLBIALL. Invalidate the whole tlb
Pokitto 5:7e5c566b1760 1042 */
Pokitto 5:7e5c566b1760 1043
Pokitto 5:7e5c566b1760 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Pokitto 5:7e5c566b1760 1045 #if 1
Pokitto 5:7e5c566b1760 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Pokitto 5:7e5c566b1760 1047 #else
Pokitto 5:7e5c566b1760 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Pokitto 5:7e5c566b1760 1049 __TLBIALL = 0;
Pokitto 5:7e5c566b1760 1050 #endif
Pokitto 5:7e5c566b1760 1051 __DSB();
Pokitto 5:7e5c566b1760 1052 __ISB();
Pokitto 5:7e5c566b1760 1053 }
Pokitto 5:7e5c566b1760 1054
Pokitto 5:7e5c566b1760 1055 /******************************** BTB maintenance operations ************************************************/
Pokitto 5:7e5c566b1760 1056 /** \brief Invalidate entire branch predictor array
Pokitto 5:7e5c566b1760 1057
Pokitto 5:7e5c566b1760 1058 BPIALL. Branch Predictor Invalidate All.
Pokitto 5:7e5c566b1760 1059 */
Pokitto 5:7e5c566b1760 1060
Pokitto 5:7e5c566b1760 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Pokitto 5:7e5c566b1760 1062 #if 1
Pokitto 5:7e5c566b1760 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Pokitto 5:7e5c566b1760 1064 #else
Pokitto 5:7e5c566b1760 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Pokitto 5:7e5c566b1760 1066 __BPIALL = 0;
Pokitto 5:7e5c566b1760 1067 #endif
Pokitto 5:7e5c566b1760 1068 __DSB(); //ensure completion of the invalidation
Pokitto 5:7e5c566b1760 1069 __ISB(); //ensure instruction fetch path sees new state
Pokitto 5:7e5c566b1760 1070 }
Pokitto 5:7e5c566b1760 1071
Pokitto 5:7e5c566b1760 1072
Pokitto 5:7e5c566b1760 1073 /******************************** L1 cache operations ******************************************************/
Pokitto 5:7e5c566b1760 1074
Pokitto 5:7e5c566b1760 1075 /** \brief Invalidate the whole I$
Pokitto 5:7e5c566b1760 1076
Pokitto 5:7e5c566b1760 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Pokitto 5:7e5c566b1760 1078 */
Pokitto 5:7e5c566b1760 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Pokitto 5:7e5c566b1760 1080 #if 1
Pokitto 5:7e5c566b1760 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Pokitto 5:7e5c566b1760 1082 #else
Pokitto 5:7e5c566b1760 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Pokitto 5:7e5c566b1760 1084 __ICIALLU = 0;
Pokitto 5:7e5c566b1760 1085 #endif
Pokitto 5:7e5c566b1760 1086 __DSB(); //ensure completion of the invalidation
Pokitto 5:7e5c566b1760 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Pokitto 5:7e5c566b1760 1088 }
Pokitto 5:7e5c566b1760 1089
Pokitto 5:7e5c566b1760 1090 /** \brief Clean D$ by MVA
Pokitto 5:7e5c566b1760 1091
Pokitto 5:7e5c566b1760 1092 DCCMVAC. Data cache clean by MVA to PoC
Pokitto 5:7e5c566b1760 1093 */
Pokitto 5:7e5c566b1760 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Pokitto 5:7e5c566b1760 1095 #if 1
Pokitto 5:7e5c566b1760 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Pokitto 5:7e5c566b1760 1097 #else
Pokitto 5:7e5c566b1760 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Pokitto 5:7e5c566b1760 1099 __DCCMVAC = (uint32_t)va;
Pokitto 5:7e5c566b1760 1100 #endif
Pokitto 5:7e5c566b1760 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:7e5c566b1760 1102 }
Pokitto 5:7e5c566b1760 1103
Pokitto 5:7e5c566b1760 1104 /** \brief Invalidate D$ by MVA
Pokitto 5:7e5c566b1760 1105
Pokitto 5:7e5c566b1760 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Pokitto 5:7e5c566b1760 1107 */
Pokitto 5:7e5c566b1760 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Pokitto 5:7e5c566b1760 1109 #if 1
Pokitto 5:7e5c566b1760 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Pokitto 5:7e5c566b1760 1111 #else
Pokitto 5:7e5c566b1760 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Pokitto 5:7e5c566b1760 1113 __DCIMVAC = (uint32_t)va;
Pokitto 5:7e5c566b1760 1114 #endif
Pokitto 5:7e5c566b1760 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:7e5c566b1760 1116 }
Pokitto 5:7e5c566b1760 1117
Pokitto 5:7e5c566b1760 1118 /** \brief Clean and Invalidate D$ by MVA
Pokitto 5:7e5c566b1760 1119
Pokitto 5:7e5c566b1760 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Pokitto 5:7e5c566b1760 1121 */
Pokitto 5:7e5c566b1760 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Pokitto 5:7e5c566b1760 1123 #if 1
Pokitto 5:7e5c566b1760 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Pokitto 5:7e5c566b1760 1125 #else
Pokitto 5:7e5c566b1760 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Pokitto 5:7e5c566b1760 1127 __DCCIMVAC = (uint32_t)va;
Pokitto 5:7e5c566b1760 1128 #endif
Pokitto 5:7e5c566b1760 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:7e5c566b1760 1130 }
Pokitto 5:7e5c566b1760 1131
Pokitto 5:7e5c566b1760 1132 /** \brief Clean and Invalidate the entire data or unified cache
Pokitto 5:7e5c566b1760 1133
Pokitto 5:7e5c566b1760 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Pokitto 5:7e5c566b1760 1135 */
Pokitto 5:7e5c566b1760 1136 extern void __v7_all_cache(uint32_t op);
Pokitto 5:7e5c566b1760 1137
Pokitto 5:7e5c566b1760 1138
Pokitto 5:7e5c566b1760 1139 /** \brief Invalidate the whole D$
Pokitto 5:7e5c566b1760 1140
Pokitto 5:7e5c566b1760 1141 DCISW. Invalidate by Set/Way
Pokitto 5:7e5c566b1760 1142 */
Pokitto 5:7e5c566b1760 1143
Pokitto 5:7e5c566b1760 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Pokitto 5:7e5c566b1760 1145 __v7_all_cache(0);
Pokitto 5:7e5c566b1760 1146 }
Pokitto 5:7e5c566b1760 1147
Pokitto 5:7e5c566b1760 1148 /** \brief Clean the whole D$
Pokitto 5:7e5c566b1760 1149
Pokitto 5:7e5c566b1760 1150 DCCSW. Clean by Set/Way
Pokitto 5:7e5c566b1760 1151 */
Pokitto 5:7e5c566b1760 1152
Pokitto 5:7e5c566b1760 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Pokitto 5:7e5c566b1760 1154 __v7_all_cache(1);
Pokitto 5:7e5c566b1760 1155 }
Pokitto 5:7e5c566b1760 1156
Pokitto 5:7e5c566b1760 1157 /** \brief Clean and invalidate the whole D$
Pokitto 5:7e5c566b1760 1158
Pokitto 5:7e5c566b1760 1159 DCCISW. Clean and Invalidate by Set/Way
Pokitto 5:7e5c566b1760 1160 */
Pokitto 5:7e5c566b1760 1161
Pokitto 5:7e5c566b1760 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Pokitto 5:7e5c566b1760 1163 __v7_all_cache(2);
Pokitto 5:7e5c566b1760 1164 }
Pokitto 5:7e5c566b1760 1165
Pokitto 5:7e5c566b1760 1166 #include "core_ca_mmu.h"
Pokitto 5:7e5c566b1760 1167
Pokitto 5:7e5c566b1760 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Pokitto 5:7e5c566b1760 1169
Pokitto 5:7e5c566b1760 1170 #error TASKING Compiler support not implemented for Cortex-A
Pokitto 5:7e5c566b1760 1171
Pokitto 5:7e5c566b1760 1172 #endif
Pokitto 5:7e5c566b1760 1173
Pokitto 5:7e5c566b1760 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Pokitto 5:7e5c566b1760 1175
Pokitto 5:7e5c566b1760 1176
Pokitto 5:7e5c566b1760 1177 #endif /* __CORE_CAFUNC_H__ */