Pokitto_ - PokittoLib with changes to lcd refresh etc.

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Pokitto Community Team / Pokitto_

PokittoLib with changes to lcd refresh etc.

Dependents: Pokittris

Fork of Pokitto by Pokitto Community Team

This is a fork by user @Spinal, and is used in Pokittris for testing. Do not import this to your own program.

mbed-pokitto/targets/cmsis/core_cm4.h@11:02ad9c807a21, 2017-10-15 (annotated)

Committer:: spinal
Date:: Sun Oct 15 18:03:02 2017 +0000
Revision:: 11:02ad9c807a21
Parent:: 5:7e5c566b1760

fixed 4color refreshRegion code

Who changed what in which revision?

User	Revision	Line number	New contents of line
Pokitto	5:7e5c566b1760	1	/************************************************************************//
Pokitto	5:7e5c566b1760	2	* @file core_cm4.h
Pokitto	5:7e5c566b1760	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Pokitto	5:7e5c566b1760	4	* @version V3.20
Pokitto	5:7e5c566b1760	5	* @date 25. February 2013
Pokitto	5:7e5c566b1760	6	*
Pokitto	5:7e5c566b1760	7	* @note
Pokitto	5:7e5c566b1760	8	*
Pokitto	5:7e5c566b1760	9	******************************************************************************/
Pokitto	5:7e5c566b1760	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
Pokitto	5:7e5c566b1760	11
Pokitto	5:7e5c566b1760	12	All rights reserved.
Pokitto	5:7e5c566b1760	13	Redistribution and use in source and binary forms, with or without
Pokitto	5:7e5c566b1760	14	modification, are permitted provided that the following conditions are met:
Pokitto	5:7e5c566b1760	15	- Redistributions of source code must retain the above copyright
Pokitto	5:7e5c566b1760	16	notice, this list of conditions and the following disclaimer.
Pokitto	5:7e5c566b1760	17	- Redistributions in binary form must reproduce the above copyright
Pokitto	5:7e5c566b1760	18	notice, this list of conditions and the following disclaimer in the
Pokitto	5:7e5c566b1760	19	documentation and/or other materials provided with the distribution.
Pokitto	5:7e5c566b1760	20	- Neither the name of ARM nor the names of its contributors may be used
Pokitto	5:7e5c566b1760	21	to endorse or promote products derived from this software without
Pokitto	5:7e5c566b1760	22	specific prior written permission.
Pokitto	5:7e5c566b1760	23	*
Pokitto	5:7e5c566b1760	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Pokitto	5:7e5c566b1760	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Pokitto	5:7e5c566b1760	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Pokitto	5:7e5c566b1760	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Pokitto	5:7e5c566b1760	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Pokitto	5:7e5c566b1760	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Pokitto	5:7e5c566b1760	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Pokitto	5:7e5c566b1760	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Pokitto	5:7e5c566b1760	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Pokitto	5:7e5c566b1760	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Pokitto	5:7e5c566b1760	34	POSSIBILITY OF SUCH DAMAGE.
Pokitto	5:7e5c566b1760	35	---------------------------------------------------------------------------*/
Pokitto	5:7e5c566b1760	36
Pokitto	5:7e5c566b1760	37
Pokitto	5:7e5c566b1760	38	#if defined ( __ICCARM__ )
Pokitto	5:7e5c566b1760	39	#pragma system_include /* treat file as system include file for MISRA check */
Pokitto	5:7e5c566b1760	40	#endif
Pokitto	5:7e5c566b1760	41
Pokitto	5:7e5c566b1760	42	#ifdef __cplusplus
Pokitto	5:7e5c566b1760	43	extern "C" {
Pokitto	5:7e5c566b1760	44	#endif
Pokitto	5:7e5c566b1760	45
Pokitto	5:7e5c566b1760	46	#ifndef __CORE_CM4_H_GENERIC
Pokitto	5:7e5c566b1760	47	#define __CORE_CM4_H_GENERIC
Pokitto	5:7e5c566b1760	48
Pokitto	5:7e5c566b1760	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Pokitto	5:7e5c566b1760	50	CMSIS violates the following MISRA-C:2004 rules:
Pokitto	5:7e5c566b1760	51
Pokitto	5:7e5c566b1760	52	\li Required Rule 8.5, object/function definition in header file.<br>
Pokitto	5:7e5c566b1760	53	Function definitions in header files are used to allow 'inlining'.
Pokitto	5:7e5c566b1760	54
Pokitto	5:7e5c566b1760	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Pokitto	5:7e5c566b1760	56	Unions are used for effective representation of core registers.
Pokitto	5:7e5c566b1760	57
Pokitto	5:7e5c566b1760	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Pokitto	5:7e5c566b1760	59	Function-like macros are used to allow more efficient code.
Pokitto	5:7e5c566b1760	60	*/
Pokitto	5:7e5c566b1760	61
Pokitto	5:7e5c566b1760	62
Pokitto	5:7e5c566b1760	63	/*******************************************************************************
Pokitto	5:7e5c566b1760	64	* CMSIS definitions
Pokitto	5:7e5c566b1760	65	******************************************************************************/
Pokitto	5:7e5c566b1760	66	/** \ingroup Cortex_M4
Pokitto	5:7e5c566b1760	67	@{
Pokitto	5:7e5c566b1760	68	*/
Pokitto	5:7e5c566b1760	69
Pokitto	5:7e5c566b1760	70	/* CMSIS CM4 definitions */
Pokitto	5:7e5c566b1760	71	#define __CM4_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
Pokitto	5:7e5c566b1760	72	#define __CM4_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
Pokitto	5:7e5c566b1760	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
Pokitto	5:7e5c566b1760	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Pokitto	5:7e5c566b1760	75
Pokitto	5:7e5c566b1760	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
Pokitto	5:7e5c566b1760	77
Pokitto	5:7e5c566b1760	78
Pokitto	5:7e5c566b1760	79	#if defined ( __CC_ARM )
Pokitto	5:7e5c566b1760	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Pokitto	5:7e5c566b1760	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Pokitto	5:7e5c566b1760	82	#define __STATIC_INLINE static __inline
Pokitto	5:7e5c566b1760	83
Pokitto	5:7e5c566b1760	84	#elif defined ( __ICCARM__ )
Pokitto	5:7e5c566b1760	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
Pokitto	5:7e5c566b1760	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Pokitto	5:7e5c566b1760	87	#define __STATIC_INLINE static inline
Pokitto	5:7e5c566b1760	88
Pokitto	5:7e5c566b1760	89	#elif defined ( __TMS470__ )
Pokitto	5:7e5c566b1760	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Pokitto	5:7e5c566b1760	91	#define __STATIC_INLINE static inline
Pokitto	5:7e5c566b1760	92
Pokitto	5:7e5c566b1760	93	#elif defined ( __GNUC__ )
Pokitto	5:7e5c566b1760	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
Pokitto	5:7e5c566b1760	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
Pokitto	5:7e5c566b1760	96	#define __STATIC_INLINE static inline
Pokitto	5:7e5c566b1760	97
Pokitto	5:7e5c566b1760	98	#elif defined ( __TASKING__ )
Pokitto	5:7e5c566b1760	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Pokitto	5:7e5c566b1760	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Pokitto	5:7e5c566b1760	101	#define __STATIC_INLINE static inline
Pokitto	5:7e5c566b1760	102
Pokitto	5:7e5c566b1760	103	#endif
Pokitto	5:7e5c566b1760	104
Pokitto	5:7e5c566b1760	105	/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Pokitto	5:7e5c566b1760	106	*/
Pokitto	5:7e5c566b1760	107	#if defined ( __CC_ARM )
Pokitto	5:7e5c566b1760	108	#if defined __TARGET_FPU_VFP
Pokitto	5:7e5c566b1760	109	#if (__FPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	110	#define __FPU_USED 1
Pokitto	5:7e5c566b1760	111	#else
Pokitto	5:7e5c566b1760	112	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	5:7e5c566b1760	113	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	114	#endif
Pokitto	5:7e5c566b1760	115	#else
Pokitto	5:7e5c566b1760	116	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	117	#endif
Pokitto	5:7e5c566b1760	118
Pokitto	5:7e5c566b1760	119	#elif defined ( __ICCARM__ )
Pokitto	5:7e5c566b1760	120	#if defined __ARMVFP__
Pokitto	5:7e5c566b1760	121	#if (__FPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	122	#define __FPU_USED 1
Pokitto	5:7e5c566b1760	123	#else
Pokitto	5:7e5c566b1760	124	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	5:7e5c566b1760	125	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	126	#endif
Pokitto	5:7e5c566b1760	127	#else
Pokitto	5:7e5c566b1760	128	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	129	#endif
Pokitto	5:7e5c566b1760	130
Pokitto	5:7e5c566b1760	131	#elif defined ( __TMS470__ )
Pokitto	5:7e5c566b1760	132	#if defined __TI_VFP_SUPPORT__
Pokitto	5:7e5c566b1760	133	#if (__FPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	134	#define __FPU_USED 1
Pokitto	5:7e5c566b1760	135	#else
Pokitto	5:7e5c566b1760	136	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	5:7e5c566b1760	137	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	138	#endif
Pokitto	5:7e5c566b1760	139	#else
Pokitto	5:7e5c566b1760	140	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	141	#endif
Pokitto	5:7e5c566b1760	142
Pokitto	5:7e5c566b1760	143	#elif defined ( __GNUC__ )
Pokitto	5:7e5c566b1760	144	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Pokitto	5:7e5c566b1760	145	#if (__FPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	146	#define __FPU_USED 1
Pokitto	5:7e5c566b1760	147	#else
Pokitto	5:7e5c566b1760	148	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	5:7e5c566b1760	149	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	150	#endif
Pokitto	5:7e5c566b1760	151	#else
Pokitto	5:7e5c566b1760	152	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	153	#endif
Pokitto	5:7e5c566b1760	154
Pokitto	5:7e5c566b1760	155	#elif defined ( __TASKING__ )
Pokitto	5:7e5c566b1760	156	#if defined __FPU_VFP__
Pokitto	5:7e5c566b1760	157	#if (__FPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	158	#define __FPU_USED 1
Pokitto	5:7e5c566b1760	159	#else
Pokitto	5:7e5c566b1760	160	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto	5:7e5c566b1760	161	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	162	#endif
Pokitto	5:7e5c566b1760	163	#else
Pokitto	5:7e5c566b1760	164	#define __FPU_USED 0
Pokitto	5:7e5c566b1760	165	#endif
Pokitto	5:7e5c566b1760	166	#endif
Pokitto	5:7e5c566b1760	167
Pokitto	5:7e5c566b1760	168	#include <stdint.h> /* standard types definitions */
Pokitto	5:7e5c566b1760	169	#include <core_cmInstr.h> /* Core Instruction Access */
Pokitto	5:7e5c566b1760	170	#include <core_cmFunc.h> /* Core Function Access */
Pokitto	5:7e5c566b1760	171	#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
Pokitto	5:7e5c566b1760	172
Pokitto	5:7e5c566b1760	173	#endif /* __CORE_CM4_H_GENERIC */
Pokitto	5:7e5c566b1760	174
Pokitto	5:7e5c566b1760	175	#ifndef __CMSIS_GENERIC
Pokitto	5:7e5c566b1760	176
Pokitto	5:7e5c566b1760	177	#ifndef __CORE_CM4_H_DEPENDANT
Pokitto	5:7e5c566b1760	178	#define __CORE_CM4_H_DEPENDANT
Pokitto	5:7e5c566b1760	179
Pokitto	5:7e5c566b1760	180	/* check device defines and use defaults */
Pokitto	5:7e5c566b1760	181	#if defined __CHECK_DEVICE_DEFINES
Pokitto	5:7e5c566b1760	182	#ifndef __CM4_REV
Pokitto	5:7e5c566b1760	183	#define __CM4_REV 0x0000
Pokitto	5:7e5c566b1760	184	#warning "__CM4_REV not defined in device header file; using default!"
Pokitto	5:7e5c566b1760	185	#endif
Pokitto	5:7e5c566b1760	186
Pokitto	5:7e5c566b1760	187	#ifndef __FPU_PRESENT
Pokitto	5:7e5c566b1760	188	#define __FPU_PRESENT 0
Pokitto	5:7e5c566b1760	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
Pokitto	5:7e5c566b1760	190	#endif
Pokitto	5:7e5c566b1760	191
Pokitto	5:7e5c566b1760	192	#ifndef __MPU_PRESENT
Pokitto	5:7e5c566b1760	193	#define __MPU_PRESENT 0
Pokitto	5:7e5c566b1760	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
Pokitto	5:7e5c566b1760	195	#endif
Pokitto	5:7e5c566b1760	196
Pokitto	5:7e5c566b1760	197	#ifndef __NVIC_PRIO_BITS
Pokitto	5:7e5c566b1760	198	#define __NVIC_PRIO_BITS 4
Pokitto	5:7e5c566b1760	199	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Pokitto	5:7e5c566b1760	200	#endif
Pokitto	5:7e5c566b1760	201
Pokitto	5:7e5c566b1760	202	#ifndef __Vendor_SysTickConfig
Pokitto	5:7e5c566b1760	203	#define __Vendor_SysTickConfig 0
Pokitto	5:7e5c566b1760	204	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Pokitto	5:7e5c566b1760	205	#endif
Pokitto	5:7e5c566b1760	206	#endif
Pokitto	5:7e5c566b1760	207
Pokitto	5:7e5c566b1760	208	/* IO definitions (access restrictions to peripheral registers) */
Pokitto	5:7e5c566b1760	209	/**
Pokitto	5:7e5c566b1760	210	\defgroup CMSIS_glob_defs CMSIS Global Defines
Pokitto	5:7e5c566b1760	211
Pokitto	5:7e5c566b1760	212	<strong>IO Type Qualifiers</strong> are used
Pokitto	5:7e5c566b1760	213	\li to specify the access to peripheral variables.
Pokitto	5:7e5c566b1760	214	\li for automatic generation of peripheral register debug information.
Pokitto	5:7e5c566b1760	215	*/
Pokitto	5:7e5c566b1760	216	#ifdef __cplusplus
Pokitto	5:7e5c566b1760	217	#define __I volatile /!< Defines 'read only' permissions /
Pokitto	5:7e5c566b1760	218	#else
Pokitto	5:7e5c566b1760	219	#define __I volatile const /!< Defines 'read only' permissions /
Pokitto	5:7e5c566b1760	220	#endif
Pokitto	5:7e5c566b1760	221	#define __O volatile /!< Defines 'write only' permissions /
Pokitto	5:7e5c566b1760	222	#define __IO volatile /!< Defines 'read / write' permissions /
Pokitto	5:7e5c566b1760	223
Pokitto	5:7e5c566b1760	224	/@} end of group Cortex_M4 /
Pokitto	5:7e5c566b1760	225
Pokitto	5:7e5c566b1760	226
Pokitto	5:7e5c566b1760	227
Pokitto	5:7e5c566b1760	228	/*******************************************************************************
Pokitto	5:7e5c566b1760	229	* Register Abstraction
Pokitto	5:7e5c566b1760	230	Core Register contain:
Pokitto	5:7e5c566b1760	231	- Core Register
Pokitto	5:7e5c566b1760	232	- Core NVIC Register
Pokitto	5:7e5c566b1760	233	- Core SCB Register
Pokitto	5:7e5c566b1760	234	- Core SysTick Register
Pokitto	5:7e5c566b1760	235	- Core Debug Register
Pokitto	5:7e5c566b1760	236	- Core MPU Register
Pokitto	5:7e5c566b1760	237	- Core FPU Register
Pokitto	5:7e5c566b1760	238	******************************************************************************/
Pokitto	5:7e5c566b1760	239	/** \defgroup CMSIS_core_register Defines and Type Definitions
Pokitto	5:7e5c566b1760	240	\brief Type definitions and defines for Cortex-M processor based devices.
Pokitto	5:7e5c566b1760	241	*/
Pokitto	5:7e5c566b1760	242
Pokitto	5:7e5c566b1760	243	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	244	\defgroup CMSIS_CORE Status and Control Registers
Pokitto	5:7e5c566b1760	245	\brief Core Register type definitions.
Pokitto	5:7e5c566b1760	246	@{
Pokitto	5:7e5c566b1760	247	*/
Pokitto	5:7e5c566b1760	248
Pokitto	5:7e5c566b1760	249	/** \brief Union type to access the Application Program Status Register (APSR).
Pokitto	5:7e5c566b1760	250	*/
Pokitto	5:7e5c566b1760	251	typedef union
Pokitto	5:7e5c566b1760	252	{
Pokitto	5:7e5c566b1760	253	struct
Pokitto	5:7e5c566b1760	254	{
Pokitto	5:7e5c566b1760	255	#if (__CORTEX_M != 0x04)
Pokitto	5:7e5c566b1760	256	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
Pokitto	5:7e5c566b1760	257	#else
Pokitto	5:7e5c566b1760	258	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Pokitto	5:7e5c566b1760	259	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Pokitto	5:7e5c566b1760	260	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Pokitto	5:7e5c566b1760	261	#endif
Pokitto	5:7e5c566b1760	262	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Pokitto	5:7e5c566b1760	263	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Pokitto	5:7e5c566b1760	264	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Pokitto	5:7e5c566b1760	265	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Pokitto	5:7e5c566b1760	266	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Pokitto	5:7e5c566b1760	267	} b; /!< Structure used for bit access /
Pokitto	5:7e5c566b1760	268	uint32_t w; /!< Type used for word access /
Pokitto	5:7e5c566b1760	269	} APSR_Type;
Pokitto	5:7e5c566b1760	270
Pokitto	5:7e5c566b1760	271
Pokitto	5:7e5c566b1760	272	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Pokitto	5:7e5c566b1760	273	*/
Pokitto	5:7e5c566b1760	274	typedef union
Pokitto	5:7e5c566b1760	275	{
Pokitto	5:7e5c566b1760	276	struct
Pokitto	5:7e5c566b1760	277	{
Pokitto	5:7e5c566b1760	278	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Pokitto	5:7e5c566b1760	279	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Pokitto	5:7e5c566b1760	280	} b; /!< Structure used for bit access /
Pokitto	5:7e5c566b1760	281	uint32_t w; /!< Type used for word access /
Pokitto	5:7e5c566b1760	282	} IPSR_Type;
Pokitto	5:7e5c566b1760	283
Pokitto	5:7e5c566b1760	284
Pokitto	5:7e5c566b1760	285	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Pokitto	5:7e5c566b1760	286	*/
Pokitto	5:7e5c566b1760	287	typedef union
Pokitto	5:7e5c566b1760	288	{
Pokitto	5:7e5c566b1760	289	struct
Pokitto	5:7e5c566b1760	290	{
Pokitto	5:7e5c566b1760	291	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Pokitto	5:7e5c566b1760	292	#if (__CORTEX_M != 0x04)
Pokitto	5:7e5c566b1760	293	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
Pokitto	5:7e5c566b1760	294	#else
Pokitto	5:7e5c566b1760	295	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Pokitto	5:7e5c566b1760	296	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Pokitto	5:7e5c566b1760	297	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Pokitto	5:7e5c566b1760	298	#endif
Pokitto	5:7e5c566b1760	299	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Pokitto	5:7e5c566b1760	300	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Pokitto	5:7e5c566b1760	301	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Pokitto	5:7e5c566b1760	302	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Pokitto	5:7e5c566b1760	303	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Pokitto	5:7e5c566b1760	304	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Pokitto	5:7e5c566b1760	305	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Pokitto	5:7e5c566b1760	306	} b; /!< Structure used for bit access /
Pokitto	5:7e5c566b1760	307	uint32_t w; /!< Type used for word access /
Pokitto	5:7e5c566b1760	308	} xPSR_Type;
Pokitto	5:7e5c566b1760	309
Pokitto	5:7e5c566b1760	310
Pokitto	5:7e5c566b1760	311	/** \brief Union type to access the Control Registers (CONTROL).
Pokitto	5:7e5c566b1760	312	*/
Pokitto	5:7e5c566b1760	313	typedef union
Pokitto	5:7e5c566b1760	314	{
Pokitto	5:7e5c566b1760	315	struct
Pokitto	5:7e5c566b1760	316	{
Pokitto	5:7e5c566b1760	317	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Pokitto	5:7e5c566b1760	318	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Pokitto	5:7e5c566b1760	319	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Pokitto	5:7e5c566b1760	320	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Pokitto	5:7e5c566b1760	321	} b; /!< Structure used for bit access /
Pokitto	5:7e5c566b1760	322	uint32_t w; /!< Type used for word access /
Pokitto	5:7e5c566b1760	323	} CONTROL_Type;
Pokitto	5:7e5c566b1760	324
Pokitto	5:7e5c566b1760	325	/@} end of group CMSIS_CORE /
Pokitto	5:7e5c566b1760	326
Pokitto	5:7e5c566b1760	327
Pokitto	5:7e5c566b1760	328	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	329	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Pokitto	5:7e5c566b1760	330	\brief Type definitions for the NVIC Registers
Pokitto	5:7e5c566b1760	331	@{
Pokitto	5:7e5c566b1760	332	*/
Pokitto	5:7e5c566b1760	333
Pokitto	5:7e5c566b1760	334	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Pokitto	5:7e5c566b1760	335	*/
Pokitto	5:7e5c566b1760	336	typedef struct
Pokitto	5:7e5c566b1760	337	{
Pokitto	5:7e5c566b1760	338	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Pokitto	5:7e5c566b1760	339	uint32_t RESERVED0[24];
Pokitto	5:7e5c566b1760	340	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Pokitto	5:7e5c566b1760	341	uint32_t RSERVED1[24];
Pokitto	5:7e5c566b1760	342	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Pokitto	5:7e5c566b1760	343	uint32_t RESERVED2[24];
Pokitto	5:7e5c566b1760	344	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Pokitto	5:7e5c566b1760	345	uint32_t RESERVED3[24];
Pokitto	5:7e5c566b1760	346	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Pokitto	5:7e5c566b1760	347	uint32_t RESERVED4[56];
Pokitto	5:7e5c566b1760	348	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Pokitto	5:7e5c566b1760	349	uint32_t RESERVED5[644];
Pokitto	5:7e5c566b1760	350	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Pokitto	5:7e5c566b1760	351	} NVIC_Type;
Pokitto	5:7e5c566b1760	352
Pokitto	5:7e5c566b1760	353	/* Software Triggered Interrupt Register Definitions */
Pokitto	5:7e5c566b1760	354	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Pokitto	5:7e5c566b1760	355	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
Pokitto	5:7e5c566b1760	356
Pokitto	5:7e5c566b1760	357	/@} end of group CMSIS_NVIC /
Pokitto	5:7e5c566b1760	358
Pokitto	5:7e5c566b1760	359
Pokitto	5:7e5c566b1760	360	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	361	\defgroup CMSIS_SCB System Control Block (SCB)
Pokitto	5:7e5c566b1760	362	\brief Type definitions for the System Control Block Registers
Pokitto	5:7e5c566b1760	363	@{
Pokitto	5:7e5c566b1760	364	*/
Pokitto	5:7e5c566b1760	365
Pokitto	5:7e5c566b1760	366	/** \brief Structure type to access the System Control Block (SCB).
Pokitto	5:7e5c566b1760	367	*/
Pokitto	5:7e5c566b1760	368	typedef struct
Pokitto	5:7e5c566b1760	369	{
Pokitto	5:7e5c566b1760	370	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Pokitto	5:7e5c566b1760	371	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Pokitto	5:7e5c566b1760	372	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Pokitto	5:7e5c566b1760	373	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Pokitto	5:7e5c566b1760	374	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Pokitto	5:7e5c566b1760	375	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Pokitto	5:7e5c566b1760	376	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Pokitto	5:7e5c566b1760	377	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Pokitto	5:7e5c566b1760	378	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Pokitto	5:7e5c566b1760	379	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Pokitto	5:7e5c566b1760	380	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Pokitto	5:7e5c566b1760	381	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Pokitto	5:7e5c566b1760	382	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Pokitto	5:7e5c566b1760	383	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Pokitto	5:7e5c566b1760	384	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Pokitto	5:7e5c566b1760	385	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Pokitto	5:7e5c566b1760	386	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Pokitto	5:7e5c566b1760	387	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Pokitto	5:7e5c566b1760	388	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Pokitto	5:7e5c566b1760	389	uint32_t RESERVED0[5];
Pokitto	5:7e5c566b1760	390	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Pokitto	5:7e5c566b1760	391	} SCB_Type;
Pokitto	5:7e5c566b1760	392
Pokitto	5:7e5c566b1760	393	/* SCB CPUID Register Definitions */
Pokitto	5:7e5c566b1760	394	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Pokitto	5:7e5c566b1760	395	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Pokitto	5:7e5c566b1760	396
Pokitto	5:7e5c566b1760	397	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Pokitto	5:7e5c566b1760	398	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Pokitto	5:7e5c566b1760	399
Pokitto	5:7e5c566b1760	400	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Pokitto	5:7e5c566b1760	401	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Pokitto	5:7e5c566b1760	402
Pokitto	5:7e5c566b1760	403	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Pokitto	5:7e5c566b1760	404	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Pokitto	5:7e5c566b1760	405
Pokitto	5:7e5c566b1760	406	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Pokitto	5:7e5c566b1760	407	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
Pokitto	5:7e5c566b1760	408
Pokitto	5:7e5c566b1760	409	/* SCB Interrupt Control State Register Definitions */
Pokitto	5:7e5c566b1760	410	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Pokitto	5:7e5c566b1760	411	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Pokitto	5:7e5c566b1760	412
Pokitto	5:7e5c566b1760	413	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Pokitto	5:7e5c566b1760	414	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Pokitto	5:7e5c566b1760	415
Pokitto	5:7e5c566b1760	416	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Pokitto	5:7e5c566b1760	417	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Pokitto	5:7e5c566b1760	418
Pokitto	5:7e5c566b1760	419	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Pokitto	5:7e5c566b1760	420	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Pokitto	5:7e5c566b1760	421
Pokitto	5:7e5c566b1760	422	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Pokitto	5:7e5c566b1760	423	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Pokitto	5:7e5c566b1760	424
Pokitto	5:7e5c566b1760	425	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Pokitto	5:7e5c566b1760	426	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Pokitto	5:7e5c566b1760	427
Pokitto	5:7e5c566b1760	428	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Pokitto	5:7e5c566b1760	429	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Pokitto	5:7e5c566b1760	430
Pokitto	5:7e5c566b1760	431	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Pokitto	5:7e5c566b1760	432	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Pokitto	5:7e5c566b1760	433
Pokitto	5:7e5c566b1760	434	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Pokitto	5:7e5c566b1760	435	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Pokitto	5:7e5c566b1760	436
Pokitto	5:7e5c566b1760	437	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Pokitto	5:7e5c566b1760	438	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
Pokitto	5:7e5c566b1760	439
Pokitto	5:7e5c566b1760	440	/* SCB Vector Table Offset Register Definitions */
Pokitto	5:7e5c566b1760	441	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Pokitto	5:7e5c566b1760	442	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Pokitto	5:7e5c566b1760	443
Pokitto	5:7e5c566b1760	444	/* SCB Application Interrupt and Reset Control Register Definitions */
Pokitto	5:7e5c566b1760	445	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Pokitto	5:7e5c566b1760	446	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Pokitto	5:7e5c566b1760	447
Pokitto	5:7e5c566b1760	448	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Pokitto	5:7e5c566b1760	449	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Pokitto	5:7e5c566b1760	450
Pokitto	5:7e5c566b1760	451	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Pokitto	5:7e5c566b1760	452	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Pokitto	5:7e5c566b1760	453
Pokitto	5:7e5c566b1760	454	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Pokitto	5:7e5c566b1760	455	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Pokitto	5:7e5c566b1760	456
Pokitto	5:7e5c566b1760	457	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Pokitto	5:7e5c566b1760	458	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Pokitto	5:7e5c566b1760	459
Pokitto	5:7e5c566b1760	460	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Pokitto	5:7e5c566b1760	461	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Pokitto	5:7e5c566b1760	462
Pokitto	5:7e5c566b1760	463	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Pokitto	5:7e5c566b1760	464	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
Pokitto	5:7e5c566b1760	465
Pokitto	5:7e5c566b1760	466	/* SCB System Control Register Definitions */
Pokitto	5:7e5c566b1760	467	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Pokitto	5:7e5c566b1760	468	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Pokitto	5:7e5c566b1760	469
Pokitto	5:7e5c566b1760	470	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Pokitto	5:7e5c566b1760	471	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Pokitto	5:7e5c566b1760	472
Pokitto	5:7e5c566b1760	473	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Pokitto	5:7e5c566b1760	474	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Pokitto	5:7e5c566b1760	475
Pokitto	5:7e5c566b1760	476	/* SCB Configuration Control Register Definitions */
Pokitto	5:7e5c566b1760	477	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Pokitto	5:7e5c566b1760	478	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Pokitto	5:7e5c566b1760	479
Pokitto	5:7e5c566b1760	480	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Pokitto	5:7e5c566b1760	481	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Pokitto	5:7e5c566b1760	482
Pokitto	5:7e5c566b1760	483	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Pokitto	5:7e5c566b1760	484	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Pokitto	5:7e5c566b1760	485
Pokitto	5:7e5c566b1760	486	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Pokitto	5:7e5c566b1760	487	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Pokitto	5:7e5c566b1760	488
Pokitto	5:7e5c566b1760	489	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Pokitto	5:7e5c566b1760	490	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Pokitto	5:7e5c566b1760	491
Pokitto	5:7e5c566b1760	492	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Pokitto	5:7e5c566b1760	493	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
Pokitto	5:7e5c566b1760	494
Pokitto	5:7e5c566b1760	495	/* SCB System Handler Control and State Register Definitions */
Pokitto	5:7e5c566b1760	496	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Pokitto	5:7e5c566b1760	497	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Pokitto	5:7e5c566b1760	498
Pokitto	5:7e5c566b1760	499	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Pokitto	5:7e5c566b1760	500	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Pokitto	5:7e5c566b1760	501
Pokitto	5:7e5c566b1760	502	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Pokitto	5:7e5c566b1760	503	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Pokitto	5:7e5c566b1760	504
Pokitto	5:7e5c566b1760	505	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Pokitto	5:7e5c566b1760	506	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Pokitto	5:7e5c566b1760	507
Pokitto	5:7e5c566b1760	508	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Pokitto	5:7e5c566b1760	509	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Pokitto	5:7e5c566b1760	510
Pokitto	5:7e5c566b1760	511	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Pokitto	5:7e5c566b1760	512	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Pokitto	5:7e5c566b1760	513
Pokitto	5:7e5c566b1760	514	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Pokitto	5:7e5c566b1760	515	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Pokitto	5:7e5c566b1760	516
Pokitto	5:7e5c566b1760	517	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Pokitto	5:7e5c566b1760	518	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Pokitto	5:7e5c566b1760	519
Pokitto	5:7e5c566b1760	520	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Pokitto	5:7e5c566b1760	521	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Pokitto	5:7e5c566b1760	522
Pokitto	5:7e5c566b1760	523	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Pokitto	5:7e5c566b1760	524	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Pokitto	5:7e5c566b1760	525
Pokitto	5:7e5c566b1760	526	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Pokitto	5:7e5c566b1760	527	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Pokitto	5:7e5c566b1760	528
Pokitto	5:7e5c566b1760	529	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Pokitto	5:7e5c566b1760	530	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Pokitto	5:7e5c566b1760	531
Pokitto	5:7e5c566b1760	532	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Pokitto	5:7e5c566b1760	533	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Pokitto	5:7e5c566b1760	534
Pokitto	5:7e5c566b1760	535	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Pokitto	5:7e5c566b1760	536	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
Pokitto	5:7e5c566b1760	537
Pokitto	5:7e5c566b1760	538	/* SCB Configurable Fault Status Registers Definitions */
Pokitto	5:7e5c566b1760	539	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Pokitto	5:7e5c566b1760	540	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Pokitto	5:7e5c566b1760	541
Pokitto	5:7e5c566b1760	542	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Pokitto	5:7e5c566b1760	543	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Pokitto	5:7e5c566b1760	544
Pokitto	5:7e5c566b1760	545	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Pokitto	5:7e5c566b1760	546	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Pokitto	5:7e5c566b1760	547
Pokitto	5:7e5c566b1760	548	/* SCB Hard Fault Status Registers Definitions */
Pokitto	5:7e5c566b1760	549	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Pokitto	5:7e5c566b1760	550	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Pokitto	5:7e5c566b1760	551
Pokitto	5:7e5c566b1760	552	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Pokitto	5:7e5c566b1760	553	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Pokitto	5:7e5c566b1760	554
Pokitto	5:7e5c566b1760	555	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Pokitto	5:7e5c566b1760	556	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Pokitto	5:7e5c566b1760	557
Pokitto	5:7e5c566b1760	558	/* SCB Debug Fault Status Register Definitions */
Pokitto	5:7e5c566b1760	559	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Pokitto	5:7e5c566b1760	560	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Pokitto	5:7e5c566b1760	561
Pokitto	5:7e5c566b1760	562	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Pokitto	5:7e5c566b1760	563	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Pokitto	5:7e5c566b1760	564
Pokitto	5:7e5c566b1760	565	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Pokitto	5:7e5c566b1760	566	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Pokitto	5:7e5c566b1760	567
Pokitto	5:7e5c566b1760	568	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Pokitto	5:7e5c566b1760	569	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Pokitto	5:7e5c566b1760	570
Pokitto	5:7e5c566b1760	571	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Pokitto	5:7e5c566b1760	572	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
Pokitto	5:7e5c566b1760	573
Pokitto	5:7e5c566b1760	574	/@} end of group CMSIS_SCB /
Pokitto	5:7e5c566b1760	575
Pokitto	5:7e5c566b1760	576
Pokitto	5:7e5c566b1760	577	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	578	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Pokitto	5:7e5c566b1760	579	\brief Type definitions for the System Control and ID Register not in the SCB
Pokitto	5:7e5c566b1760	580	@{
Pokitto	5:7e5c566b1760	581	*/
Pokitto	5:7e5c566b1760	582
Pokitto	5:7e5c566b1760	583	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Pokitto	5:7e5c566b1760	584	*/
Pokitto	5:7e5c566b1760	585	typedef struct
Pokitto	5:7e5c566b1760	586	{
Pokitto	5:7e5c566b1760	587	uint32_t RESERVED0[1];
Pokitto	5:7e5c566b1760	588	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Pokitto	5:7e5c566b1760	589	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Pokitto	5:7e5c566b1760	590	} SCnSCB_Type;
Pokitto	5:7e5c566b1760	591
Pokitto	5:7e5c566b1760	592	/* Interrupt Controller Type Register Definitions */
Pokitto	5:7e5c566b1760	593	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Pokitto	5:7e5c566b1760	594	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
Pokitto	5:7e5c566b1760	595
Pokitto	5:7e5c566b1760	596	/* Auxiliary Control Register Definitions */
Pokitto	5:7e5c566b1760	597	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
Pokitto	5:7e5c566b1760	598	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
Pokitto	5:7e5c566b1760	599
Pokitto	5:7e5c566b1760	600	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
Pokitto	5:7e5c566b1760	601	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
Pokitto	5:7e5c566b1760	602
Pokitto	5:7e5c566b1760	603	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Pokitto	5:7e5c566b1760	604	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Pokitto	5:7e5c566b1760	605
Pokitto	5:7e5c566b1760	606	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
Pokitto	5:7e5c566b1760	607	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
Pokitto	5:7e5c566b1760	608
Pokitto	5:7e5c566b1760	609	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Pokitto	5:7e5c566b1760	610	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
Pokitto	5:7e5c566b1760	611
Pokitto	5:7e5c566b1760	612	/@} end of group CMSIS_SCnotSCB /
Pokitto	5:7e5c566b1760	613
Pokitto	5:7e5c566b1760	614
Pokitto	5:7e5c566b1760	615	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	616	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Pokitto	5:7e5c566b1760	617	\brief Type definitions for the System Timer Registers.
Pokitto	5:7e5c566b1760	618	@{
Pokitto	5:7e5c566b1760	619	*/
Pokitto	5:7e5c566b1760	620
Pokitto	5:7e5c566b1760	621	/** \brief Structure type to access the System Timer (SysTick).
Pokitto	5:7e5c566b1760	622	*/
Pokitto	5:7e5c566b1760	623	typedef struct
Pokitto	5:7e5c566b1760	624	{
Pokitto	5:7e5c566b1760	625	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Pokitto	5:7e5c566b1760	626	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Pokitto	5:7e5c566b1760	627	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Pokitto	5:7e5c566b1760	628	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Pokitto	5:7e5c566b1760	629	} SysTick_Type;
Pokitto	5:7e5c566b1760	630
Pokitto	5:7e5c566b1760	631	/* SysTick Control / Status Register Definitions */
Pokitto	5:7e5c566b1760	632	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Pokitto	5:7e5c566b1760	633	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Pokitto	5:7e5c566b1760	634
Pokitto	5:7e5c566b1760	635	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Pokitto	5:7e5c566b1760	636	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Pokitto	5:7e5c566b1760	637
Pokitto	5:7e5c566b1760	638	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Pokitto	5:7e5c566b1760	639	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Pokitto	5:7e5c566b1760	640
Pokitto	5:7e5c566b1760	641	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Pokitto	5:7e5c566b1760	642	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
Pokitto	5:7e5c566b1760	643
Pokitto	5:7e5c566b1760	644	/* SysTick Reload Register Definitions */
Pokitto	5:7e5c566b1760	645	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Pokitto	5:7e5c566b1760	646	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
Pokitto	5:7e5c566b1760	647
Pokitto	5:7e5c566b1760	648	/* SysTick Current Register Definitions */
Pokitto	5:7e5c566b1760	649	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Pokitto	5:7e5c566b1760	650	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
Pokitto	5:7e5c566b1760	651
Pokitto	5:7e5c566b1760	652	/* SysTick Calibration Register Definitions */
Pokitto	5:7e5c566b1760	653	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Pokitto	5:7e5c566b1760	654	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Pokitto	5:7e5c566b1760	655
Pokitto	5:7e5c566b1760	656	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Pokitto	5:7e5c566b1760	657	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Pokitto	5:7e5c566b1760	658
Pokitto	5:7e5c566b1760	659	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Pokitto	5:7e5c566b1760	660	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
Pokitto	5:7e5c566b1760	661
Pokitto	5:7e5c566b1760	662	/@} end of group CMSIS_SysTick /
Pokitto	5:7e5c566b1760	663
Pokitto	5:7e5c566b1760	664
Pokitto	5:7e5c566b1760	665	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	666	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Pokitto	5:7e5c566b1760	667	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Pokitto	5:7e5c566b1760	668	@{
Pokitto	5:7e5c566b1760	669	*/
Pokitto	5:7e5c566b1760	670
Pokitto	5:7e5c566b1760	671	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Pokitto	5:7e5c566b1760	672	*/
Pokitto	5:7e5c566b1760	673	typedef struct
Pokitto	5:7e5c566b1760	674	{
Pokitto	5:7e5c566b1760	675	__O union
Pokitto	5:7e5c566b1760	676	{
Pokitto	5:7e5c566b1760	677	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Pokitto	5:7e5c566b1760	678	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Pokitto	5:7e5c566b1760	679	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Pokitto	5:7e5c566b1760	680	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Pokitto	5:7e5c566b1760	681	uint32_t RESERVED0[864];
Pokitto	5:7e5c566b1760	682	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Pokitto	5:7e5c566b1760	683	uint32_t RESERVED1[15];
Pokitto	5:7e5c566b1760	684	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Pokitto	5:7e5c566b1760	685	uint32_t RESERVED2[15];
Pokitto	5:7e5c566b1760	686	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Pokitto	5:7e5c566b1760	687	uint32_t RESERVED3[29];
Pokitto	5:7e5c566b1760	688	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Pokitto	5:7e5c566b1760	689	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Pokitto	5:7e5c566b1760	690	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Pokitto	5:7e5c566b1760	691	uint32_t RESERVED4[43];
Pokitto	5:7e5c566b1760	692	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Pokitto	5:7e5c566b1760	693	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Pokitto	5:7e5c566b1760	694	uint32_t RESERVED5[6];
Pokitto	5:7e5c566b1760	695	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Pokitto	5:7e5c566b1760	696	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Pokitto	5:7e5c566b1760	697	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Pokitto	5:7e5c566b1760	698	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Pokitto	5:7e5c566b1760	699	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Pokitto	5:7e5c566b1760	700	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Pokitto	5:7e5c566b1760	701	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Pokitto	5:7e5c566b1760	702	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Pokitto	5:7e5c566b1760	703	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Pokitto	5:7e5c566b1760	704	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Pokitto	5:7e5c566b1760	705	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Pokitto	5:7e5c566b1760	706	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Pokitto	5:7e5c566b1760	707	} ITM_Type;
Pokitto	5:7e5c566b1760	708
Pokitto	5:7e5c566b1760	709	/* ITM Trace Privilege Register Definitions */
Pokitto	5:7e5c566b1760	710	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Pokitto	5:7e5c566b1760	711	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
Pokitto	5:7e5c566b1760	712
Pokitto	5:7e5c566b1760	713	/* ITM Trace Control Register Definitions */
Pokitto	5:7e5c566b1760	714	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Pokitto	5:7e5c566b1760	715	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Pokitto	5:7e5c566b1760	716
Pokitto	5:7e5c566b1760	717	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Pokitto	5:7e5c566b1760	718	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Pokitto	5:7e5c566b1760	719
Pokitto	5:7e5c566b1760	720	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Pokitto	5:7e5c566b1760	721	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Pokitto	5:7e5c566b1760	722
Pokitto	5:7e5c566b1760	723	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Pokitto	5:7e5c566b1760	724	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Pokitto	5:7e5c566b1760	725
Pokitto	5:7e5c566b1760	726	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Pokitto	5:7e5c566b1760	727	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Pokitto	5:7e5c566b1760	728
Pokitto	5:7e5c566b1760	729	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Pokitto	5:7e5c566b1760	730	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Pokitto	5:7e5c566b1760	731
Pokitto	5:7e5c566b1760	732	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Pokitto	5:7e5c566b1760	733	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Pokitto	5:7e5c566b1760	734
Pokitto	5:7e5c566b1760	735	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Pokitto	5:7e5c566b1760	736	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Pokitto	5:7e5c566b1760	737
Pokitto	5:7e5c566b1760	738	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Pokitto	5:7e5c566b1760	739	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
Pokitto	5:7e5c566b1760	740
Pokitto	5:7e5c566b1760	741	/* ITM Integration Write Register Definitions */
Pokitto	5:7e5c566b1760	742	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Pokitto	5:7e5c566b1760	743	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
Pokitto	5:7e5c566b1760	744
Pokitto	5:7e5c566b1760	745	/* ITM Integration Read Register Definitions */
Pokitto	5:7e5c566b1760	746	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Pokitto	5:7e5c566b1760	747	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
Pokitto	5:7e5c566b1760	748
Pokitto	5:7e5c566b1760	749	/* ITM Integration Mode Control Register Definitions */
Pokitto	5:7e5c566b1760	750	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Pokitto	5:7e5c566b1760	751	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
Pokitto	5:7e5c566b1760	752
Pokitto	5:7e5c566b1760	753	/* ITM Lock Status Register Definitions */
Pokitto	5:7e5c566b1760	754	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Pokitto	5:7e5c566b1760	755	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Pokitto	5:7e5c566b1760	756
Pokitto	5:7e5c566b1760	757	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Pokitto	5:7e5c566b1760	758	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Pokitto	5:7e5c566b1760	759
Pokitto	5:7e5c566b1760	760	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Pokitto	5:7e5c566b1760	761	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
Pokitto	5:7e5c566b1760	762
Pokitto	5:7e5c566b1760	763	/@}/ /* end of group CMSIS_ITM */
Pokitto	5:7e5c566b1760	764
Pokitto	5:7e5c566b1760	765
Pokitto	5:7e5c566b1760	766	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	767	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Pokitto	5:7e5c566b1760	768	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Pokitto	5:7e5c566b1760	769	@{
Pokitto	5:7e5c566b1760	770	*/
Pokitto	5:7e5c566b1760	771
Pokitto	5:7e5c566b1760	772	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Pokitto	5:7e5c566b1760	773	*/
Pokitto	5:7e5c566b1760	774	typedef struct
Pokitto	5:7e5c566b1760	775	{
Pokitto	5:7e5c566b1760	776	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Pokitto	5:7e5c566b1760	777	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Pokitto	5:7e5c566b1760	778	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Pokitto	5:7e5c566b1760	779	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Pokitto	5:7e5c566b1760	780	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Pokitto	5:7e5c566b1760	781	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Pokitto	5:7e5c566b1760	782	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Pokitto	5:7e5c566b1760	783	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Pokitto	5:7e5c566b1760	784	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Pokitto	5:7e5c566b1760	785	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Pokitto	5:7e5c566b1760	786	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Pokitto	5:7e5c566b1760	787	uint32_t RESERVED0[1];
Pokitto	5:7e5c566b1760	788	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Pokitto	5:7e5c566b1760	789	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Pokitto	5:7e5c566b1760	790	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Pokitto	5:7e5c566b1760	791	uint32_t RESERVED1[1];
Pokitto	5:7e5c566b1760	792	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Pokitto	5:7e5c566b1760	793	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Pokitto	5:7e5c566b1760	794	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Pokitto	5:7e5c566b1760	795	uint32_t RESERVED2[1];
Pokitto	5:7e5c566b1760	796	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Pokitto	5:7e5c566b1760	797	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Pokitto	5:7e5c566b1760	798	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Pokitto	5:7e5c566b1760	799	} DWT_Type;
Pokitto	5:7e5c566b1760	800
Pokitto	5:7e5c566b1760	801	/* DWT Control Register Definitions */
Pokitto	5:7e5c566b1760	802	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Pokitto	5:7e5c566b1760	803	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Pokitto	5:7e5c566b1760	804
Pokitto	5:7e5c566b1760	805	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Pokitto	5:7e5c566b1760	806	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Pokitto	5:7e5c566b1760	807
Pokitto	5:7e5c566b1760	808	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Pokitto	5:7e5c566b1760	809	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Pokitto	5:7e5c566b1760	810
Pokitto	5:7e5c566b1760	811	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Pokitto	5:7e5c566b1760	812	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Pokitto	5:7e5c566b1760	813
Pokitto	5:7e5c566b1760	814	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Pokitto	5:7e5c566b1760	815	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Pokitto	5:7e5c566b1760	816
Pokitto	5:7e5c566b1760	817	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Pokitto	5:7e5c566b1760	818	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Pokitto	5:7e5c566b1760	819
Pokitto	5:7e5c566b1760	820	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Pokitto	5:7e5c566b1760	821	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Pokitto	5:7e5c566b1760	822
Pokitto	5:7e5c566b1760	823	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Pokitto	5:7e5c566b1760	824	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Pokitto	5:7e5c566b1760	825
Pokitto	5:7e5c566b1760	826	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Pokitto	5:7e5c566b1760	827	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Pokitto	5:7e5c566b1760	828
Pokitto	5:7e5c566b1760	829	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Pokitto	5:7e5c566b1760	830	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Pokitto	5:7e5c566b1760	831
Pokitto	5:7e5c566b1760	832	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Pokitto	5:7e5c566b1760	833	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Pokitto	5:7e5c566b1760	834
Pokitto	5:7e5c566b1760	835	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Pokitto	5:7e5c566b1760	836	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Pokitto	5:7e5c566b1760	837
Pokitto	5:7e5c566b1760	838	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Pokitto	5:7e5c566b1760	839	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Pokitto	5:7e5c566b1760	840
Pokitto	5:7e5c566b1760	841	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Pokitto	5:7e5c566b1760	842	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Pokitto	5:7e5c566b1760	843
Pokitto	5:7e5c566b1760	844	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Pokitto	5:7e5c566b1760	845	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Pokitto	5:7e5c566b1760	846
Pokitto	5:7e5c566b1760	847	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Pokitto	5:7e5c566b1760	848	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Pokitto	5:7e5c566b1760	849
Pokitto	5:7e5c566b1760	850	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Pokitto	5:7e5c566b1760	851	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Pokitto	5:7e5c566b1760	852
Pokitto	5:7e5c566b1760	853	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Pokitto	5:7e5c566b1760	854	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
Pokitto	5:7e5c566b1760	855
Pokitto	5:7e5c566b1760	856	/* DWT CPI Count Register Definitions */
Pokitto	5:7e5c566b1760	857	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Pokitto	5:7e5c566b1760	858	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
Pokitto	5:7e5c566b1760	859
Pokitto	5:7e5c566b1760	860	/* DWT Exception Overhead Count Register Definitions */
Pokitto	5:7e5c566b1760	861	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Pokitto	5:7e5c566b1760	862	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
Pokitto	5:7e5c566b1760	863
Pokitto	5:7e5c566b1760	864	/* DWT Sleep Count Register Definitions */
Pokitto	5:7e5c566b1760	865	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Pokitto	5:7e5c566b1760	866	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Pokitto	5:7e5c566b1760	867
Pokitto	5:7e5c566b1760	868	/* DWT LSU Count Register Definitions */
Pokitto	5:7e5c566b1760	869	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Pokitto	5:7e5c566b1760	870	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
Pokitto	5:7e5c566b1760	871
Pokitto	5:7e5c566b1760	872	/* DWT Folded-instruction Count Register Definitions */
Pokitto	5:7e5c566b1760	873	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Pokitto	5:7e5c566b1760	874	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
Pokitto	5:7e5c566b1760	875
Pokitto	5:7e5c566b1760	876	/* DWT Comparator Mask Register Definitions */
Pokitto	5:7e5c566b1760	877	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Pokitto	5:7e5c566b1760	878	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
Pokitto	5:7e5c566b1760	879
Pokitto	5:7e5c566b1760	880	/* DWT Comparator Function Register Definitions */
Pokitto	5:7e5c566b1760	881	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Pokitto	5:7e5c566b1760	882	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Pokitto	5:7e5c566b1760	883
Pokitto	5:7e5c566b1760	884	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Pokitto	5:7e5c566b1760	885	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Pokitto	5:7e5c566b1760	886
Pokitto	5:7e5c566b1760	887	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Pokitto	5:7e5c566b1760	888	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Pokitto	5:7e5c566b1760	889
Pokitto	5:7e5c566b1760	890	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Pokitto	5:7e5c566b1760	891	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Pokitto	5:7e5c566b1760	892
Pokitto	5:7e5c566b1760	893	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Pokitto	5:7e5c566b1760	894	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Pokitto	5:7e5c566b1760	895
Pokitto	5:7e5c566b1760	896	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Pokitto	5:7e5c566b1760	897	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Pokitto	5:7e5c566b1760	898
Pokitto	5:7e5c566b1760	899	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Pokitto	5:7e5c566b1760	900	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Pokitto	5:7e5c566b1760	901
Pokitto	5:7e5c566b1760	902	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Pokitto	5:7e5c566b1760	903	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Pokitto	5:7e5c566b1760	904
Pokitto	5:7e5c566b1760	905	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Pokitto	5:7e5c566b1760	906	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
Pokitto	5:7e5c566b1760	907
Pokitto	5:7e5c566b1760	908	/@}/ /* end of group CMSIS_DWT */
Pokitto	5:7e5c566b1760	909
Pokitto	5:7e5c566b1760	910
Pokitto	5:7e5c566b1760	911	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	912	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Pokitto	5:7e5c566b1760	913	\brief Type definitions for the Trace Port Interface (TPI)
Pokitto	5:7e5c566b1760	914	@{
Pokitto	5:7e5c566b1760	915	*/
Pokitto	5:7e5c566b1760	916
Pokitto	5:7e5c566b1760	917	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Pokitto	5:7e5c566b1760	918	*/
Pokitto	5:7e5c566b1760	919	typedef struct
Pokitto	5:7e5c566b1760	920	{
Pokitto	5:7e5c566b1760	921	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Pokitto	5:7e5c566b1760	922	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Pokitto	5:7e5c566b1760	923	uint32_t RESERVED0[2];
Pokitto	5:7e5c566b1760	924	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Pokitto	5:7e5c566b1760	925	uint32_t RESERVED1[55];
Pokitto	5:7e5c566b1760	926	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Pokitto	5:7e5c566b1760	927	uint32_t RESERVED2[131];
Pokitto	5:7e5c566b1760	928	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Pokitto	5:7e5c566b1760	929	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Pokitto	5:7e5c566b1760	930	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Pokitto	5:7e5c566b1760	931	uint32_t RESERVED3[759];
Pokitto	5:7e5c566b1760	932	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Pokitto	5:7e5c566b1760	933	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Pokitto	5:7e5c566b1760	934	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Pokitto	5:7e5c566b1760	935	uint32_t RESERVED4[1];
Pokitto	5:7e5c566b1760	936	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Pokitto	5:7e5c566b1760	937	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Pokitto	5:7e5c566b1760	938	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Pokitto	5:7e5c566b1760	939	uint32_t RESERVED5[39];
Pokitto	5:7e5c566b1760	940	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Pokitto	5:7e5c566b1760	941	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Pokitto	5:7e5c566b1760	942	uint32_t RESERVED7[8];
Pokitto	5:7e5c566b1760	943	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Pokitto	5:7e5c566b1760	944	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Pokitto	5:7e5c566b1760	945	} TPI_Type;
Pokitto	5:7e5c566b1760	946
Pokitto	5:7e5c566b1760	947	/* TPI Asynchronous Clock Prescaler Register Definitions */
Pokitto	5:7e5c566b1760	948	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Pokitto	5:7e5c566b1760	949	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
Pokitto	5:7e5c566b1760	950
Pokitto	5:7e5c566b1760	951	/* TPI Selected Pin Protocol Register Definitions */
Pokitto	5:7e5c566b1760	952	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Pokitto	5:7e5c566b1760	953	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
Pokitto	5:7e5c566b1760	954
Pokitto	5:7e5c566b1760	955	/* TPI Formatter and Flush Status Register Definitions */
Pokitto	5:7e5c566b1760	956	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Pokitto	5:7e5c566b1760	957	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Pokitto	5:7e5c566b1760	958
Pokitto	5:7e5c566b1760	959	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Pokitto	5:7e5c566b1760	960	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Pokitto	5:7e5c566b1760	961
Pokitto	5:7e5c566b1760	962	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Pokitto	5:7e5c566b1760	963	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Pokitto	5:7e5c566b1760	964
Pokitto	5:7e5c566b1760	965	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Pokitto	5:7e5c566b1760	966	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
Pokitto	5:7e5c566b1760	967
Pokitto	5:7e5c566b1760	968	/* TPI Formatter and Flush Control Register Definitions */
Pokitto	5:7e5c566b1760	969	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Pokitto	5:7e5c566b1760	970	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Pokitto	5:7e5c566b1760	971
Pokitto	5:7e5c566b1760	972	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Pokitto	5:7e5c566b1760	973	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Pokitto	5:7e5c566b1760	974
Pokitto	5:7e5c566b1760	975	/* TPI TRIGGER Register Definitions */
Pokitto	5:7e5c566b1760	976	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Pokitto	5:7e5c566b1760	977	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
Pokitto	5:7e5c566b1760	978
Pokitto	5:7e5c566b1760	979	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Pokitto	5:7e5c566b1760	980	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Pokitto	5:7e5c566b1760	981	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Pokitto	5:7e5c566b1760	982
Pokitto	5:7e5c566b1760	983	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Pokitto	5:7e5c566b1760	984	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Pokitto	5:7e5c566b1760	985
Pokitto	5:7e5c566b1760	986	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Pokitto	5:7e5c566b1760	987	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Pokitto	5:7e5c566b1760	988
Pokitto	5:7e5c566b1760	989	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Pokitto	5:7e5c566b1760	990	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Pokitto	5:7e5c566b1760	991
Pokitto	5:7e5c566b1760	992	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Pokitto	5:7e5c566b1760	993	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Pokitto	5:7e5c566b1760	994
Pokitto	5:7e5c566b1760	995	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Pokitto	5:7e5c566b1760	996	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Pokitto	5:7e5c566b1760	997
Pokitto	5:7e5c566b1760	998	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Pokitto	5:7e5c566b1760	999	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
Pokitto	5:7e5c566b1760	1000
Pokitto	5:7e5c566b1760	1001	/* TPI ITATBCTR2 Register Definitions */
Pokitto	5:7e5c566b1760	1002	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Pokitto	5:7e5c566b1760	1003	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
Pokitto	5:7e5c566b1760	1004
Pokitto	5:7e5c566b1760	1005	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Pokitto	5:7e5c566b1760	1006	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Pokitto	5:7e5c566b1760	1007	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Pokitto	5:7e5c566b1760	1008
Pokitto	5:7e5c566b1760	1009	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Pokitto	5:7e5c566b1760	1010	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Pokitto	5:7e5c566b1760	1011
Pokitto	5:7e5c566b1760	1012	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Pokitto	5:7e5c566b1760	1013	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Pokitto	5:7e5c566b1760	1014
Pokitto	5:7e5c566b1760	1015	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Pokitto	5:7e5c566b1760	1016	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Pokitto	5:7e5c566b1760	1017
Pokitto	5:7e5c566b1760	1018	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Pokitto	5:7e5c566b1760	1019	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Pokitto	5:7e5c566b1760	1020
Pokitto	5:7e5c566b1760	1021	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Pokitto	5:7e5c566b1760	1022	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Pokitto	5:7e5c566b1760	1023
Pokitto	5:7e5c566b1760	1024	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Pokitto	5:7e5c566b1760	1025	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
Pokitto	5:7e5c566b1760	1026
Pokitto	5:7e5c566b1760	1027	/* TPI ITATBCTR0 Register Definitions */
Pokitto	5:7e5c566b1760	1028	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Pokitto	5:7e5c566b1760	1029	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
Pokitto	5:7e5c566b1760	1030
Pokitto	5:7e5c566b1760	1031	/* TPI Integration Mode Control Register Definitions */
Pokitto	5:7e5c566b1760	1032	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Pokitto	5:7e5c566b1760	1033	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
Pokitto	5:7e5c566b1760	1034
Pokitto	5:7e5c566b1760	1035	/* TPI DEVID Register Definitions */
Pokitto	5:7e5c566b1760	1036	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Pokitto	5:7e5c566b1760	1037	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Pokitto	5:7e5c566b1760	1038
Pokitto	5:7e5c566b1760	1039	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Pokitto	5:7e5c566b1760	1040	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Pokitto	5:7e5c566b1760	1041
Pokitto	5:7e5c566b1760	1042	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Pokitto	5:7e5c566b1760	1043	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Pokitto	5:7e5c566b1760	1044
Pokitto	5:7e5c566b1760	1045	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Pokitto	5:7e5c566b1760	1046	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Pokitto	5:7e5c566b1760	1047
Pokitto	5:7e5c566b1760	1048	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Pokitto	5:7e5c566b1760	1049	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Pokitto	5:7e5c566b1760	1050
Pokitto	5:7e5c566b1760	1051	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Pokitto	5:7e5c566b1760	1052	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
Pokitto	5:7e5c566b1760	1053
Pokitto	5:7e5c566b1760	1054	/* TPI DEVTYPE Register Definitions */
Pokitto	5:7e5c566b1760	1055	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Pokitto	5:7e5c566b1760	1056	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
Pokitto	5:7e5c566b1760	1057
Pokitto	5:7e5c566b1760	1058	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Pokitto	5:7e5c566b1760	1059	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Pokitto	5:7e5c566b1760	1060
Pokitto	5:7e5c566b1760	1061	/@}/ /* end of group CMSIS_TPI */
Pokitto	5:7e5c566b1760	1062
Pokitto	5:7e5c566b1760	1063
Pokitto	5:7e5c566b1760	1064	#if (__MPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	1065	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	1066	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Pokitto	5:7e5c566b1760	1067	\brief Type definitions for the Memory Protection Unit (MPU)
Pokitto	5:7e5c566b1760	1068	@{
Pokitto	5:7e5c566b1760	1069	*/
Pokitto	5:7e5c566b1760	1070
Pokitto	5:7e5c566b1760	1071	/** \brief Structure type to access the Memory Protection Unit (MPU).
Pokitto	5:7e5c566b1760	1072	*/
Pokitto	5:7e5c566b1760	1073	typedef struct
Pokitto	5:7e5c566b1760	1074	{
Pokitto	5:7e5c566b1760	1075	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Pokitto	5:7e5c566b1760	1076	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Pokitto	5:7e5c566b1760	1077	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Pokitto	5:7e5c566b1760	1078	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Pokitto	5:7e5c566b1760	1079	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Pokitto	5:7e5c566b1760	1080	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Pokitto	5:7e5c566b1760	1081	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Pokitto	5:7e5c566b1760	1082	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Pokitto	5:7e5c566b1760	1083	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Pokitto	5:7e5c566b1760	1084	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Pokitto	5:7e5c566b1760	1085	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Pokitto	5:7e5c566b1760	1086	} MPU_Type;
Pokitto	5:7e5c566b1760	1087
Pokitto	5:7e5c566b1760	1088	/* MPU Type Register */
Pokitto	5:7e5c566b1760	1089	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Pokitto	5:7e5c566b1760	1090	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Pokitto	5:7e5c566b1760	1091
Pokitto	5:7e5c566b1760	1092	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Pokitto	5:7e5c566b1760	1093	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Pokitto	5:7e5c566b1760	1094
Pokitto	5:7e5c566b1760	1095	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Pokitto	5:7e5c566b1760	1096	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
Pokitto	5:7e5c566b1760	1097
Pokitto	5:7e5c566b1760	1098	/* MPU Control Register */
Pokitto	5:7e5c566b1760	1099	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Pokitto	5:7e5c566b1760	1100	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Pokitto	5:7e5c566b1760	1101
Pokitto	5:7e5c566b1760	1102	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Pokitto	5:7e5c566b1760	1103	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Pokitto	5:7e5c566b1760	1104
Pokitto	5:7e5c566b1760	1105	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Pokitto	5:7e5c566b1760	1106	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
Pokitto	5:7e5c566b1760	1107
Pokitto	5:7e5c566b1760	1108	/* MPU Region Number Register */
Pokitto	5:7e5c566b1760	1109	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Pokitto	5:7e5c566b1760	1110	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
Pokitto	5:7e5c566b1760	1111
Pokitto	5:7e5c566b1760	1112	/* MPU Region Base Address Register */
Pokitto	5:7e5c566b1760	1113	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Pokitto	5:7e5c566b1760	1114	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Pokitto	5:7e5c566b1760	1115
Pokitto	5:7e5c566b1760	1116	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Pokitto	5:7e5c566b1760	1117	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Pokitto	5:7e5c566b1760	1118
Pokitto	5:7e5c566b1760	1119	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Pokitto	5:7e5c566b1760	1120	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
Pokitto	5:7e5c566b1760	1121
Pokitto	5:7e5c566b1760	1122	/* MPU Region Attribute and Size Register */
Pokitto	5:7e5c566b1760	1123	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Pokitto	5:7e5c566b1760	1124	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Pokitto	5:7e5c566b1760	1125
Pokitto	5:7e5c566b1760	1126	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Pokitto	5:7e5c566b1760	1127	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Pokitto	5:7e5c566b1760	1128
Pokitto	5:7e5c566b1760	1129	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Pokitto	5:7e5c566b1760	1130	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Pokitto	5:7e5c566b1760	1131
Pokitto	5:7e5c566b1760	1132	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Pokitto	5:7e5c566b1760	1133	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Pokitto	5:7e5c566b1760	1134
Pokitto	5:7e5c566b1760	1135	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Pokitto	5:7e5c566b1760	1136	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Pokitto	5:7e5c566b1760	1137
Pokitto	5:7e5c566b1760	1138	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Pokitto	5:7e5c566b1760	1139	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Pokitto	5:7e5c566b1760	1140
Pokitto	5:7e5c566b1760	1141	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Pokitto	5:7e5c566b1760	1142	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Pokitto	5:7e5c566b1760	1143
Pokitto	5:7e5c566b1760	1144	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Pokitto	5:7e5c566b1760	1145	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Pokitto	5:7e5c566b1760	1146
Pokitto	5:7e5c566b1760	1147	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Pokitto	5:7e5c566b1760	1148	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Pokitto	5:7e5c566b1760	1149
Pokitto	5:7e5c566b1760	1150	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Pokitto	5:7e5c566b1760	1151	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
Pokitto	5:7e5c566b1760	1152
Pokitto	5:7e5c566b1760	1153	/@} end of group CMSIS_MPU /
Pokitto	5:7e5c566b1760	1154	#endif
Pokitto	5:7e5c566b1760	1155
Pokitto	5:7e5c566b1760	1156
Pokitto	5:7e5c566b1760	1157	#if (__FPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	1158	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	1159	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Pokitto	5:7e5c566b1760	1160	\brief Type definitions for the Floating Point Unit (FPU)
Pokitto	5:7e5c566b1760	1161	@{
Pokitto	5:7e5c566b1760	1162	*/
Pokitto	5:7e5c566b1760	1163
Pokitto	5:7e5c566b1760	1164	/** \brief Structure type to access the Floating Point Unit (FPU).
Pokitto	5:7e5c566b1760	1165	*/
Pokitto	5:7e5c566b1760	1166	typedef struct
Pokitto	5:7e5c566b1760	1167	{
Pokitto	5:7e5c566b1760	1168	uint32_t RESERVED0[1];
Pokitto	5:7e5c566b1760	1169	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Pokitto	5:7e5c566b1760	1170	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Pokitto	5:7e5c566b1760	1171	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Pokitto	5:7e5c566b1760	1172	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Pokitto	5:7e5c566b1760	1173	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Pokitto	5:7e5c566b1760	1174	} FPU_Type;
Pokitto	5:7e5c566b1760	1175
Pokitto	5:7e5c566b1760	1176	/* Floating-Point Context Control Register */
Pokitto	5:7e5c566b1760	1177	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
Pokitto	5:7e5c566b1760	1178	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Pokitto	5:7e5c566b1760	1179
Pokitto	5:7e5c566b1760	1180	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
Pokitto	5:7e5c566b1760	1181	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Pokitto	5:7e5c566b1760	1182
Pokitto	5:7e5c566b1760	1183	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
Pokitto	5:7e5c566b1760	1184	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Pokitto	5:7e5c566b1760	1185
Pokitto	5:7e5c566b1760	1186	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
Pokitto	5:7e5c566b1760	1187	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Pokitto	5:7e5c566b1760	1188
Pokitto	5:7e5c566b1760	1189	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
Pokitto	5:7e5c566b1760	1190	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Pokitto	5:7e5c566b1760	1191
Pokitto	5:7e5c566b1760	1192	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
Pokitto	5:7e5c566b1760	1193	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Pokitto	5:7e5c566b1760	1194
Pokitto	5:7e5c566b1760	1195	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
Pokitto	5:7e5c566b1760	1196	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Pokitto	5:7e5c566b1760	1197
Pokitto	5:7e5c566b1760	1198	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
Pokitto	5:7e5c566b1760	1199	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Pokitto	5:7e5c566b1760	1200
Pokitto	5:7e5c566b1760	1201	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Pokitto	5:7e5c566b1760	1202	#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /!< FPCCR: Lazy state preservation active bit Mask /
Pokitto	5:7e5c566b1760	1203
Pokitto	5:7e5c566b1760	1204	/* Floating-Point Context Address Register */
Pokitto	5:7e5c566b1760	1205	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
Pokitto	5:7e5c566b1760	1206	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Pokitto	5:7e5c566b1760	1207
Pokitto	5:7e5c566b1760	1208	/* Floating-Point Default Status Control Register */
Pokitto	5:7e5c566b1760	1209	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
Pokitto	5:7e5c566b1760	1210	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Pokitto	5:7e5c566b1760	1211
Pokitto	5:7e5c566b1760	1212	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
Pokitto	5:7e5c566b1760	1213	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Pokitto	5:7e5c566b1760	1214
Pokitto	5:7e5c566b1760	1215	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
Pokitto	5:7e5c566b1760	1216	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Pokitto	5:7e5c566b1760	1217
Pokitto	5:7e5c566b1760	1218	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
Pokitto	5:7e5c566b1760	1219	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Pokitto	5:7e5c566b1760	1220
Pokitto	5:7e5c566b1760	1221	/* Media and FP Feature Register 0 */
Pokitto	5:7e5c566b1760	1222	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
Pokitto	5:7e5c566b1760	1223	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Pokitto	5:7e5c566b1760	1224
Pokitto	5:7e5c566b1760	1225	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
Pokitto	5:7e5c566b1760	1226	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Pokitto	5:7e5c566b1760	1227
Pokitto	5:7e5c566b1760	1228	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
Pokitto	5:7e5c566b1760	1229	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Pokitto	5:7e5c566b1760	1230
Pokitto	5:7e5c566b1760	1231	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
Pokitto	5:7e5c566b1760	1232	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Pokitto	5:7e5c566b1760	1233
Pokitto	5:7e5c566b1760	1234	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
Pokitto	5:7e5c566b1760	1235	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Pokitto	5:7e5c566b1760	1236
Pokitto	5:7e5c566b1760	1237	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
Pokitto	5:7e5c566b1760	1238	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Pokitto	5:7e5c566b1760	1239
Pokitto	5:7e5c566b1760	1240	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
Pokitto	5:7e5c566b1760	1241	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Pokitto	5:7e5c566b1760	1242
Pokitto	5:7e5c566b1760	1243	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Pokitto	5:7e5c566b1760	1244	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /!< MVFR0: A_SIMD registers bits Mask /
Pokitto	5:7e5c566b1760	1245
Pokitto	5:7e5c566b1760	1246	/* Media and FP Feature Register 1 */
Pokitto	5:7e5c566b1760	1247	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
Pokitto	5:7e5c566b1760	1248	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Pokitto	5:7e5c566b1760	1249
Pokitto	5:7e5c566b1760	1250	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
Pokitto	5:7e5c566b1760	1251	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Pokitto	5:7e5c566b1760	1252
Pokitto	5:7e5c566b1760	1253	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
Pokitto	5:7e5c566b1760	1254	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Pokitto	5:7e5c566b1760	1255
Pokitto	5:7e5c566b1760	1256	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Pokitto	5:7e5c566b1760	1257	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /!< MVFR1: FtZ mode bits Mask /
Pokitto	5:7e5c566b1760	1258
Pokitto	5:7e5c566b1760	1259	/@} end of group CMSIS_FPU /
Pokitto	5:7e5c566b1760	1260	#endif
Pokitto	5:7e5c566b1760	1261
Pokitto	5:7e5c566b1760	1262
Pokitto	5:7e5c566b1760	1263	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	1264	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Pokitto	5:7e5c566b1760	1265	\brief Type definitions for the Core Debug Registers
Pokitto	5:7e5c566b1760	1266	@{
Pokitto	5:7e5c566b1760	1267	*/
Pokitto	5:7e5c566b1760	1268
Pokitto	5:7e5c566b1760	1269	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Pokitto	5:7e5c566b1760	1270	*/
Pokitto	5:7e5c566b1760	1271	typedef struct
Pokitto	5:7e5c566b1760	1272	{
Pokitto	5:7e5c566b1760	1273	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Pokitto	5:7e5c566b1760	1274	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Pokitto	5:7e5c566b1760	1275	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Pokitto	5:7e5c566b1760	1276	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Pokitto	5:7e5c566b1760	1277	} CoreDebug_Type;
Pokitto	5:7e5c566b1760	1278
Pokitto	5:7e5c566b1760	1279	/* Debug Halting Control and Status Register */
Pokitto	5:7e5c566b1760	1280	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Pokitto	5:7e5c566b1760	1281	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Pokitto	5:7e5c566b1760	1282
Pokitto	5:7e5c566b1760	1283	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Pokitto	5:7e5c566b1760	1284	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Pokitto	5:7e5c566b1760	1285
Pokitto	5:7e5c566b1760	1286	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Pokitto	5:7e5c566b1760	1287	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Pokitto	5:7e5c566b1760	1288
Pokitto	5:7e5c566b1760	1289	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Pokitto	5:7e5c566b1760	1290	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Pokitto	5:7e5c566b1760	1291
Pokitto	5:7e5c566b1760	1292	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Pokitto	5:7e5c566b1760	1293	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Pokitto	5:7e5c566b1760	1294
Pokitto	5:7e5c566b1760	1295	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Pokitto	5:7e5c566b1760	1296	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Pokitto	5:7e5c566b1760	1297
Pokitto	5:7e5c566b1760	1298	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Pokitto	5:7e5c566b1760	1299	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Pokitto	5:7e5c566b1760	1300
Pokitto	5:7e5c566b1760	1301	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Pokitto	5:7e5c566b1760	1302	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Pokitto	5:7e5c566b1760	1303
Pokitto	5:7e5c566b1760	1304	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Pokitto	5:7e5c566b1760	1305	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Pokitto	5:7e5c566b1760	1306
Pokitto	5:7e5c566b1760	1307	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Pokitto	5:7e5c566b1760	1308	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Pokitto	5:7e5c566b1760	1309
Pokitto	5:7e5c566b1760	1310	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Pokitto	5:7e5c566b1760	1311	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Pokitto	5:7e5c566b1760	1312
Pokitto	5:7e5c566b1760	1313	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Pokitto	5:7e5c566b1760	1314	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Pokitto	5:7e5c566b1760	1315
Pokitto	5:7e5c566b1760	1316	/* Debug Core Register Selector Register */
Pokitto	5:7e5c566b1760	1317	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Pokitto	5:7e5c566b1760	1318	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Pokitto	5:7e5c566b1760	1319
Pokitto	5:7e5c566b1760	1320	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Pokitto	5:7e5c566b1760	1321	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
Pokitto	5:7e5c566b1760	1322
Pokitto	5:7e5c566b1760	1323	/* Debug Exception and Monitor Control Register */
Pokitto	5:7e5c566b1760	1324	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Pokitto	5:7e5c566b1760	1325	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Pokitto	5:7e5c566b1760	1326
Pokitto	5:7e5c566b1760	1327	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Pokitto	5:7e5c566b1760	1328	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Pokitto	5:7e5c566b1760	1329
Pokitto	5:7e5c566b1760	1330	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Pokitto	5:7e5c566b1760	1331	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Pokitto	5:7e5c566b1760	1332
Pokitto	5:7e5c566b1760	1333	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Pokitto	5:7e5c566b1760	1334	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Pokitto	5:7e5c566b1760	1335
Pokitto	5:7e5c566b1760	1336	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Pokitto	5:7e5c566b1760	1337	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Pokitto	5:7e5c566b1760	1338
Pokitto	5:7e5c566b1760	1339	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Pokitto	5:7e5c566b1760	1340	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Pokitto	5:7e5c566b1760	1341
Pokitto	5:7e5c566b1760	1342	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Pokitto	5:7e5c566b1760	1343	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Pokitto	5:7e5c566b1760	1344
Pokitto	5:7e5c566b1760	1345	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Pokitto	5:7e5c566b1760	1346	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Pokitto	5:7e5c566b1760	1347
Pokitto	5:7e5c566b1760	1348	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Pokitto	5:7e5c566b1760	1349	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Pokitto	5:7e5c566b1760	1350
Pokitto	5:7e5c566b1760	1351	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Pokitto	5:7e5c566b1760	1352	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Pokitto	5:7e5c566b1760	1353
Pokitto	5:7e5c566b1760	1354	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Pokitto	5:7e5c566b1760	1355	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Pokitto	5:7e5c566b1760	1356
Pokitto	5:7e5c566b1760	1357	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Pokitto	5:7e5c566b1760	1358	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Pokitto	5:7e5c566b1760	1359
Pokitto	5:7e5c566b1760	1360	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Pokitto	5:7e5c566b1760	1361	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Pokitto	5:7e5c566b1760	1362
Pokitto	5:7e5c566b1760	1363	/@} end of group CMSIS_CoreDebug /
Pokitto	5:7e5c566b1760	1364
Pokitto	5:7e5c566b1760	1365
Pokitto	5:7e5c566b1760	1366	/** \ingroup CMSIS_core_register
Pokitto	5:7e5c566b1760	1367	\defgroup CMSIS_core_base Core Definitions
Pokitto	5:7e5c566b1760	1368	\brief Definitions for base addresses, unions, and structures.
Pokitto	5:7e5c566b1760	1369	@{
Pokitto	5:7e5c566b1760	1370	*/
Pokitto	5:7e5c566b1760	1371
Pokitto	5:7e5c566b1760	1372	/* Memory mapping of Cortex-M4 Hardware */
Pokitto	5:7e5c566b1760	1373	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Pokitto	5:7e5c566b1760	1374	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Pokitto	5:7e5c566b1760	1375	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Pokitto	5:7e5c566b1760	1376	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Pokitto	5:7e5c566b1760	1377	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Pokitto	5:7e5c566b1760	1378	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Pokitto	5:7e5c566b1760	1379	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Pokitto	5:7e5c566b1760	1380	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Pokitto	5:7e5c566b1760	1381
Pokitto	5:7e5c566b1760	1382	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Pokitto	5:7e5c566b1760	1383	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Pokitto	5:7e5c566b1760	1384	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Pokitto	5:7e5c566b1760	1385	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Pokitto	5:7e5c566b1760	1386	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Pokitto	5:7e5c566b1760	1387	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Pokitto	5:7e5c566b1760	1388	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Pokitto	5:7e5c566b1760	1389	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Pokitto	5:7e5c566b1760	1390
Pokitto	5:7e5c566b1760	1391	#if (__MPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	1392	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Pokitto	5:7e5c566b1760	1393	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Pokitto	5:7e5c566b1760	1394	#endif
Pokitto	5:7e5c566b1760	1395
Pokitto	5:7e5c566b1760	1396	#if (__FPU_PRESENT == 1)
Pokitto	5:7e5c566b1760	1397	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Pokitto	5:7e5c566b1760	1398	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Pokitto	5:7e5c566b1760	1399	#endif
Pokitto	5:7e5c566b1760	1400
Pokitto	5:7e5c566b1760	1401	/@} /
Pokitto	5:7e5c566b1760	1402
Pokitto	5:7e5c566b1760	1403
Pokitto	5:7e5c566b1760	1404
Pokitto	5:7e5c566b1760	1405	/*******************************************************************************
Pokitto	5:7e5c566b1760	1406	* Hardware Abstraction Layer
Pokitto	5:7e5c566b1760	1407	Core Function Interface contains:
Pokitto	5:7e5c566b1760	1408	- Core NVIC Functions
Pokitto	5:7e5c566b1760	1409	- Core SysTick Functions
Pokitto	5:7e5c566b1760	1410	- Core Debug Functions
Pokitto	5:7e5c566b1760	1411	- Core Register Access Functions
Pokitto	5:7e5c566b1760	1412	******************************************************************************/
Pokitto	5:7e5c566b1760	1413	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Pokitto	5:7e5c566b1760	1414	*/
Pokitto	5:7e5c566b1760	1415
Pokitto	5:7e5c566b1760	1416
Pokitto	5:7e5c566b1760	1417
Pokitto	5:7e5c566b1760	1418	/* ########################## NVIC functions #################################### */
Pokitto	5:7e5c566b1760	1419	/** \ingroup CMSIS_Core_FunctionInterface
Pokitto	5:7e5c566b1760	1420	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Pokitto	5:7e5c566b1760	1421	\brief Functions that manage interrupts and exceptions via the NVIC.
Pokitto	5:7e5c566b1760	1422	@{
Pokitto	5:7e5c566b1760	1423	*/
Pokitto	5:7e5c566b1760	1424
Pokitto	5:7e5c566b1760	1425	/** \brief Set Priority Grouping
Pokitto	5:7e5c566b1760	1426
Pokitto	5:7e5c566b1760	1427	The function sets the priority grouping field using the required unlock sequence.
Pokitto	5:7e5c566b1760	1428	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Pokitto	5:7e5c566b1760	1429	Only values from 0..7 are used.
Pokitto	5:7e5c566b1760	1430	In case of a conflict between priority grouping and available
Pokitto	5:7e5c566b1760	1431	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Pokitto	5:7e5c566b1760	1432
Pokitto	5:7e5c566b1760	1433	\param [in] PriorityGroup Priority grouping field.
Pokitto	5:7e5c566b1760	1434	*/
Pokitto	5:7e5c566b1760	1435	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Pokitto	5:7e5c566b1760	1436	{
Pokitto	5:7e5c566b1760	1437	uint32_t reg_value;
Pokitto	5:7e5c566b1760	1438	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
Pokitto	5:7e5c566b1760	1439
Pokitto	5:7e5c566b1760	1440	reg_value = SCB->AIRCR; /* read old register configuration */
Pokitto	5:7e5c566b1760	1441	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
Pokitto	5:7e5c566b1760	1442	reg_value = (reg_value \|
Pokitto	5:7e5c566b1760	1443	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
Pokitto	5:7e5c566b1760	1444	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
Pokitto	5:7e5c566b1760	1445	SCB->AIRCR = reg_value;
Pokitto	5:7e5c566b1760	1446	}
Pokitto	5:7e5c566b1760	1447
Pokitto	5:7e5c566b1760	1448
Pokitto	5:7e5c566b1760	1449	/** \brief Get Priority Grouping
Pokitto	5:7e5c566b1760	1450
Pokitto	5:7e5c566b1760	1451	The function reads the priority grouping field from the NVIC Interrupt Controller.
Pokitto	5:7e5c566b1760	1452
Pokitto	5:7e5c566b1760	1453	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Pokitto	5:7e5c566b1760	1454	*/
Pokitto	5:7e5c566b1760	1455	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Pokitto	5:7e5c566b1760	1456	{
Pokitto	5:7e5c566b1760	1457	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
Pokitto	5:7e5c566b1760	1458	}
Pokitto	5:7e5c566b1760	1459
Pokitto	5:7e5c566b1760	1460
Pokitto	5:7e5c566b1760	1461	/** \brief Enable External Interrupt
Pokitto	5:7e5c566b1760	1462
Pokitto	5:7e5c566b1760	1463	The function enables a device-specific interrupt in the NVIC interrupt controller.
Pokitto	5:7e5c566b1760	1464
Pokitto	5:7e5c566b1760	1465	\param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto	5:7e5c566b1760	1466	*/
Pokitto	5:7e5c566b1760	1467	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Pokitto	5:7e5c566b1760	1468	{
Pokitto	5:7e5c566b1760	1469	/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
Pokitto	5:7e5c566b1760	1470	NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
Pokitto	5:7e5c566b1760	1471	}
Pokitto	5:7e5c566b1760	1472
Pokitto	5:7e5c566b1760	1473
Pokitto	5:7e5c566b1760	1474	/** \brief Disable External Interrupt
Pokitto	5:7e5c566b1760	1475
Pokitto	5:7e5c566b1760	1476	The function disables a device-specific interrupt in the NVIC interrupt controller.
Pokitto	5:7e5c566b1760	1477
Pokitto	5:7e5c566b1760	1478	\param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto	5:7e5c566b1760	1479	*/
Pokitto	5:7e5c566b1760	1480	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Pokitto	5:7e5c566b1760	1481	{
Pokitto	5:7e5c566b1760	1482	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
Pokitto	5:7e5c566b1760	1483	}
Pokitto	5:7e5c566b1760	1484
Pokitto	5:7e5c566b1760	1485
Pokitto	5:7e5c566b1760	1486	/** \brief Get Pending Interrupt
Pokitto	5:7e5c566b1760	1487
Pokitto	5:7e5c566b1760	1488	The function reads the pending register in the NVIC and returns the pending bit
Pokitto	5:7e5c566b1760	1489	for the specified interrupt.
Pokitto	5:7e5c566b1760	1490
Pokitto	5:7e5c566b1760	1491	\param [in] IRQn Interrupt number.
Pokitto	5:7e5c566b1760	1492
Pokitto	5:7e5c566b1760	1493	\return 0 Interrupt status is not pending.
Pokitto	5:7e5c566b1760	1494	\return 1 Interrupt status is pending.
Pokitto	5:7e5c566b1760	1495	*/
Pokitto	5:7e5c566b1760	1496	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Pokitto	5:7e5c566b1760	1497	{
Pokitto	5:7e5c566b1760	1498	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
Pokitto	5:7e5c566b1760	1499	}
Pokitto	5:7e5c566b1760	1500
Pokitto	5:7e5c566b1760	1501
Pokitto	5:7e5c566b1760	1502	/** \brief Set Pending Interrupt
Pokitto	5:7e5c566b1760	1503
Pokitto	5:7e5c566b1760	1504	The function sets the pending bit of an external interrupt.
Pokitto	5:7e5c566b1760	1505
Pokitto	5:7e5c566b1760	1506	\param [in] IRQn Interrupt number. Value cannot be negative.
Pokitto	5:7e5c566b1760	1507	*/
Pokitto	5:7e5c566b1760	1508	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Pokitto	5:7e5c566b1760	1509	{
Pokitto	5:7e5c566b1760	1510	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
Pokitto	5:7e5c566b1760	1511	}
Pokitto	5:7e5c566b1760	1512
Pokitto	5:7e5c566b1760	1513
Pokitto	5:7e5c566b1760	1514	/** \brief Clear Pending Interrupt
Pokitto	5:7e5c566b1760	1515
Pokitto	5:7e5c566b1760	1516	The function clears the pending bit of an external interrupt.
Pokitto	5:7e5c566b1760	1517
Pokitto	5:7e5c566b1760	1518	\param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto	5:7e5c566b1760	1519	*/
Pokitto	5:7e5c566b1760	1520	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Pokitto	5:7e5c566b1760	1521	{
Pokitto	5:7e5c566b1760	1522	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Pokitto	5:7e5c566b1760	1523	}
Pokitto	5:7e5c566b1760	1524
Pokitto	5:7e5c566b1760	1525
Pokitto	5:7e5c566b1760	1526	/** \brief Get Active Interrupt
Pokitto	5:7e5c566b1760	1527
Pokitto	5:7e5c566b1760	1528	The function reads the active register in NVIC and returns the active bit.
Pokitto	5:7e5c566b1760	1529
Pokitto	5:7e5c566b1760	1530	\param [in] IRQn Interrupt number.
Pokitto	5:7e5c566b1760	1531
Pokitto	5:7e5c566b1760	1532	\return 0 Interrupt status is not active.
Pokitto	5:7e5c566b1760	1533	\return 1 Interrupt status is active.
Pokitto	5:7e5c566b1760	1534	*/
Pokitto	5:7e5c566b1760	1535	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Pokitto	5:7e5c566b1760	1536	{
Pokitto	5:7e5c566b1760	1537	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
Pokitto	5:7e5c566b1760	1538	}
Pokitto	5:7e5c566b1760	1539
Pokitto	5:7e5c566b1760	1540
Pokitto	5:7e5c566b1760	1541	/** \brief Set Interrupt Priority
Pokitto	5:7e5c566b1760	1542
Pokitto	5:7e5c566b1760	1543	The function sets the priority of an interrupt.
Pokitto	5:7e5c566b1760	1544
Pokitto	5:7e5c566b1760	1545	\note The priority cannot be set for every core interrupt.
Pokitto	5:7e5c566b1760	1546
Pokitto	5:7e5c566b1760	1547	\param [in] IRQn Interrupt number.
Pokitto	5:7e5c566b1760	1548	\param [in] priority Priority to set.
Pokitto	5:7e5c566b1760	1549	*/
Pokitto	5:7e5c566b1760	1550	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Pokitto	5:7e5c566b1760	1551	{
Pokitto	5:7e5c566b1760	1552	if(IRQn < 0) {
Pokitto	5:7e5c566b1760	1553	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
Pokitto	5:7e5c566b1760	1554	else {
Pokitto	5:7e5c566b1760	1555	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
Pokitto	5:7e5c566b1760	1556	}
Pokitto	5:7e5c566b1760	1557
Pokitto	5:7e5c566b1760	1558
Pokitto	5:7e5c566b1760	1559	/** \brief Get Interrupt Priority
Pokitto	5:7e5c566b1760	1560
Pokitto	5:7e5c566b1760	1561	The function reads the priority of an interrupt. The interrupt
Pokitto	5:7e5c566b1760	1562	number can be positive to specify an external (device specific)
Pokitto	5:7e5c566b1760	1563	interrupt, or negative to specify an internal (core) interrupt.
Pokitto	5:7e5c566b1760	1564
Pokitto	5:7e5c566b1760	1565
Pokitto	5:7e5c566b1760	1566	\param [in] IRQn Interrupt number.
Pokitto	5:7e5c566b1760	1567	\return Interrupt Priority. Value is aligned automatically to the implemented
Pokitto	5:7e5c566b1760	1568	priority bits of the microcontroller.
Pokitto	5:7e5c566b1760	1569	*/
Pokitto	5:7e5c566b1760	1570	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Pokitto	5:7e5c566b1760	1571	{
Pokitto	5:7e5c566b1760	1572
Pokitto	5:7e5c566b1760	1573	if(IRQn < 0) {
Pokitto	5:7e5c566b1760	1574	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
Pokitto	5:7e5c566b1760	1575	else {
Pokitto	5:7e5c566b1760	1576	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Pokitto	5:7e5c566b1760	1577	}
Pokitto	5:7e5c566b1760	1578
Pokitto	5:7e5c566b1760	1579
Pokitto	5:7e5c566b1760	1580	/** \brief Encode Priority
Pokitto	5:7e5c566b1760	1581
Pokitto	5:7e5c566b1760	1582	The function encodes the priority for an interrupt with the given priority group,
Pokitto	5:7e5c566b1760	1583	preemptive priority value, and subpriority value.
Pokitto	5:7e5c566b1760	1584	In case of a conflict between priority grouping and available
Pokitto	5:7e5c566b1760	1585	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
Pokitto	5:7e5c566b1760	1586
Pokitto	5:7e5c566b1760	1587	\param [in] PriorityGroup Used priority group.
Pokitto	5:7e5c566b1760	1588	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Pokitto	5:7e5c566b1760	1589	\param [in] SubPriority Subpriority value (starting from 0).
Pokitto	5:7e5c566b1760	1590	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Pokitto	5:7e5c566b1760	1591	*/
Pokitto	5:7e5c566b1760	1592	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Pokitto	5:7e5c566b1760	1593	{
Pokitto	5:7e5c566b1760	1594	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Pokitto	5:7e5c566b1760	1595	uint32_t PreemptPriorityBits;
Pokitto	5:7e5c566b1760	1596	uint32_t SubPriorityBits;
Pokitto	5:7e5c566b1760	1597
Pokitto	5:7e5c566b1760	1598	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Pokitto	5:7e5c566b1760	1599	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Pokitto	5:7e5c566b1760	1600
Pokitto	5:7e5c566b1760	1601	return (
Pokitto	5:7e5c566b1760	1602	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
Pokitto	5:7e5c566b1760	1603	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
Pokitto	5:7e5c566b1760	1604	);
Pokitto	5:7e5c566b1760	1605	}
Pokitto	5:7e5c566b1760	1606
Pokitto	5:7e5c566b1760	1607
Pokitto	5:7e5c566b1760	1608	/** \brief Decode Priority
Pokitto	5:7e5c566b1760	1609
Pokitto	5:7e5c566b1760	1610	The function decodes an interrupt priority value with a given priority group to
Pokitto	5:7e5c566b1760	1611	preemptive priority value and subpriority value.
Pokitto	5:7e5c566b1760	1612	In case of a conflict between priority grouping and available
Pokitto	5:7e5c566b1760	1613	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Pokitto	5:7e5c566b1760	1614
Pokitto	5:7e5c566b1760	1615	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Pokitto	5:7e5c566b1760	1616	\param [in] PriorityGroup Used priority group.
Pokitto	5:7e5c566b1760	1617	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Pokitto	5:7e5c566b1760	1618	\param [out] pSubPriority Subpriority value (starting from 0).
Pokitto	5:7e5c566b1760	1619	*/
Pokitto	5:7e5c566b1760	1620	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Pokitto	5:7e5c566b1760	1621	{
Pokitto	5:7e5c566b1760	1622	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Pokitto	5:7e5c566b1760	1623	uint32_t PreemptPriorityBits;
Pokitto	5:7e5c566b1760	1624	uint32_t SubPriorityBits;
Pokitto	5:7e5c566b1760	1625
Pokitto	5:7e5c566b1760	1626	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Pokitto	5:7e5c566b1760	1627	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Pokitto	5:7e5c566b1760	1628
Pokitto	5:7e5c566b1760	1629	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
Pokitto	5:7e5c566b1760	1630	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
Pokitto	5:7e5c566b1760	1631	}
Pokitto	5:7e5c566b1760	1632
Pokitto	5:7e5c566b1760	1633
Pokitto	5:7e5c566b1760	1634	/** \brief System Reset
Pokitto	5:7e5c566b1760	1635
Pokitto	5:7e5c566b1760	1636	The function initiates a system reset request to reset the MCU.
Pokitto	5:7e5c566b1760	1637	*/
Pokitto	5:7e5c566b1760	1638	__STATIC_INLINE void NVIC_SystemReset(void)
Pokitto	5:7e5c566b1760	1639	{
Pokitto	5:7e5c566b1760	1640	__DSB(); /* Ensure all outstanding memory accesses included
Pokitto	5:7e5c566b1760	1641	buffered write are completed before reset */
Pokitto	5:7e5c566b1760	1642	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
Pokitto	5:7e5c566b1760	1643	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Pokitto	5:7e5c566b1760	1644	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
Pokitto	5:7e5c566b1760	1645	__DSB(); /* Ensure completion of memory access */
Pokitto	5:7e5c566b1760	1646	while(1); /* wait until reset */
Pokitto	5:7e5c566b1760	1647	}
Pokitto	5:7e5c566b1760	1648
Pokitto	5:7e5c566b1760	1649	/@} end of CMSIS_Core_NVICFunctions /
Pokitto	5:7e5c566b1760	1650
Pokitto	5:7e5c566b1760	1651
Pokitto	5:7e5c566b1760	1652
Pokitto	5:7e5c566b1760	1653	/* ################################## SysTick function ############################################ */
Pokitto	5:7e5c566b1760	1654	/** \ingroup CMSIS_Core_FunctionInterface
Pokitto	5:7e5c566b1760	1655	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Pokitto	5:7e5c566b1760	1656	\brief Functions that configure the System.
Pokitto	5:7e5c566b1760	1657	@{
Pokitto	5:7e5c566b1760	1658	*/
Pokitto	5:7e5c566b1760	1659
Pokitto	5:7e5c566b1760	1660	#if (__Vendor_SysTickConfig == 0)
Pokitto	5:7e5c566b1760	1661
Pokitto	5:7e5c566b1760	1662	/** \brief System Tick Configuration
Pokitto	5:7e5c566b1760	1663
Pokitto	5:7e5c566b1760	1664	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Pokitto	5:7e5c566b1760	1665	Counter is in free running mode to generate periodic interrupts.
Pokitto	5:7e5c566b1760	1666
Pokitto	5:7e5c566b1760	1667	\param [in] ticks Number of ticks between two interrupts.
Pokitto	5:7e5c566b1760	1668
Pokitto	5:7e5c566b1760	1669	\return 0 Function succeeded.
Pokitto	5:7e5c566b1760	1670	\return 1 Function failed.
Pokitto	5:7e5c566b1760	1671
Pokitto	5:7e5c566b1760	1672	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Pokitto	5:7e5c566b1760	1673	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Pokitto	5:7e5c566b1760	1674	must contain a vendor-specific implementation of this function.
Pokitto	5:7e5c566b1760	1675
Pokitto	5:7e5c566b1760	1676	*/
Pokitto	5:7e5c566b1760	1677	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Pokitto	5:7e5c566b1760	1678	{
Pokitto	5:7e5c566b1760	1679	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Pokitto	5:7e5c566b1760	1680
Pokitto	5:7e5c566b1760	1681	SysTick->LOAD = ticks - 1; /* set reload register */
Pokitto	5:7e5c566b1760	1682	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Pokitto	5:7e5c566b1760	1683	SysTick->VAL = 0; /* Load the SysTick Counter Value */
Pokitto	5:7e5c566b1760	1684	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Pokitto	5:7e5c566b1760	1685	SysTick_CTRL_TICKINT_Msk \|
Pokitto	5:7e5c566b1760	1686	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Pokitto	5:7e5c566b1760	1687	return (0); /* Function successful */
Pokitto	5:7e5c566b1760	1688	}
Pokitto	5:7e5c566b1760	1689
Pokitto	5:7e5c566b1760	1690	#endif
Pokitto	5:7e5c566b1760	1691
Pokitto	5:7e5c566b1760	1692	/@} end of CMSIS_Core_SysTickFunctions /
Pokitto	5:7e5c566b1760	1693
Pokitto	5:7e5c566b1760	1694
Pokitto	5:7e5c566b1760	1695
Pokitto	5:7e5c566b1760	1696	/* ##################################### Debug In/Output function ########################################### */
Pokitto	5:7e5c566b1760	1697	/** \ingroup CMSIS_Core_FunctionInterface
Pokitto	5:7e5c566b1760	1698	\defgroup CMSIS_core_DebugFunctions ITM Functions
Pokitto	5:7e5c566b1760	1699	\brief Functions that access the ITM debug interface.
Pokitto	5:7e5c566b1760	1700	@{
Pokitto	5:7e5c566b1760	1701	*/
Pokitto	5:7e5c566b1760	1702
Pokitto	5:7e5c566b1760	1703	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Pokitto	5:7e5c566b1760	1704	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Pokitto	5:7e5c566b1760	1705
Pokitto	5:7e5c566b1760	1706
Pokitto	5:7e5c566b1760	1707	/** \brief ITM Send Character
Pokitto	5:7e5c566b1760	1708
Pokitto	5:7e5c566b1760	1709	The function transmits a character via the ITM channel 0, and
Pokitto	5:7e5c566b1760	1710	\li Just returns when no debugger is connected that has booked the output.
Pokitto	5:7e5c566b1760	1711	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Pokitto	5:7e5c566b1760	1712
Pokitto	5:7e5c566b1760	1713	\param [in] ch Character to transmit.
Pokitto	5:7e5c566b1760	1714
Pokitto	5:7e5c566b1760	1715	\returns Character to transmit.
Pokitto	5:7e5c566b1760	1716	*/
Pokitto	5:7e5c566b1760	1717	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Pokitto	5:7e5c566b1760	1718	{
Pokitto	5:7e5c566b1760	1719	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
Pokitto	5:7e5c566b1760	1720	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
Pokitto	5:7e5c566b1760	1721	{
Pokitto	5:7e5c566b1760	1722	while (ITM->PORT[0].u32 == 0);
Pokitto	5:7e5c566b1760	1723	ITM->PORT[0].u8 = (uint8_t) ch;
Pokitto	5:7e5c566b1760	1724	}
Pokitto	5:7e5c566b1760	1725	return (ch);
Pokitto	5:7e5c566b1760	1726	}
Pokitto	5:7e5c566b1760	1727
Pokitto	5:7e5c566b1760	1728
Pokitto	5:7e5c566b1760	1729	/** \brief ITM Receive Character
Pokitto	5:7e5c566b1760	1730
Pokitto	5:7e5c566b1760	1731	The function inputs a character via the external variable \ref ITM_RxBuffer.
Pokitto	5:7e5c566b1760	1732
Pokitto	5:7e5c566b1760	1733	\return Received character.
Pokitto	5:7e5c566b1760	1734	\return -1 No character pending.
Pokitto	5:7e5c566b1760	1735	*/
Pokitto	5:7e5c566b1760	1736	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Pokitto	5:7e5c566b1760	1737	int32_t ch = -1; /* no character available */
Pokitto	5:7e5c566b1760	1738
Pokitto	5:7e5c566b1760	1739	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Pokitto	5:7e5c566b1760	1740	ch = ITM_RxBuffer;
Pokitto	5:7e5c566b1760	1741	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Pokitto	5:7e5c566b1760	1742	}
Pokitto	5:7e5c566b1760	1743
Pokitto	5:7e5c566b1760	1744	return (ch);
Pokitto	5:7e5c566b1760	1745	}
Pokitto	5:7e5c566b1760	1746
Pokitto	5:7e5c566b1760	1747
Pokitto	5:7e5c566b1760	1748	/** \brief ITM Check Character
Pokitto	5:7e5c566b1760	1749
Pokitto	5:7e5c566b1760	1750	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Pokitto	5:7e5c566b1760	1751
Pokitto	5:7e5c566b1760	1752	\return 0 No character available.
Pokitto	5:7e5c566b1760	1753	\return 1 Character available.
Pokitto	5:7e5c566b1760	1754	*/
Pokitto	5:7e5c566b1760	1755	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Pokitto	5:7e5c566b1760	1756
Pokitto	5:7e5c566b1760	1757	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Pokitto	5:7e5c566b1760	1758	return (0); /* no character available */
Pokitto	5:7e5c566b1760	1759	} else {
Pokitto	5:7e5c566b1760	1760	return (1); /* character available */
Pokitto	5:7e5c566b1760	1761	}
Pokitto	5:7e5c566b1760	1762	}
Pokitto	5:7e5c566b1760	1763
Pokitto	5:7e5c566b1760	1764	/@} end of CMSIS_core_DebugFunctions /
Pokitto	5:7e5c566b1760	1765
Pokitto	5:7e5c566b1760	1766	#endif /* __CORE_CM4_H_DEPENDANT */
Pokitto	5:7e5c566b1760	1767
Pokitto	5:7e5c566b1760	1768	#endif /* __CMSIS_GENERIC */
Pokitto	5:7e5c566b1760	1769
Pokitto	5:7e5c566b1760	1770	#ifdef __cplusplus
Pokitto	5:7e5c566b1760	1771	}
Pokitto	5:7e5c566b1760	1772	#endif

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Type:	Library
Created:	15 Oct 2017
Imports:	0
Forks:	0
Commits:	12
Dependents:	1
Dependencies:	0
Followers:	48

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mbed-pokitto/targets/cmsis/core_cm4.h@11:02ad9c807a21, 2017-10-15 (annotated)

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