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mbed-os/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h@1:b36bbc1c6d27, 2020-04-11 (annotated)

Committer:
demayer
Date:
Sat Apr 11 08:15:48 2020 +0000
Revision:
1:b36bbc1c6d27
Parent:
0:6bf0743ece18 
IMU-library in .h und .cpp file aufgeteilt

Who changed what in which revision?

UserRevisionLine numberNew contents of line
demayer 0:6bf0743ece18 1 /*
demayer 0:6bf0743ece18 2 * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
demayer 0:6bf0743ece18 3 *
demayer 0:6bf0743ece18 4 * SPDX-License-Identifier: Apache-2.0
demayer 0:6bf0743ece18 5 *
demayer 0:6bf0743ece18 6 * Licensed under the Apache License, Version 2.0 (the License); you may
demayer 0:6bf0743ece18 7 * not use this file except in compliance with the License.
demayer 0:6bf0743ece18 8 * You may obtain a copy of the License at
demayer 0:6bf0743ece18 9 *
demayer 0:6bf0743ece18 10 * www.apache.org/licenses/LICENSE-2.0
demayer 0:6bf0743ece18 11 *
demayer 0:6bf0743ece18 12 * Unless required by applicable law or agreed to in writing, software
demayer 0:6bf0743ece18 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
demayer 0:6bf0743ece18 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
demayer 0:6bf0743ece18 15 * See the License for the specific language governing permissions and
demayer 0:6bf0743ece18 16 * limitations under the License.
demayer 0:6bf0743ece18 17 *
demayer 0:6bf0743ece18 18 * -----------------------------------------------------------------------------
demayer 0:6bf0743ece18 19 *
demayer 0:6bf0743ece18 20 * Project: CMSIS-RTOS RTX
demayer 0:6bf0743ece18 21 * Title: Cortex-M Core definitions
demayer 0:6bf0743ece18 22 *
demayer 0:6bf0743ece18 23 * -----------------------------------------------------------------------------
demayer 0:6bf0743ece18 24 */
demayer 0:6bf0743ece18 25
demayer 0:6bf0743ece18 26 #ifndef RTX_CORE_CM_H_
demayer 0:6bf0743ece18 27 #define RTX_CORE_CM_H_
demayer 0:6bf0743ece18 28
demayer 0:6bf0743ece18 29 #include <cmsis.h>
demayer 0:6bf0743ece18 30
demayer 0:6bf0743ece18 31 #ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS
demayer 0:6bf0743ece18 32 #define __DOMAIN_NS 1U
demayer 0:6bf0743ece18 33 #endif
demayer 0:6bf0743ece18 34
demayer 0:6bf0743ece18 35 #ifndef __DOMAIN_NS
demayer 0:6bf0743ece18 36 #define __DOMAIN_NS 0U
demayer 0:6bf0743ece18 37 #elif ((__DOMAIN_NS == 1U) && \
demayer 0:6bf0743ece18 38 ((__ARM_ARCH_6M__ == 1U) || \
demayer 0:6bf0743ece18 39 (__ARM_ARCH_7M__ == 1U) || \
demayer 0:6bf0743ece18 40 (__ARM_ARCH_7EM__ == 1U)))
demayer 0:6bf0743ece18 41 #error "Non-secure domain requires ARMv8-M Architecture!"
demayer 0:6bf0743ece18 42 #endif
demayer 0:6bf0743ece18 43
demayer 0:6bf0743ece18 44 #ifndef __EXCLUSIVE_ACCESS
demayer 0:6bf0743ece18 45 #if ((__ARM_ARCH_7M__ == 1U) || \
demayer 0:6bf0743ece18 46 (__ARM_ARCH_7EM__ == 1U) || \
demayer 0:6bf0743ece18 47 (__ARM_ARCH_8M_BASE__ == 1U) || \
demayer 0:6bf0743ece18 48 (__ARM_ARCH_8M_MAIN__ == 1U))
demayer 0:6bf0743ece18 49 #define __EXCLUSIVE_ACCESS 1U
demayer 0:6bf0743ece18 50 #else
demayer 0:6bf0743ece18 51 #define __EXCLUSIVE_ACCESS 0U
demayer 0:6bf0743ece18 52 #endif
demayer 0:6bf0743ece18 53 #endif
demayer 0:6bf0743ece18 54
demayer 0:6bf0743ece18 55 #define IS_PRIVILEGED() ((__get_CONTROL() & 1U) == 0U)
demayer 0:6bf0743ece18 56
demayer 0:6bf0743ece18 57 #define IS_IRQ_MODE() (__get_IPSR() != 0U)
demayer 0:6bf0743ece18 58
demayer 0:6bf0743ece18 59 #if ((__ARM_ARCH_7M__ == 1U) || \
demayer 0:6bf0743ece18 60 (__ARM_ARCH_7EM__ == 1U) || \
demayer 0:6bf0743ece18 61 (__ARM_ARCH_8M_MAIN__ == 1U))
demayer 0:6bf0743ece18 62 #define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U))
demayer 0:6bf0743ece18 63 #else
demayer 0:6bf0743ece18 64 #define IS_IRQ_MASKED() (__get_PRIMASK() != 0U)
demayer 0:6bf0743ece18 65 #endif
demayer 0:6bf0743ece18 66
demayer 0:6bf0743ece18 67 #define xPSR_INIT(...) 0x01000000U
demayer 0:6bf0743ece18 68
demayer 0:6bf0743ece18 69 #if (__DOMAIN_NS == 1U)
demayer 0:6bf0743ece18 70 #define STACK_FRAME_INIT 0xBCU
demayer 0:6bf0743ece18 71 #else
demayer 0:6bf0743ece18 72 #define STACK_FRAME_INIT 0xFDU
demayer 0:6bf0743ece18 73 #endif
demayer 0:6bf0743ece18 74
demayer 0:6bf0743ece18 75 // Stack Frame:
demayer 0:6bf0743ece18 76 // - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR
demayer 0:6bf0743ece18 77 // - Basic: R4-R11, R0-R3, R12, LR, PC, xPSR
demayer 0:6bf0743ece18 78 #if (__FPU_USED == 1U)
demayer 0:6bf0743ece18 79 #define STACK_OFFSET_R0(stack_frame) \
demayer 0:6bf0743ece18 80 ((((stack_frame) & 0x10U) == 0U) ? ((16U+8U)*4U) : \
demayer 0:6bf0743ece18 81 (8U *4U))
demayer 0:6bf0743ece18 82 #else
demayer 0:6bf0743ece18 83 #define STACK_OFFSET_R0(stack_frame) (8U *4U)
demayer 0:6bf0743ece18 84 #endif
demayer 0:6bf0743ece18 85
demayer 0:6bf0743ece18 86 #define OS_TICK_HANDLER SysTick_Handler
demayer 0:6bf0743ece18 87
demayer 0:6bf0743ece18 88
demayer 0:6bf0743ece18 89 // ==== Service Calls definitions ====
demayer 0:6bf0743ece18 90
demayer 0:6bf0743ece18 91 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 92
demayer 0:6bf0743ece18 93 #if ((__ARM_ARCH_7M__ == 1U) || \
demayer 0:6bf0743ece18 94 (__ARM_ARCH_7EM__ == 1U) || \
demayer 0:6bf0743ece18 95 (__ARM_ARCH_8M_MAIN__ == 1U))
demayer 0:6bf0743ece18 96 #define __SVC_INDIRECT(n) __svc_indirect(n)
demayer 0:6bf0743ece18 97 #elif ((__ARM_ARCH_6M__ == 1U) || \
demayer 0:6bf0743ece18 98 (__ARM_ARCH_8M_BASE__ == 1U))
demayer 0:6bf0743ece18 99 #define __SVC_INDIRECT(n) __svc_indirect_r7(n)
demayer 0:6bf0743ece18 100 #endif
demayer 0:6bf0743ece18 101
demayer 0:6bf0743ece18 102 #if (__FPU_USED == 1U)
demayer 0:6bf0743ece18 103 #define SVC_SETUP_PSP \
demayer 0:6bf0743ece18 104 uint32_t control = __get_CONTROL(); \
demayer 0:6bf0743ece18 105 if ((control & 2U) == 0U) { \
demayer 0:6bf0743ece18 106 __set_PSP((__get_MSP() - ((control & 4U) ? 104U : 32U)) & ~7U); \
demayer 0:6bf0743ece18 107 }
demayer 0:6bf0743ece18 108 #else
demayer 0:6bf0743ece18 109 #define SVC_SETUP_PSP \
demayer 0:6bf0743ece18 110 uint32_t control = __get_CONTROL(); \
demayer 0:6bf0743ece18 111 if ((control & 2U) == 0U) { \
demayer 0:6bf0743ece18 112 __set_PSP((__get_MSP() - 32U) & ~7U); \
demayer 0:6bf0743ece18 113 }
demayer 0:6bf0743ece18 114 #endif
demayer 0:6bf0743ece18 115
demayer 0:6bf0743ece18 116 #define SVC0_0N(f,t) \
demayer 0:6bf0743ece18 117 __SVC_INDIRECT(0) t svc##f (t(*)()); \
demayer 0:6bf0743ece18 118 t svcRtx##f (void); \
demayer 0:6bf0743ece18 119 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 120 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 121 svc##f(svcRtx##f); \
demayer 0:6bf0743ece18 122 }
demayer 0:6bf0743ece18 123
demayer 0:6bf0743ece18 124 #define SVC0_0(f,t) \
demayer 0:6bf0743ece18 125 __SVC_INDIRECT(0) t svc##f (t(*)()); \
demayer 0:6bf0743ece18 126 t svcRtx##f (void); \
demayer 0:6bf0743ece18 127 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 128 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 129 return svc##f(svcRtx##f); \
demayer 0:6bf0743ece18 130 }
demayer 0:6bf0743ece18 131
demayer 0:6bf0743ece18 132 #define SVC0_0M(f,t) \
demayer 0:6bf0743ece18 133 __SVC_INDIRECT(0) t svc##f (t(*)()); \
demayer 0:6bf0743ece18 134 t svcRtx##f (void); \
demayer 0:6bf0743ece18 135 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 136 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 137 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 138 return svc##f(svcRtx##f); \
demayer 0:6bf0743ece18 139 }
demayer 0:6bf0743ece18 140
demayer 0:6bf0743ece18 141 #define SVC0_1N(f,t,t1) \
demayer 0:6bf0743ece18 142 __SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
demayer 0:6bf0743ece18 143 t svcRtx##f (t1 a1); \
demayer 0:6bf0743ece18 144 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 145 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 146 svc##f(svcRtx##f,a1); \
demayer 0:6bf0743ece18 147 }
demayer 0:6bf0743ece18 148
demayer 0:6bf0743ece18 149 #define SVC0_1(f,t,t1) \
demayer 0:6bf0743ece18 150 __SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
demayer 0:6bf0743ece18 151 t svcRtx##f (t1 a1); \
demayer 0:6bf0743ece18 152 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 153 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 154 return svc##f(svcRtx##f,a1); \
demayer 0:6bf0743ece18 155 }
demayer 0:6bf0743ece18 156
demayer 0:6bf0743ece18 157 #define SVC0_1M(f,t,t1) \
demayer 0:6bf0743ece18 158 __SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \
demayer 0:6bf0743ece18 159 t svcRtx##f (t1 a1); \
demayer 0:6bf0743ece18 160 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 161 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 162 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 163 return svc##f(svcRtx##f,a1); \
demayer 0:6bf0743ece18 164 }
demayer 0:6bf0743ece18 165
demayer 0:6bf0743ece18 166 #define SVC0_2(f,t,t1,t2) \
demayer 0:6bf0743ece18 167 __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \
demayer 0:6bf0743ece18 168 t svcRtx##f (t1 a1, t2 a2); \
demayer 0:6bf0743ece18 169 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 170 __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
demayer 0:6bf0743ece18 171 return svc##f(svcRtx##f,a1,a2); \
demayer 0:6bf0743ece18 172 }
demayer 0:6bf0743ece18 173
demayer 0:6bf0743ece18 174 #define SVC0_2M(f,t,t1,t2) \
demayer 0:6bf0743ece18 175 __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \
demayer 0:6bf0743ece18 176 t svcRtx##f (t1 a1, t2 a2); \
demayer 0:6bf0743ece18 177 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 178 __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
demayer 0:6bf0743ece18 179 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 180 return svc##f(svcRtx##f,a1,a2); \
demayer 0:6bf0743ece18 181 }
demayer 0:6bf0743ece18 182
demayer 0:6bf0743ece18 183 #define SVC0_3(f,t,t1,t2,t3) \
demayer 0:6bf0743ece18 184 __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \
demayer 0:6bf0743ece18 185 t svcRtx##f (t1 a1, t2 a2, t3 a3); \
demayer 0:6bf0743ece18 186 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 187 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
demayer 0:6bf0743ece18 188 return svc##f(svcRtx##f,a1,a2,a3); \
demayer 0:6bf0743ece18 189 }
demayer 0:6bf0743ece18 190
demayer 0:6bf0743ece18 191 #define SVC0_3M(f,t,t1,t2,t3) \
demayer 0:6bf0743ece18 192 __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \
demayer 0:6bf0743ece18 193 t svcRtx##f (t1 a1, t2 a2, t3 a3); \
demayer 0:6bf0743ece18 194 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 195 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
demayer 0:6bf0743ece18 196 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 197 return svc##f(svcRtx##f,a1,a2,a3); \
demayer 0:6bf0743ece18 198 }
demayer 0:6bf0743ece18 199
demayer 0:6bf0743ece18 200 #define SVC0_4(f,t,t1,t2,t3,t4) \
demayer 0:6bf0743ece18 201 __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \
demayer 0:6bf0743ece18 202 t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \
demayer 0:6bf0743ece18 203 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 204 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
demayer 0:6bf0743ece18 205 return svc##f(svcRtx##f,a1,a2,a3,a4); \
demayer 0:6bf0743ece18 206 }
demayer 0:6bf0743ece18 207
demayer 0:6bf0743ece18 208 #define SVC0_4M(f,t,t1,t2,t3,t4) \
demayer 0:6bf0743ece18 209 __SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \
demayer 0:6bf0743ece18 210 t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \
demayer 0:6bf0743ece18 211 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 212 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
demayer 0:6bf0743ece18 213 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 214 return svc##f(svcRtx##f,a1,a2,a3,a4); \
demayer 0:6bf0743ece18 215 }
demayer 0:6bf0743ece18 216
demayer 0:6bf0743ece18 217 #elif defined(__ICCARM__)
demayer 0:6bf0743ece18 218
demayer 0:6bf0743ece18 219 #if ((__ARM_ARCH_7M__ == 1U) || \
demayer 0:6bf0743ece18 220 (__ARM_ARCH_7EM__ == 1U) || \
demayer 0:6bf0743ece18 221 (__ARM_ARCH_8M_MAIN__ == 1U))
demayer 0:6bf0743ece18 222 #define SVC_Setup(f) \
demayer 0:6bf0743ece18 223 __asm( \
demayer 0:6bf0743ece18 224 "mov r12,%0\n" \
demayer 0:6bf0743ece18 225 :: "r"(&f): "r12" \
demayer 0:6bf0743ece18 226 );
demayer 0:6bf0743ece18 227 #elif ((__ARM_ARCH_6M__ == 1U) || \
demayer 0:6bf0743ece18 228 (__ARM_ARCH_8M_BASE__ == 1U))
demayer 0:6bf0743ece18 229 #define SVC_Setup(f) \
demayer 0:6bf0743ece18 230 __asm( \
demayer 0:6bf0743ece18 231 "mov r7,%0\n" \
demayer 0:6bf0743ece18 232 :: "r"(&f): "r7" \
demayer 0:6bf0743ece18 233 );
demayer 0:6bf0743ece18 234 #endif
demayer 0:6bf0743ece18 235
demayer 0:6bf0743ece18 236 #define STRINGIFY(a) #a
demayer 0:6bf0743ece18 237 #define __SVC_INDIRECT(n) _Pragma(STRINGIFY(swi_number = n)) __swi
demayer 0:6bf0743ece18 238
demayer 0:6bf0743ece18 239 #if (__FPU_USED == 1U)
demayer 0:6bf0743ece18 240 #define SVC_SETUP_PSP \
demayer 0:6bf0743ece18 241 uint32_t control = __get_CONTROL(); \
demayer 0:6bf0743ece18 242 if ((control & 2U) == 0U) { \
demayer 0:6bf0743ece18 243 __set_PSP((__get_MSP() - ((control & 4U) ? 104U : 32U)) & ~7U); \
demayer 0:6bf0743ece18 244 }
demayer 0:6bf0743ece18 245 #else
demayer 0:6bf0743ece18 246 #define SVC_SETUP_PSP \
demayer 0:6bf0743ece18 247 uint32_t control = __get_CONTROL(); \
demayer 0:6bf0743ece18 248 if ((control & 2U) == 0U) { \
demayer 0:6bf0743ece18 249 __set_PSP((__get_MSP() - 32U) & ~7U); \
demayer 0:6bf0743ece18 250 }
demayer 0:6bf0743ece18 251 #endif
demayer 0:6bf0743ece18 252
demayer 0:6bf0743ece18 253 #define SVC0_0N(f,t) \
demayer 0:6bf0743ece18 254 __SVC_INDIRECT(0) t svc##f (); \
demayer 0:6bf0743ece18 255 t svcRtx##f (void); \
demayer 0:6bf0743ece18 256 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 257 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 258 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 259 svc##f(); \
demayer 0:6bf0743ece18 260 }
demayer 0:6bf0743ece18 261
demayer 0:6bf0743ece18 262 #define SVC0_0(f,t) \
demayer 0:6bf0743ece18 263 __SVC_INDIRECT(0) t svc##f (); \
demayer 0:6bf0743ece18 264 t svcRtx##f (void); \
demayer 0:6bf0743ece18 265 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 266 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 267 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 268 return svc##f(); \
demayer 0:6bf0743ece18 269 }
demayer 0:6bf0743ece18 270
demayer 0:6bf0743ece18 271 #define SVC0_0M(f,t) \
demayer 0:6bf0743ece18 272 __SVC_INDIRECT(0) t svc##f (); \
demayer 0:6bf0743ece18 273 t svcRtx##f (void); \
demayer 0:6bf0743ece18 274 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 275 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 276 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 277 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 278 return svc##f(); \
demayer 0:6bf0743ece18 279 }
demayer 0:6bf0743ece18 280
demayer 0:6bf0743ece18 281 #define SVC0_1N(f,t,t1) \
demayer 0:6bf0743ece18 282 __SVC_INDIRECT(0) t svc##f (t1 a1); \
demayer 0:6bf0743ece18 283 t svcRtx##f (t1 a1); \
demayer 0:6bf0743ece18 284 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 285 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 286 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 287 svc##f(a1); \
demayer 0:6bf0743ece18 288 }
demayer 0:6bf0743ece18 289
demayer 0:6bf0743ece18 290 #define SVC0_1(f,t,t1) \
demayer 0:6bf0743ece18 291 __SVC_INDIRECT(0) t svc##f (t1 a1); \
demayer 0:6bf0743ece18 292 t svcRtx##f (t1 a1); \
demayer 0:6bf0743ece18 293 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 294 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 295 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 296 return svc##f(a1); \
demayer 0:6bf0743ece18 297 }
demayer 0:6bf0743ece18 298
demayer 0:6bf0743ece18 299 #define SVC0_1M(f,t,t1) \
demayer 0:6bf0743ece18 300 __SVC_INDIRECT(0) t svc##f (t1 a1); \
demayer 0:6bf0743ece18 301 t svcRtx##f (t1 a1); \
demayer 0:6bf0743ece18 302 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 303 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 304 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 305 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 306 return svc##f(a1); \
demayer 0:6bf0743ece18 307 }
demayer 0:6bf0743ece18 308
demayer 0:6bf0743ece18 309 #define SVC0_2(f,t,t1,t2) \
demayer 0:6bf0743ece18 310 __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \
demayer 0:6bf0743ece18 311 t svcRtx##f (t1 a1, t2 a2); \
demayer 0:6bf0743ece18 312 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 313 __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
demayer 0:6bf0743ece18 314 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 315 return svc##f(a1,a2); \
demayer 0:6bf0743ece18 316 }
demayer 0:6bf0743ece18 317
demayer 0:6bf0743ece18 318 #define SVC0_2M(f,t,t1,t2) \
demayer 0:6bf0743ece18 319 __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \
demayer 0:6bf0743ece18 320 t svcRtx##f (t1 a1, t2 a2); \
demayer 0:6bf0743ece18 321 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 322 __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
demayer 0:6bf0743ece18 323 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 324 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 325 return svc##f(a1,a2); \
demayer 0:6bf0743ece18 326 }
demayer 0:6bf0743ece18 327
demayer 0:6bf0743ece18 328 #define SVC0_3(f,t,t1,t2,t3) \
demayer 0:6bf0743ece18 329 __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \
demayer 0:6bf0743ece18 330 t svcRtx##f (t1 a1, t2 a2, t3 a3); \
demayer 0:6bf0743ece18 331 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 332 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
demayer 0:6bf0743ece18 333 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 334 return svc##f(a1,a2,a3); \
demayer 0:6bf0743ece18 335 }
demayer 0:6bf0743ece18 336
demayer 0:6bf0743ece18 337 #define SVC0_3M(f,t,t1,t2,t3) \
demayer 0:6bf0743ece18 338 __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \
demayer 0:6bf0743ece18 339 t svcRtx##f (t1 a1, t2 a2, t3 a3); \
demayer 0:6bf0743ece18 340 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 341 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
demayer 0:6bf0743ece18 342 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 343 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 344 return svc##f(a1,a2,a3); \
demayer 0:6bf0743ece18 345 }
demayer 0:6bf0743ece18 346
demayer 0:6bf0743ece18 347 #define SVC0_4(f,t,t1,t2,t3,t4) \
demayer 0:6bf0743ece18 348 __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \
demayer 0:6bf0743ece18 349 t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \
demayer 0:6bf0743ece18 350 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 351 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
demayer 0:6bf0743ece18 352 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 353 return svc##f(a1,a2,a3,a4); \
demayer 0:6bf0743ece18 354 }
demayer 0:6bf0743ece18 355
demayer 0:6bf0743ece18 356 #define SVC0_4M(f,t,t1,t2,t3,t4) \
demayer 0:6bf0743ece18 357 __SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \
demayer 0:6bf0743ece18 358 t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \
demayer 0:6bf0743ece18 359 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 360 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
demayer 0:6bf0743ece18 361 SVC_SETUP_PSP \
demayer 0:6bf0743ece18 362 SVC_Setup(svcRtx##f); \
demayer 0:6bf0743ece18 363 return svc##f(a1,a2,a3,a4); \
demayer 0:6bf0743ece18 364 }
demayer 0:6bf0743ece18 365
demayer 0:6bf0743ece18 366 #else // !(defined(__CC_ARM) || defined(__ICCARM__))
demayer 0:6bf0743ece18 367
demayer 0:6bf0743ece18 368 #if ((__ARM_ARCH_7M__ == 1U) || \
demayer 0:6bf0743ece18 369 (__ARM_ARCH_7EM__ == 1U) || \
demayer 0:6bf0743ece18 370 (__ARM_ARCH_8M_MAIN__ == 1U))
demayer 0:6bf0743ece18 371 #define SVC_RegF "r12"
demayer 0:6bf0743ece18 372 #elif ((__ARM_ARCH_6M__ == 1U) || \
demayer 0:6bf0743ece18 373 (__ARM_ARCH_8M_BASE__ == 1U))
demayer 0:6bf0743ece18 374 #define SVC_RegF "r7"
demayer 0:6bf0743ece18 375 #endif
demayer 0:6bf0743ece18 376
demayer 0:6bf0743ece18 377 #define SVC_ArgN(n) \
demayer 0:6bf0743ece18 378 register uint32_t __r##n __ASM("r"#n)
demayer 0:6bf0743ece18 379
demayer 0:6bf0743ece18 380 #define SVC_ArgR(n,a) \
demayer 0:6bf0743ece18 381 register uint32_t __r##n __ASM("r"#n) = (uint32_t)a
demayer 0:6bf0743ece18 382
demayer 0:6bf0743ece18 383 #define SVC_ArgF(f) \
demayer 0:6bf0743ece18 384 register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)f
demayer 0:6bf0743ece18 385
demayer 0:6bf0743ece18 386 #define SVC_In0 "r"(__rf)
demayer 0:6bf0743ece18 387 #define SVC_In1 "r"(__rf),"r"(__r0)
demayer 0:6bf0743ece18 388 #define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1)
demayer 0:6bf0743ece18 389 #define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2)
demayer 0:6bf0743ece18 390 #define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3)
demayer 0:6bf0743ece18 391
demayer 0:6bf0743ece18 392 #define SVC_Out0
demayer 0:6bf0743ece18 393 #define SVC_Out1 "=r"(__r0)
demayer 0:6bf0743ece18 394 #define SVC_Out2 "=r"(__r0),"=r"(__r1)
demayer 0:6bf0743ece18 395
demayer 0:6bf0743ece18 396 #define SVC_CL0
demayer 0:6bf0743ece18 397 #define SVC_CL1 "r1"
demayer 0:6bf0743ece18 398 #define SVC_CL2 "r0","r1"
demayer 0:6bf0743ece18 399
demayer 0:6bf0743ece18 400 #define SVC_Call0(in, out, cl) \
demayer 0:6bf0743ece18 401 __ASM volatile ("svc 0" : out : in : cl)
demayer 0:6bf0743ece18 402
demayer 0:6bf0743ece18 403 #if ((__ARM_ARCH_7M__ == 1U) || \
demayer 0:6bf0743ece18 404 (__ARM_ARCH_7EM__ == 1U) || \
demayer 0:6bf0743ece18 405 (__ARM_ARCH_8M_MAIN__ == 1U))
demayer 0:6bf0743ece18 406 #if (__FPU_USED == 1U)
demayer 0:6bf0743ece18 407 #define SVC_Call0M(in, out, cl) \
demayer 0:6bf0743ece18 408 register uint32_t val; \
demayer 0:6bf0743ece18 409 __ASM volatile ( \
demayer 0:6bf0743ece18 410 ".syntax unified\n\t" \
demayer 0:6bf0743ece18 411 "mrs %[val],control\n\t" \
demayer 0:6bf0743ece18 412 "tst %[val],#2\n\t" \
demayer 0:6bf0743ece18 413 "bne 0f\n\t" \
demayer 0:6bf0743ece18 414 "tst %[val],#4\n\t" \
demayer 0:6bf0743ece18 415 "mrs %[val],msp\n\t" \
demayer 0:6bf0743ece18 416 "ite eq\n\t" \
demayer 0:6bf0743ece18 417 "subeq %[val],#32\n\t" \
demayer 0:6bf0743ece18 418 "subne %[val],#104\n\t" \
demayer 0:6bf0743ece18 419 "bic %[val],#7\n\t" \
demayer 0:6bf0743ece18 420 "msr psp,%[val]\n\t" \
demayer 0:6bf0743ece18 421 "0:\n\t" \
demayer 0:6bf0743ece18 422 "svc 0" \
demayer 0:6bf0743ece18 423 : out, [val] "=&l" (val) : in : cl)
demayer 0:6bf0743ece18 424 #else
demayer 0:6bf0743ece18 425 #define SVC_Call0M(in, out, cl) \
demayer 0:6bf0743ece18 426 register uint32_t val; \
demayer 0:6bf0743ece18 427 __ASM volatile ( \
demayer 0:6bf0743ece18 428 ".syntax unified\n\t" \
demayer 0:6bf0743ece18 429 "mrs %[val],control\n\t" \
demayer 0:6bf0743ece18 430 "tst %[val],#2\n\t" \
demayer 0:6bf0743ece18 431 "bne 0f\n\t" \
demayer 0:6bf0743ece18 432 "mrs %[val],msp\n\t" \
demayer 0:6bf0743ece18 433 "subs %[val],#32\n\t" \
demayer 0:6bf0743ece18 434 "bic %[val],#7\n\t" \
demayer 0:6bf0743ece18 435 "msr psp,%[val]\n\t" \
demayer 0:6bf0743ece18 436 "0:\n\t" \
demayer 0:6bf0743ece18 437 "svc 0" \
demayer 0:6bf0743ece18 438 : out, [val] "=&l" (val) : in : cl)
demayer 0:6bf0743ece18 439 #endif
demayer 0:6bf0743ece18 440 #elif ((__ARM_ARCH_6M__ == 1U) || \
demayer 0:6bf0743ece18 441 (__ARM_ARCH_8M_BASE__ == 1U))
demayer 0:6bf0743ece18 442 #define SVC_Call0M(in, out, cl) \
demayer 0:6bf0743ece18 443 register uint32_t val; \
demayer 0:6bf0743ece18 444 __ASM volatile ( \
demayer 0:6bf0743ece18 445 ".syntax unified\n\t" \
demayer 0:6bf0743ece18 446 "mrs %[val],control\n\t" \
demayer 0:6bf0743ece18 447 "lsls %[val],#30\n\t" \
demayer 0:6bf0743ece18 448 "bmi 0f\n\t" \
demayer 0:6bf0743ece18 449 "mrs %[val],msp\n\t" \
demayer 0:6bf0743ece18 450 "subs %[val],#32\n\t" \
demayer 0:6bf0743ece18 451 "lsrs %[val],#3\n\t" \
demayer 0:6bf0743ece18 452 "lsls %[val],#3\n\t" \
demayer 0:6bf0743ece18 453 "msr psp,%[val]\n\t" \
demayer 0:6bf0743ece18 454 "0:\n\t" \
demayer 0:6bf0743ece18 455 "svc 0" \
demayer 0:6bf0743ece18 456 : out, [val] "=&l" (val) : in : cl)
demayer 0:6bf0743ece18 457 #endif
demayer 0:6bf0743ece18 458
demayer 0:6bf0743ece18 459 #define SVC0_0N(f,t) \
demayer 0:6bf0743ece18 460 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 461 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 462 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 463 SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2); \
demayer 0:6bf0743ece18 464 }
demayer 0:6bf0743ece18 465
demayer 0:6bf0743ece18 466 #define SVC0_0(f,t) \
demayer 0:6bf0743ece18 467 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 468 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 469 SVC_ArgN(0); \
demayer 0:6bf0743ece18 470 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 471 SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1); \
demayer 0:6bf0743ece18 472 return (t) __r0; \
demayer 0:6bf0743ece18 473 }
demayer 0:6bf0743ece18 474
demayer 0:6bf0743ece18 475 #define SVC0_0M(f,t) \
demayer 0:6bf0743ece18 476 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 477 __STATIC_INLINE t __svc##f (void) { \
demayer 0:6bf0743ece18 478 SVC_ArgN(0); \
demayer 0:6bf0743ece18 479 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 480 SVC_Call0M(SVC_In0, SVC_Out1, SVC_CL1); \
demayer 0:6bf0743ece18 481 return (t) __r0; \
demayer 0:6bf0743ece18 482 }
demayer 0:6bf0743ece18 483
demayer 0:6bf0743ece18 484 #define SVC0_1N(f,t,t1) \
demayer 0:6bf0743ece18 485 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 486 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 487 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 488 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 489 SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1); \
demayer 0:6bf0743ece18 490 }
demayer 0:6bf0743ece18 491
demayer 0:6bf0743ece18 492 #define SVC0_1(f,t,t1) \
demayer 0:6bf0743ece18 493 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 494 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 495 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 496 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 497 SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1); \
demayer 0:6bf0743ece18 498 return (t) __r0; \
demayer 0:6bf0743ece18 499 }
demayer 0:6bf0743ece18 500
demayer 0:6bf0743ece18 501 #define SVC0_1M(f,t,t1) \
demayer 0:6bf0743ece18 502 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 503 __STATIC_INLINE t __svc##f (t1 a1) { \
demayer 0:6bf0743ece18 504 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 505 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 506 SVC_Call0M(SVC_In1, SVC_Out1, SVC_CL1); \
demayer 0:6bf0743ece18 507 return (t) __r0; \
demayer 0:6bf0743ece18 508 }
demayer 0:6bf0743ece18 509
demayer 0:6bf0743ece18 510 #define SVC0_2(f,t,t1,t2) \
demayer 0:6bf0743ece18 511 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 512 __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
demayer 0:6bf0743ece18 513 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 514 SVC_ArgR(1,a2); \
demayer 0:6bf0743ece18 515 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 516 SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0); \
demayer 0:6bf0743ece18 517 return (t) __r0; \
demayer 0:6bf0743ece18 518 }
demayer 0:6bf0743ece18 519
demayer 0:6bf0743ece18 520 #define SVC0_2M(f,t,t1,t2) \
demayer 0:6bf0743ece18 521 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 522 __STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \
demayer 0:6bf0743ece18 523 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 524 SVC_ArgR(1,a2); \
demayer 0:6bf0743ece18 525 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 526 SVC_Call0M(SVC_In2, SVC_Out1, SVC_CL0); \
demayer 0:6bf0743ece18 527 return (t) __r0; \
demayer 0:6bf0743ece18 528 }
demayer 0:6bf0743ece18 529
demayer 0:6bf0743ece18 530 #define SVC0_3(f,t,t1,t2,t3) \
demayer 0:6bf0743ece18 531 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 532 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
demayer 0:6bf0743ece18 533 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 534 SVC_ArgR(1,a2); \
demayer 0:6bf0743ece18 535 SVC_ArgR(2,a3); \
demayer 0:6bf0743ece18 536 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 537 SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0); \
demayer 0:6bf0743ece18 538 return (t) __r0; \
demayer 0:6bf0743ece18 539 }
demayer 0:6bf0743ece18 540
demayer 0:6bf0743ece18 541 #define SVC0_3M(f,t,t1,t2,t3) \
demayer 0:6bf0743ece18 542 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 543 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \
demayer 0:6bf0743ece18 544 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 545 SVC_ArgR(1,a2); \
demayer 0:6bf0743ece18 546 SVC_ArgR(2,a3); \
demayer 0:6bf0743ece18 547 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 548 SVC_Call0M(SVC_In3, SVC_Out1, SVC_CL0); \
demayer 0:6bf0743ece18 549 return (t) __r0; \
demayer 0:6bf0743ece18 550 }
demayer 0:6bf0743ece18 551
demayer 0:6bf0743ece18 552 #define SVC0_4(f,t,t1,t2,t3,t4) \
demayer 0:6bf0743ece18 553 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 554 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
demayer 0:6bf0743ece18 555 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 556 SVC_ArgR(1,a2); \
demayer 0:6bf0743ece18 557 SVC_ArgR(2,a3); \
demayer 0:6bf0743ece18 558 SVC_ArgR(3,a4); \
demayer 0:6bf0743ece18 559 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 560 SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0); \
demayer 0:6bf0743ece18 561 return (t) __r0; \
demayer 0:6bf0743ece18 562 }
demayer 0:6bf0743ece18 563
demayer 0:6bf0743ece18 564 #define SVC0_4M(f,t,t1,t2,t3,t4) \
demayer 0:6bf0743ece18 565 __attribute__((always_inline)) \
demayer 0:6bf0743ece18 566 __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
demayer 0:6bf0743ece18 567 SVC_ArgR(0,a1); \
demayer 0:6bf0743ece18 568 SVC_ArgR(1,a2); \
demayer 0:6bf0743ece18 569 SVC_ArgR(2,a3); \
demayer 0:6bf0743ece18 570 SVC_ArgR(3,a4); \
demayer 0:6bf0743ece18 571 SVC_ArgF(svcRtx##f); \
demayer 0:6bf0743ece18 572 SVC_Call0M(SVC_In4, SVC_Out1, SVC_CL0); \
demayer 0:6bf0743ece18 573 return (t) __r0; \
demayer 0:6bf0743ece18 574 }
demayer 0:6bf0743ece18 575
demayer 0:6bf0743ece18 576 #endif
demayer 0:6bf0743ece18 577
demayer 0:6bf0743ece18 578
demayer 0:6bf0743ece18 579 // ==== Core Peripherals functions ====
demayer 0:6bf0743ece18 580
demayer 0:6bf0743ece18 581 /// Initialize SVC and PendSV System Service Calls
demayer 0:6bf0743ece18 582 __STATIC_INLINE void SVC_Initialize (void) {
demayer 0:6bf0743ece18 583 #if ((__ARM_ARCH_8M_MAIN__ == 1U) || (defined(__CORTEX_M) && (__CORTEX_M == 7U)))
demayer 0:6bf0743ece18 584 uint32_t p, n;
demayer 0:6bf0743ece18 585
demayer 0:6bf0743ece18 586 SCB->SHPR[10] = 0xFFU;
demayer 0:6bf0743ece18 587 n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U));
demayer 0:6bf0743ece18 588 p = NVIC_GetPriorityGrouping();
demayer 0:6bf0743ece18 589 if (p >= n) {
demayer 0:6bf0743ece18 590 n = p + 1U;
demayer 0:6bf0743ece18 591 }
demayer 0:6bf0743ece18 592 SCB->SHPR[7] = (uint8_t)(0xFEU << n);
demayer 0:6bf0743ece18 593 #elif (__ARM_ARCH_8M_BASE__ == 1U)
demayer 0:6bf0743ece18 594 uint32_t n;
demayer 0:6bf0743ece18 595
demayer 0:6bf0743ece18 596 SCB->SHPR[1] |= 0x00FF0000U;
demayer 0:6bf0743ece18 597 n = SCB->SHPR[1];
demayer 0:6bf0743ece18 598 SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U;
demayer 0:6bf0743ece18 599 #elif ((__ARM_ARCH_7M__ == 1U) || \
demayer 0:6bf0743ece18 600 (__ARM_ARCH_7EM__ == 1U))
demayer 0:6bf0743ece18 601 uint32_t p, n;
demayer 0:6bf0743ece18 602
demayer 0:6bf0743ece18 603 SCB->SHP[10] = 0xFFU;
demayer 0:6bf0743ece18 604 n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U));
demayer 0:6bf0743ece18 605 p = NVIC_GetPriorityGrouping();
demayer 0:6bf0743ece18 606 if (p >= n) {
demayer 0:6bf0743ece18 607 n = p + 1U;
demayer 0:6bf0743ece18 608 }
demayer 0:6bf0743ece18 609
demayer 0:6bf0743ece18 610 /* Only change the SVCall priority if uVisor is not present. */
demayer 0:6bf0743ece18 611 #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
demayer 0:6bf0743ece18 612 SCB->SHP[7] = (uint8_t)(0xFEU << n);
demayer 0:6bf0743ece18 613 #endif
demayer 0:6bf0743ece18 614 #elif (__ARM_ARCH_6M__ == 1U)
demayer 0:6bf0743ece18 615 uint32_t n;
demayer 0:6bf0743ece18 616
demayer 0:6bf0743ece18 617 SCB->SHP[1] |= 0x00FF0000U;
demayer 0:6bf0743ece18 618 n = SCB->SHP[1];
demayer 0:6bf0743ece18 619 SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U;
demayer 0:6bf0743ece18 620 #endif
demayer 0:6bf0743ece18 621 }
demayer 0:6bf0743ece18 622
demayer 0:6bf0743ece18 623 /// Get Pending SV (Service Call) Flag
demayer 0:6bf0743ece18 624 /// \return Pending SV Flag
demayer 0:6bf0743ece18 625 __STATIC_INLINE uint8_t GetPendSV (void) {
demayer 0:6bf0743ece18 626 return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24));
demayer 0:6bf0743ece18 627 }
demayer 0:6bf0743ece18 628
demayer 0:6bf0743ece18 629 /// Clear Pending SV (Service Call) Flag
demayer 0:6bf0743ece18 630 __STATIC_INLINE void ClrPendSV (void) {
demayer 0:6bf0743ece18 631 SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;
demayer 0:6bf0743ece18 632 }
demayer 0:6bf0743ece18 633
demayer 0:6bf0743ece18 634 /// Set Pending SV (Service Call) Flag
demayer 0:6bf0743ece18 635 __STATIC_INLINE void SetPendSV (void) {
demayer 0:6bf0743ece18 636 SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
demayer 0:6bf0743ece18 637 }
demayer 0:6bf0743ece18 638
demayer 0:6bf0743ece18 639
demayer 0:6bf0743ece18 640 // ==== Exclusive Access Operation ====
demayer 0:6bf0743ece18 641
demayer 0:6bf0743ece18 642 #if (__EXCLUSIVE_ACCESS == 1U)
demayer 0:6bf0743ece18 643
demayer 0:6bf0743ece18 644 /// Atomic Access Operation: Write (8-bit)
demayer 0:6bf0743ece18 645 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 646 /// \param[in] val Value to write
demayer 0:6bf0743ece18 647 /// \return Previous value
demayer 0:6bf0743ece18 648 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 649 static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
demayer 0:6bf0743ece18 650 mov r2,r0
demayer 0:6bf0743ece18 651 1
demayer 0:6bf0743ece18 652 ldrexb r0,[r2]
demayer 0:6bf0743ece18 653 strexb r3,r1,[r2]
demayer 0:6bf0743ece18 654 cbz r3,%F2
demayer 0:6bf0743ece18 655 b %B1
demayer 0:6bf0743ece18 656 2
demayer 0:6bf0743ece18 657 bx lr
demayer 0:6bf0743ece18 658 }
demayer 0:6bf0743ece18 659 #else
demayer 0:6bf0743ece18 660 __STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {
demayer 0:6bf0743ece18 661 #ifdef __ICCARM__
demayer 0:6bf0743ece18 662 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 663 #endif
demayer 0:6bf0743ece18 664 register uint32_t res;
demayer 0:6bf0743ece18 665 #ifdef __ICCARM__
demayer 0:6bf0743ece18 666 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 667 #endif
demayer 0:6bf0743ece18 668 register uint8_t ret;
demayer 0:6bf0743ece18 669
demayer 0:6bf0743ece18 670 __ASM volatile (
demayer 0:6bf0743ece18 671 #ifndef __ICCARM__
demayer 0:6bf0743ece18 672 ".syntax unified\n\t"
demayer 0:6bf0743ece18 673 #endif
demayer 0:6bf0743ece18 674 "1:\n\t"
demayer 0:6bf0743ece18 675 "ldrexb %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 676 "strexb %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 677 "cbz %[res],2f\n\t"
demayer 0:6bf0743ece18 678 "b 1b\n"
demayer 0:6bf0743ece18 679 "2:"
demayer 0:6bf0743ece18 680 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 681 [res] "=&l" (res)
demayer 0:6bf0743ece18 682 : [mem] "l" (mem),
demayer 0:6bf0743ece18 683 [val] "l" (val)
demayer 0:6bf0743ece18 684 : "memory"
demayer 0:6bf0743ece18 685 );
demayer 0:6bf0743ece18 686
demayer 0:6bf0743ece18 687 return ret;
demayer 0:6bf0743ece18 688 }
demayer 0:6bf0743ece18 689 #endif
demayer 0:6bf0743ece18 690
demayer 0:6bf0743ece18 691 /// Atomic Access Operation: Set bits (32-bit)
demayer 0:6bf0743ece18 692 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 693 /// \param[in] bits Bit mask
demayer 0:6bf0743ece18 694 /// \return New value
demayer 0:6bf0743ece18 695 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 696 static __asm uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
demayer 0:6bf0743ece18 697 mov r2,r0
demayer 0:6bf0743ece18 698 1
demayer 0:6bf0743ece18 699 ldrex r0,[r2]
demayer 0:6bf0743ece18 700 orr r0,r0,r1
demayer 0:6bf0743ece18 701 strex r3,r0,[r2]
demayer 0:6bf0743ece18 702 cbz r3,%F2
demayer 0:6bf0743ece18 703 b %B1
demayer 0:6bf0743ece18 704 2
demayer 0:6bf0743ece18 705 bx lr
demayer 0:6bf0743ece18 706 }
demayer 0:6bf0743ece18 707 #else
demayer 0:6bf0743ece18 708 __STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
demayer 0:6bf0743ece18 709 #ifdef __ICCARM__
demayer 0:6bf0743ece18 710 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 711 #endif
demayer 0:6bf0743ece18 712 register uint32_t val, res;
demayer 0:6bf0743ece18 713 #ifdef __ICCARM__
demayer 0:6bf0743ece18 714 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 715 #endif
demayer 0:6bf0743ece18 716 register uint32_t ret;
demayer 0:6bf0743ece18 717
demayer 0:6bf0743ece18 718 __ASM volatile (
demayer 0:6bf0743ece18 719 #ifndef __ICCARM__
demayer 0:6bf0743ece18 720 ".syntax unified\n\t"
demayer 0:6bf0743ece18 721 #endif
demayer 0:6bf0743ece18 722 "1:\n\t"
demayer 0:6bf0743ece18 723 "ldrex %[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 724 #if (__ARM_ARCH_8M_BASE__ == 1U)
demayer 0:6bf0743ece18 725 "mov %[ret],%[val]\n\t"
demayer 0:6bf0743ece18 726 "orrs %[ret],%[bits]\n\t"
demayer 0:6bf0743ece18 727 #else
demayer 0:6bf0743ece18 728 "orr %[ret],%[val],%[bits]\n\t"
demayer 0:6bf0743ece18 729 #endif
demayer 0:6bf0743ece18 730 "strex %[res],%[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 731 "cbz %[res],2f\n\t"
demayer 0:6bf0743ece18 732 "b 1b\n"
demayer 0:6bf0743ece18 733 "2:"
demayer 0:6bf0743ece18 734 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 735 [val] "=&l" (val),
demayer 0:6bf0743ece18 736 [res] "=&l" (res)
demayer 0:6bf0743ece18 737 : [mem] "l" (mem),
demayer 0:6bf0743ece18 738 [bits] "l" (bits)
demayer 0:6bf0743ece18 739 #if (__ARM_ARCH_8M_BASE__ == 1U)
demayer 0:6bf0743ece18 740 : "memory", "cc"
demayer 0:6bf0743ece18 741 #else
demayer 0:6bf0743ece18 742 : "memory"
demayer 0:6bf0743ece18 743 #endif
demayer 0:6bf0743ece18 744 );
demayer 0:6bf0743ece18 745
demayer 0:6bf0743ece18 746 return ret;
demayer 0:6bf0743ece18 747 }
demayer 0:6bf0743ece18 748 #endif
demayer 0:6bf0743ece18 749
demayer 0:6bf0743ece18 750 /// Atomic Access Operation: Clear bits (32-bit)
demayer 0:6bf0743ece18 751 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 752 /// \param[in] bits Bit mask
demayer 0:6bf0743ece18 753 /// \return Previous value
demayer 0:6bf0743ece18 754 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 755 static __asm uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
demayer 0:6bf0743ece18 756 push {r4,lr}
demayer 0:6bf0743ece18 757 mov r2,r0
demayer 0:6bf0743ece18 758 1
demayer 0:6bf0743ece18 759 ldrex r0,[r2]
demayer 0:6bf0743ece18 760 bic r4,r0,r1
demayer 0:6bf0743ece18 761 strex r3,r4,[r2]
demayer 0:6bf0743ece18 762 cbz r3,%F2
demayer 0:6bf0743ece18 763 b %B1
demayer 0:6bf0743ece18 764 2
demayer 0:6bf0743ece18 765 pop {r4,pc}
demayer 0:6bf0743ece18 766 }
demayer 0:6bf0743ece18 767 #else
demayer 0:6bf0743ece18 768 __STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
demayer 0:6bf0743ece18 769 #ifdef __ICCARM__
demayer 0:6bf0743ece18 770 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 771 #endif
demayer 0:6bf0743ece18 772 register uint32_t val, res;
demayer 0:6bf0743ece18 773 #ifdef __ICCARM__
demayer 0:6bf0743ece18 774 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 775 #endif
demayer 0:6bf0743ece18 776 register uint32_t ret;
demayer 0:6bf0743ece18 777
demayer 0:6bf0743ece18 778 __ASM volatile (
demayer 0:6bf0743ece18 779 #ifndef __ICCARM__
demayer 0:6bf0743ece18 780 ".syntax unified\n\t"
demayer 0:6bf0743ece18 781 #endif
demayer 0:6bf0743ece18 782 "1:\n\t"
demayer 0:6bf0743ece18 783 "ldrex %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 784 #if (__ARM_ARCH_8M_BASE__ == 1U)
demayer 0:6bf0743ece18 785 "mov %[val],%[ret]\n\t"
demayer 0:6bf0743ece18 786 "bics %[val],%[bits]\n\t"
demayer 0:6bf0743ece18 787 #else
demayer 0:6bf0743ece18 788 "bic %[val],%[ret],%[bits]\n\t"
demayer 0:6bf0743ece18 789 #endif
demayer 0:6bf0743ece18 790 "strex %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 791 "cbz %[res],2f\n\t"
demayer 0:6bf0743ece18 792 "b 1b\n"
demayer 0:6bf0743ece18 793 "2:"
demayer 0:6bf0743ece18 794 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 795 [val] "=&l" (val),
demayer 0:6bf0743ece18 796 [res] "=&l" (res)
demayer 0:6bf0743ece18 797 : [mem] "l" (mem),
demayer 0:6bf0743ece18 798 [bits] "l" (bits)
demayer 0:6bf0743ece18 799 #if (__ARM_ARCH_8M_BASE__ == 1U)
demayer 0:6bf0743ece18 800 : "memory", "cc"
demayer 0:6bf0743ece18 801 #else
demayer 0:6bf0743ece18 802 : "memory"
demayer 0:6bf0743ece18 803 #endif
demayer 0:6bf0743ece18 804 );
demayer 0:6bf0743ece18 805
demayer 0:6bf0743ece18 806 return ret;
demayer 0:6bf0743ece18 807 }
demayer 0:6bf0743ece18 808 #endif
demayer 0:6bf0743ece18 809
demayer 0:6bf0743ece18 810 /// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them
demayer 0:6bf0743ece18 811 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 812 /// \param[in] bits Bit mask
demayer 0:6bf0743ece18 813 /// \return Active bits before clearing or 0 if not active
demayer 0:6bf0743ece18 814 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 815 static __asm uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
demayer 0:6bf0743ece18 816 push {r4,lr}
demayer 0:6bf0743ece18 817 mov r2,r0
demayer 0:6bf0743ece18 818 1
demayer 0:6bf0743ece18 819 ldrex r0,[r2]
demayer 0:6bf0743ece18 820 and r4,r0,r1
demayer 0:6bf0743ece18 821 cmp r4,r1
demayer 0:6bf0743ece18 822 beq %F2
demayer 0:6bf0743ece18 823 clrex
demayer 0:6bf0743ece18 824 movs r0,#0
demayer 0:6bf0743ece18 825 pop {r4,pc}
demayer 0:6bf0743ece18 826 2
demayer 0:6bf0743ece18 827 bic r4,r0,r1
demayer 0:6bf0743ece18 828 strex r3,r4,[r2]
demayer 0:6bf0743ece18 829 cbz r3,%F3
demayer 0:6bf0743ece18 830 b %B1
demayer 0:6bf0743ece18 831 3
demayer 0:6bf0743ece18 832 pop {r4,pc}
demayer 0:6bf0743ece18 833 }
demayer 0:6bf0743ece18 834 #else
demayer 0:6bf0743ece18 835 __STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
demayer 0:6bf0743ece18 836 #ifdef __ICCARM__
demayer 0:6bf0743ece18 837 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 838 #endif
demayer 0:6bf0743ece18 839 register uint32_t val, res;
demayer 0:6bf0743ece18 840 #ifdef __ICCARM__
demayer 0:6bf0743ece18 841 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 842 #endif
demayer 0:6bf0743ece18 843 register uint32_t ret;
demayer 0:6bf0743ece18 844
demayer 0:6bf0743ece18 845 __ASM volatile (
demayer 0:6bf0743ece18 846 #ifndef __ICCARM__
demayer 0:6bf0743ece18 847 ".syntax unified\n\t"
demayer 0:6bf0743ece18 848 #endif
demayer 0:6bf0743ece18 849 "1:\n\t"
demayer 0:6bf0743ece18 850 "ldrex %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 851 #if (__ARM_ARCH_8M_BASE__ == 1U)
demayer 0:6bf0743ece18 852 "mov %[val],%[ret]\n\t"
demayer 0:6bf0743ece18 853 "ands %[val],%[bits]\n\t"
demayer 0:6bf0743ece18 854 #else
demayer 0:6bf0743ece18 855 "and %[val],%[ret],%[bits]\n\t"
demayer 0:6bf0743ece18 856 #endif
demayer 0:6bf0743ece18 857 "cmp %[val],%[bits]\n\t"
demayer 0:6bf0743ece18 858 "beq 2f\n\t"
demayer 0:6bf0743ece18 859 "clrex\n\t"
demayer 0:6bf0743ece18 860 "movs %[ret],#0\n\t"
demayer 0:6bf0743ece18 861 "b 3f\n"
demayer 0:6bf0743ece18 862 "2:\n\t"
demayer 0:6bf0743ece18 863 #if (__ARM_ARCH_8M_BASE__ == 1U)
demayer 0:6bf0743ece18 864 "mov %[val],%[ret]\n\t"
demayer 0:6bf0743ece18 865 "bics %[val],%[bits]\n\t"
demayer 0:6bf0743ece18 866 #else
demayer 0:6bf0743ece18 867 "bic %[val],%[ret],%[bits]\n\t"
demayer 0:6bf0743ece18 868 #endif
demayer 0:6bf0743ece18 869 "strex %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 870 "cbz %[res],3f\n\t"
demayer 0:6bf0743ece18 871 "b 1b\n"
demayer 0:6bf0743ece18 872 "3:"
demayer 0:6bf0743ece18 873 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 874 [val] "=&l" (val),
demayer 0:6bf0743ece18 875 [res] "=&l" (res)
demayer 0:6bf0743ece18 876 : [mem] "l" (mem),
demayer 0:6bf0743ece18 877 [bits] "l" (bits)
demayer 0:6bf0743ece18 878 : "cc", "memory"
demayer 0:6bf0743ece18 879 );
demayer 0:6bf0743ece18 880
demayer 0:6bf0743ece18 881 return ret;
demayer 0:6bf0743ece18 882 }
demayer 0:6bf0743ece18 883 #endif
demayer 0:6bf0743ece18 884
demayer 0:6bf0743ece18 885 /// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them
demayer 0:6bf0743ece18 886 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 887 /// \param[in] bits Bit mask
demayer 0:6bf0743ece18 888 /// \return Active bits before clearing or 0 if not active
demayer 0:6bf0743ece18 889 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 890 static __asm uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
demayer 0:6bf0743ece18 891 push {r4,lr}
demayer 0:6bf0743ece18 892 mov r2,r0
demayer 0:6bf0743ece18 893 1
demayer 0:6bf0743ece18 894 ldrex r0,[r2]
demayer 0:6bf0743ece18 895 tst r0,r1
demayer 0:6bf0743ece18 896 bne %F2
demayer 0:6bf0743ece18 897 clrex
demayer 0:6bf0743ece18 898 movs r0,#0
demayer 0:6bf0743ece18 899 pop {r4,pc}
demayer 0:6bf0743ece18 900 2
demayer 0:6bf0743ece18 901 bic r4,r0,r1
demayer 0:6bf0743ece18 902 strex r3,r4,[r2]
demayer 0:6bf0743ece18 903 cbz r3,%F3
demayer 0:6bf0743ece18 904 b %B1
demayer 0:6bf0743ece18 905 3
demayer 0:6bf0743ece18 906 pop {r4,pc}
demayer 0:6bf0743ece18 907 }
demayer 0:6bf0743ece18 908 #else
demayer 0:6bf0743ece18 909 __STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
demayer 0:6bf0743ece18 910 #ifdef __ICCARM__
demayer 0:6bf0743ece18 911 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 912 #endif
demayer 0:6bf0743ece18 913 register uint32_t val, res;
demayer 0:6bf0743ece18 914 #ifdef __ICCARM__
demayer 0:6bf0743ece18 915 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 916 #endif
demayer 0:6bf0743ece18 917 register uint32_t ret;
demayer 0:6bf0743ece18 918
demayer 0:6bf0743ece18 919 __ASM volatile (
demayer 0:6bf0743ece18 920 #ifndef __ICCARM__
demayer 0:6bf0743ece18 921 ".syntax unified\n\t"
demayer 0:6bf0743ece18 922 #endif
demayer 0:6bf0743ece18 923 "1:\n\t"
demayer 0:6bf0743ece18 924 "ldrex %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 925 "tst %[ret],%[bits]\n\t"
demayer 0:6bf0743ece18 926 "bne 2f\n\t"
demayer 0:6bf0743ece18 927 "clrex\n\t"
demayer 0:6bf0743ece18 928 "movs %[ret],#0\n\t"
demayer 0:6bf0743ece18 929 "b 3f\n"
demayer 0:6bf0743ece18 930 "2:\n\t"
demayer 0:6bf0743ece18 931 #if (__ARM_ARCH_8M_BASE__ == 1U)
demayer 0:6bf0743ece18 932 "mov %[val],%[ret]\n\t"
demayer 0:6bf0743ece18 933 "bics %[val],%[bits]\n\t"
demayer 0:6bf0743ece18 934 #else
demayer 0:6bf0743ece18 935 "bic %[val],%[ret],%[bits]\n\t"
demayer 0:6bf0743ece18 936 #endif
demayer 0:6bf0743ece18 937 "strex %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 938 "cbz %[res],3f\n\t"
demayer 0:6bf0743ece18 939 "b 1b\n"
demayer 0:6bf0743ece18 940 "3:"
demayer 0:6bf0743ece18 941 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 942 [val] "=&l" (val),
demayer 0:6bf0743ece18 943 [res] "=&l" (res)
demayer 0:6bf0743ece18 944 : [mem] "l" (mem),
demayer 0:6bf0743ece18 945 [bits] "l" (bits)
demayer 0:6bf0743ece18 946 : "cc", "memory"
demayer 0:6bf0743ece18 947 );
demayer 0:6bf0743ece18 948
demayer 0:6bf0743ece18 949 return ret;
demayer 0:6bf0743ece18 950 }
demayer 0:6bf0743ece18 951 #endif
demayer 0:6bf0743ece18 952
demayer 0:6bf0743ece18 953 /// Atomic Access Operation: Increment (32-bit)
demayer 0:6bf0743ece18 954 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 955 /// \return Previous value
demayer 0:6bf0743ece18 956 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 957 static __asm uint32_t atomic_inc32 (uint32_t *mem) {
demayer 0:6bf0743ece18 958 mov r2,r0
demayer 0:6bf0743ece18 959 1
demayer 0:6bf0743ece18 960 ldrex r0,[r2]
demayer 0:6bf0743ece18 961 adds r1,r0,#1
demayer 0:6bf0743ece18 962 strex r3,r1,[r2]
demayer 0:6bf0743ece18 963 cbz r3,%F2
demayer 0:6bf0743ece18 964 b %B1
demayer 0:6bf0743ece18 965 2
demayer 0:6bf0743ece18 966 bx lr
demayer 0:6bf0743ece18 967 }
demayer 0:6bf0743ece18 968 #else
demayer 0:6bf0743ece18 969 __STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) {
demayer 0:6bf0743ece18 970 #ifdef __ICCARM__
demayer 0:6bf0743ece18 971 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 972 #endif
demayer 0:6bf0743ece18 973 register uint32_t val, res;
demayer 0:6bf0743ece18 974 #ifdef __ICCARM__
demayer 0:6bf0743ece18 975 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 976 #endif
demayer 0:6bf0743ece18 977 register uint32_t ret;
demayer 0:6bf0743ece18 978
demayer 0:6bf0743ece18 979 __ASM volatile (
demayer 0:6bf0743ece18 980 #ifndef __ICCARM__
demayer 0:6bf0743ece18 981 ".syntax unified\n\t"
demayer 0:6bf0743ece18 982 #endif
demayer 0:6bf0743ece18 983 "1:\n\t"
demayer 0:6bf0743ece18 984 "ldrex %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 985 "adds %[val],%[ret],#1\n\t"
demayer 0:6bf0743ece18 986 "strex %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 987 "cbz %[res],2f\n\t"
demayer 0:6bf0743ece18 988 "b 1b\n"
demayer 0:6bf0743ece18 989 "2:"
demayer 0:6bf0743ece18 990 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 991 [val] "=&l" (val),
demayer 0:6bf0743ece18 992 [res] "=&l" (res)
demayer 0:6bf0743ece18 993 : [mem] "l" (mem)
demayer 0:6bf0743ece18 994 : "cc", "memory"
demayer 0:6bf0743ece18 995 );
demayer 0:6bf0743ece18 996
demayer 0:6bf0743ece18 997 return ret;
demayer 0:6bf0743ece18 998 }
demayer 0:6bf0743ece18 999 #endif
demayer 0:6bf0743ece18 1000
demayer 0:6bf0743ece18 1001 /// atomic Access Operation: Increment (32-bit) if Less Than
demayer 0:6bf0743ece18 1002 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 1003 /// \param[in] max Maximum value
demayer 0:6bf0743ece18 1004 /// \return Previous value
demayer 0:6bf0743ece18 1005 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 1006 static __asm uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) {
demayer 0:6bf0743ece18 1007 push {r4,lr}
demayer 0:6bf0743ece18 1008 mov r2,r0
demayer 0:6bf0743ece18 1009 1
demayer 0:6bf0743ece18 1010 ldrex r0,[r2]
demayer 0:6bf0743ece18 1011 cmp r1,r0
demayer 0:6bf0743ece18 1012 bhi %F2
demayer 0:6bf0743ece18 1013 clrex
demayer 0:6bf0743ece18 1014 pop {r4,pc}
demayer 0:6bf0743ece18 1015 2
demayer 0:6bf0743ece18 1016 adds r4,r0,#1
demayer 0:6bf0743ece18 1017 strex r3,r4,[r2]
demayer 0:6bf0743ece18 1018 cbz r3,%F3
demayer 0:6bf0743ece18 1019 b %B1
demayer 0:6bf0743ece18 1020 3
demayer 0:6bf0743ece18 1021 pop {r4,pc}
demayer 0:6bf0743ece18 1022 }
demayer 0:6bf0743ece18 1023 #else
demayer 0:6bf0743ece18 1024 __STATIC_INLINE uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) {
demayer 0:6bf0743ece18 1025 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1026 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 1027 #endif
demayer 0:6bf0743ece18 1028 register uint32_t val, res;
demayer 0:6bf0743ece18 1029 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1030 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 1031 #endif
demayer 0:6bf0743ece18 1032 register uint32_t ret;
demayer 0:6bf0743ece18 1033
demayer 0:6bf0743ece18 1034 __ASM volatile (
demayer 0:6bf0743ece18 1035 #ifndef __ICCARM__
demayer 0:6bf0743ece18 1036 ".syntax unified\n\t"
demayer 0:6bf0743ece18 1037 #endif
demayer 0:6bf0743ece18 1038 "1:\n\t"
demayer 0:6bf0743ece18 1039 "ldrex %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1040 "cmp %[max],%[ret]\n\t"
demayer 0:6bf0743ece18 1041 "bhi 2f\n\t"
demayer 0:6bf0743ece18 1042 "clrex\n\t"
demayer 0:6bf0743ece18 1043 "b 3f\n"
demayer 0:6bf0743ece18 1044 "2:\n\t"
demayer 0:6bf0743ece18 1045 "adds %[val],%[ret],#1\n\t"
demayer 0:6bf0743ece18 1046 "strex %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1047 "cbz %[res],3f\n\t"
demayer 0:6bf0743ece18 1048 "b 1b\n"
demayer 0:6bf0743ece18 1049 "3:"
demayer 0:6bf0743ece18 1050 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 1051 [val] "=&l" (val),
demayer 0:6bf0743ece18 1052 [res] "=&l" (res)
demayer 0:6bf0743ece18 1053 : [mem] "l" (mem),
demayer 0:6bf0743ece18 1054 [max] "l" (max)
demayer 0:6bf0743ece18 1055 : "cc", "memory"
demayer 0:6bf0743ece18 1056 );
demayer 0:6bf0743ece18 1057
demayer 0:6bf0743ece18 1058 return ret;
demayer 0:6bf0743ece18 1059 }
demayer 0:6bf0743ece18 1060 #endif
demayer 0:6bf0743ece18 1061
demayer 0:6bf0743ece18 1062 /// Atomic Access Operation: Increment (16-bit) if Less Than
demayer 0:6bf0743ece18 1063 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 1064 /// \param[in] max Maximum value
demayer 0:6bf0743ece18 1065 /// \return Previous value
demayer 0:6bf0743ece18 1066 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 1067 static __asm uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
demayer 0:6bf0743ece18 1068 push {r4,lr}
demayer 0:6bf0743ece18 1069 mov r2,r0
demayer 0:6bf0743ece18 1070 1
demayer 0:6bf0743ece18 1071 ldrexh r0,[r2]
demayer 0:6bf0743ece18 1072 cmp r1,r0
demayer 0:6bf0743ece18 1073 bhi %F2
demayer 0:6bf0743ece18 1074 clrex
demayer 0:6bf0743ece18 1075 pop {r4,pc}
demayer 0:6bf0743ece18 1076 2
demayer 0:6bf0743ece18 1077 adds r4,r0,#1
demayer 0:6bf0743ece18 1078 strexh r3,r4,[r2]
demayer 0:6bf0743ece18 1079 cbz r3,%F3
demayer 0:6bf0743ece18 1080 b %B1
demayer 0:6bf0743ece18 1081 3
demayer 0:6bf0743ece18 1082 pop {r4,pc}
demayer 0:6bf0743ece18 1083 }
demayer 0:6bf0743ece18 1084 #else
demayer 0:6bf0743ece18 1085 __STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {
demayer 0:6bf0743ece18 1086 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1087 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 1088 #endif
demayer 0:6bf0743ece18 1089 register uint32_t val, res;
demayer 0:6bf0743ece18 1090 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1091 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 1092 #endif
demayer 0:6bf0743ece18 1093 register uint16_t ret;
demayer 0:6bf0743ece18 1094
demayer 0:6bf0743ece18 1095 __ASM volatile (
demayer 0:6bf0743ece18 1096 #ifndef __ICCARM__
demayer 0:6bf0743ece18 1097 ".syntax unified\n\t"
demayer 0:6bf0743ece18 1098 #endif
demayer 0:6bf0743ece18 1099 "1:\n\t"
demayer 0:6bf0743ece18 1100 "ldrexh %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1101 "cmp %[max],%[ret]\n\t"
demayer 0:6bf0743ece18 1102 "bhi 2f\n\t"
demayer 0:6bf0743ece18 1103 "clrex\n\t"
demayer 0:6bf0743ece18 1104 "b 3f\n"
demayer 0:6bf0743ece18 1105 "2:\n\t"
demayer 0:6bf0743ece18 1106 "adds %[val],%[ret],#1\n\t"
demayer 0:6bf0743ece18 1107 "strexh %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1108 "cbz %[res],3f\n\t"
demayer 0:6bf0743ece18 1109 "b 1b\n"
demayer 0:6bf0743ece18 1110 "3:"
demayer 0:6bf0743ece18 1111 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 1112 [val] "=&l" (val),
demayer 0:6bf0743ece18 1113 [res] "=&l" (res)
demayer 0:6bf0743ece18 1114 : [mem] "l" (mem),
demayer 0:6bf0743ece18 1115 [max] "l" (max)
demayer 0:6bf0743ece18 1116 : "cc", "memory"
demayer 0:6bf0743ece18 1117 );
demayer 0:6bf0743ece18 1118
demayer 0:6bf0743ece18 1119 return ret;
demayer 0:6bf0743ece18 1120 }
demayer 0:6bf0743ece18 1121 #endif
demayer 0:6bf0743ece18 1122
demayer 0:6bf0743ece18 1123 /// Atomic Access Operation: Increment (16-bit) and clear on Limit
demayer 0:6bf0743ece18 1124 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 1125 /// \param[in] max Maximum value
demayer 0:6bf0743ece18 1126 /// \return Previous value
demayer 0:6bf0743ece18 1127 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 1128 static __asm uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
demayer 0:6bf0743ece18 1129 push {r4,lr}
demayer 0:6bf0743ece18 1130 mov r2,r0
demayer 0:6bf0743ece18 1131 1
demayer 0:6bf0743ece18 1132 ldrexh r0,[r2]
demayer 0:6bf0743ece18 1133 adds r4,r0,#1
demayer 0:6bf0743ece18 1134 cmp r1,r4
demayer 0:6bf0743ece18 1135 bhi %F2
demayer 0:6bf0743ece18 1136 movs r4,#0
demayer 0:6bf0743ece18 1137 2
demayer 0:6bf0743ece18 1138 strexh r3,r4,[r2]
demayer 0:6bf0743ece18 1139 cbz r3,%F3
demayer 0:6bf0743ece18 1140 b %B1
demayer 0:6bf0743ece18 1141 3
demayer 0:6bf0743ece18 1142 pop {r4,pc}
demayer 0:6bf0743ece18 1143 }
demayer 0:6bf0743ece18 1144 #else
demayer 0:6bf0743ece18 1145 __STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {
demayer 0:6bf0743ece18 1146 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1147 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 1148 #endif
demayer 0:6bf0743ece18 1149 register uint32_t val, res;
demayer 0:6bf0743ece18 1150 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1151 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 1152 #endif
demayer 0:6bf0743ece18 1153 register uint16_t ret;
demayer 0:6bf0743ece18 1154
demayer 0:6bf0743ece18 1155 __ASM volatile (
demayer 0:6bf0743ece18 1156 #ifndef __ICCARM__
demayer 0:6bf0743ece18 1157 ".syntax unified\n\t"
demayer 0:6bf0743ece18 1158 #endif
demayer 0:6bf0743ece18 1159 "1:\n\t"
demayer 0:6bf0743ece18 1160 "ldrexh %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1161 "adds %[val],%[ret],#1\n\t"
demayer 0:6bf0743ece18 1162 "cmp %[lim],%[val]\n\t"
demayer 0:6bf0743ece18 1163 "bhi 2f\n\t"
demayer 0:6bf0743ece18 1164 "movs %[val],#0\n"
demayer 0:6bf0743ece18 1165 "2:\n\t"
demayer 0:6bf0743ece18 1166 "strexh %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1167 "cbz %[res],3f\n\t"
demayer 0:6bf0743ece18 1168 "b 1b\n"
demayer 0:6bf0743ece18 1169 "3:"
demayer 0:6bf0743ece18 1170 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 1171 [val] "=&l" (val),
demayer 0:6bf0743ece18 1172 [res] "=&l" (res)
demayer 0:6bf0743ece18 1173 : [mem] "l" (mem),
demayer 0:6bf0743ece18 1174 [lim] "l" (lim)
demayer 0:6bf0743ece18 1175 : "cc", "memory"
demayer 0:6bf0743ece18 1176 );
demayer 0:6bf0743ece18 1177
demayer 0:6bf0743ece18 1178 return ret;
demayer 0:6bf0743ece18 1179 }
demayer 0:6bf0743ece18 1180 #endif
demayer 0:6bf0743ece18 1181
demayer 0:6bf0743ece18 1182 /// Atomic Access Operation: Decrement (32-bit) if Not Zero
demayer 0:6bf0743ece18 1183 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 1184 /// \return Previous value
demayer 0:6bf0743ece18 1185 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 1186 static __asm uint32_t atomic_dec32_nz (uint32_t *mem) {
demayer 0:6bf0743ece18 1187 mov r2,r0
demayer 0:6bf0743ece18 1188 1
demayer 0:6bf0743ece18 1189 ldrex r0,[r2]
demayer 0:6bf0743ece18 1190 cbnz r0,%F2
demayer 0:6bf0743ece18 1191 clrex
demayer 0:6bf0743ece18 1192 bx lr
demayer 0:6bf0743ece18 1193 2
demayer 0:6bf0743ece18 1194 subs r1,r0,#1
demayer 0:6bf0743ece18 1195 strex r3,r1,[r2]
demayer 0:6bf0743ece18 1196 cbz r3,%F3
demayer 0:6bf0743ece18 1197 b %B1
demayer 0:6bf0743ece18 1198 3
demayer 0:6bf0743ece18 1199 bx lr
demayer 0:6bf0743ece18 1200 }
demayer 0:6bf0743ece18 1201 #else
demayer 0:6bf0743ece18 1202 __STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) {
demayer 0:6bf0743ece18 1203 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1204 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 1205 #endif
demayer 0:6bf0743ece18 1206 register uint32_t val, res;
demayer 0:6bf0743ece18 1207 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1208 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 1209 #endif
demayer 0:6bf0743ece18 1210 register uint32_t ret;
demayer 0:6bf0743ece18 1211
demayer 0:6bf0743ece18 1212 __ASM volatile (
demayer 0:6bf0743ece18 1213 #ifndef __ICCARM__
demayer 0:6bf0743ece18 1214 ".syntax unified\n\t"
demayer 0:6bf0743ece18 1215 #endif
demayer 0:6bf0743ece18 1216 "1:\n\t"
demayer 0:6bf0743ece18 1217 "ldrex %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1218 "cbnz %[ret],2f\n\t"
demayer 0:6bf0743ece18 1219 "clrex\n\t"
demayer 0:6bf0743ece18 1220 "b 3f\n"
demayer 0:6bf0743ece18 1221 "2:\n\t"
demayer 0:6bf0743ece18 1222 "subs %[val],%[ret],#1\n\t"
demayer 0:6bf0743ece18 1223 "strex %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1224 "cbz %[res],3f\n\t"
demayer 0:6bf0743ece18 1225 "b 1b\n"
demayer 0:6bf0743ece18 1226 "3:"
demayer 0:6bf0743ece18 1227 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 1228 [val] "=&l" (val),
demayer 0:6bf0743ece18 1229 [res] "=&l" (res)
demayer 0:6bf0743ece18 1230 : [mem] "l" (mem)
demayer 0:6bf0743ece18 1231 : "cc", "memory"
demayer 0:6bf0743ece18 1232 );
demayer 0:6bf0743ece18 1233
demayer 0:6bf0743ece18 1234 return ret;
demayer 0:6bf0743ece18 1235 }
demayer 0:6bf0743ece18 1236 #endif
demayer 0:6bf0743ece18 1237
demayer 0:6bf0743ece18 1238 /// Atomic Access Operation: Decrement (16-bit) if Not Zero
demayer 0:6bf0743ece18 1239 /// \param[in] mem Memory address
demayer 0:6bf0743ece18 1240 /// \return Previous value
demayer 0:6bf0743ece18 1241 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 1242 static __asm uint16_t atomic_dec16_nz (uint16_t *mem) {
demayer 0:6bf0743ece18 1243 mov r2,r0
demayer 0:6bf0743ece18 1244 1
demayer 0:6bf0743ece18 1245 ldrexh r0,[r2]
demayer 0:6bf0743ece18 1246 cbnz r0,%F2
demayer 0:6bf0743ece18 1247 clrex
demayer 0:6bf0743ece18 1248 bx lr
demayer 0:6bf0743ece18 1249 2
demayer 0:6bf0743ece18 1250 subs r1,r0,#1
demayer 0:6bf0743ece18 1251 strexh r3,r1,[r2]
demayer 0:6bf0743ece18 1252 cbz r3,%F3
demayer 0:6bf0743ece18 1253 b %B1
demayer 0:6bf0743ece18 1254 3
demayer 0:6bf0743ece18 1255 bx lr
demayer 0:6bf0743ece18 1256 }
demayer 0:6bf0743ece18 1257 #else
demayer 0:6bf0743ece18 1258 __STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) {
demayer 0:6bf0743ece18 1259 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1260 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 1261 #endif
demayer 0:6bf0743ece18 1262 register uint32_t val, res;
demayer 0:6bf0743ece18 1263 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1264 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 1265 #endif
demayer 0:6bf0743ece18 1266 register uint16_t ret;
demayer 0:6bf0743ece18 1267
demayer 0:6bf0743ece18 1268 __ASM volatile (
demayer 0:6bf0743ece18 1269 #ifndef __ICCARM__
demayer 0:6bf0743ece18 1270 ".syntax unified\n\t"
demayer 0:6bf0743ece18 1271 #endif
demayer 0:6bf0743ece18 1272 "1:\n\t"
demayer 0:6bf0743ece18 1273 "ldrexh %[ret],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1274 "cbnz %[ret],2f\n\t"
demayer 0:6bf0743ece18 1275 "clrex\n\t"
demayer 0:6bf0743ece18 1276 "b 3f\n"
demayer 0:6bf0743ece18 1277 "2:\n\t"
demayer 0:6bf0743ece18 1278 "subs %[val],%[ret],#1\n\t"
demayer 0:6bf0743ece18 1279 "strexh %[res],%[val],[%[mem]]\n\t"
demayer 0:6bf0743ece18 1280 "cbz %[res],3f\n\t"
demayer 0:6bf0743ece18 1281 "b 1b\n"
demayer 0:6bf0743ece18 1282 "3:"
demayer 0:6bf0743ece18 1283 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 1284 [val] "=&l" (val),
demayer 0:6bf0743ece18 1285 [res] "=&l" (res)
demayer 0:6bf0743ece18 1286 : [mem] "l" (mem)
demayer 0:6bf0743ece18 1287 : "cc", "memory"
demayer 0:6bf0743ece18 1288 );
demayer 0:6bf0743ece18 1289
demayer 0:6bf0743ece18 1290 return ret;
demayer 0:6bf0743ece18 1291 }
demayer 0:6bf0743ece18 1292 #endif
demayer 0:6bf0743ece18 1293
demayer 0:6bf0743ece18 1294 /// Atomic Access Operation: Link Get
demayer 0:6bf0743ece18 1295 /// \param[in] root Root address
demayer 0:6bf0743ece18 1296 /// \return Link
demayer 0:6bf0743ece18 1297 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 1298 static __asm void *atomic_link_get (void **root) {
demayer 0:6bf0743ece18 1299 mov r2,r0
demayer 0:6bf0743ece18 1300 1
demayer 0:6bf0743ece18 1301 ldrex r0,[r2]
demayer 0:6bf0743ece18 1302 cbnz r0,%F2
demayer 0:6bf0743ece18 1303 clrex
demayer 0:6bf0743ece18 1304 bx lr
demayer 0:6bf0743ece18 1305 2
demayer 0:6bf0743ece18 1306 ldr r1,[r0]
demayer 0:6bf0743ece18 1307 strex r3,r1,[r2]
demayer 0:6bf0743ece18 1308 cbz r3,%F3
demayer 0:6bf0743ece18 1309 b %B1
demayer 0:6bf0743ece18 1310 3
demayer 0:6bf0743ece18 1311 bx lr
demayer 0:6bf0743ece18 1312 }
demayer 0:6bf0743ece18 1313 #else
demayer 0:6bf0743ece18 1314 __STATIC_INLINE void *atomic_link_get (void **root) {
demayer 0:6bf0743ece18 1315 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1316 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 1317 #endif
demayer 0:6bf0743ece18 1318 register uint32_t val, res;
demayer 0:6bf0743ece18 1319 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1320 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 1321 #endif
demayer 0:6bf0743ece18 1322 register void *ret;
demayer 0:6bf0743ece18 1323
demayer 0:6bf0743ece18 1324 __ASM volatile (
demayer 0:6bf0743ece18 1325 #ifndef __ICCARM__
demayer 0:6bf0743ece18 1326 ".syntax unified\n\t"
demayer 0:6bf0743ece18 1327 #endif
demayer 0:6bf0743ece18 1328 "1:\n\t"
demayer 0:6bf0743ece18 1329 "ldrex %[ret],[%[root]]\n\t"
demayer 0:6bf0743ece18 1330 "cbnz %[ret],2f\n\t"
demayer 0:6bf0743ece18 1331 "clrex\n\t"
demayer 0:6bf0743ece18 1332 "b 3f\n"
demayer 0:6bf0743ece18 1333 "2:\n\t"
demayer 0:6bf0743ece18 1334 "ldr %[val],[%[ret]]\n\t"
demayer 0:6bf0743ece18 1335 "strex %[res],%[val],[%[root]]\n\t"
demayer 0:6bf0743ece18 1336 "cbz %[res],3f\n\t"
demayer 0:6bf0743ece18 1337 "b 1b\n"
demayer 0:6bf0743ece18 1338 "3:"
demayer 0:6bf0743ece18 1339 : [ret] "=&l" (ret),
demayer 0:6bf0743ece18 1340 [val] "=&l" (val),
demayer 0:6bf0743ece18 1341 [res] "=&l" (res)
demayer 0:6bf0743ece18 1342 : [root] "l" (root)
demayer 0:6bf0743ece18 1343 : "cc", "memory"
demayer 0:6bf0743ece18 1344 );
demayer 0:6bf0743ece18 1345
demayer 0:6bf0743ece18 1346 return ret;
demayer 0:6bf0743ece18 1347 }
demayer 0:6bf0743ece18 1348 #endif
demayer 0:6bf0743ece18 1349
demayer 0:6bf0743ece18 1350 /// Atomic Access Operation: Link Put
demayer 0:6bf0743ece18 1351 /// \param[in] root Root address
demayer 0:6bf0743ece18 1352 /// \param[in] lnk Link
demayer 0:6bf0743ece18 1353 #if defined(__CC_ARM)
demayer 0:6bf0743ece18 1354 static __asm void atomic_link_put (void **root, void *link) {
demayer 0:6bf0743ece18 1355 1
demayer 0:6bf0743ece18 1356 ldr r2,[r0]
demayer 0:6bf0743ece18 1357 str r2,[r1]
demayer 0:6bf0743ece18 1358 dmb
demayer 0:6bf0743ece18 1359 ldrex r2,[r0]
demayer 0:6bf0743ece18 1360 ldr r3,[r1]
demayer 0:6bf0743ece18 1361 cmp r3,r2
demayer 0:6bf0743ece18 1362 bne %B1
demayer 0:6bf0743ece18 1363 strex r3,r1,[r0]
demayer 0:6bf0743ece18 1364 cbz r3,%F2
demayer 0:6bf0743ece18 1365 b %B1
demayer 0:6bf0743ece18 1366 2
demayer 0:6bf0743ece18 1367 bx lr
demayer 0:6bf0743ece18 1368 }
demayer 0:6bf0743ece18 1369 #else
demayer 0:6bf0743ece18 1370 __STATIC_INLINE void atomic_link_put (void **root, void *link) {
demayer 0:6bf0743ece18 1371 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1372 #pragma diag_suppress=Pe550
demayer 0:6bf0743ece18 1373 #endif
demayer 0:6bf0743ece18 1374 register uint32_t val1, val2, res;
demayer 0:6bf0743ece18 1375 #ifdef __ICCARM__
demayer 0:6bf0743ece18 1376 #pragma diag_default=Pe550
demayer 0:6bf0743ece18 1377 #endif
demayer 0:6bf0743ece18 1378
demayer 0:6bf0743ece18 1379 __ASM volatile (
demayer 0:6bf0743ece18 1380 #ifndef __ICCARM__
demayer 0:6bf0743ece18 1381 ".syntax unified\n\t"
demayer 0:6bf0743ece18 1382 #endif
demayer 0:6bf0743ece18 1383 "1:\n\t"
demayer 0:6bf0743ece18 1384 "ldr %[val1],[%[root]]\n\t"
demayer 0:6bf0743ece18 1385 "str %[val1],[%[link]]\n\t"
demayer 0:6bf0743ece18 1386 "dmb\n\t"
demayer 0:6bf0743ece18 1387 "ldrex %[val1],[%[root]]\n\t"
demayer 0:6bf0743ece18 1388 "ldr %[val2],[%[link]]\n\t"
demayer 0:6bf0743ece18 1389 "cmp %[val2],%[val1]\n\t"
demayer 0:6bf0743ece18 1390 "bne 1b\n\t"
demayer 0:6bf0743ece18 1391 "strex %[res],%[link],[%[root]]\n\t"
demayer 0:6bf0743ece18 1392 "cbz %[res],2f\n\t"
demayer 0:6bf0743ece18 1393 "b 1b\n"
demayer 0:6bf0743ece18 1394 "2:"
demayer 0:6bf0743ece18 1395 : [val1] "=&l" (val1),
demayer 0:6bf0743ece18 1396 [val2] "=&l" (val2),
demayer 0:6bf0743ece18 1397 [res] "=&l" (res)
demayer 0:6bf0743ece18 1398 : [root] "l" (root),
demayer 0:6bf0743ece18 1399 [link] "l" (link)
demayer 0:6bf0743ece18 1400 : "cc", "memory"
demayer 0:6bf0743ece18 1401 );
demayer 0:6bf0743ece18 1402 }
demayer 0:6bf0743ece18 1403 #endif
demayer 0:6bf0743ece18 1404
demayer 0:6bf0743ece18 1405 #endif // (__EXCLUSIVE_ACCESS == 1U)
demayer 0:6bf0743ece18 1406
demayer 0:6bf0743ece18 1407
demayer 0:6bf0743ece18 1408 #endif // RTX_CORE_CM_H_