Orefatoi / Mbed 2 deprecated afero_node_suntory_171018

pwm period is now 200us instead of the default 20ms veml6040 config is now AF_BIT | TRIG_BIT

Dependencies:   mbed MMA8451Q USBDevice WakeUp vt100

Fork of afero_node_suntory_2017_06_15 by Orefatoi

util/KL25Z_SystemInit.c@23:e4d2316383a1, 2017-10-18 (annotated)

Committer:
Rhyme
Date:
Wed Oct 18 00:31:13 2017 +0000
Revision:
23:e4d2316383a1
Parent:
5:9d5c7ee80f3b 
pwm period is now 200us from default 20ms; veml6040->setCOLORCOnf is now AF_BIT | TRIG_BIT from 0x00;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wataloh 5:9d5c7ee80f3b 1 #if defined (TARGET_KL25Z)
wataloh 5:9d5c7ee80f3b 2 /*
wataloh 5:9d5c7ee80f3b 3 ** ###################################################################
wataloh 5:9d5c7ee80f3b 4 ** Processor: MKL25Z128VLK4
wataloh 5:9d5c7ee80f3b 5 ** Compilers: ARM Compiler
wataloh 5:9d5c7ee80f3b 6 ** Freescale C/C++ for Embedded ARM
wataloh 5:9d5c7ee80f3b 7 ** GNU C Compiler
wataloh 5:9d5c7ee80f3b 8 ** IAR ANSI C/C++ Compiler for ARM
wataloh 5:9d5c7ee80f3b 9 **
wataloh 5:9d5c7ee80f3b 10 ** Reference manual: KL25RM, Rev.1, Jun 2012
wataloh 5:9d5c7ee80f3b 11 ** Version: rev. 1.1, 2012-06-21
wataloh 5:9d5c7ee80f3b 12 **
wataloh 5:9d5c7ee80f3b 13 ** Abstract:
wataloh 5:9d5c7ee80f3b 14 ** Provides a system configuration function and a global variable that
wataloh 5:9d5c7ee80f3b 15 ** contains the system frequency. It configures the device and initializes
wataloh 5:9d5c7ee80f3b 16 ** the oscillator (PLL) that is part of the microcontroller device.
wataloh 5:9d5c7ee80f3b 17 **
wataloh 5:9d5c7ee80f3b 18 ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
wataloh 5:9d5c7ee80f3b 19 **
wataloh 5:9d5c7ee80f3b 20 ** http: www.freescale.com
wataloh 5:9d5c7ee80f3b 21 ** mail: support@freescale.com
wataloh 5:9d5c7ee80f3b 22 **
wataloh 5:9d5c7ee80f3b 23 ** Revisions:
wataloh 5:9d5c7ee80f3b 24 ** - rev. 1.0 (2012-06-13)
wataloh 5:9d5c7ee80f3b 25 ** Initial version.
wataloh 5:9d5c7ee80f3b 26 ** - rev. 1.1 (2012-06-21)
wataloh 5:9d5c7ee80f3b 27 ** Update according to reference manual rev. 1.
wataloh 5:9d5c7ee80f3b 28 **
wataloh 5:9d5c7ee80f3b 29 ** ###################################################################
wataloh 5:9d5c7ee80f3b 30 */
wataloh 5:9d5c7ee80f3b 31
wataloh 5:9d5c7ee80f3b 32 /**
wataloh 5:9d5c7ee80f3b 33 * @file MKL25Z4
wataloh 5:9d5c7ee80f3b 34 * @version 1.1
wataloh 5:9d5c7ee80f3b 35 * @date 2012-06-21
wataloh 5:9d5c7ee80f3b 36 * @brief Device specific configuration file for MKL25Z4 (implementation file)
wataloh 5:9d5c7ee80f3b 37 *
wataloh 5:9d5c7ee80f3b 38 * Provides a system configuration function and a global variable that contains
wataloh 5:9d5c7ee80f3b 39 * the system frequency. It configures the device and initializes the oscillator
wataloh 5:9d5c7ee80f3b 40 * (PLL) that is part of the microcontroller device.
wataloh 5:9d5c7ee80f3b 41 */
wataloh 5:9d5c7ee80f3b 42
wataloh 5:9d5c7ee80f3b 43 #include <stdint.h>
wataloh 5:9d5c7ee80f3b 44 #include "MKL25Z4.h"
wataloh 5:9d5c7ee80f3b 45
wataloh 5:9d5c7ee80f3b 46 //MODIFICATION: We DO want watchdog, uC default after reset is enabled with timeout=1024ms (2^10*LPO=1KHz)
wataloh 5:9d5c7ee80f3b 47 //#define DISABLE_WDOG 1
wataloh 5:9d5c7ee80f3b 48
wataloh 5:9d5c7ee80f3b 49 #define CLOCK_SETUP 1
wataloh 5:9d5c7ee80f3b 50 /* Predefined clock setups
wataloh 5:9d5c7ee80f3b 51 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
wataloh 5:9d5c7ee80f3b 52 Reference clock source for MCG module is the slow internal clock source 32.768kHz
wataloh 5:9d5c7ee80f3b 53 Core clock = 41.94MHz, BusClock = 13.98MHz
wataloh 5:9d5c7ee80f3b 54 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
wataloh 5:9d5c7ee80f3b 55 Reference clock source for MCG module is an external crystal 8MHz
wataloh 5:9d5c7ee80f3b 56 Core clock = 48MHz, BusClock = 24MHz
wataloh 5:9d5c7ee80f3b 57 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
wataloh 5:9d5c7ee80f3b 58 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
wataloh 5:9d5c7ee80f3b 59 Core clock = 8MHz, BusClock = 8MHz
wataloh 5:9d5c7ee80f3b 60 3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
wataloh 5:9d5c7ee80f3b 61 Reference clock source for MCG module is an external crystal 32.768kHz
wataloh 5:9d5c7ee80f3b 62 Core clock = 47.97MHz, BusClock = 23.98MHz
wataloh 5:9d5c7ee80f3b 63 This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
wataloh 5:9d5c7ee80f3b 64 RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
wataloh 5:9d5c7ee80f3b 65 accuracy durring the reset period. RTC will reset on power down.
wataloh 5:9d5c7ee80f3b 66 */
wataloh 5:9d5c7ee80f3b 67
wataloh 5:9d5c7ee80f3b 68 /*----------------------------------------------------------------------------
wataloh 5:9d5c7ee80f3b 69 Define clock source values
wataloh 5:9d5c7ee80f3b 70 *----------------------------------------------------------------------------*/
wataloh 5:9d5c7ee80f3b 71 #if (CLOCK_SETUP == 0)
wataloh 5:9d5c7ee80f3b 72 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 73 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 74 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 75 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
wataloh 5:9d5c7ee80f3b 76 #elif (CLOCK_SETUP == 1)
wataloh 5:9d5c7ee80f3b 77 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 78 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 79 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 80 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
wataloh 5:9d5c7ee80f3b 81 #elif (CLOCK_SETUP == 2)
wataloh 5:9d5c7ee80f3b 82 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 83 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 84 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 85 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
wataloh 5:9d5c7ee80f3b 86 #elif (CLOCK_SETUP == 3)
wataloh 5:9d5c7ee80f3b 87 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 88 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 89 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
wataloh 5:9d5c7ee80f3b 90 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
wataloh 5:9d5c7ee80f3b 91 #endif /* (CLOCK_SETUP == 3) */
wataloh 5:9d5c7ee80f3b 92
wataloh 5:9d5c7ee80f3b 93 /* ----------------------------------------------------------------------------
wataloh 5:9d5c7ee80f3b 94 -- Core clock
wataloh 5:9d5c7ee80f3b 95 ---------------------------------------------------------------------------- */
wataloh 5:9d5c7ee80f3b 96
wataloh 5:9d5c7ee80f3b 97 //MODIFICATION: That vartiable already exists
wataloh 5:9d5c7ee80f3b 98 // uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
wataloh 5:9d5c7ee80f3b 99
wataloh 5:9d5c7ee80f3b 100 /* ----------------------------------------------------------------------------
wataloh 5:9d5c7ee80f3b 101 -- SystemInit()
wataloh 5:9d5c7ee80f3b 102 ---------------------------------------------------------------------------- */
wataloh 5:9d5c7ee80f3b 103
wataloh 5:9d5c7ee80f3b 104 void $Sub$$SystemInit (void) {
wataloh 5:9d5c7ee80f3b 105
wataloh 5:9d5c7ee80f3b 106 //MODIFICATION:
wataloh 5:9d5c7ee80f3b 107 // That variable already exists, we set it here
wataloh 5:9d5c7ee80f3b 108 SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
wataloh 5:9d5c7ee80f3b 109 // We want visual indication of boot time with red LED on
wataloh 5:9d5c7ee80f3b 110 //TODO
wataloh 5:9d5c7ee80f3b 111
wataloh 5:9d5c7ee80f3b 112 #if (DISABLE_WDOG)
wataloh 5:9d5c7ee80f3b 113 /* Disable the WDOG module */
wataloh 5:9d5c7ee80f3b 114 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
wataloh 5:9d5c7ee80f3b 115 SIM->COPC = (uint32_t)0x00u;
wataloh 5:9d5c7ee80f3b 116 #endif /* (DISABLE_WDOG) */
wataloh 5:9d5c7ee80f3b 117 #if (CLOCK_SETUP == 0)
wataloh 5:9d5c7ee80f3b 118 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
wataloh 5:9d5c7ee80f3b 119 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
wataloh 5:9d5c7ee80f3b 120 /* Switch to FEI Mode */
wataloh 5:9d5c7ee80f3b 121 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
wataloh 5:9d5c7ee80f3b 122 MCG->C1 = (uint8_t)0x06U;
wataloh 5:9d5c7ee80f3b 123 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
wataloh 5:9d5c7ee80f3b 124 MCG->C2 = (uint8_t)0x00U;
wataloh 5:9d5c7ee80f3b 125 /* MCG->C4: DMX32=0,DRST_DRS=1 */
wataloh 5:9d5c7ee80f3b 126 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
wataloh 5:9d5c7ee80f3b 127 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
wataloh 5:9d5c7ee80f3b 128 OSC0->CR = (uint8_t)0x80U;
wataloh 5:9d5c7ee80f3b 129 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
wataloh 5:9d5c7ee80f3b 130 MCG->C5 = (uint8_t)0x00U;
wataloh 5:9d5c7ee80f3b 131 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
wataloh 5:9d5c7ee80f3b 132 MCG->C6 = (uint8_t)0x00U;
wataloh 5:9d5c7ee80f3b 133 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
wataloh 5:9d5c7ee80f3b 134 }
wataloh 5:9d5c7ee80f3b 135 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
wataloh 5:9d5c7ee80f3b 136 }
wataloh 5:9d5c7ee80f3b 137 #elif (CLOCK_SETUP == 1)
wataloh 5:9d5c7ee80f3b 138 /* SIM->SCGC5: PORTA=1 */
wataloh 5:9d5c7ee80f3b 139 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
wataloh 5:9d5c7ee80f3b 140 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
wataloh 5:9d5c7ee80f3b 141 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
wataloh 5:9d5c7ee80f3b 142 /* PORTA->PCR18: ISF=0,MUX=0 */
wataloh 5:9d5c7ee80f3b 143 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
wataloh 5:9d5c7ee80f3b 144 /* PORTA->PCR19: ISF=0,MUX=0 */
wataloh 5:9d5c7ee80f3b 145 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
wataloh 5:9d5c7ee80f3b 146 /* Switch to FBE Mode */
wataloh 5:9d5c7ee80f3b 147 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
wataloh 5:9d5c7ee80f3b 148 OSC0->CR = (uint8_t)0x89U;
wataloh 5:9d5c7ee80f3b 149 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
wataloh 5:9d5c7ee80f3b 150 MCG->C2 = (uint8_t)0x24U;
wataloh 5:9d5c7ee80f3b 151 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
wataloh 5:9d5c7ee80f3b 152 MCG->C1 = (uint8_t)0x9AU;
wataloh 5:9d5c7ee80f3b 153 /* MCG->C4: DMX32=0,DRST_DRS=0 */
wataloh 5:9d5c7ee80f3b 154 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
wataloh 5:9d5c7ee80f3b 155 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
wataloh 5:9d5c7ee80f3b 156 MCG->C5 = (uint8_t)0x01U;
wataloh 5:9d5c7ee80f3b 157 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
wataloh 5:9d5c7ee80f3b 158 MCG->C6 = (uint8_t)0x00U;
wataloh 5:9d5c7ee80f3b 159 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
wataloh 5:9d5c7ee80f3b 160 }
wataloh 5:9d5c7ee80f3b 161 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
wataloh 5:9d5c7ee80f3b 162 }
wataloh 5:9d5c7ee80f3b 163 /* Switch to PBE Mode */
wataloh 5:9d5c7ee80f3b 164 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
wataloh 5:9d5c7ee80f3b 165 MCG->C6 = (uint8_t)0x40U;
wataloh 5:9d5c7ee80f3b 166 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
wataloh 5:9d5c7ee80f3b 167 }
wataloh 5:9d5c7ee80f3b 168 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
wataloh 5:9d5c7ee80f3b 169 }
wataloh 5:9d5c7ee80f3b 170 /* Switch to PEE Mode */
wataloh 5:9d5c7ee80f3b 171 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
wataloh 5:9d5c7ee80f3b 172 MCG->C1 = (uint8_t)0x1AU;
wataloh 5:9d5c7ee80f3b 173 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
wataloh 5:9d5c7ee80f3b 174 }
wataloh 5:9d5c7ee80f3b 175 #elif (CLOCK_SETUP == 2)
wataloh 5:9d5c7ee80f3b 176 /* SIM->SCGC5: PORTA=1 */
wataloh 5:9d5c7ee80f3b 177 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
wataloh 5:9d5c7ee80f3b 178 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
wataloh 5:9d5c7ee80f3b 179 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
wataloh 5:9d5c7ee80f3b 180 /* PORTA->PCR18: ISF=0,MUX=0 */
wataloh 5:9d5c7ee80f3b 181 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
wataloh 5:9d5c7ee80f3b 182 /* PORTA->PCR19: ISF=0,MUX=0 */
wataloh 5:9d5c7ee80f3b 183 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
wataloh 5:9d5c7ee80f3b 184 /* Switch to FBE Mode */
wataloh 5:9d5c7ee80f3b 185 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
wataloh 5:9d5c7ee80f3b 186 OSC0->CR = (uint8_t)0x89U;
wataloh 5:9d5c7ee80f3b 187 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
wataloh 5:9d5c7ee80f3b 188 MCG->C2 = (uint8_t)0x24U;
wataloh 5:9d5c7ee80f3b 189 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
wataloh 5:9d5c7ee80f3b 190 MCG->C1 = (uint8_t)0x9AU;
wataloh 5:9d5c7ee80f3b 191 /* MCG->C4: DMX32=0,DRST_DRS=0 */
wataloh 5:9d5c7ee80f3b 192 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
wataloh 5:9d5c7ee80f3b 193 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
wataloh 5:9d5c7ee80f3b 194 MCG->C5 = (uint8_t)0x00U;
wataloh 5:9d5c7ee80f3b 195 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
wataloh 5:9d5c7ee80f3b 196 MCG->C6 = (uint8_t)0x00U;
wataloh 5:9d5c7ee80f3b 197 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
wataloh 5:9d5c7ee80f3b 198 }
wataloh 5:9d5c7ee80f3b 199 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
wataloh 5:9d5c7ee80f3b 200 }
wataloh 5:9d5c7ee80f3b 201 /* Switch to BLPE Mode */
wataloh 5:9d5c7ee80f3b 202 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
wataloh 5:9d5c7ee80f3b 203 MCG->C2 = (uint8_t)0x26U;
wataloh 5:9d5c7ee80f3b 204 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
wataloh 5:9d5c7ee80f3b 205 }
wataloh 5:9d5c7ee80f3b 206 #elif (CLOCK_SETUP == 3)
wataloh 5:9d5c7ee80f3b 207 /* SIM->SCGC5: PORTA=1 */
wataloh 5:9d5c7ee80f3b 208 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
wataloh 5:9d5c7ee80f3b 209 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
wataloh 5:9d5c7ee80f3b 210 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
wataloh 5:9d5c7ee80f3b 211 /* PORTA->PCR[3]: ISF=0,MUX=0 */
wataloh 5:9d5c7ee80f3b 212 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
wataloh 5:9d5c7ee80f3b 213 /* PORTA->PCR[4]: ISF=0,MUX=0 */
wataloh 5:9d5c7ee80f3b 214 PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
wataloh 5:9d5c7ee80f3b 215 /* Switch to FEE Mode */
wataloh 5:9d5c7ee80f3b 216 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
wataloh 5:9d5c7ee80f3b 217 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
wataloh 5:9d5c7ee80f3b 218 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
wataloh 5:9d5c7ee80f3b 219 OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
wataloh 5:9d5c7ee80f3b 220 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
wataloh 5:9d5c7ee80f3b 221 MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
wataloh 5:9d5c7ee80f3b 222 /* MCG->C4: DMX32=1,DRST_DRS=1 */
wataloh 5:9d5c7ee80f3b 223 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
wataloh 5:9d5c7ee80f3b 224 MCG_C4_DRST_DRS(0x02)
wataloh 5:9d5c7ee80f3b 225 )) | (uint8_t)(
wataloh 5:9d5c7ee80f3b 226 MCG_C4_DMX32_MASK |
wataloh 5:9d5c7ee80f3b 227 MCG_C4_DRST_DRS(0x01)
wataloh 5:9d5c7ee80f3b 228 ));
wataloh 5:9d5c7ee80f3b 229 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
wataloh 5:9d5c7ee80f3b 230 }
wataloh 5:9d5c7ee80f3b 231 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
wataloh 5:9d5c7ee80f3b 232 }
wataloh 5:9d5c7ee80f3b 233 #endif /* (CLOCK_SETUP == 3) */
wataloh 5:9d5c7ee80f3b 234 }
wataloh 5:9d5c7ee80f3b 235 #endif // TARGET_KL25Z