pwm period is now 200us instead of the default 20ms veml6040 config is now AF_BIT | TRIG_BIT
Dependencies: mbed MMA8451Q USBDevice WakeUp vt100
Fork of afero_node_suntory_2017_06_15 by
util/MCUResetReason.cpp@10:02e481a80843, 2017-03-29 (annotated)
- Committer:
- wataloh
- Date:
- Wed Mar 29 00:42:12 2017 +0000
- Revision:
- 10:02e481a80843
Reset reason is uploaded to Afero cloud via color JSON string.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
wataloh | 10:02e481a80843 | 1 | #include "MCUResetReason.hpp" |
wataloh | 10:02e481a80843 | 2 | |
wataloh | 10:02e481a80843 | 3 | /** |
wataloh | 10:02e481a80843 | 4 | * System Reset Status Register 0 (RCM_SRS0) 0x4007_F000 |
wataloh | 10:02e481a80843 | 5 | * |
wataloh | 10:02e481a80843 | 6 | * bit[7] : POR Power-On Reset |
wataloh | 10:02e481a80843 | 7 | * bit[6] : PIN External Reset Pin |
wataloh | 10:02e481a80843 | 8 | * bit[5] : WDOG Watchdog |
wataloh | 10:02e481a80843 | 9 | * bit[4] : (Reserved) |
wataloh | 10:02e481a80843 | 10 | * bit[3] : LOL Loss-of-Lock Reset |
wataloh | 10:02e481a80843 | 11 | * bit[2] : LOC Loss-of-Clock Reset |
wataloh | 10:02e481a80843 | 12 | * bit[1] : LVD Low-Voltage Detect Reset |
wataloh | 10:02e481a80843 | 13 | * bit[0] : WAKEUP Low Leakage Wakeup Reset |
wataloh | 10:02e481a80843 | 14 | */ |
wataloh | 10:02e481a80843 | 15 | #define REG_RCM_SRS0 (uint8_t *)0x4007F000 |
wataloh | 10:02e481a80843 | 16 | #define POR_RESET_BIT 0x80 |
wataloh | 10:02e481a80843 | 17 | #define PIN_RESET_BIT 0x40 |
wataloh | 10:02e481a80843 | 18 | #define WDG_RESET_BIT 0x20 |
wataloh | 10:02e481a80843 | 19 | #define LOL_RESET_BIT 0x08 |
wataloh | 10:02e481a80843 | 20 | #define LOC_RESET_BIT 0x04 |
wataloh | 10:02e481a80843 | 21 | #define LVD_RESET_BIT 0x02 |
wataloh | 10:02e481a80843 | 22 | #define WUP_RESET_BIT 0x01 |
wataloh | 10:02e481a80843 | 23 | /** |
wataloh | 10:02e481a80843 | 24 | * System Reset Status Register 1 (RCM_SRS1) 0x4007_F001 |
wataloh | 10:02e481a80843 | 25 | * |
wataloh | 10:02e481a80843 | 26 | * bit[7:6] (Reserved) |
wataloh | 10:02e481a80843 | 27 | * bit[5] : SACKERR Stop Mode Acknowledge Error Reset |
wataloh | 10:02e481a80843 | 28 | * bit[4] : (Reserved) |
wataloh | 10:02e481a80843 | 29 | * bit[3] : MDM_AP MDM-AP System Reset Request |
wataloh | 10:02e481a80843 | 30 | * bit[2] : SW Software Reset |
wataloh | 10:02e481a80843 | 31 | * bit[1] : LOCKUP Core Lockup |
wataloh | 10:02e481a80843 | 32 | * bit[0] : (Reserved) |
wataloh | 10:02e481a80843 | 33 | */ |
wataloh | 10:02e481a80843 | 34 | #define REG_RCM_SRS1 (uint8_t *)0x4007F001 |
wataloh | 10:02e481a80843 | 35 | #define SACK_RESET_BIT 0x20 |
wataloh | 10:02e481a80843 | 36 | #define MDM_RESET_BIT 0x08 |
wataloh | 10:02e481a80843 | 37 | #define SW_RESET_BIT 0x04 |
wataloh | 10:02e481a80843 | 38 | #define LOCKUP_RESET_BIT 0x02 |
wataloh | 10:02e481a80843 | 39 | |
wataloh | 10:02e481a80843 | 40 | /** |
wataloh | 10:02e481a80843 | 41 | * Software Reset |
wataloh | 10:02e481a80843 | 42 | * |
wataloh | 10:02e481a80843 | 43 | * From Cortex-M0 Devices Generic User Guide |
wataloh | 10:02e481a80843 | 44 | * 4.3.4 Application Interrupt and Reset Control Register |
wataloh | 10:02e481a80843 | 45 | * |
wataloh | 10:02e481a80843 | 46 | * Bit[31:16] : VECTCKEY |
wataloh | 10:02e481a80843 | 47 | * Bit[15] : ENDIANESS |
wataloh | 10:02e481a80843 | 48 | * Bit[14:3] : (Reserved) |
wataloh | 10:02e481a80843 | 49 | * Bit[2] : SYSRESETREQ |
wataloh | 10:02e481a80843 | 50 | * Bit[1] : VECTCLRACTIVE (reserved for debug use) |
wataloh | 10:02e481a80843 | 51 | * Bit[0] : (Reserved) |
wataloh | 10:02e481a80843 | 52 | * |
wataloh | 10:02e481a80843 | 53 | * Note: To trigger software reset, both VECTKEY=0x05FA and SYSRESETREQ |
wataloh | 10:02e481a80843 | 54 | * must be written at once, therefore the value will be |
wataloh | 10:02e481a80843 | 55 | * 0x05FA0004 |
wataloh | 10:02e481a80843 | 56 | */ |
wataloh | 10:02e481a80843 | 57 | |
wataloh | 10:02e481a80843 | 58 | MCUResetReason *self = NULL; |
wataloh | 10:02e481a80843 | 59 | |
wataloh | 10:02e481a80843 | 60 | const char *MCUResetReason::str_reset_reason[] = { |
wataloh | 10:02e481a80843 | 61 | "Power On Reset", |
wataloh | 10:02e481a80843 | 62 | "External Pin Reset", |
wataloh | 10:02e481a80843 | 63 | "Watch Dog Reset : Forgot to feed?", |
wataloh | 10:02e481a80843 | 64 | "Loss of Lock Reset", |
wataloh | 10:02e481a80843 | 65 | "Loss of Clock Reset", |
wataloh | 10:02e481a80843 | 66 | "Low-Voltage Detect Reset", |
wataloh | 10:02e481a80843 | 67 | "Low Leakage Wakeup Reset", |
wataloh | 10:02e481a80843 | 68 | "Stop Mode Acknowledge Error Reset", |
wataloh | 10:02e481a80843 | 69 | "MDM-AP System Reset Request", |
wataloh | 10:02e481a80843 | 70 | "Software Reset", |
wataloh | 10:02e481a80843 | 71 | "Core Lockup Reset" |
wataloh | 10:02e481a80843 | 72 | }; |
wataloh | 10:02e481a80843 | 73 | |
wataloh | 10:02e481a80843 | 74 | MCUResetReason::MCUResetReason() |
wataloh | 10:02e481a80843 | 75 | { |
wataloh | 10:02e481a80843 | 76 | SRS[0] = *REG_RCM_SRS0 ; |
wataloh | 10:02e481a80843 | 77 | SRS[1] = *REG_RCM_SRS1 ; |
wataloh | 10:02e481a80843 | 78 | } |
wataloh | 10:02e481a80843 | 79 | |
wataloh | 10:02e481a80843 | 80 | MCUResetReason* MCUResetReason::ref() |
wataloh | 10:02e481a80843 | 81 | { |
wataloh | 10:02e481a80843 | 82 | return self != NULL ? self : self = new MCUResetReason(); |
wataloh | 10:02e481a80843 | 83 | } |
wataloh | 10:02e481a80843 | 84 | |
wataloh | 10:02e481a80843 | 85 | void MCUResetReason::clearFlag() |
wataloh | 10:02e481a80843 | 86 | { |
wataloh | 10:02e481a80843 | 87 | SRS[0] = PIN_RESET_BIT; |
wataloh | 10:02e481a80843 | 88 | SRS[1] = 0; |
wataloh | 10:02e481a80843 | 89 | } |
wataloh | 10:02e481a80843 | 90 | |
wataloh | 10:02e481a80843 | 91 | MCUResetReason::RESET_REASON MCUResetReason::getResetReason(void) |
wataloh | 10:02e481a80843 | 92 | { |
wataloh | 10:02e481a80843 | 93 | RESET_REASON reason; |
wataloh | 10:02e481a80843 | 94 | |
wataloh | 10:02e481a80843 | 95 | if (SRS[0] & POR_RESET_BIT) { |
wataloh | 10:02e481a80843 | 96 | reason = POWER_ON; |
wataloh | 10:02e481a80843 | 97 | } else if (SRS[0] & PIN_RESET_BIT) { |
wataloh | 10:02e481a80843 | 98 | reason = EXTERNAL_PIN; |
wataloh | 10:02e481a80843 | 99 | } else if (SRS[0] & WDG_RESET_BIT) { |
wataloh | 10:02e481a80843 | 100 | reason = WATCHDOG; |
wataloh | 10:02e481a80843 | 101 | } else if (SRS[0] & LOL_RESET_BIT) { |
wataloh | 10:02e481a80843 | 102 | reason = LOSS_OF_LOCK; |
wataloh | 10:02e481a80843 | 103 | } else if (SRS[0] & LOC_RESET_BIT) { |
wataloh | 10:02e481a80843 | 104 | reason = LOSS_OF_CLOCK; |
wataloh | 10:02e481a80843 | 105 | } else if (SRS[0] & LVD_RESET_BIT) { |
wataloh | 10:02e481a80843 | 106 | reason = LOW_VOLTAGE_DETECT; |
wataloh | 10:02e481a80843 | 107 | } else if (SRS[0] & WUP_RESET_BIT) { |
wataloh | 10:02e481a80843 | 108 | reason = LOW_LEAKAGE_WAKEUP; |
wataloh | 10:02e481a80843 | 109 | } else if (SRS[1] & SACK_RESET_BIT) { |
wataloh | 10:02e481a80843 | 110 | reason = STOP_MODE_ACK_ERROR; |
wataloh | 10:02e481a80843 | 111 | } else if (SRS[1] & MDM_RESET_BIT) { |
wataloh | 10:02e481a80843 | 112 | reason = MDM_AP_SYSTEM_RESET_REQUEST; |
wataloh | 10:02e481a80843 | 113 | } else if (SRS[1] & SW_RESET_BIT) { |
wataloh | 10:02e481a80843 | 114 | reason = SOFTWARE; |
wataloh | 10:02e481a80843 | 115 | } else if (SRS[1] & LOCKUP_RESET_BIT) { |
wataloh | 10:02e481a80843 | 116 | reason = CORE_LOCKUP; |
wataloh | 10:02e481a80843 | 117 | } |
wataloh | 10:02e481a80843 | 118 | return reason; |
wataloh | 10:02e481a80843 | 119 | } |
wataloh | 10:02e481a80843 | 120 | |
wataloh | 10:02e481a80843 | 121 | const char* MCUResetReason::getResetReasonStr() |
wataloh | 10:02e481a80843 | 122 | { |
wataloh | 10:02e481a80843 | 123 | return str_reset_reason[getResetReason()]; |
wataloh | 10:02e481a80843 | 124 | } |
wataloh | 10:02e481a80843 | 125 |