NXP / Mbed 2 deprecated mcr20_wireless_uart

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Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

RF_Drivers_Freescale/MCR20Overwrites.h@8:e4c9f2b7a9d2, 2015-03-05 (annotated)

Committer:
sam_grove
Date:
Thu Mar 05 20:40:54 2015 +0000
Revision:
8:e4c9f2b7a9d2
Parent:
RF_Drivers_FSL/MCR20Overwrites.h@5:69f1634cd40b 
rename directories;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 5:69f1634cd40b 1 /*!
FSL\B36402 5:69f1634cd40b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
FSL\B36402 5:69f1634cd40b 3 * All rights reserved.
FSL\B36402 5:69f1634cd40b 4 *
FSL\B36402 5:69f1634cd40b 5 * \file MCR20Overwrites.h
FSL\B36402 5:69f1634cd40b 6 * Description: Overwrites header file for MCR20 Register values
FSL\B36402 5:69f1634cd40b 7 *
FSL\B36402 5:69f1634cd40b 8 * Redistribution and use in source and binary forms, with or without modification,
FSL\B36402 5:69f1634cd40b 9 * are permitted provided that the following conditions are met:
FSL\B36402 5:69f1634cd40b 10 *
FSL\B36402 5:69f1634cd40b 11 * o Redistributions of source code must retain the above copyright notice, this list
FSL\B36402 5:69f1634cd40b 12 * of conditions and the following disclaimer.
FSL\B36402 5:69f1634cd40b 13 *
FSL\B36402 5:69f1634cd40b 14 * o Redistributions in binary form must reproduce the above copyright notice, this
FSL\B36402 5:69f1634cd40b 15 * list of conditions and the following disclaimer in the documentation and/or
FSL\B36402 5:69f1634cd40b 16 * other materials provided with the distribution.
FSL\B36402 5:69f1634cd40b 17 *
FSL\B36402 5:69f1634cd40b 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
FSL\B36402 5:69f1634cd40b 19 * contributors may be used to endorse or promote products derived from this
FSL\B36402 5:69f1634cd40b 20 * software without specific prior written permission.
FSL\B36402 5:69f1634cd40b 21 *
FSL\B36402 5:69f1634cd40b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
FSL\B36402 5:69f1634cd40b 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
FSL\B36402 5:69f1634cd40b 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
FSL\B36402 5:69f1634cd40b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
FSL\B36402 5:69f1634cd40b 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
FSL\B36402 5:69f1634cd40b 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
FSL\B36402 5:69f1634cd40b 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
FSL\B36402 5:69f1634cd40b 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
FSL\B36402 5:69f1634cd40b 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
FSL\B36402 5:69f1634cd40b 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
FSL\B36402 5:69f1634cd40b 32 */
FSL\B36402 5:69f1634cd40b 33
FSL\B36402 5:69f1634cd40b 34 #ifndef OVERWRITES_H_
FSL\B36402 5:69f1634cd40b 35 #define OVERWRITES_H_
FSL\B36402 5:69f1634cd40b 36
FSL\B36402 5:69f1634cd40b 37 typedef struct overwrites_tag {
FSL\B36402 5:69f1634cd40b 38 char address;
FSL\B36402 5:69f1634cd40b 39 char data;
FSL\B36402 5:69f1634cd40b 40 }overwrites_t;
FSL\B36402 5:69f1634cd40b 41
FSL\B36402 5:69f1634cd40b 42
FSL\B36402 5:69f1634cd40b 43 /*****************************************************************************************************************/
FSL\B36402 5:69f1634cd40b 44 // This file is created exclusively for use with the transceiver 2.0 silicon
FSL\B36402 5:69f1634cd40b 45 // and is provided for the world to use. It contains a list of all
FSL\B36402 5:69f1634cd40b 46 // known overwrite values. Overwrite values are non-default register
FSL\B36402 5:69f1634cd40b 47 // values that configure the transceiver device to a more optimally performing
FSL\B36402 5:69f1634cd40b 48 // posture. It is expected that low level software (i.e. PHY) will
FSL\B36402 5:69f1634cd40b 49 // consume this file as a #include, and transfer the contents to the
FSL\B36402 5:69f1634cd40b 50 // the indicated addresses in the transceiver's memory space. This file has
FSL\B36402 5:69f1634cd40b 51 // at least one required entry, that being its own version current version
FSL\B36402 5:69f1634cd40b 52 // number, to be stored at transceiver's location 0x3B the
FSL\B36402 5:69f1634cd40b 53 // OVERWRITES_VERSION_NUMBER register. The RAM register is provided in
FSL\B36402 5:69f1634cd40b 54 // the transceiver address space to assist in future debug efforts. The
FSL\B36402 5:69f1634cd40b 55 // analyst may read this location (once device has been booted with
FSL\B36402 5:69f1634cd40b 56 // mysterious software) and have a good indication of what register
FSL\B36402 5:69f1634cd40b 57 // overwrites were performed (with all versions of the overwrites.h file
FSL\B36402 5:69f1634cd40b 58 // being archived forever at the Compass location shown above.
FSL\B36402 5:69f1634cd40b 59 //
FSL\B36402 5:69f1634cd40b 60 // The transceiver has an indirect register (IAR) space. Write access to this space
FSL\B36402 5:69f1634cd40b 61 // requires 3 or more writes:
FSL\B36402 5:69f1634cd40b 62 // 1st) the first write is an index value to the indirect (write Bit7=0, register access Bit 6=0) + 0x3E
FSL\B36402 5:69f1634cd40b 63 // 2nd) IAR Register #0x00 - 0xFF.
FSL\B36402 5:69f1634cd40b 64 // 3rd) The data to write
FSL\B36402 5:69f1634cd40b 65 // nth) Burst mode additional data if required.
FSL\B36402 5:69f1634cd40b 66 //
FSL\B36402 5:69f1634cd40b 67 // Write access to direct space requires only a single address, data pair.
FSL\B36402 5:69f1634cd40b 68
FSL\B36402 5:69f1634cd40b 69 overwrites_t const overwrites_direct[] ={
FSL\B36402 5:69f1634cd40b 70 {0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak)
FSL\B36402 5:69f1634cd40b 71 {0x23, 0x17} //PA_PWR new default Power Step is "23"
FSL\B36402 5:69f1634cd40b 72 };
FSL\B36402 5:69f1634cd40b 73
FSL\B36402 5:69f1634cd40b 74 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 75 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 76 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 77 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 78 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
FSL\B36402 5:69f1634cd40b 79 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 80 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 81 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 82 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 83 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 84 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 85 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 86 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 87 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 88 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 89 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 90 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
FSL\B36402 5:69f1634cd40b 91 {0x52, 0x55}, //AGC_THR1 RSSI tune up
FSL\B36402 5:69f1634cd40b 92 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
FSL\B36402 5:69f1634cd40b 93 {0x66, 0x5F}, //ATT_RSSI1 tune up
FSL\B36402 5:69f1634cd40b 94 {0x67, 0x8F}, //ATT_RSSI2 tune up
FSL\B36402 5:69f1634cd40b 95 {0x68, 0x61}, //RSSI_OFFSET
FSL\B36402 5:69f1634cd40b 96 {0x78, 0x03}, //CHF_PMAGAIN
FSL\B36402 5:69f1634cd40b 97 {0x22, 0x50}, //CCA1_THRESH
FSL\B36402 5:69f1634cd40b 98 {0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity
FSL\B36402 5:69f1634cd40b 99 {0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak)
FSL\B36402 5:69f1634cd40b 100 };
FSL\B36402 5:69f1634cd40b 101
FSL\B36402 5:69f1634cd40b 102
FSL\B36402 5:69f1634cd40b 103 /* begin of deprecated versions
FSL\B36402 5:69f1634cd40b 104
FSL\B36402 5:69f1634cd40b 105 ==VERSION 1==
FSL\B36402 5:69f1634cd40b 106 (version 1 is empty)
FSL\B36402 5:69f1634cd40b 107
FSL\B36402 5:69f1634cd40b 108 ==VERSION 2==
FSL\B36402 5:69f1634cd40b 109 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 110 {0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 111 };
FSL\B36402 5:69f1634cd40b 112
FSL\B36402 5:69f1634cd40b 113 ==VERSION 3==
FSL\B36402 5:69f1634cd40b 114 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 115 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 116 {0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 117 {0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 118 };
FSL\B36402 5:69f1634cd40b 119
FSL\B36402 5:69f1634cd40b 120 ==VERSION 4==
FSL\B36402 5:69f1634cd40b 121 overwrites_t const overwrites_direct[] ={
FSL\B36402 5:69f1634cd40b 122 {0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default
FSL\B36402 5:69f1634cd40b 123 };
FSL\B36402 5:69f1634cd40b 124
FSL\B36402 5:69f1634cd40b 125 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 126 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 127 {0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 128 {0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 129 {0x8A, 0x71} //PA_TUNING: override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
FSL\B36402 5:69f1634cd40b 130 };
FSL\B36402 5:69f1634cd40b 131
FSL\B36402 5:69f1634cd40b 132 ==VERSION 5==
FSL\B36402 5:69f1634cd40b 133 overwrites_t const overwrites_direct[] ={
FSL\B36402 5:69f1634cd40b 134 {0x3B, 0x05} //version 05: updates Channel Filter Register set (21 Dec 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 135 };
FSL\B36402 5:69f1634cd40b 136
FSL\B36402 5:69f1634cd40b 137 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 138 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 139 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 140 {0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 141 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
FSL\B36402 5:69f1634cd40b 142 {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 143 {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 144 {0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 145 {0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 146 {0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 147 {0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 148 {0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 149 {0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 150 {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 151 {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 152 {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 153 };
FSL\B36402 5:69f1634cd40b 154
FSL\B36402 5:69f1634cd40b 155 ==VERSION 6==
FSL\B36402 5:69f1634cd40b 156 overwrites_t const overwrites_direct[] ={
FSL\B36402 5:69f1634cd40b 157 {0x3B, 0x06} //version 06: disable PA calibration
FSL\B36402 5:69f1634cd40b 158 };
FSL\B36402 5:69f1634cd40b 159
FSL\B36402 5:69f1634cd40b 160 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 161 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 162 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 163 {0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 164 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
FSL\B36402 5:69f1634cd40b 165 {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 166 {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 167 {0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 168 {0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 169 {0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 170 {0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 171 {0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 172 {0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 173 {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 174 {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 175 {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 176 {0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration
FSL\B36402 5:69f1634cd40b 177 };
FSL\B36402 5:69f1634cd40b 178
FSL\B36402 5:69f1634cd40b 179 ==VERSION 7==
FSL\B36402 5:69f1634cd40b 180 overwrites_t const overwrites_direct[] ={
FSL\B36402 5:69f1634cd40b 181 {0x3B, 0x07} //version 07: updated registers for ED/RSSI
FSL\B36402 5:69f1634cd40b 182 };
FSL\B36402 5:69f1634cd40b 183
FSL\B36402 5:69f1634cd40b 184 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 185 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 186 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 187 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 188 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
FSL\B36402 5:69f1634cd40b 189 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 190 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 191 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 192 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 193 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 194 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 195 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 196 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 197 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 198 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 199 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 200 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
FSL\B36402 5:69f1634cd40b 201 {0x52, 0x73}, //AGC_THR1 RSSI tune up
FSL\B36402 5:69f1634cd40b 202 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
FSL\B36402 5:69f1634cd40b 203 {0x66, 0x5F}, //ATT_RSSI1 tune up
FSL\B36402 5:69f1634cd40b 204 {0x67, 0x8F}, //ATT_RSSI2 tune up
FSL\B36402 5:69f1634cd40b 205 {0x68, 0x60}, //RSSI_OFFSET
FSL\B36402 5:69f1634cd40b 206 {0x69, 0x65} //RSSI_SLOPE
FSL\B36402 5:69f1634cd40b 207 };
FSL\B36402 5:69f1634cd40b 208
FSL\B36402 5:69f1634cd40b 209
FSL\B36402 5:69f1634cd40b 210 ==VERSION 8==
FSL\B36402 5:69f1634cd40b 211 overwrites_t const overwrites_direct[] ={
FSL\B36402 5:69f1634cd40b 212 {0x3B, 0x08} //version 08: updated registers for ED/RSSI
FSL\B36402 5:69f1634cd40b 213 };
FSL\B36402 5:69f1634cd40b 214
FSL\B36402 5:69f1634cd40b 215 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 216 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 217 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 218 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 219 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
FSL\B36402 5:69f1634cd40b 220 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 221 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 222 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 223 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 224 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 225 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 226 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 227 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 228 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 229 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 230 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 231 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
FSL\B36402 5:69f1634cd40b 232 {0x52, 0x73}, //AGC_THR1 RSSI tune up
FSL\B36402 5:69f1634cd40b 233 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
FSL\B36402 5:69f1634cd40b 234 {0x66, 0x5F}, //ATT_RSSI1 tune up
FSL\B36402 5:69f1634cd40b 235 {0x67, 0x8F}, //ATT_RSSI2 tune up
FSL\B36402 5:69f1634cd40b 236 {0x69, 0x65} //RSSI_SLOPE
FSL\B36402 5:69f1634cd40b 237 {0x68, 0x61}, //RSSI_OFFSET
FSL\B36402 5:69f1634cd40b 238 {0x78, 0x03} //CHF_PMAGAIN
FSL\B36402 5:69f1634cd40b 239 };
FSL\B36402 5:69f1634cd40b 240
FSL\B36402 5:69f1634cd40b 241
FSL\B36402 5:69f1634cd40b 242 ==VERSION 9==
FSL\B36402 5:69f1634cd40b 243 overwrites_t const overwrites_direct[] ={
FSL\B36402 5:69f1634cd40b 244 {0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep
FSL\B36402 5:69f1634cd40b 245 {0x23, 0x17} //PA_PWR new default value
FSL\B36402 5:69f1634cd40b 246 };
FSL\B36402 5:69f1634cd40b 247
FSL\B36402 5:69f1634cd40b 248 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 249 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 250 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 251 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 252 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
FSL\B36402 5:69f1634cd40b 253 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 254 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 255 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 256 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 257 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 258 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 259 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 260 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 261 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 262 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 263 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 264 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
FSL\B36402 5:69f1634cd40b 265 {0x52, 0x55}, //AGC_THR1 RSSI tune up
FSL\B36402 5:69f1634cd40b 266 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
FSL\B36402 5:69f1634cd40b 267 {0x66, 0x5F}, //ATT_RSSI1 tune up
FSL\B36402 5:69f1634cd40b 268 {0x67, 0x8F}, //ATT_RSSI2 tune up
FSL\B36402 5:69f1634cd40b 269 {0x68, 0x61}, //RSSI_OFFSET
FSL\B36402 5:69f1634cd40b 270 {0x78, 0x03} //CHF_PMAGAIN
FSL\B36402 5:69f1634cd40b 271 };
FSL\B36402 5:69f1634cd40b 272
FSL\B36402 5:69f1634cd40b 273 ==VERSION A==
FSL\B36402 5:69f1634cd40b 274 overwrites_t const overwrites_direct[] ={
FSL\B36402 5:69f1634cd40b 275 {0x3B, 0x0A} //version 0A: updated registers for CCA
FSL\B36402 5:69f1634cd40b 276 {0x23, 0x17} //PA_PWR new default Power Step is "23"
FSL\B36402 5:69f1634cd40b 277 };
FSL\B36402 5:69f1634cd40b 278
FSL\B36402 5:69f1634cd40b 279 overwrites_t const overwrites_indirect[] ={
FSL\B36402 5:69f1634cd40b 280 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
FSL\B36402 5:69f1634cd40b 281 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
FSL\B36402 5:69f1634cd40b 282 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
FSL\B36402 5:69f1634cd40b 283 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
FSL\B36402 5:69f1634cd40b 284 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 285 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 286 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 287 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 288 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 289 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 290 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 291 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 292 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 293 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 294 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
FSL\B36402 5:69f1634cd40b 295 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
FSL\B36402 5:69f1634cd40b 296 {0x52, 0x55}, //AGC_THR1 RSSI tune up
FSL\B36402 5:69f1634cd40b 297 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
FSL\B36402 5:69f1634cd40b 298 {0x66, 0x5F}, //ATT_RSSI1 tune up
FSL\B36402 5:69f1634cd40b 299 {0x67, 0x8F}, //ATT_RSSI2 tune up
FSL\B36402 5:69f1634cd40b 300 {0x68, 0x61}, //RSSI_OFFSET
FSL\B36402 5:69f1634cd40b 301 {0x78, 0x03} //CHF_PMAGAIN
FSL\B36402 5:69f1634cd40b 302 {0x22, 0x50} //CCA1_THRESH
FSL\B36402 5:69f1634cd40b 303 };
FSL\B36402 5:69f1634cd40b 304
FSL\B36402 5:69f1634cd40b 305 end of deprecated versions */
FSL\B36402 5:69f1634cd40b 306
FSL\B36402 5:69f1634cd40b 307
FSL\B36402 5:69f1634cd40b 308 #endif //OVERWRITES_H_
FSL\B36402 5:69f1634cd40b 309