NXP / Mbed 2 deprecated mcr20_wireless_uart

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

Committer:
sam_grove
Date:
Thu Mar 05 20:40:54 2015 +0000
Revision:
8:e4c9f2b7a9d2
Parent:
RF_Drivers_FSL/MCR20Drv.c@5:69f1634cd40b
rename directories;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 5:69f1634cd40b 1 /*!
FSL\B36402 5:69f1634cd40b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
FSL\B36402 5:69f1634cd40b 3 * All rights reserved.
FSL\B36402 5:69f1634cd40b 4 *
FSL\B36402 5:69f1634cd40b 5 * \file MCR20Drv.c
FSL\B36402 5:69f1634cd40b 6 *
FSL\B36402 5:69f1634cd40b 7 * Redistribution and use in source and binary forms, with or without modification,
FSL\B36402 5:69f1634cd40b 8 * are permitted provided that the following conditions are met:
FSL\B36402 5:69f1634cd40b 9 *
FSL\B36402 5:69f1634cd40b 10 * o Redistributions of source code must retain the above copyright notice, this list
FSL\B36402 5:69f1634cd40b 11 * of conditions and the following disclaimer.
FSL\B36402 5:69f1634cd40b 12 *
FSL\B36402 5:69f1634cd40b 13 * o Redistributions in binary form must reproduce the above copyright notice, this
FSL\B36402 5:69f1634cd40b 14 * list of conditions and the following disclaimer in the documentation and/or
FSL\B36402 5:69f1634cd40b 15 * other materials provided with the distribution.
FSL\B36402 5:69f1634cd40b 16 *
FSL\B36402 5:69f1634cd40b 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
FSL\B36402 5:69f1634cd40b 18 * contributors may be used to endorse or promote products derived from this
FSL\B36402 5:69f1634cd40b 19 * software without specific prior written permission.
FSL\B36402 5:69f1634cd40b 20 *
FSL\B36402 5:69f1634cd40b 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
FSL\B36402 5:69f1634cd40b 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
FSL\B36402 5:69f1634cd40b 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
FSL\B36402 5:69f1634cd40b 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
FSL\B36402 5:69f1634cd40b 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
FSL\B36402 5:69f1634cd40b 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
FSL\B36402 5:69f1634cd40b 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
FSL\B36402 5:69f1634cd40b 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
FSL\B36402 5:69f1634cd40b 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
FSL\B36402 5:69f1634cd40b 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
FSL\B36402 5:69f1634cd40b 31 */
FSL\B36402 5:69f1634cd40b 32
FSL\B36402 5:69f1634cd40b 33
FSL\B36402 5:69f1634cd40b 34 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 35 * INCLUDED HEADERS *
FSL\B36402 5:69f1634cd40b 36 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 37 * Add to this section all the headers that this module needs to include. *
FSL\B36402 5:69f1634cd40b 38 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 39 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 40
FSL\B36402 5:69f1634cd40b 41 #include "MCR20Drv.h"
FSL\B36402 5:69f1634cd40b 42 #include "MCR20Reg.h"
FSL\B36402 5:69f1634cd40b 43
FSL\B36402 5:69f1634cd40b 44 //#include "EmbeddedTypes.h"
FSL\B36402 5:69f1634cd40b 45
FSL\B36402 5:69f1634cd40b 46 #include <stdint.h>
FSL\B36402 5:69f1634cd40b 47 #include <string.h>
FSL\B36402 5:69f1634cd40b 48
FSL\B36402 5:69f1634cd40b 49 #include "low_level_RF.h"
FSL\B36402 5:69f1634cd40b 50 //#include "arm_hal_interrupt.h"
FSL\B36402 5:69f1634cd40b 51 //#include "arm_hal_phy.h"
FSL\B36402 5:69f1634cd40b 52 //#include "driverRFPhy.h"
FSL\B36402 5:69f1634cd40b 53 //#include "driverAtmelRFInterface.h"
FSL\B36402 5:69f1634cd40b 54 //#include "low_level_RF.h"
FSL\B36402 5:69f1634cd40b 55
FSL\B36402 5:69f1634cd40b 56 //#include "SPI.h"
FSL\B36402 5:69f1634cd40b 57 //#include "fsl_gpio_driver.h"
FSL\B36402 5:69f1634cd40b 58 //#include "fsl_os_abstraction.h"
FSL\B36402 5:69f1634cd40b 59
FSL\B36402 5:69f1634cd40b 60
FSL\B36402 5:69f1634cd40b 61 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 62 * PRIVATE VARIABLES *
FSL\B36402 5:69f1634cd40b 63 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 64 * Add to this section all the variables and constants that have local *
FSL\B36402 5:69f1634cd40b 65 * (file) scope. *
FSL\B36402 5:69f1634cd40b 66 * Each of this declarations shall be preceded by the 'static' keyword. *
FSL\B36402 5:69f1634cd40b 67 * These variables / constants cannot be accessed outside this module. *
FSL\B36402 5:69f1634cd40b 68 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 69 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 70
FSL\B36402 5:69f1634cd40b 71 uint8_t gXcvrSpiInstance_c = 0;
FSL\B36402 5:69f1634cd40b 72
FSL\B36402 5:69f1634cd40b 73 static uint32_t mPhyIrqDisableCnt = 1;
FSL\B36402 5:69f1634cd40b 74
FSL\B36402 5:69f1634cd40b 75 void spi_master_init(uint32_t instance)
FSL\B36402 5:69f1634cd40b 76 {
FSL\B36402 5:69f1634cd40b 77 }
FSL\B36402 5:69f1634cd40b 78
FSL\B36402 5:69f1634cd40b 79 void spi_master_configure_speed(uint32_t instance, uint32_t freq)
FSL\B36402 5:69f1634cd40b 80 {
FSL\B36402 5:69f1634cd40b 81 spi.frequency(freq);
FSL\B36402 5:69f1634cd40b 82 }
FSL\B36402 5:69f1634cd40b 83
FSL\B36402 5:69f1634cd40b 84 void gXcvrAssertCS_d(void) {
FSL\B36402 5:69f1634cd40b 85 RF_CS_Set(0);
FSL\B36402 5:69f1634cd40b 86 }
FSL\B36402 5:69f1634cd40b 87
FSL\B36402 5:69f1634cd40b 88 void gXcvrDeassertCS_d(void) {
FSL\B36402 5:69f1634cd40b 89 RF_CS_Set(1);
FSL\B36402 5:69f1634cd40b 90 }
FSL\B36402 5:69f1634cd40b 91
FSL\B36402 5:69f1634cd40b 92 #if 0
FSL\B36402 5:69f1634cd40b 93 /* GPIO configuration */
FSL\B36402 5:69f1634cd40b 94 const gpio_output_pin_user_config_t mXcvrSpiCsCfg = {
FSL\B36402 5:69f1634cd40b 95 .pinName = kGpioXcvrSpiCsPin,
FSL\B36402 5:69f1634cd40b 96 .config.outputLogic = 1,
FSL\B36402 5:69f1634cd40b 97 .config.slewRate = kPortFastSlewRate,
FSL\B36402 5:69f1634cd40b 98 #if FSL_FEATURE_PORT_HAS_OPEN_DRAIN
FSL\B36402 5:69f1634cd40b 99 .config.isOpenDrainEnabled = false,
FSL\B36402 5:69f1634cd40b 100 #endif
FSL\B36402 5:69f1634cd40b 101 .config.driveStrength = kPortLowDriveStrength,
FSL\B36402 5:69f1634cd40b 102 };
FSL\B36402 5:69f1634cd40b 103
FSL\B36402 5:69f1634cd40b 104 const gpio_input_pin_user_config_t mXcvrIrqPinCfg = {
FSL\B36402 5:69f1634cd40b 105 .pinName = kGpioXcvrIrqPin,
FSL\B36402 5:69f1634cd40b 106 .config.isPullEnable = false,
FSL\B36402 5:69f1634cd40b 107 .config.pullSelect = kPortPullDown,
FSL\B36402 5:69f1634cd40b 108 .config.isPassiveFilterEnabled = false,
FSL\B36402 5:69f1634cd40b 109 .config.interrupt = kPortIntDisabled
FSL\B36402 5:69f1634cd40b 110 };
FSL\B36402 5:69f1634cd40b 111 #endif
FSL\B36402 5:69f1634cd40b 112
FSL\B36402 5:69f1634cd40b 113 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 114 * PUBLIC VARIABLES *
FSL\B36402 5:69f1634cd40b 115 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 116 * Add to this section all the variables and constants that have global *
FSL\B36402 5:69f1634cd40b 117 * (project) scope. *
FSL\B36402 5:69f1634cd40b 118 * These variables / constants can be accessed outside this module. *
FSL\B36402 5:69f1634cd40b 119 * These variables / constants shall be preceded by the 'extern' keyword in *
FSL\B36402 5:69f1634cd40b 120 * the interface header. *
FSL\B36402 5:69f1634cd40b 121 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 122 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 123
FSL\B36402 5:69f1634cd40b 124 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 125 * PRIVATE FUNCTIONS PROTOTYPES *
FSL\B36402 5:69f1634cd40b 126 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 127 * Add to this section all the functions prototypes that have local (file) *
FSL\B36402 5:69f1634cd40b 128 * scope. *
FSL\B36402 5:69f1634cd40b 129 * These functions cannot be accessed outside this module. *
FSL\B36402 5:69f1634cd40b 130 * These declarations shall be preceded by the 'static' keyword. *
FSL\B36402 5:69f1634cd40b 131 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 132 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 133
FSL\B36402 5:69f1634cd40b 134 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 135 * PRIVATE FUNCTIONS *
FSL\B36402 5:69f1634cd40b 136 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 137 * Add to this section all the functions that have local (file) scope. *
FSL\B36402 5:69f1634cd40b 138 * These functions cannot be accessed outside this module. *
FSL\B36402 5:69f1634cd40b 139 * These definitions shall be preceded by the 'static' keyword. *
FSL\B36402 5:69f1634cd40b 140 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 141 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 142
FSL\B36402 5:69f1634cd40b 143
FSL\B36402 5:69f1634cd40b 144 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 145 * PUBLIC FUNCTIONS *
FSL\B36402 5:69f1634cd40b 146 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 147 * Add to this section all the functions that have global (project) scope. *
FSL\B36402 5:69f1634cd40b 148 * These functions can be accessed outside this module. *
FSL\B36402 5:69f1634cd40b 149 * These functions shall have their declarations (prototypes) within the *
FSL\B36402 5:69f1634cd40b 150 * interface header file and shall be preceded by the 'extern' keyword. *
FSL\B36402 5:69f1634cd40b 151 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 152 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 153
FSL\B36402 5:69f1634cd40b 154 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 155 * Name: MCR20Drv_Init
FSL\B36402 5:69f1634cd40b 156 * Description: -
FSL\B36402 5:69f1634cd40b 157 * Parameters: -
FSL\B36402 5:69f1634cd40b 158 * Return: -
FSL\B36402 5:69f1634cd40b 159 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 160 void MCR20Drv_Init
FSL\B36402 5:69f1634cd40b 161 (
FSL\B36402 5:69f1634cd40b 162 void
FSL\B36402 5:69f1634cd40b 163 )
FSL\B36402 5:69f1634cd40b 164 {
FSL\B36402 5:69f1634cd40b 165 #if 0
FSL\B36402 5:69f1634cd40b 166 spi_master_init(gXcvrSpiInstance_c);
FSL\B36402 5:69f1634cd40b 167 spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
FSL\B36402 5:69f1634cd40b 168
FSL\B36402 5:69f1634cd40b 169 /* Override SPI CS pin function. Set pin as GPIO */
FSL\B36402 5:69f1634cd40b 170 PORT_HAL_SetMuxMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrSpiCsPin)],
FSL\B36402 5:69f1634cd40b 171 GPIO_EXTRACT_PIN(kGpioXcvrSpiCsPin),
FSL\B36402 5:69f1634cd40b 172 kPortMuxAsGpio);
FSL\B36402 5:69f1634cd40b 173 GPIO_DRV_OutputPinInit(&mXcvrSpiCsCfg);
FSL\B36402 5:69f1634cd40b 174 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 175 #endif
FSL\B36402 5:69f1634cd40b 176
FSL\B36402 5:69f1634cd40b 177 }
FSL\B36402 5:69f1634cd40b 178
FSL\B36402 5:69f1634cd40b 179 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 180 * Name: MCR20Drv_DirectAccessSPIWrite
FSL\B36402 5:69f1634cd40b 181 * Description: -
FSL\B36402 5:69f1634cd40b 182 * Parameters: -
FSL\B36402 5:69f1634cd40b 183 * Return: -
FSL\B36402 5:69f1634cd40b 184 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 185 void MCR20Drv_DirectAccessSPIWrite
FSL\B36402 5:69f1634cd40b 186 (
FSL\B36402 5:69f1634cd40b 187 uint8_t address,
FSL\B36402 5:69f1634cd40b 188 uint8_t value
FSL\B36402 5:69f1634cd40b 189 )
FSL\B36402 5:69f1634cd40b 190 {
FSL\B36402 5:69f1634cd40b 191 uint16_t txData;
FSL\B36402 5:69f1634cd40b 192
FSL\B36402 5:69f1634cd40b 193 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 194
FSL\B36402 5:69f1634cd40b 195 spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
FSL\B36402 5:69f1634cd40b 196
FSL\B36402 5:69f1634cd40b 197 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 198
FSL\B36402 5:69f1634cd40b 199 txData = (address & TransceiverSPI_DirectRegisterAddressMask);
FSL\B36402 5:69f1634cd40b 200 txData |= value << 8;
FSL\B36402 5:69f1634cd40b 201
FSL\B36402 5:69f1634cd40b 202 spi_master_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, NULL, sizeof(txData));
FSL\B36402 5:69f1634cd40b 203
FSL\B36402 5:69f1634cd40b 204 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 205 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 206 }
FSL\B36402 5:69f1634cd40b 207
FSL\B36402 5:69f1634cd40b 208 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 209 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
FSL\B36402 5:69f1634cd40b 210 * Description: -
FSL\B36402 5:69f1634cd40b 211 * Parameters: -
FSL\B36402 5:69f1634cd40b 212 * Return: -
FSL\B36402 5:69f1634cd40b 213 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 214 void MCR20Drv_DirectAccessSPIMultiByteWrite
FSL\B36402 5:69f1634cd40b 215 (
FSL\B36402 5:69f1634cd40b 216 uint8_t startAddress,
FSL\B36402 5:69f1634cd40b 217 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 218 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 219 )
FSL\B36402 5:69f1634cd40b 220 {
FSL\B36402 5:69f1634cd40b 221 uint8_t txData;
FSL\B36402 5:69f1634cd40b 222
FSL\B36402 5:69f1634cd40b 223 if( (numOfBytes == 0) || (byteArray == NULL) )
FSL\B36402 5:69f1634cd40b 224 {
FSL\B36402 5:69f1634cd40b 225 return;
FSL\B36402 5:69f1634cd40b 226 }
FSL\B36402 5:69f1634cd40b 227
FSL\B36402 5:69f1634cd40b 228 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 229
FSL\B36402 5:69f1634cd40b 230 spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
FSL\B36402 5:69f1634cd40b 231
FSL\B36402 5:69f1634cd40b 232 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 233
FSL\B36402 5:69f1634cd40b 234 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask);
FSL\B36402 5:69f1634cd40b 235
FSL\B36402 5:69f1634cd40b 236 spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, sizeof(txData));
FSL\B36402 5:69f1634cd40b 237 spi_master_transfer(gXcvrSpiInstance_c, byteArray, NULL, numOfBytes);
FSL\B36402 5:69f1634cd40b 238
FSL\B36402 5:69f1634cd40b 239 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 240 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 241 }
FSL\B36402 5:69f1634cd40b 242
FSL\B36402 5:69f1634cd40b 243 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 244 * Name: MCR20Drv_PB_SPIByteWrite
FSL\B36402 5:69f1634cd40b 245 * Description: -
FSL\B36402 5:69f1634cd40b 246 * Parameters: -
FSL\B36402 5:69f1634cd40b 247 * Return: -
FSL\B36402 5:69f1634cd40b 248 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 249 void MCR20Drv_PB_SPIByteWrite
FSL\B36402 5:69f1634cd40b 250 (
FSL\B36402 5:69f1634cd40b 251 uint8_t address,
FSL\B36402 5:69f1634cd40b 252 uint8_t value
FSL\B36402 5:69f1634cd40b 253 )
FSL\B36402 5:69f1634cd40b 254 {
FSL\B36402 5:69f1634cd40b 255 uint32_t txData;
FSL\B36402 5:69f1634cd40b 256
FSL\B36402 5:69f1634cd40b 257 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 258
FSL\B36402 5:69f1634cd40b 259 spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
FSL\B36402 5:69f1634cd40b 260
FSL\B36402 5:69f1634cd40b 261 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 262
FSL\B36402 5:69f1634cd40b 263 txData = TransceiverSPI_WriteSelect |
FSL\B36402 5:69f1634cd40b 264 TransceiverSPI_PacketBuffAccessSelect |
FSL\B36402 5:69f1634cd40b 265 TransceiverSPI_PacketBuffByteModeSelect;
FSL\B36402 5:69f1634cd40b 266 txData |= (address) << 8;
FSL\B36402 5:69f1634cd40b 267 txData |= (value) << 16;
FSL\B36402 5:69f1634cd40b 268
FSL\B36402 5:69f1634cd40b 269 spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, 3);
FSL\B36402 5:69f1634cd40b 270
FSL\B36402 5:69f1634cd40b 271 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 272 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 273 }
FSL\B36402 5:69f1634cd40b 274
FSL\B36402 5:69f1634cd40b 275 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 276 * Name: MCR20Drv_PB_SPIBurstWrite
FSL\B36402 5:69f1634cd40b 277 * Description: -
FSL\B36402 5:69f1634cd40b 278 * Parameters: -
FSL\B36402 5:69f1634cd40b 279 * Return: -
FSL\B36402 5:69f1634cd40b 280 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 281 void MCR20Drv_PB_SPIBurstWrite
FSL\B36402 5:69f1634cd40b 282 (
FSL\B36402 5:69f1634cd40b 283 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 284 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 285 )
FSL\B36402 5:69f1634cd40b 286 {
FSL\B36402 5:69f1634cd40b 287 uint8_t txData;
FSL\B36402 5:69f1634cd40b 288
FSL\B36402 5:69f1634cd40b 289 if( (numOfBytes == 0) || (byteArray == NULL) )
FSL\B36402 5:69f1634cd40b 290 {
FSL\B36402 5:69f1634cd40b 291 return;
FSL\B36402 5:69f1634cd40b 292 }
FSL\B36402 5:69f1634cd40b 293
FSL\B36402 5:69f1634cd40b 294 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 295
FSL\B36402 5:69f1634cd40b 296 spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
FSL\B36402 5:69f1634cd40b 297
FSL\B36402 5:69f1634cd40b 298 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 299
FSL\B36402 5:69f1634cd40b 300 txData = TransceiverSPI_WriteSelect |
FSL\B36402 5:69f1634cd40b 301 TransceiverSPI_PacketBuffAccessSelect |
FSL\B36402 5:69f1634cd40b 302 TransceiverSPI_PacketBuffBurstModeSelect;
FSL\B36402 5:69f1634cd40b 303
FSL\B36402 5:69f1634cd40b 304 spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, 1);
FSL\B36402 5:69f1634cd40b 305 spi_master_transfer(gXcvrSpiInstance_c, byteArray, NULL, numOfBytes);
FSL\B36402 5:69f1634cd40b 306
FSL\B36402 5:69f1634cd40b 307 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 308 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 309 }
FSL\B36402 5:69f1634cd40b 310
FSL\B36402 5:69f1634cd40b 311 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 312 * Name: MCR20Drv_DirectAccessSPIRead
FSL\B36402 5:69f1634cd40b 313 * Description: -
FSL\B36402 5:69f1634cd40b 314 * Parameters: -
FSL\B36402 5:69f1634cd40b 315 * Return: -
FSL\B36402 5:69f1634cd40b 316 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 317
FSL\B36402 5:69f1634cd40b 318 uint8_t MCR20Drv_DirectAccessSPIRead
FSL\B36402 5:69f1634cd40b 319 (
FSL\B36402 5:69f1634cd40b 320 uint8_t address
FSL\B36402 5:69f1634cd40b 321 )
FSL\B36402 5:69f1634cd40b 322 {
FSL\B36402 5:69f1634cd40b 323 uint8_t txData;
FSL\B36402 5:69f1634cd40b 324 uint8_t rxData;
FSL\B36402 5:69f1634cd40b 325
FSL\B36402 5:69f1634cd40b 326 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 327
FSL\B36402 5:69f1634cd40b 328 spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
FSL\B36402 5:69f1634cd40b 329
FSL\B36402 5:69f1634cd40b 330 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 331
FSL\B36402 5:69f1634cd40b 332 txData = (address & TransceiverSPI_DirectRegisterAddressMask) |
FSL\B36402 5:69f1634cd40b 333 TransceiverSPI_ReadSelect;
FSL\B36402 5:69f1634cd40b 334
FSL\B36402 5:69f1634cd40b 335 spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, sizeof(txData));
FSL\B36402 5:69f1634cd40b 336 spi_master_transfer(gXcvrSpiInstance_c, NULL, &rxData, sizeof(rxData));
FSL\B36402 5:69f1634cd40b 337
FSL\B36402 5:69f1634cd40b 338 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 339 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 340
FSL\B36402 5:69f1634cd40b 341 return rxData;
FSL\B36402 5:69f1634cd40b 342
FSL\B36402 5:69f1634cd40b 343 }
FSL\B36402 5:69f1634cd40b 344
FSL\B36402 5:69f1634cd40b 345 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 346 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
FSL\B36402 5:69f1634cd40b 347 * Description: -
FSL\B36402 5:69f1634cd40b 348 * Parameters: -
FSL\B36402 5:69f1634cd40b 349 * Return: -
FSL\B36402 5:69f1634cd40b 350 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 351 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
FSL\B36402 5:69f1634cd40b 352 (
FSL\B36402 5:69f1634cd40b 353 uint8_t startAddress,
FSL\B36402 5:69f1634cd40b 354 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 355 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 356 )
FSL\B36402 5:69f1634cd40b 357 {
FSL\B36402 5:69f1634cd40b 358 uint8_t txData;
FSL\B36402 5:69f1634cd40b 359 uint8_t phyIRQSTS1;
FSL\B36402 5:69f1634cd40b 360
FSL\B36402 5:69f1634cd40b 361 if( (numOfBytes == 0) || (byteArray == NULL) )
FSL\B36402 5:69f1634cd40b 362 {
FSL\B36402 5:69f1634cd40b 363 return 0;
FSL\B36402 5:69f1634cd40b 364 }
FSL\B36402 5:69f1634cd40b 365
FSL\B36402 5:69f1634cd40b 366 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 367
FSL\B36402 5:69f1634cd40b 368 spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
FSL\B36402 5:69f1634cd40b 369
FSL\B36402 5:69f1634cd40b 370 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 371
FSL\B36402 5:69f1634cd40b 372 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) |
FSL\B36402 5:69f1634cd40b 373 TransceiverSPI_ReadSelect;
FSL\B36402 5:69f1634cd40b 374
FSL\B36402 5:69f1634cd40b 375 spi_master_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
FSL\B36402 5:69f1634cd40b 376 spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes);
FSL\B36402 5:69f1634cd40b 377
FSL\B36402 5:69f1634cd40b 378 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 379 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 380
FSL\B36402 5:69f1634cd40b 381 return phyIRQSTS1;
FSL\B36402 5:69f1634cd40b 382 }
FSL\B36402 5:69f1634cd40b 383
FSL\B36402 5:69f1634cd40b 384 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 385 * Name: MCR20Drv_PB_SPIBurstRead
FSL\B36402 5:69f1634cd40b 386 * Description: -
FSL\B36402 5:69f1634cd40b 387 * Parameters: -
FSL\B36402 5:69f1634cd40b 388 * Return: -
FSL\B36402 5:69f1634cd40b 389 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 390 uint8_t MCR20Drv_PB_SPIBurstRead
FSL\B36402 5:69f1634cd40b 391 (
FSL\B36402 5:69f1634cd40b 392 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 393 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 394 )
FSL\B36402 5:69f1634cd40b 395 {
FSL\B36402 5:69f1634cd40b 396 uint8_t txData;
FSL\B36402 5:69f1634cd40b 397 uint8_t phyIRQSTS1;
FSL\B36402 5:69f1634cd40b 398
FSL\B36402 5:69f1634cd40b 399 if( (numOfBytes == 0) || (byteArray == NULL) )
FSL\B36402 5:69f1634cd40b 400 {
FSL\B36402 5:69f1634cd40b 401 return 0;
FSL\B36402 5:69f1634cd40b 402 }
FSL\B36402 5:69f1634cd40b 403
FSL\B36402 5:69f1634cd40b 404 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 405
FSL\B36402 5:69f1634cd40b 406 spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
FSL\B36402 5:69f1634cd40b 407
FSL\B36402 5:69f1634cd40b 408 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 409
FSL\B36402 5:69f1634cd40b 410 txData = TransceiverSPI_ReadSelect |
FSL\B36402 5:69f1634cd40b 411 TransceiverSPI_PacketBuffAccessSelect |
FSL\B36402 5:69f1634cd40b 412 TransceiverSPI_PacketBuffBurstModeSelect;
FSL\B36402 5:69f1634cd40b 413
FSL\B36402 5:69f1634cd40b 414 spi_master_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
FSL\B36402 5:69f1634cd40b 415 spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes);
FSL\B36402 5:69f1634cd40b 416
FSL\B36402 5:69f1634cd40b 417 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 418 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 419
FSL\B36402 5:69f1634cd40b 420 return phyIRQSTS1;
FSL\B36402 5:69f1634cd40b 421 }
FSL\B36402 5:69f1634cd40b 422
FSL\B36402 5:69f1634cd40b 423 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 424 * Name: MCR20Drv_IndirectAccessSPIWrite
FSL\B36402 5:69f1634cd40b 425 * Description: -
FSL\B36402 5:69f1634cd40b 426 * Parameters: -
FSL\B36402 5:69f1634cd40b 427 * Return: -
FSL\B36402 5:69f1634cd40b 428 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 429 void MCR20Drv_IndirectAccessSPIWrite
FSL\B36402 5:69f1634cd40b 430 (
FSL\B36402 5:69f1634cd40b 431 uint8_t address,
FSL\B36402 5:69f1634cd40b 432 uint8_t value
FSL\B36402 5:69f1634cd40b 433 )
FSL\B36402 5:69f1634cd40b 434 {
FSL\B36402 5:69f1634cd40b 435 uint32_t txData;
FSL\B36402 5:69f1634cd40b 436
FSL\B36402 5:69f1634cd40b 437 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 438
FSL\B36402 5:69f1634cd40b 439 spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
FSL\B36402 5:69f1634cd40b 440
FSL\B36402 5:69f1634cd40b 441 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 442
FSL\B36402 5:69f1634cd40b 443 txData = TransceiverSPI_IARIndexReg;
FSL\B36402 5:69f1634cd40b 444 txData |= (address) << 8;
FSL\B36402 5:69f1634cd40b 445 txData |= (value) << 16;
FSL\B36402 5:69f1634cd40b 446
FSL\B36402 5:69f1634cd40b 447 spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, 3);
FSL\B36402 5:69f1634cd40b 448
FSL\B36402 5:69f1634cd40b 449 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 450 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 451 }
FSL\B36402 5:69f1634cd40b 452
FSL\B36402 5:69f1634cd40b 453 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 454 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
FSL\B36402 5:69f1634cd40b 455 * Description: -
FSL\B36402 5:69f1634cd40b 456 * Parameters: -
FSL\B36402 5:69f1634cd40b 457 * Return: -
FSL\B36402 5:69f1634cd40b 458 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 459 void MCR20Drv_IndirectAccessSPIMultiByteWrite
FSL\B36402 5:69f1634cd40b 460 (
FSL\B36402 5:69f1634cd40b 461 uint8_t startAddress,
FSL\B36402 5:69f1634cd40b 462 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 463 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 464 )
FSL\B36402 5:69f1634cd40b 465 {
FSL\B36402 5:69f1634cd40b 466 uint16_t txData;
FSL\B36402 5:69f1634cd40b 467
FSL\B36402 5:69f1634cd40b 468 if( (numOfBytes == 0) || (byteArray == NULL) )
FSL\B36402 5:69f1634cd40b 469 {
FSL\B36402 5:69f1634cd40b 470 return;
FSL\B36402 5:69f1634cd40b 471 }
FSL\B36402 5:69f1634cd40b 472
FSL\B36402 5:69f1634cd40b 473 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 474
FSL\B36402 5:69f1634cd40b 475 spi_master_configure_speed(gXcvrSpiInstance_c, 16000000);
FSL\B36402 5:69f1634cd40b 476
FSL\B36402 5:69f1634cd40b 477 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 478
FSL\B36402 5:69f1634cd40b 479 txData = TransceiverSPI_IARIndexReg;
FSL\B36402 5:69f1634cd40b 480 txData |= (startAddress) << 8;
FSL\B36402 5:69f1634cd40b 481
FSL\B36402 5:69f1634cd40b 482 spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData));
FSL\B36402 5:69f1634cd40b 483 spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, NULL, numOfBytes);
FSL\B36402 5:69f1634cd40b 484
FSL\B36402 5:69f1634cd40b 485 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 486 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 487 }
FSL\B36402 5:69f1634cd40b 488
FSL\B36402 5:69f1634cd40b 489 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 490 * Name: MCR20Drv_IndirectAccessSPIRead
FSL\B36402 5:69f1634cd40b 491 * Description: -
FSL\B36402 5:69f1634cd40b 492 * Parameters: -
FSL\B36402 5:69f1634cd40b 493 * Return: -
FSL\B36402 5:69f1634cd40b 494 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 495 uint8_t MCR20Drv_IndirectAccessSPIRead
FSL\B36402 5:69f1634cd40b 496 (
FSL\B36402 5:69f1634cd40b 497 uint8_t address
FSL\B36402 5:69f1634cd40b 498 )
FSL\B36402 5:69f1634cd40b 499 {
FSL\B36402 5:69f1634cd40b 500 uint16_t txData;
FSL\B36402 5:69f1634cd40b 501 uint8_t rxData;
FSL\B36402 5:69f1634cd40b 502
FSL\B36402 5:69f1634cd40b 503 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 504
FSL\B36402 5:69f1634cd40b 505 spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
FSL\B36402 5:69f1634cd40b 506
FSL\B36402 5:69f1634cd40b 507 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 508
FSL\B36402 5:69f1634cd40b 509 txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect;
FSL\B36402 5:69f1634cd40b 510 txData |= (address) << 8;
FSL\B36402 5:69f1634cd40b 511
FSL\B36402 5:69f1634cd40b 512 spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData));
FSL\B36402 5:69f1634cd40b 513 spi_master_transfer(gXcvrSpiInstance_c, NULL, &rxData, sizeof(rxData));
FSL\B36402 5:69f1634cd40b 514
FSL\B36402 5:69f1634cd40b 515 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 516 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 517
FSL\B36402 5:69f1634cd40b 518 return rxData;
FSL\B36402 5:69f1634cd40b 519 }
FSL\B36402 5:69f1634cd40b 520
FSL\B36402 5:69f1634cd40b 521 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 522 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
FSL\B36402 5:69f1634cd40b 523 * Description: -
FSL\B36402 5:69f1634cd40b 524 * Parameters: -
FSL\B36402 5:69f1634cd40b 525 * Return: -
FSL\B36402 5:69f1634cd40b 526 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 527 void MCR20Drv_IndirectAccessSPIMultiByteRead
FSL\B36402 5:69f1634cd40b 528 (
FSL\B36402 5:69f1634cd40b 529 uint8_t startAddress,
FSL\B36402 5:69f1634cd40b 530 uint8_t * byteArray,
FSL\B36402 5:69f1634cd40b 531 uint8_t numOfBytes
FSL\B36402 5:69f1634cd40b 532 )
FSL\B36402 5:69f1634cd40b 533 {
FSL\B36402 5:69f1634cd40b 534 uint16_t txData;
FSL\B36402 5:69f1634cd40b 535
FSL\B36402 5:69f1634cd40b 536 if( (numOfBytes == 0) || (byteArray == NULL) )
FSL\B36402 5:69f1634cd40b 537 {
FSL\B36402 5:69f1634cd40b 538 return;
FSL\B36402 5:69f1634cd40b 539 }
FSL\B36402 5:69f1634cd40b 540
FSL\B36402 5:69f1634cd40b 541 ProtectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 542
FSL\B36402 5:69f1634cd40b 543 spi_master_configure_speed(gXcvrSpiInstance_c, 8000000);
FSL\B36402 5:69f1634cd40b 544
FSL\B36402 5:69f1634cd40b 545 gXcvrAssertCS_d();
FSL\B36402 5:69f1634cd40b 546
FSL\B36402 5:69f1634cd40b 547 txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect);
FSL\B36402 5:69f1634cd40b 548 txData |= (startAddress) << 8;
FSL\B36402 5:69f1634cd40b 549
FSL\B36402 5:69f1634cd40b 550 spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData));
FSL\B36402 5:69f1634cd40b 551 spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes);
FSL\B36402 5:69f1634cd40b 552
FSL\B36402 5:69f1634cd40b 553 gXcvrDeassertCS_d();
FSL\B36402 5:69f1634cd40b 554 UnprotectFromMCR20Interrupt();
FSL\B36402 5:69f1634cd40b 555 }
FSL\B36402 5:69f1634cd40b 556
FSL\B36402 5:69f1634cd40b 557 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 558 * Name: MCR20Drv_IRQ_PortConfig
FSL\B36402 5:69f1634cd40b 559 * Description: -
FSL\B36402 5:69f1634cd40b 560 * Parameters: -
FSL\B36402 5:69f1634cd40b 561 * Return: -
FSL\B36402 5:69f1634cd40b 562 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 563 void MCR20Drv_IRQ_PortConfig
FSL\B36402 5:69f1634cd40b 564 (
FSL\B36402 5:69f1634cd40b 565 void
FSL\B36402 5:69f1634cd40b 566 )
FSL\B36402 5:69f1634cd40b 567 {
FSL\B36402 5:69f1634cd40b 568 #if 0
FSL\B36402 5:69f1634cd40b 569 PORT_HAL_SetMuxMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)],
FSL\B36402 5:69f1634cd40b 570 GPIO_EXTRACT_PIN(kGpioXcvrIrqPin),
FSL\B36402 5:69f1634cd40b 571 kPortMuxAsGpio);
FSL\B36402 5:69f1634cd40b 572 GPIO_DRV_InputPinInit(&mXcvrIrqPinCfg);
FSL\B36402 5:69f1634cd40b 573 #endif
FSL\B36402 5:69f1634cd40b 574 }
FSL\B36402 5:69f1634cd40b 575
FSL\B36402 5:69f1634cd40b 576 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 577 * Name: MCR20Drv_IsIrqPending
FSL\B36402 5:69f1634cd40b 578 * Description: -
FSL\B36402 5:69f1634cd40b 579 * Parameters: -
FSL\B36402 5:69f1634cd40b 580 * Return: -
FSL\B36402 5:69f1634cd40b 581 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 582 uint32_t MCR20Drv_IsIrqPending
FSL\B36402 5:69f1634cd40b 583 (
FSL\B36402 5:69f1634cd40b 584 void
FSL\B36402 5:69f1634cd40b 585 )
FSL\B36402 5:69f1634cd40b 586 {
FSL\B36402 5:69f1634cd40b 587 #if 0
FSL\B36402 5:69f1634cd40b 588 if( GPIO_DRV_ReadPinInput(kGpioXcvrIrqPin) )
FSL\B36402 5:69f1634cd40b 589 {
FSL\B36402 5:69f1634cd40b 590 return FALSE;
FSL\B36402 5:69f1634cd40b 591 }
FSL\B36402 5:69f1634cd40b 592 return TRUE;
FSL\B36402 5:69f1634cd40b 593 #endif
FSL\B36402 5:69f1634cd40b 594 return TRUE;
FSL\B36402 5:69f1634cd40b 595 }
FSL\B36402 5:69f1634cd40b 596
FSL\B36402 5:69f1634cd40b 597 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 598 * Name: MCR20Drv_IRQ_Disable
FSL\B36402 5:69f1634cd40b 599 * Description: -
FSL\B36402 5:69f1634cd40b 600 * Parameters: -
FSL\B36402 5:69f1634cd40b 601 * Return: -
FSL\B36402 5:69f1634cd40b 602 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 603 void MCR20Drv_IRQ_Disable // TODO
FSL\B36402 5:69f1634cd40b 604 (
FSL\B36402 5:69f1634cd40b 605 void
FSL\B36402 5:69f1634cd40b 606 )
FSL\B36402 5:69f1634cd40b 607 {
FSL\B36402 5:69f1634cd40b 608 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 609
FSL\B36402 5:69f1634cd40b 610 if( mPhyIrqDisableCnt == 0 )
FSL\B36402 5:69f1634cd40b 611 {
FSL\B36402 5:69f1634cd40b 612 // PORT_HAL_SetPinIntMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)],
FSL\B36402 5:69f1634cd40b 613 // GPIO_EXTRACT_PIN(kGpioXcvrIrqPin),
FSL\B36402 5:69f1634cd40b 614 // kPortIntDisabled);
FSL\B36402 5:69f1634cd40b 615 }
FSL\B36402 5:69f1634cd40b 616
FSL\B36402 5:69f1634cd40b 617 mPhyIrqDisableCnt++;
FSL\B36402 5:69f1634cd40b 618
FSL\B36402 5:69f1634cd40b 619 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 620 }
FSL\B36402 5:69f1634cd40b 621
FSL\B36402 5:69f1634cd40b 622 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 623 * Name: MCR20Drv_IRQ_Enable
FSL\B36402 5:69f1634cd40b 624 * Description: -
FSL\B36402 5:69f1634cd40b 625 * Parameters: -
FSL\B36402 5:69f1634cd40b 626 * Return: -
FSL\B36402 5:69f1634cd40b 627 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 628 void MCR20Drv_IRQ_Enable // TODO
FSL\B36402 5:69f1634cd40b 629 (
FSL\B36402 5:69f1634cd40b 630 void
FSL\B36402 5:69f1634cd40b 631 )
FSL\B36402 5:69f1634cd40b 632 {
FSL\B36402 5:69f1634cd40b 633 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 634
FSL\B36402 5:69f1634cd40b 635 if( mPhyIrqDisableCnt )
FSL\B36402 5:69f1634cd40b 636 {
FSL\B36402 5:69f1634cd40b 637 mPhyIrqDisableCnt--;
FSL\B36402 5:69f1634cd40b 638
FSL\B36402 5:69f1634cd40b 639 if( mPhyIrqDisableCnt == 0 )
FSL\B36402 5:69f1634cd40b 640 {
FSL\B36402 5:69f1634cd40b 641 // PORT_HAL_SetPinIntMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)],
FSL\B36402 5:69f1634cd40b 642 // GPIO_EXTRACT_PIN(kGpioXcvrIrqPin),
FSL\B36402 5:69f1634cd40b 643 // kPortIntLogicZero);
FSL\B36402 5:69f1634cd40b 644 }
FSL\B36402 5:69f1634cd40b 645 }
FSL\B36402 5:69f1634cd40b 646
FSL\B36402 5:69f1634cd40b 647 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 648 }
FSL\B36402 5:69f1634cd40b 649
FSL\B36402 5:69f1634cd40b 650 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 651 * Name: MCR20Drv_IRQ_IsEnabled
FSL\B36402 5:69f1634cd40b 652 * Description: -
FSL\B36402 5:69f1634cd40b 653 * Parameters: -
FSL\B36402 5:69f1634cd40b 654 * Return: -
FSL\B36402 5:69f1634cd40b 655 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 656 uint32_t MCR20Drv_IRQ_IsEnabled
FSL\B36402 5:69f1634cd40b 657 (
FSL\B36402 5:69f1634cd40b 658 void
FSL\B36402 5:69f1634cd40b 659 )
FSL\B36402 5:69f1634cd40b 660 {
FSL\B36402 5:69f1634cd40b 661 #if 0
FSL\B36402 5:69f1634cd40b 662 port_interrupt_config_t mode;
FSL\B36402 5:69f1634cd40b 663
FSL\B36402 5:69f1634cd40b 664 mode = PORT_HAL_GetPinIntMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)],
FSL\B36402 5:69f1634cd40b 665 GPIO_EXTRACT_PIN(kGpioXcvrIrqPin));
FSL\B36402 5:69f1634cd40b 666 return (mode != kPortIntDisabled);
FSL\B36402 5:69f1634cd40b 667 #endif
FSL\B36402 5:69f1634cd40b 668 return 0;
FSL\B36402 5:69f1634cd40b 669 }
FSL\B36402 5:69f1634cd40b 670
FSL\B36402 5:69f1634cd40b 671 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 672 * Name: MCR20Drv_IRQ_Clear
FSL\B36402 5:69f1634cd40b 673 * Description: -
FSL\B36402 5:69f1634cd40b 674 * Parameters: -
FSL\B36402 5:69f1634cd40b 675 * Return: -
FSL\B36402 5:69f1634cd40b 676 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 677 void MCR20Drv_IRQ_Clear
FSL\B36402 5:69f1634cd40b 678 (
FSL\B36402 5:69f1634cd40b 679 void
FSL\B36402 5:69f1634cd40b 680 )
FSL\B36402 5:69f1634cd40b 681 {
FSL\B36402 5:69f1634cd40b 682 // GPIO_DRV_ClearPinIntFlag(kGpioXcvrIrqPin);
FSL\B36402 5:69f1634cd40b 683 }
FSL\B36402 5:69f1634cd40b 684
FSL\B36402 5:69f1634cd40b 685 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 686 * Name: MCR20Drv_RST_Assert
FSL\B36402 5:69f1634cd40b 687 * Description: -
FSL\B36402 5:69f1634cd40b 688 * Parameters: -
FSL\B36402 5:69f1634cd40b 689 * Return: -
FSL\B36402 5:69f1634cd40b 690 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 691 void MCR20Drv_RST_B_Assert
FSL\B36402 5:69f1634cd40b 692 (
FSL\B36402 5:69f1634cd40b 693 void
FSL\B36402 5:69f1634cd40b 694 )
FSL\B36402 5:69f1634cd40b 695 {
FSL\B36402 5:69f1634cd40b 696 //GPIO_DRV_ClearPinOutput(kGpioXcvrResetPin);
FSL\B36402 5:69f1634cd40b 697 }
FSL\B36402 5:69f1634cd40b 698
FSL\B36402 5:69f1634cd40b 699 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 700 * Name: MCR20Drv_RST_Deassert
FSL\B36402 5:69f1634cd40b 701 * Description: -
FSL\B36402 5:69f1634cd40b 702 * Parameters: -
FSL\B36402 5:69f1634cd40b 703 * Return: -
FSL\B36402 5:69f1634cd40b 704 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 705 void MCR20Drv_RST_B_Deassert
FSL\B36402 5:69f1634cd40b 706 (
FSL\B36402 5:69f1634cd40b 707 void
FSL\B36402 5:69f1634cd40b 708 )
FSL\B36402 5:69f1634cd40b 709 {
FSL\B36402 5:69f1634cd40b 710 //GPIO_DRV_SetPinOutput(kGpioXcvrResetPin);
FSL\B36402 5:69f1634cd40b 711 }
FSL\B36402 5:69f1634cd40b 712
FSL\B36402 5:69f1634cd40b 713 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 714 * Name: MCR20Drv_SoftRST_Assert
FSL\B36402 5:69f1634cd40b 715 * Description: -
FSL\B36402 5:69f1634cd40b 716 * Parameters: -
FSL\B36402 5:69f1634cd40b 717 * Return: -
FSL\B36402 5:69f1634cd40b 718 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 719 void MCR20Drv_SoftRST_Assert
FSL\B36402 5:69f1634cd40b 720 (
FSL\B36402 5:69f1634cd40b 721 void
FSL\B36402 5:69f1634cd40b 722 )
FSL\B36402 5:69f1634cd40b 723 {
FSL\B36402 5:69f1634cd40b 724 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
FSL\B36402 5:69f1634cd40b 725 }
FSL\B36402 5:69f1634cd40b 726
FSL\B36402 5:69f1634cd40b 727 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 728 * Name: MCR20Drv_SoftRST_Deassert
FSL\B36402 5:69f1634cd40b 729 * Description: -
FSL\B36402 5:69f1634cd40b 730 * Parameters: -
FSL\B36402 5:69f1634cd40b 731 * Return: -
FSL\B36402 5:69f1634cd40b 732 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 733 void MCR20Drv_SoftRST_Deassert
FSL\B36402 5:69f1634cd40b 734 (
FSL\B36402 5:69f1634cd40b 735 void
FSL\B36402 5:69f1634cd40b 736 )
FSL\B36402 5:69f1634cd40b 737 {
FSL\B36402 5:69f1634cd40b 738 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
FSL\B36402 5:69f1634cd40b 739 }
FSL\B36402 5:69f1634cd40b 740
FSL\B36402 5:69f1634cd40b 741 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 742 * Name: MCR20Drv_Soft_RESET
FSL\B36402 5:69f1634cd40b 743 * Description: -
FSL\B36402 5:69f1634cd40b 744 * Parameters: -
FSL\B36402 5:69f1634cd40b 745 * Return: -
FSL\B36402 5:69f1634cd40b 746 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 747 void MCR20Drv_Soft_RESET
FSL\B36402 5:69f1634cd40b 748 (
FSL\B36402 5:69f1634cd40b 749 void
FSL\B36402 5:69f1634cd40b 750 )
FSL\B36402 5:69f1634cd40b 751 {
FSL\B36402 5:69f1634cd40b 752 //assert SOG_RST
FSL\B36402 5:69f1634cd40b 753 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
FSL\B36402 5:69f1634cd40b 754
FSL\B36402 5:69f1634cd40b 755 //deassert SOG_RST
FSL\B36402 5:69f1634cd40b 756 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
FSL\B36402 5:69f1634cd40b 757 }
FSL\B36402 5:69f1634cd40b 758
FSL\B36402 5:69f1634cd40b 759 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 760 * Name: MCR20Drv_RESET
FSL\B36402 5:69f1634cd40b 761 * Description: -
FSL\B36402 5:69f1634cd40b 762 * Parameters: -
FSL\B36402 5:69f1634cd40b 763 * Return: -
FSL\B36402 5:69f1634cd40b 764 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 765 void MCR20Drv_RESET
FSL\B36402 5:69f1634cd40b 766 (
FSL\B36402 5:69f1634cd40b 767 void
FSL\B36402 5:69f1634cd40b 768 )
FSL\B36402 5:69f1634cd40b 769 {
FSL\B36402 5:69f1634cd40b 770 volatile uint32_t delay = 1000;
FSL\B36402 5:69f1634cd40b 771 //assert RST_B
FSL\B36402 5:69f1634cd40b 772 MCR20Drv_RST_B_Assert();
FSL\B36402 5:69f1634cd40b 773
FSL\B36402 5:69f1634cd40b 774 // TODO
FSL\B36402 5:69f1634cd40b 775 while(delay--);
FSL\B36402 5:69f1634cd40b 776
FSL\B36402 5:69f1634cd40b 777 //deassert RST_B
FSL\B36402 5:69f1634cd40b 778 MCR20Drv_RST_B_Deassert();
FSL\B36402 5:69f1634cd40b 779 }
FSL\B36402 5:69f1634cd40b 780
FSL\B36402 5:69f1634cd40b 781 /*---------------------------------------------------------------------------
FSL\B36402 5:69f1634cd40b 782 * Name: MCR20Drv_Set_CLK_OUT_Freq
FSL\B36402 5:69f1634cd40b 783 * Description: -
FSL\B36402 5:69f1634cd40b 784 * Parameters: -
FSL\B36402 5:69f1634cd40b 785 * Return: -
FSL\B36402 5:69f1634cd40b 786 *---------------------------------------------------------------------------*/
FSL\B36402 5:69f1634cd40b 787 void MCR20Drv_Set_CLK_OUT_Freq
FSL\B36402 5:69f1634cd40b 788 (
FSL\B36402 5:69f1634cd40b 789 uint8_t freqDiv
FSL\B36402 5:69f1634cd40b 790 )
FSL\B36402 5:69f1634cd40b 791 {
FSL\B36402 5:69f1634cd40b 792 uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND;
FSL\B36402 5:69f1634cd40b 793
FSL\B36402 5:69f1634cd40b 794 if(freqDiv == gCLK_OUT_FREQ_DISABLE)
FSL\B36402 5:69f1634cd40b 795 {
FSL\B36402 5:69f1634cd40b 796 clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled
FSL\B36402 5:69f1634cd40b 797 }
FSL\B36402 5:69f1634cd40b 798
FSL\B36402 5:69f1634cd40b 799 MCR20Drv_DirectAccessSPIWrite((uint8_t) CLK_OUT_CTRL, clkOutCtrlReg);
FSL\B36402 5:69f1634cd40b 800 }
FSL\B36402 5:69f1634cd40b 801
FSL\B36402 5:69f1634cd40b 802