NXP / Mbed 2 deprecated mcr20_wireless_uart

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

Committer:
sam_grove
Date:
Thu Mar 05 20:40:54 2015 +0000
Revision:
8:e4c9f2b7a9d2
Parent:
RF_Drivers_FSL/driverRFPhy.h@5:69f1634cd40b
rename directories;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 5:69f1634cd40b 1 /*
FSL\B36402 5:69f1634cd40b 2 * driverRFPhy.h
FSL\B36402 5:69f1634cd40b 3 *
FSL\B36402 5:69f1634cd40b 4 * Created on: 14 July 2014
FSL\B36402 5:69f1634cd40b 5 * Author: mBed Team
FSL\B36402 5:69f1634cd40b 6 */
FSL\B36402 5:69f1634cd40b 7
FSL\B36402 5:69f1634cd40b 8 #ifndef DRIVERRFPHY_H_
FSL\B36402 5:69f1634cd40b 9 #define DRIVERRFPHY_H_
FSL\B36402 5:69f1634cd40b 10
FSL\B36402 5:69f1634cd40b 11 #include "arm_hal_phy.h"
FSL\B36402 5:69f1634cd40b 12
FSL\B36402 5:69f1634cd40b 13 #ifdef __cplusplus
FSL\B36402 5:69f1634cd40b 14 extern "C" {
FSL\B36402 5:69f1634cd40b 15 #endif
FSL\B36402 5:69f1634cd40b 16
FSL\B36402 5:69f1634cd40b 17 /*Run calibration every 5 minutes*/
FSL\B36402 5:69f1634cd40b 18 #define RF_CALIBRATION_INTERVAL 6000000
FSL\B36402 5:69f1634cd40b 19 /*Wait ACK for 2.5ms*/
FSL\B36402 5:69f1634cd40b 20 #define RF_ACK_WAIT_TIMEOUT 50
FSL\B36402 5:69f1634cd40b 21
FSL\B36402 5:69f1634cd40b 22 #define RF_BUFFER_SIZE 128
FSL\B36402 5:69f1634cd40b 23 #define RF_DEFAULT_CHANNEL 11
FSL\B36402 5:69f1634cd40b 24
FSL\B36402 5:69f1634cd40b 25 /*Radio RX and TX state definitions*/
FSL\B36402 5:69f1634cd40b 26 #define RFF_ON 0x01
FSL\B36402 5:69f1634cd40b 27 #define RFF_RX 0x02
FSL\B36402 5:69f1634cd40b 28 #define RFF_TX 0x04
FSL\B36402 5:69f1634cd40b 29 #define RFF_CCA 0x08
FSL\B36402 5:69f1634cd40b 30
FSL\B36402 5:69f1634cd40b 31 /*Atmel RF states*/
FSL\B36402 5:69f1634cd40b 32 typedef enum
FSL\B36402 5:69f1634cd40b 33 {
FSL\B36402 5:69f1634cd40b 34 NOP = 0x00,
FSL\B36402 5:69f1634cd40b 35 BUSY_RX = 0x01,
FSL\B36402 5:69f1634cd40b 36 RF_TX_START = 0x02,
FSL\B36402 5:69f1634cd40b 37 FORCE_TRX_OFF = 0x03,
FSL\B36402 5:69f1634cd40b 38 FORCE_PLL_ON = 0x04,
FSL\B36402 5:69f1634cd40b 39 RX_ON = 0x06,
FSL\B36402 5:69f1634cd40b 40 TRX_OFF = 0x08,
FSL\B36402 5:69f1634cd40b 41 PLL_ON = 0x09,
FSL\B36402 5:69f1634cd40b 42 BUSY_RX_AACK = 0x11,
FSL\B36402 5:69f1634cd40b 43 SLEEP = 0x0F,
FSL\B36402 5:69f1634cd40b 44 RX_AACK_ON = 0x16,
FSL\B36402 5:69f1634cd40b 45 TX_ARET_ON = 0x19
FSL\B36402 5:69f1634cd40b 46 }rf_trx_states_t;
FSL\B36402 5:69f1634cd40b 47
FSL\B36402 5:69f1634cd40b 48 extern void rf_ack_wait_timer_start(uint16_t slots);
FSL\B36402 5:69f1634cd40b 49 extern void rf_ack_wait_timer_stop(void);
FSL\B36402 5:69f1634cd40b 50 extern void rf_handle_cca_ed_done(void);
FSL\B36402 5:69f1634cd40b 51 extern void rf_handle_tx_end(void);
FSL\B36402 5:69f1634cd40b 52 extern void rf_handle_rx_end(void);
FSL\B36402 5:69f1634cd40b 53 extern void rf_on(void);
FSL\B36402 5:69f1634cd40b 54 extern void rf_receive(void);
FSL\B36402 5:69f1634cd40b 55 extern void rf_poll_trx_state_change(rf_trx_states_t trx_state);
FSL\B36402 5:69f1634cd40b 56 extern void rf_init(void);
FSL\B36402 5:69f1634cd40b 57 extern void rf_set_mac_address(const uint8_t *ptr);
FSL\B36402 5:69f1634cd40b 58 extern int8_t rf_device_register(void);
FSL\B36402 5:69f1634cd40b 59 extern int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle);
FSL\B36402 5:69f1634cd40b 60 extern void rf_cca_abort(void);
FSL\B36402 5:69f1634cd40b 61 extern void rf_read_mac_address(uint8_t *ptr);
FSL\B36402 5:69f1634cd40b 62 extern int8_t rf_read_random(void);
FSL\B36402 5:69f1634cd40b 63 extern void rf_calibration_cb(void);
FSL\B36402 5:69f1634cd40b 64 extern uint8_t rf_init_phy_mode(void);
FSL\B36402 5:69f1634cd40b 65 extern void rf_ack_wait_timer_interrupt(void);
FSL\B36402 5:69f1634cd40b 66 extern void rf_calibration_timer_interrupt(void);
FSL\B36402 5:69f1634cd40b 67 extern void rf_calibration_timer_start(uint32_t slots);
FSL\B36402 5:69f1634cd40b 68 extern void rf_front_end_rx_lna(void);
FSL\B36402 5:69f1634cd40b 69 extern void rf_front_end_sleep(void);
FSL\B36402 5:69f1634cd40b 70 static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
FSL\B36402 5:69f1634cd40b 71 static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
FSL\B36402 5:69f1634cd40b 72 static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
FSL\B36402 5:69f1634cd40b 73
FSL\B36402 5:69f1634cd40b 74 #ifdef __cplusplus
FSL\B36402 5:69f1634cd40b 75 }
FSL\B36402 5:69f1634cd40b 76 #endif
FSL\B36402 5:69f1634cd40b 77 #endif /* DRIVERRFPHY_H_ */