NXP / Mbed 2 deprecated mcr20_wireless_uart

The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

RF_Drivers_Atmel/driverAtmelRFInterface.h@4:d47832caea44, 2015-03-05 (annotated)

Committer:
sam_grove
Date:
Thu Mar 05 20:35:27 2015 +0000
Revision:
4:d47832caea44
Parent:
RF_Drivers/driverAtmelRFInterface.h@2:3e7685cfb2a7 
updates

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 2:3e7685cfb2a7 1 /*
sam_grove 2:3e7685cfb2a7 2 * driverAtmelRFInterface.h
sam_grove 2:3e7685cfb2a7 3 *
sam_grove 2:3e7685cfb2a7 4 * Created on: 14 July 2014
sam_grove 2:3e7685cfb2a7 5 * Author: mBed Team
sam_grove 2:3e7685cfb2a7 6 */
sam_grove 2:3e7685cfb2a7 7
sam_grove 2:3e7685cfb2a7 8 #ifndef DRIVERRFINTERFACE_H_
sam_grove 2:3e7685cfb2a7 9 #define DRIVERRFINTERFACE_H_
sam_grove 2:3e7685cfb2a7 10
sam_grove 2:3e7685cfb2a7 11
sam_grove 2:3e7685cfb2a7 12 /*Delay between transfers(bytes) (32*DLYBCT)/MCK -> (32*6/120MHz=1.6us)*/
sam_grove 2:3e7685cfb2a7 13 #define SPI_DLYBCT 6
sam_grove 2:3e7685cfb2a7 14 /*Delay before SPCK DLYBS/MCK -> 140/120MHz=1.16us)*/
sam_grove 2:3e7685cfb2a7 15 #define SPI_DLYBS 140
sam_grove 2:3e7685cfb2a7 16 /*Serial clock baud rate MCK/SCBR -> 120MHz/18=6.7MHz)*/
sam_grove 2:3e7685cfb2a7 17 #define SPI_SCBR 18
sam_grove 2:3e7685cfb2a7 18
sam_grove 2:3e7685cfb2a7 19 #define PHY_ACK_WAIT_TICK_VAL 185
sam_grove 2:3e7685cfb2a7 20 #define PHY_CALIBRATION_TICK_VAL 185
sam_grove 2:3e7685cfb2a7 21 #define PHY_ACK_WAIT_TIMER 1
sam_grove 2:3e7685cfb2a7 22 #define PHY_CALIBRATION_TIMER 2
sam_grove 2:3e7685cfb2a7 23
sam_grove 2:3e7685cfb2a7 24 /*Supported transceivers*/
sam_grove 2:3e7685cfb2a7 25 #define PART_AT86RF231 0x03
sam_grove 2:3e7685cfb2a7 26 #define PART_AT86RF212 0x07
sam_grove 2:3e7685cfb2a7 27 #define PART_AT86RF233 0x0B
sam_grove 2:3e7685cfb2a7 28 #define VERSION_AT86RF212 0x01
sam_grove 2:3e7685cfb2a7 29 #define VERSION_AT86RF212B 0x03
sam_grove 2:3e7685cfb2a7 30
sam_grove 2:3e7685cfb2a7 31 /*RF Configuration Registers*/
sam_grove 2:3e7685cfb2a7 32 #define TRX_STATUS 0x01
sam_grove 2:3e7685cfb2a7 33 #define TRX_STATE 0x02
sam_grove 2:3e7685cfb2a7 34 #define TRX_CTRL_0 0x03
sam_grove 2:3e7685cfb2a7 35 #define TRX_CTRL_1 0x04
sam_grove 2:3e7685cfb2a7 36 #define PHY_TX_PWR 0x05
sam_grove 2:3e7685cfb2a7 37 #define PHY_RSSI 0x06
sam_grove 2:3e7685cfb2a7 38 #define PHY_ED_LEVEL 0x07
sam_grove 2:3e7685cfb2a7 39 #define PHY_CC_CCA 0x08
sam_grove 2:3e7685cfb2a7 40 #define RX_CTRL 0x0A
sam_grove 2:3e7685cfb2a7 41 #define SFD_VALUE 0x0B
sam_grove 2:3e7685cfb2a7 42 #define TRX_CTRL_2 0x0C
sam_grove 2:3e7685cfb2a7 43 #define ANT_DIV 0x0D
sam_grove 2:3e7685cfb2a7 44 #define IRQ_MASK 0x0E
sam_grove 2:3e7685cfb2a7 45 #define IRQ_STATUS 0x0F
sam_grove 2:3e7685cfb2a7 46 #define VREG_CTRL 0x10
sam_grove 2:3e7685cfb2a7 47 #define BATMON 0x11
sam_grove 2:3e7685cfb2a7 48 #define XOSC_CTRL 0x12
sam_grove 2:3e7685cfb2a7 49 #define CC_CTRL_0 0x13
sam_grove 2:3e7685cfb2a7 50 #define CC_CTRL_1 0x14
sam_grove 2:3e7685cfb2a7 51 #define RX_SYN 0x15
sam_grove 2:3e7685cfb2a7 52 #define TRX_RPC 0x16
sam_grove 2:3e7685cfb2a7 53 #define RF_CTRL_0 0x16
sam_grove 2:3e7685cfb2a7 54 #define XAH_CTRL_1 0x17
sam_grove 2:3e7685cfb2a7 55 #define FTN_CTRL 0x18
sam_grove 2:3e7685cfb2a7 56 #define PLL_CF 0x1A
sam_grove 2:3e7685cfb2a7 57 #define PLL_DCU 0x1B
sam_grove 2:3e7685cfb2a7 58 #define PART_NUM 0x1C
sam_grove 2:3e7685cfb2a7 59 #define VERSION_NUM 0x1D
sam_grove 2:3e7685cfb2a7 60 #define MAN_ID_0 0x1E
sam_grove 2:3e7685cfb2a7 61 #define MAN_ID_1 0x1F
sam_grove 2:3e7685cfb2a7 62 #define SHORT_ADDR_0 0x20
sam_grove 2:3e7685cfb2a7 63 #define SHORT_ADDR_1 0x21
sam_grove 2:3e7685cfb2a7 64 #define PAN_ID_0 0x22
sam_grove 2:3e7685cfb2a7 65 #define PAN_ID_1 0x23
sam_grove 2:3e7685cfb2a7 66 #define IEEE_ADDR_0 0x24
sam_grove 2:3e7685cfb2a7 67 #define IEEE_ADDR_1 0x25
sam_grove 2:3e7685cfb2a7 68 #define IEEE_ADDR_2 0x26
sam_grove 2:3e7685cfb2a7 69 #define IEEE_ADDR_3 0x27
sam_grove 2:3e7685cfb2a7 70 #define IEEE_ADDR_4 0x28
sam_grove 2:3e7685cfb2a7 71 #define IEEE_ADDR_5 0x29
sam_grove 2:3e7685cfb2a7 72 #define IEEE_ADDR_6 0x2A
sam_grove 2:3e7685cfb2a7 73 #define IEEE_ADDR_7 0x2B
sam_grove 2:3e7685cfb2a7 74 #define XAH_CTRL_0 0x2C
sam_grove 2:3e7685cfb2a7 75 #define CSMA_SEED_0 0x2D
sam_grove 2:3e7685cfb2a7 76 #define CSMA_SEED_1 0x2E
sam_grove 2:3e7685cfb2a7 77 #define CSMA_BE 0x2F
sam_grove 2:3e7685cfb2a7 78
sam_grove 2:3e7685cfb2a7 79 /* CSMA_SEED_1*/
sam_grove 2:3e7685cfb2a7 80 #define AACK_FVN_MODE1 7
sam_grove 2:3e7685cfb2a7 81 #define AACK_FVN_MODE0 6
sam_grove 2:3e7685cfb2a7 82 #define AACK_SET_PD 5
sam_grove 2:3e7685cfb2a7 83 #define AACK_DIS_ACK 4
sam_grove 2:3e7685cfb2a7 84 #define AACK_I_AM_COORD 3
sam_grove 2:3e7685cfb2a7 85 #define CSMA_SEED_12 2
sam_grove 2:3e7685cfb2a7 86 #define CSMA_SEED_11 1
sam_grove 2:3e7685cfb2a7 87 #define CSMA_SEED_10 0
sam_grove 2:3e7685cfb2a7 88
sam_grove 2:3e7685cfb2a7 89 /*TRX_STATUS bits*/
sam_grove 2:3e7685cfb2a7 90 #define CCA_STATUS 0x40
sam_grove 2:3e7685cfb2a7 91 #define CCA_DONE 0x80
sam_grove 2:3e7685cfb2a7 92
sam_grove 2:3e7685cfb2a7 93 /*PHY_CC_CCA bits*/
sam_grove 2:3e7685cfb2a7 94 #define CCA_REQUEST 0x80
sam_grove 2:3e7685cfb2a7 95 #define CCA_MODE_1 0x20
sam_grove 2:3e7685cfb2a7 96 #define CCA_MODE_3 0x60
sam_grove 2:3e7685cfb2a7 97
sam_grove 2:3e7685cfb2a7 98 /*IRQ_MASK bits*/
sam_grove 2:3e7685cfb2a7 99 #define RX_START 0x04
sam_grove 2:3e7685cfb2a7 100 #define TRX_END 0x08
sam_grove 2:3e7685cfb2a7 101 #define CCA_ED_DONE 0x10
sam_grove 2:3e7685cfb2a7 102 #define AMI 0x20
sam_grove 2:3e7685cfb2a7 103 #define TRX_UR 0x40
sam_grove 2:3e7685cfb2a7 104
sam_grove 2:3e7685cfb2a7 105 /*ANT_DIV bits*/
sam_grove 2:3e7685cfb2a7 106 #define ANT_DIV_EN 0x08
sam_grove 2:3e7685cfb2a7 107 #define ANT_EXT_SW_EN 0x04
sam_grove 2:3e7685cfb2a7 108 #define ANT_CTRL_DEFAULT 0x03
sam_grove 2:3e7685cfb2a7 109
sam_grove 2:3e7685cfb2a7 110 /*TRX_CTRL_1 bits*/
sam_grove 2:3e7685cfb2a7 111 #define PA_EXT_EN 0x80
sam_grove 2:3e7685cfb2a7 112
sam_grove 2:3e7685cfb2a7 113 /*FTN_CTRL bits*/
sam_grove 2:3e7685cfb2a7 114 #define FTN_START 0x80
sam_grove 2:3e7685cfb2a7 115
sam_grove 2:3e7685cfb2a7 116 /*PHY_RSSI bits*/
sam_grove 2:3e7685cfb2a7 117 #define CRC_VALID 0x80
sam_grove 2:3e7685cfb2a7 118
sam_grove 2:3e7685cfb2a7 119 /*AT86RF212 PHY Modes*/
sam_grove 2:3e7685cfb2a7 120 #define BPSK_20 0x00
sam_grove 2:3e7685cfb2a7 121 #define BPSK_40 0x04
sam_grove 2:3e7685cfb2a7 122 #define BPSK_40_ALT 0x14
sam_grove 2:3e7685cfb2a7 123 #define OQPSK_SIN_RC_100 0x08
sam_grove 2:3e7685cfb2a7 124 #define OQPSK_SIN_RC_200 0x09
sam_grove 2:3e7685cfb2a7 125 #define OQPSK_RC_100 0x18
sam_grove 2:3e7685cfb2a7 126 #define OQPSK_RC_200 0x19
sam_grove 2:3e7685cfb2a7 127 #define OQPSK_SIN_250 0x0c
sam_grove 2:3e7685cfb2a7 128 #define OQPSK_SIN_500 0x0d
sam_grove 2:3e7685cfb2a7 129 #define OQPSK_SIN_500_ALT 0x0f
sam_grove 2:3e7685cfb2a7 130 #define OQPSK_RC_250 0x1c
sam_grove 2:3e7685cfb2a7 131 #define OQPSK_RC_500 0x1d
sam_grove 2:3e7685cfb2a7 132 #define OQPSK_RC_500_ALT 0x1f
sam_grove 2:3e7685cfb2a7 133 #define OQPSK_SIN_RC_400_SCR_ON 0x2A
sam_grove 2:3e7685cfb2a7 134 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A
sam_grove 2:3e7685cfb2a7 135 #define OQPSK_RC_400_SCR_ON 0x3A
sam_grove 2:3e7685cfb2a7 136 #define OQPSK_RC_400_SCR_OFF 0x1A
sam_grove 2:3e7685cfb2a7 137 #define OQPSK_SIN_1000_SCR_ON 0x2E
sam_grove 2:3e7685cfb2a7 138 #define OQPSK_SIN_1000_SCR_OFF 0x0E
sam_grove 2:3e7685cfb2a7 139 #define OQPSK_RC_1000_SCR_ON 0x3E
sam_grove 2:3e7685cfb2a7 140 #define OQPSK_RC_1000_SCR_OFF 0x1E
sam_grove 2:3e7685cfb2a7 141
sam_grove 2:3e7685cfb2a7 142 extern void rf_if_delay_function(uint16_t ticks);
sam_grove 2:3e7685cfb2a7 143 extern uint8_t rf_if_read_rnd(void);
sam_grove 2:3e7685cfb2a7 144 extern void rf_if_calibration_timer_start(uint32_t slots);
sam_grove 2:3e7685cfb2a7 145 extern void rf_if_interrupt_handler(void);
sam_grove 2:3e7685cfb2a7 146 extern void (*rf_if_get_rf_interrupt_function())(void);
sam_grove 2:3e7685cfb2a7 147 extern void rf_if_calibration_timer_interrupt(void);
sam_grove 2:3e7685cfb2a7 148 extern void rf_if_timer_init(void);
sam_grove 2:3e7685cfb2a7 149 extern void rf_if_ack_wait_timer_start(uint16_t slots);
sam_grove 2:3e7685cfb2a7 150 extern void rf_if_ack_wait_timer_stop(void);
sam_grove 2:3e7685cfb2a7 151 extern void rf_if_ack_wait_timer_interrupt(void);
sam_grove 2:3e7685cfb2a7 152 extern int8_t rf_if_set_rf_irq_pin(uint8_t port, uint8_t pin);
sam_grove 2:3e7685cfb2a7 153 extern int8_t rf_if_set_slp_tr_pin(uint8_t port, uint8_t pin);
sam_grove 2:3e7685cfb2a7 154 extern int8_t rf_if_set_reset_pin(uint8_t port, uint8_t pin);
sam_grove 2:3e7685cfb2a7 155 extern int8_t rf_if_set_spi_interface(uint8_t spi_interface, uint8_t cs_device);
sam_grove 2:3e7685cfb2a7 156 extern uint8_t rf_if_spi_exchange(uint8_t spi_if, uint8_t out);
sam_grove 2:3e7685cfb2a7 157 extern void rf_if_ack_pending_ctrl(uint8_t state);
sam_grove 2:3e7685cfb2a7 158 extern void rf_if_calibration(void);
sam_grove 2:3e7685cfb2a7 159 extern uint8_t rf_if_read_register(uint8_t addr);
sam_grove 2:3e7685cfb2a7 160 extern void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask);
sam_grove 2:3e7685cfb2a7 161 extern void rf_if_clear_bit(uint8_t addr, uint8_t bit);
sam_grove 2:3e7685cfb2a7 162 extern void rf_if_write_register(uint8_t addr, uint8_t data);
sam_grove 2:3e7685cfb2a7 163 extern void rf_if_reset_radio(void);
sam_grove 2:3e7685cfb2a7 164 extern void rf_if_enable_pa_ext(void);
sam_grove 2:3e7685cfb2a7 165 extern void rf_if_disable_pa_ext(void);
sam_grove 2:3e7685cfb2a7 166 extern void rf_if_enable_ant_div(void);
sam_grove 2:3e7685cfb2a7 167 extern void rf_if_disable_ant_div(void);
sam_grove 2:3e7685cfb2a7 168 extern void rf_if_enable_slptr(void);
sam_grove 2:3e7685cfb2a7 169 extern void rf_if_disable_slptr(void);
sam_grove 2:3e7685cfb2a7 170 extern void rf_if_write_antenna_diversity_settings(void);
sam_grove 2:3e7685cfb2a7 171 extern void rf_if_write_set_tx_power_register(uint8_t value);
sam_grove 2:3e7685cfb2a7 172 extern void rf_if_write_set_trx_rpc_register(uint8_t value);
sam_grove 2:3e7685cfb2a7 173 extern void rf_if_write_rf_settings(void);
sam_grove 2:3e7685cfb2a7 174 extern uint8_t rf_if_check_cca(void);
sam_grove 2:3e7685cfb2a7 175 extern uint8_t rf_if_check_crc(void);
sam_grove 2:3e7685cfb2a7 176 extern uint8_t rf_if_read_trx_state(void);
sam_grove 2:3e7685cfb2a7 177 extern void rf_if_read_packet(uint8_t *ptr, uint8_t len);
sam_grove 2:3e7685cfb2a7 178 extern void rf_if_write_short_addr_registers(uint8_t *short_address);
sam_grove 2:3e7685cfb2a7 179 extern uint8_t rf_if_last_acked_pending(void);
sam_grove 2:3e7685cfb2a7 180 extern void rf_if_write_pan_id_registers(uint8_t *pan_id);
sam_grove 2:3e7685cfb2a7 181 extern void rf_if_write_ieee_addr_registers(uint8_t *address);
sam_grove 2:3e7685cfb2a7 182 extern void rf_if_write_frame_buffer(uint8_t *ptr, uint8_t length);
sam_grove 2:3e7685cfb2a7 183 extern void rf_if_change_trx_state(rf_trx_states_t trx_state);
sam_grove 2:3e7685cfb2a7 184 extern void rf_if_enable_tx_end_interrupt(void);
sam_grove 2:3e7685cfb2a7 185 extern void rf_if_enable_rx_end_interrupt(void);
sam_grove 2:3e7685cfb2a7 186 extern void rf_if_enable_rx_start_interrupt(void);
sam_grove 2:3e7685cfb2a7 187 extern void rf_if_enable_cca_ed_done_interrupt(void);
sam_grove 2:3e7685cfb2a7 188 extern void rf_if_start_cca_process(void);
sam_grove 2:3e7685cfb2a7 189 extern uint8_t rf_if_read_received_frame_length(void);
sam_grove 2:3e7685cfb2a7 190 extern uint8_t rf_if_read_lqi(void);
sam_grove 2:3e7685cfb2a7 191 extern int8_t rf_if_read_rssi(void);
sam_grove 2:3e7685cfb2a7 192 extern void rf_if_set_channel_register(uint8_t channel);
sam_grove 2:3e7685cfb2a7 193
sam_grove 2:3e7685cfb2a7 194 #endif /* DRIVERRFINTERFACE_H_ */