NXP / Mbed 2 deprecated mcr20_wireless_uart

The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

RF_Drivers_Freescale/PhyTime.c@16:549f2f246ece, 2015-03-15 (annotated)

Committer:
cotigac
Date:
Sun Mar 15 06:08:30 2015 +0000
Revision:
16:549f2f246ece
Parent:
15:990a8b5664e1 
Minor updates to compile also online

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 15:990a8b5664e1 1 /*!
FSL\B36402 15:990a8b5664e1 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
FSL\B36402 15:990a8b5664e1 3 * All rights reserved.
FSL\B36402 15:990a8b5664e1 4 *
FSL\B36402 15:990a8b5664e1 5 * \file PhyTime.c
FSL\B36402 15:990a8b5664e1 6 *
FSL\B36402 15:990a8b5664e1 7 * Redistribution and use in source and binary forms, with or without modification,
FSL\B36402 15:990a8b5664e1 8 * are permitted provided that the following conditions are met:
FSL\B36402 15:990a8b5664e1 9 *
FSL\B36402 15:990a8b5664e1 10 * o Redistributions of source code must retain the above copyright notice, this list
FSL\B36402 15:990a8b5664e1 11 * of conditions and the following disclaimer.
FSL\B36402 15:990a8b5664e1 12 *
FSL\B36402 15:990a8b5664e1 13 * o Redistributions in binary form must reproduce the above copyright notice, this
FSL\B36402 15:990a8b5664e1 14 * list of conditions and the following disclaimer in the documentation and/or
FSL\B36402 15:990a8b5664e1 15 * other materials provided with the distribution.
FSL\B36402 15:990a8b5664e1 16 *
FSL\B36402 15:990a8b5664e1 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
FSL\B36402 15:990a8b5664e1 18 * contributors may be used to endorse or promote products derived from this
FSL\B36402 15:990a8b5664e1 19 * software without specific prior written permission.
FSL\B36402 15:990a8b5664e1 20 *
FSL\B36402 15:990a8b5664e1 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
FSL\B36402 15:990a8b5664e1 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
FSL\B36402 15:990a8b5664e1 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
FSL\B36402 15:990a8b5664e1 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
FSL\B36402 15:990a8b5664e1 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
FSL\B36402 15:990a8b5664e1 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
FSL\B36402 15:990a8b5664e1 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
FSL\B36402 15:990a8b5664e1 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
FSL\B36402 15:990a8b5664e1 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
FSL\B36402 15:990a8b5664e1 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
FSL\B36402 15:990a8b5664e1 31 */
FSL\B36402 15:990a8b5664e1 32
FSL\B36402 15:990a8b5664e1 33
FSL\B36402 15:990a8b5664e1 34 /************************************************************************************
FSL\B36402 15:990a8b5664e1 35 *************************************************************************************
FSL\B36402 15:990a8b5664e1 36 * Include
FSL\B36402 15:990a8b5664e1 37 *************************************************************************************
FSL\B36402 15:990a8b5664e1 38 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 39 #include "EmbeddedTypes.h"
FSL\B36402 15:990a8b5664e1 40 //#include "fsl_os_abstraction.h"
FSL\B36402 15:990a8b5664e1 41 #include "MCR20Drv.h"
FSL\B36402 15:990a8b5664e1 42 #include "MCR20Reg.h"
FSL\B36402 15:990a8b5664e1 43 #include "Phy.h"
FSL\B36402 15:990a8b5664e1 44
FSL\B36402 15:990a8b5664e1 45 //#include "FunctionLib.h"
FSL\B36402 15:990a8b5664e1 46 #include "arm_hal_interrupt.h"
FSL\B36402 15:990a8b5664e1 47
FSL\B36402 15:990a8b5664e1 48 /************************************************************************************
FSL\B36402 15:990a8b5664e1 49 *************************************************************************************
FSL\B36402 15:990a8b5664e1 50 * Private macros
FSL\B36402 15:990a8b5664e1 51 *************************************************************************************
FSL\B36402 15:990a8b5664e1 52 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 53 #define gPhyTimeMinSetupTime_c (10) /* symbols */
FSL\B36402 15:990a8b5664e1 54
FSL\B36402 15:990a8b5664e1 55 /************************************************************************************
FSL\B36402 15:990a8b5664e1 56 *************************************************************************************
FSL\B36402 15:990a8b5664e1 57 * Public memory declarations
FSL\B36402 15:990a8b5664e1 58 *************************************************************************************
FSL\B36402 15:990a8b5664e1 59 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 60 void (*gpfPhyTimeNotify)(void) = NULL;
FSL\B36402 15:990a8b5664e1 61
FSL\B36402 15:990a8b5664e1 62 /************************************************************************************
FSL\B36402 15:990a8b5664e1 63 *************************************************************************************
FSL\B36402 15:990a8b5664e1 64 * Private memory declarations
FSL\B36402 15:990a8b5664e1 65 *************************************************************************************
FSL\B36402 15:990a8b5664e1 66 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 67 static phyTimeEvent_t mPhyTimers[gMaxPhyTimers_c];
FSL\B36402 15:990a8b5664e1 68 static phyTimeEvent_t *pNextEvent;
FSL\B36402 15:990a8b5664e1 69 volatile uint32_t mPhySeqTimeout;
FSL\B36402 15:990a8b5664e1 70 volatile uint64_t gPhyTimerOverflow;
FSL\B36402 15:990a8b5664e1 71
FSL\B36402 15:990a8b5664e1 72 /************************************************************************************
FSL\B36402 15:990a8b5664e1 73 *************************************************************************************
FSL\B36402 15:990a8b5664e1 74 * Private prototypes
FSL\B36402 15:990a8b5664e1 75 *************************************************************************************
FSL\B36402 15:990a8b5664e1 76 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 77 static void PhyTime_OverflowCB( uint32_t param );
FSL\B36402 15:990a8b5664e1 78 static phyTimeEvent_t* PhyTime_GetNextEvent( void );
FSL\B36402 15:990a8b5664e1 79
FSL\B36402 15:990a8b5664e1 80 /************************************************************************************
FSL\B36402 15:990a8b5664e1 81 *************************************************************************************
FSL\B36402 15:990a8b5664e1 82 * Public functions
FSL\B36402 15:990a8b5664e1 83 *************************************************************************************
FSL\B36402 15:990a8b5664e1 84 ************************************************************************************/
FSL\B36402 15:990a8b5664e1 85
FSL\B36402 15:990a8b5664e1 86 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 87 * \brief Sets the start time of a sequence
FSL\B36402 15:990a8b5664e1 88 *
FSL\B36402 15:990a8b5664e1 89 * \param[in] startTime the start time for a sequence
FSL\B36402 15:990a8b5664e1 90 *
FSL\B36402 15:990a8b5664e1 91 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 92 void PhyTimeSetEventTrigger
FSL\B36402 15:990a8b5664e1 93 (
FSL\B36402 15:990a8b5664e1 94 uint32_t startTime
FSL\B36402 15:990a8b5664e1 95 )
FSL\B36402 15:990a8b5664e1 96 {
FSL\B36402 15:990a8b5664e1 97 uint8_t phyReg, phyCtrl3Reg;
FSL\B36402 15:990a8b5664e1 98
FSL\B36402 15:990a8b5664e1 99 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 100
FSL\B36402 15:990a8b5664e1 101 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
FSL\B36402 15:990a8b5664e1 102 phyReg |= cPHY_CTRL1_TMRTRIGEN; // enable autosequence start by TC2 match
FSL\B36402 15:990a8b5664e1 103 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL1, phyReg);
FSL\B36402 15:990a8b5664e1 104
FSL\B36402 15:990a8b5664e1 105 phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
FSL\B36402 15:990a8b5664e1 106 phyCtrl3Reg &= ~(cPHY_CTRL3_TMR2CMP_EN);// disable TMR2 compare
FSL\B36402 15:990a8b5664e1 107 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
FSL\B36402 15:990a8b5664e1 108
FSL\B36402 15:990a8b5664e1 109 MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T2PRIMECMP_LSB, (uint8_t *) &startTime, 2);
FSL\B36402 15:990a8b5664e1 110
FSL\B36402 15:990a8b5664e1 111 phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
FSL\B36402 15:990a8b5664e1 112 phyReg &= 0xF0; // do not change other IRQs status
FSL\B36402 15:990a8b5664e1 113 phyReg &= ~(cIRQSTS3_TMR2MSK); // unmask TMR2 interrupt
FSL\B36402 15:990a8b5664e1 114 phyReg |= (cIRQSTS3_TMR2IRQ); // aknowledge TMR2 IRQ
FSL\B36402 15:990a8b5664e1 115 MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
FSL\B36402 15:990a8b5664e1 116
FSL\B36402 15:990a8b5664e1 117 // TC2PRIME_EN must be enabled in PHY_CTRL4 register
FSL\B36402 15:990a8b5664e1 118 phyCtrl3Reg |= cPHY_CTRL3_TMR2CMP_EN; // enable TMR2 compare
FSL\B36402 15:990a8b5664e1 119 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
FSL\B36402 15:990a8b5664e1 120
FSL\B36402 15:990a8b5664e1 121 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 122 }
FSL\B36402 15:990a8b5664e1 123
FSL\B36402 15:990a8b5664e1 124 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 125 * \brief Disable the time trigger for a sequence.
FSL\B36402 15:990a8b5664e1 126 *
FSL\B36402 15:990a8b5664e1 127 * \remarks The sequence will start asap
FSL\B36402 15:990a8b5664e1 128 *
FSL\B36402 15:990a8b5664e1 129 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 130 void PhyTimeDisableEventTrigger
FSL\B36402 15:990a8b5664e1 131 (
FSL\B36402 15:990a8b5664e1 132 void
FSL\B36402 15:990a8b5664e1 133 )
FSL\B36402 15:990a8b5664e1 134 {
FSL\B36402 15:990a8b5664e1 135 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 136
FSL\B36402 15:990a8b5664e1 137 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 138
FSL\B36402 15:990a8b5664e1 139 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
FSL\B36402 15:990a8b5664e1 140 phyReg &= ~(cPHY_CTRL1_TMRTRIGEN); // disable autosequence start by TC2 match
FSL\B36402 15:990a8b5664e1 141 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL1, phyReg);
FSL\B36402 15:990a8b5664e1 142
FSL\B36402 15:990a8b5664e1 143 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
FSL\B36402 15:990a8b5664e1 144 phyReg &= ~(cPHY_CTRL3_TMR2CMP_EN);// disable TMR2 compare
FSL\B36402 15:990a8b5664e1 145 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyReg);
FSL\B36402 15:990a8b5664e1 146
FSL\B36402 15:990a8b5664e1 147 phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
FSL\B36402 15:990a8b5664e1 148 phyReg &= 0xF0; // do not change other IRQs status
FSL\B36402 15:990a8b5664e1 149 phyReg |= (cIRQSTS3_TMR2MSK); // mask TMR2 interrupt
FSL\B36402 15:990a8b5664e1 150 phyReg |= (cIRQSTS3_TMR2IRQ); // aknowledge TMR2 IRQ
FSL\B36402 15:990a8b5664e1 151 MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
FSL\B36402 15:990a8b5664e1 152
FSL\B36402 15:990a8b5664e1 153 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 154 }
FSL\B36402 15:990a8b5664e1 155
FSL\B36402 15:990a8b5664e1 156 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 157 * \brief Sets the timeout value for a sequence
FSL\B36402 15:990a8b5664e1 158 *
FSL\B36402 15:990a8b5664e1 159 * \param[in] pEndTime the absolute time when a sequence should terminate
FSL\B36402 15:990a8b5664e1 160 *
FSL\B36402 15:990a8b5664e1 161 * \remarks If the sequence does not finish until the timeout, it will be aborted
FSL\B36402 15:990a8b5664e1 162 *
FSL\B36402 15:990a8b5664e1 163 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 164 void PhyTimeSetEventTimeout
FSL\B36402 15:990a8b5664e1 165 (
FSL\B36402 15:990a8b5664e1 166 uint32_t *pEndTime
FSL\B36402 15:990a8b5664e1 167 )
FSL\B36402 15:990a8b5664e1 168 {
FSL\B36402 15:990a8b5664e1 169 uint8_t phyReg, phyCtrl3Reg;
FSL\B36402 15:990a8b5664e1 170
FSL\B36402 15:990a8b5664e1 171 #ifdef PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 172 if(NULL == pEndTime)
FSL\B36402 15:990a8b5664e1 173 {
FSL\B36402 15:990a8b5664e1 174 return;
FSL\B36402 15:990a8b5664e1 175 }
FSL\B36402 15:990a8b5664e1 176 #endif // PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 177
FSL\B36402 15:990a8b5664e1 178 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 179
FSL\B36402 15:990a8b5664e1 180 phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
FSL\B36402 15:990a8b5664e1 181 phyCtrl3Reg &= ~(cPHY_CTRL3_TMR3CMP_EN);// disable TMR3 compare
FSL\B36402 15:990a8b5664e1 182 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
FSL\B36402 15:990a8b5664e1 183
FSL\B36402 15:990a8b5664e1 184 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4);
FSL\B36402 15:990a8b5664e1 185 phyReg |= cPHY_CTRL4_TC3TMOUT; // enable autosequence stop by TC3 match
FSL\B36402 15:990a8b5664e1 186 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyReg);
FSL\B36402 15:990a8b5664e1 187
FSL\B36402 15:990a8b5664e1 188 mPhySeqTimeout = *pEndTime & 0x00FFFFFF;
FSL\B36402 15:990a8b5664e1 189 MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T3CMP_LSB, (uint8_t *) pEndTime, 3);
FSL\B36402 15:990a8b5664e1 190
FSL\B36402 15:990a8b5664e1 191 phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
FSL\B36402 15:990a8b5664e1 192 phyReg &= 0xF0; // do not change IRQ status
FSL\B36402 15:990a8b5664e1 193 // phyReg &= ~(cIRQSTS3_TMR3MSK); // unmask TMR3 interrupt
FSL\B36402 15:990a8b5664e1 194 phyReg |= (cIRQSTS3_TMR3IRQ); // aknowledge TMR3 IRQ
FSL\B36402 15:990a8b5664e1 195 MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
FSL\B36402 15:990a8b5664e1 196
FSL\B36402 15:990a8b5664e1 197 phyCtrl3Reg |= cPHY_CTRL3_TMR3CMP_EN; // enable TMR3 compare
FSL\B36402 15:990a8b5664e1 198 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
FSL\B36402 15:990a8b5664e1 199
FSL\B36402 15:990a8b5664e1 200 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 201 }
FSL\B36402 15:990a8b5664e1 202
FSL\B36402 15:990a8b5664e1 203 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 204 * \brief Return the timeout value for the current sequence
FSL\B36402 15:990a8b5664e1 205 *
FSL\B36402 15:990a8b5664e1 206 * \return uint32_t the timeout value
FSL\B36402 15:990a8b5664e1 207 *
FSL\B36402 15:990a8b5664e1 208 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 209 uint32_t PhyTimeGetEventTimeout( void )
FSL\B36402 15:990a8b5664e1 210 {
FSL\B36402 15:990a8b5664e1 211 return mPhySeqTimeout;
FSL\B36402 15:990a8b5664e1 212 }
FSL\B36402 15:990a8b5664e1 213
FSL\B36402 15:990a8b5664e1 214 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 215 * \brief Disables the sequence timeout
FSL\B36402 15:990a8b5664e1 216 *
FSL\B36402 15:990a8b5664e1 217 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 218 void PhyTimeDisableEventTimeout
FSL\B36402 15:990a8b5664e1 219 (
FSL\B36402 15:990a8b5664e1 220 void
FSL\B36402 15:990a8b5664e1 221 )
FSL\B36402 15:990a8b5664e1 222 {
FSL\B36402 15:990a8b5664e1 223 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 224
FSL\B36402 15:990a8b5664e1 225 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 226
FSL\B36402 15:990a8b5664e1 227 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4);
FSL\B36402 15:990a8b5664e1 228 phyReg &= ~(cPHY_CTRL4_TC3TMOUT); // disable autosequence stop by TC3 match
FSL\B36402 15:990a8b5664e1 229 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyReg);
FSL\B36402 15:990a8b5664e1 230
FSL\B36402 15:990a8b5664e1 231 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
FSL\B36402 15:990a8b5664e1 232 phyReg &= ~(cPHY_CTRL3_TMR3CMP_EN);// disable TMR3 compare
FSL\B36402 15:990a8b5664e1 233 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyReg);
FSL\B36402 15:990a8b5664e1 234
FSL\B36402 15:990a8b5664e1 235 phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
FSL\B36402 15:990a8b5664e1 236 phyReg &= 0xF0; // do not change IRQ status
FSL\B36402 15:990a8b5664e1 237 phyReg |= cIRQSTS3_TMR3IRQ; // aknowledge TMR3 IRQ
FSL\B36402 15:990a8b5664e1 238 MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
FSL\B36402 15:990a8b5664e1 239
FSL\B36402 15:990a8b5664e1 240 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 241 }
FSL\B36402 15:990a8b5664e1 242
FSL\B36402 15:990a8b5664e1 243 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 244 * \brief Reads the absolute clock from the radio
FSL\B36402 15:990a8b5664e1 245 *
FSL\B36402 15:990a8b5664e1 246 * \param[out] pRetClk pointer to a location where the current clock will be stored
FSL\B36402 15:990a8b5664e1 247 *
FSL\B36402 15:990a8b5664e1 248 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 249 void PhyTimeReadClock
FSL\B36402 15:990a8b5664e1 250 (
FSL\B36402 15:990a8b5664e1 251 uint32_t *pRetClk
FSL\B36402 15:990a8b5664e1 252 )
FSL\B36402 15:990a8b5664e1 253 {
FSL\B36402 15:990a8b5664e1 254 #ifdef PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 255 if(NULL == pRetClk)
FSL\B36402 15:990a8b5664e1 256 {
FSL\B36402 15:990a8b5664e1 257 return;
FSL\B36402 15:990a8b5664e1 258 }
FSL\B36402 15:990a8b5664e1 259 #endif // PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 260
FSL\B36402 15:990a8b5664e1 261 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 262
FSL\B36402 15:990a8b5664e1 263 MCR20Drv_DirectAccessSPIMultiByteRead( (uint8_t) EVENT_TMR_LSB, (uint8_t *) pRetClk, 3);
FSL\B36402 15:990a8b5664e1 264 *(((uint8_t *)pRetClk) + 3) = 0;
FSL\B36402 15:990a8b5664e1 265
FSL\B36402 15:990a8b5664e1 266 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 267
FSL\B36402 15:990a8b5664e1 268 }
FSL\B36402 15:990a8b5664e1 269
FSL\B36402 15:990a8b5664e1 270 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 271 * \brief Initialize the Event Timer
FSL\B36402 15:990a8b5664e1 272 *
FSL\B36402 15:990a8b5664e1 273 * \param[in] pAbsTime pointer to the location where the new time is stored
FSL\B36402 15:990a8b5664e1 274 *
FSL\B36402 15:990a8b5664e1 275 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 276 void PhyTimeInitEventTimer
FSL\B36402 15:990a8b5664e1 277 (
FSL\B36402 15:990a8b5664e1 278 uint32_t *pAbsTime
FSL\B36402 15:990a8b5664e1 279 )
FSL\B36402 15:990a8b5664e1 280 {
FSL\B36402 15:990a8b5664e1 281 uint8_t phyCtrl4Reg;
FSL\B36402 15:990a8b5664e1 282
FSL\B36402 15:990a8b5664e1 283 #ifdef PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 284 if(NULL == pAbsTime)
FSL\B36402 15:990a8b5664e1 285 {
FSL\B36402 15:990a8b5664e1 286 return;
FSL\B36402 15:990a8b5664e1 287 }
FSL\B36402 15:990a8b5664e1 288 #endif // PHY_PARAMETERS_VALIDATION
FSL\B36402 15:990a8b5664e1 289
FSL\B36402 15:990a8b5664e1 290 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 291
FSL\B36402 15:990a8b5664e1 292 phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4);
FSL\B36402 15:990a8b5664e1 293 phyCtrl4Reg |= cPHY_CTRL4_TMRLOAD; // self clearing bit
FSL\B36402 15:990a8b5664e1 294
FSL\B36402 15:990a8b5664e1 295 MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T1CMP_LSB, (uint8_t *) pAbsTime, 3);
FSL\B36402 15:990a8b5664e1 296 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL4, phyCtrl4Reg);
FSL\B36402 15:990a8b5664e1 297
FSL\B36402 15:990a8b5664e1 298 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 299 }
FSL\B36402 15:990a8b5664e1 300
FSL\B36402 15:990a8b5664e1 301 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 302 * \brief Set TMR1 timeout value
FSL\B36402 15:990a8b5664e1 303 *
FSL\B36402 15:990a8b5664e1 304 * \param[in] pWaitTimeout the timeout value
FSL\B36402 15:990a8b5664e1 305 *
FSL\B36402 15:990a8b5664e1 306 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 307 void PhyTimeSetWaitTimeout
FSL\B36402 15:990a8b5664e1 308 (
FSL\B36402 15:990a8b5664e1 309 uint32_t *pWaitTimeout
FSL\B36402 15:990a8b5664e1 310 )
FSL\B36402 15:990a8b5664e1 311 {
FSL\B36402 15:990a8b5664e1 312 uint8_t phyCtrl3Reg, irqSts3Reg;
FSL\B36402 15:990a8b5664e1 313
FSL\B36402 15:990a8b5664e1 314 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 315
FSL\B36402 15:990a8b5664e1 316 phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
FSL\B36402 15:990a8b5664e1 317 phyCtrl3Reg &= ~(cPHY_CTRL3_TMR1CMP_EN);// disable TMR1 compare
FSL\B36402 15:990a8b5664e1 318 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
FSL\B36402 15:990a8b5664e1 319
FSL\B36402 15:990a8b5664e1 320 MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T1CMP_LSB, (uint8_t *) pWaitTimeout, 3);
FSL\B36402 15:990a8b5664e1 321
FSL\B36402 15:990a8b5664e1 322 irqSts3Reg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
FSL\B36402 15:990a8b5664e1 323 irqSts3Reg &= ~(cIRQSTS3_TMR1MSK); // unmask TMR1 interrupt
FSL\B36402 15:990a8b5664e1 324 irqSts3Reg &= 0xF0; // do not change other IRQs status
FSL\B36402 15:990a8b5664e1 325 irqSts3Reg |= (cIRQSTS3_TMR1IRQ); // aknowledge TMR1 IRQ
FSL\B36402 15:990a8b5664e1 326 MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, irqSts3Reg);
FSL\B36402 15:990a8b5664e1 327
FSL\B36402 15:990a8b5664e1 328 phyCtrl3Reg |= cPHY_CTRL3_TMR1CMP_EN; // enable TMR1 compare
FSL\B36402 15:990a8b5664e1 329 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
FSL\B36402 15:990a8b5664e1 330
FSL\B36402 15:990a8b5664e1 331 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 332
FSL\B36402 15:990a8b5664e1 333 }
FSL\B36402 15:990a8b5664e1 334
FSL\B36402 15:990a8b5664e1 335 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 336 * \brief Disable the TMR1 timeout
FSL\B36402 15:990a8b5664e1 337 *
FSL\B36402 15:990a8b5664e1 338 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 339 void PhyTimeDisableWaitTimeout
FSL\B36402 15:990a8b5664e1 340 (
FSL\B36402 15:990a8b5664e1 341 void
FSL\B36402 15:990a8b5664e1 342 )
FSL\B36402 15:990a8b5664e1 343 {
FSL\B36402 15:990a8b5664e1 344 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 345
FSL\B36402 15:990a8b5664e1 346 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 347
FSL\B36402 15:990a8b5664e1 348 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
FSL\B36402 15:990a8b5664e1 349 phyReg &= ~(cPHY_CTRL3_TMR1CMP_EN);// disable TMR1 compare
FSL\B36402 15:990a8b5664e1 350 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyReg);
FSL\B36402 15:990a8b5664e1 351
FSL\B36402 15:990a8b5664e1 352 phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
FSL\B36402 15:990a8b5664e1 353 phyReg &= 0xF0; // do not change IRQ status
FSL\B36402 15:990a8b5664e1 354 phyReg |= cIRQSTS3_TMR1IRQ; // aknowledge TMR1 IRQ
FSL\B36402 15:990a8b5664e1 355 MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
FSL\B36402 15:990a8b5664e1 356
FSL\B36402 15:990a8b5664e1 357 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 358 }
FSL\B36402 15:990a8b5664e1 359
FSL\B36402 15:990a8b5664e1 360 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 361 * \brief Set TMR4 timeout value
FSL\B36402 15:990a8b5664e1 362 *
FSL\B36402 15:990a8b5664e1 363 * \param[in] pWakeUpTime absolute time
FSL\B36402 15:990a8b5664e1 364 *
FSL\B36402 15:990a8b5664e1 365 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 366 void PhyTimeSetWakeUpTime
FSL\B36402 15:990a8b5664e1 367 (
FSL\B36402 15:990a8b5664e1 368 uint32_t *pWakeUpTime
FSL\B36402 15:990a8b5664e1 369 )
FSL\B36402 15:990a8b5664e1 370 {
FSL\B36402 15:990a8b5664e1 371 uint8_t phyCtrl3Reg, irqSts3Reg;
FSL\B36402 15:990a8b5664e1 372
FSL\B36402 15:990a8b5664e1 373 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 374
FSL\B36402 15:990a8b5664e1 375 phyCtrl3Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
FSL\B36402 15:990a8b5664e1 376 // phyCtrl3Reg &= ~(cPHY_CTRL3_TMR4CMP_EN);// disable TMR4 compare
FSL\B36402 15:990a8b5664e1 377 // MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
FSL\B36402 15:990a8b5664e1 378
FSL\B36402 15:990a8b5664e1 379 MCR20Drv_DirectAccessSPIMultiByteWrite( (uint8_t) T4CMP_LSB, (uint8_t *) pWakeUpTime, 3);
FSL\B36402 15:990a8b5664e1 380
FSL\B36402 15:990a8b5664e1 381 irqSts3Reg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
FSL\B36402 15:990a8b5664e1 382 irqSts3Reg &= ~(cIRQSTS3_TMR4MSK); // unmask TMR4 interrupt
FSL\B36402 15:990a8b5664e1 383 irqSts3Reg &= 0xF0; // do not change other IRQs status
FSL\B36402 15:990a8b5664e1 384 irqSts3Reg |= (cIRQSTS3_TMR4IRQ); // aknowledge TMR4 IRQ
FSL\B36402 15:990a8b5664e1 385 MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, irqSts3Reg);
FSL\B36402 15:990a8b5664e1 386
FSL\B36402 15:990a8b5664e1 387 phyCtrl3Reg |= cPHY_CTRL3_TMR4CMP_EN; // enable TMR4 compare
FSL\B36402 15:990a8b5664e1 388 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyCtrl3Reg);
FSL\B36402 15:990a8b5664e1 389
FSL\B36402 15:990a8b5664e1 390 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 391 }
FSL\B36402 15:990a8b5664e1 392
FSL\B36402 15:990a8b5664e1 393 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 394 * \brief Check if TMR4 IRQ occured, and aknowledge it
FSL\B36402 15:990a8b5664e1 395 *
FSL\B36402 15:990a8b5664e1 396 * \return TRUE if TMR4 IRQ occured
FSL\B36402 15:990a8b5664e1 397 *
FSL\B36402 15:990a8b5664e1 398 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 399 bool_t PhyTimeIsWakeUpTimeExpired
FSL\B36402 15:990a8b5664e1 400 (
FSL\B36402 15:990a8b5664e1 401 void
FSL\B36402 15:990a8b5664e1 402 )
FSL\B36402 15:990a8b5664e1 403 {
FSL\B36402 15:990a8b5664e1 404 bool_t wakeUpIrq = FALSE;
FSL\B36402 15:990a8b5664e1 405 uint8_t phyReg;
FSL\B36402 15:990a8b5664e1 406
FSL\B36402 15:990a8b5664e1 407 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 408
FSL\B36402 15:990a8b5664e1 409 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL3);
FSL\B36402 15:990a8b5664e1 410 phyReg &= ~(cPHY_CTRL3_TMR4CMP_EN);// disable TMR4 compare
FSL\B36402 15:990a8b5664e1 411 MCR20Drv_DirectAccessSPIWrite( (uint8_t) PHY_CTRL3, phyReg);
FSL\B36402 15:990a8b5664e1 412
FSL\B36402 15:990a8b5664e1 413 phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
FSL\B36402 15:990a8b5664e1 414
FSL\B36402 15:990a8b5664e1 415 if( (phyReg & cIRQSTS3_TMR4IRQ) == cIRQSTS3_TMR4IRQ )
FSL\B36402 15:990a8b5664e1 416 {
FSL\B36402 15:990a8b5664e1 417 wakeUpIrq = TRUE;
FSL\B36402 15:990a8b5664e1 418 }
FSL\B36402 15:990a8b5664e1 419
FSL\B36402 15:990a8b5664e1 420 phyReg &= ~(cIRQSTS3_TMR4MSK); // unmask TMR4 interrupt
FSL\B36402 15:990a8b5664e1 421 phyReg &= 0xF0; // do not change other IRQs status
FSL\B36402 15:990a8b5664e1 422 phyReg |= (cIRQSTS3_TMR4IRQ); // aknowledge TMR2 IRQ
FSL\B36402 15:990a8b5664e1 423
FSL\B36402 15:990a8b5664e1 424 MCR20Drv_DirectAccessSPIWrite( (uint8_t) IRQSTS3, phyReg);
FSL\B36402 15:990a8b5664e1 425
FSL\B36402 15:990a8b5664e1 426 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 427
FSL\B36402 15:990a8b5664e1 428 return wakeUpIrq;
FSL\B36402 15:990a8b5664e1 429 }
FSL\B36402 15:990a8b5664e1 430
FSL\B36402 15:990a8b5664e1 431
FSL\B36402 15:990a8b5664e1 432 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 433 * \brief PHY Timer Interrupt Service Routine
FSL\B36402 15:990a8b5664e1 434 *
FSL\B36402 15:990a8b5664e1 435 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 436 void PhyTime_ISR(void)
FSL\B36402 15:990a8b5664e1 437 {
FSL\B36402 15:990a8b5664e1 438 if( pNextEvent->callback == PhyTime_OverflowCB )
FSL\B36402 15:990a8b5664e1 439 {
FSL\B36402 15:990a8b5664e1 440 gPhyTimerOverflow++;
FSL\B36402 15:990a8b5664e1 441 }
FSL\B36402 15:990a8b5664e1 442
FSL\B36402 15:990a8b5664e1 443 if( gpfPhyTimeNotify )
FSL\B36402 15:990a8b5664e1 444 {
FSL\B36402 15:990a8b5664e1 445 gpfPhyTimeNotify();
FSL\B36402 15:990a8b5664e1 446 }
FSL\B36402 15:990a8b5664e1 447 else
FSL\B36402 15:990a8b5664e1 448 {
FSL\B36402 15:990a8b5664e1 449 PhyTime_RunCallback();
FSL\B36402 15:990a8b5664e1 450 PhyTime_Maintenance();
FSL\B36402 15:990a8b5664e1 451 }
FSL\B36402 15:990a8b5664e1 452 }
FSL\B36402 15:990a8b5664e1 453
FSL\B36402 15:990a8b5664e1 454 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 455 * \brief Initialize the PHY Timer module
FSL\B36402 15:990a8b5664e1 456 *
FSL\B36402 15:990a8b5664e1 457 * \return phyTimeStatus_t
FSL\B36402 15:990a8b5664e1 458 *
FSL\B36402 15:990a8b5664e1 459 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 460 phyTimeStatus_t PhyTime_TimerInit( void (*cb)(void) )
FSL\B36402 15:990a8b5664e1 461 {
FSL\B36402 15:990a8b5664e1 462 if( gpfPhyTimeNotify )
FSL\B36402 15:990a8b5664e1 463 return gPhyTimeError_c;
FSL\B36402 15:990a8b5664e1 464
FSL\B36402 15:990a8b5664e1 465 gpfPhyTimeNotify = cb;
FSL\B36402 15:990a8b5664e1 466 gPhyTimerOverflow = 0;
cotigac 16:549f2f246ece 467 memset( mPhyTimers, 0, sizeof(mPhyTimers) );
FSL\B36402 15:990a8b5664e1 468
FSL\B36402 15:990a8b5664e1 469 /* Schedule Overflow Calback */
FSL\B36402 15:990a8b5664e1 470 pNextEvent = &mPhyTimers[0];
FSL\B36402 15:990a8b5664e1 471 pNextEvent->callback = PhyTime_OverflowCB;
FSL\B36402 15:990a8b5664e1 472 pNextEvent->timestamp = (gPhyTimerOverflow+1) << gPhyTimeShift_c;
FSL\B36402 15:990a8b5664e1 473 PhyTimeSetWaitTimeout( (uint32_t*)&pNextEvent->timestamp );
FSL\B36402 15:990a8b5664e1 474
FSL\B36402 15:990a8b5664e1 475 return gPhyTimeOk_c;
FSL\B36402 15:990a8b5664e1 476 }
FSL\B36402 15:990a8b5664e1 477
FSL\B36402 15:990a8b5664e1 478 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 479 * \brief Returns a 64bit timestamp value to be used by the MAC Layer
FSL\B36402 15:990a8b5664e1 480 *
FSL\B36402 15:990a8b5664e1 481 * \return phyTimeTimestamp_t PHY timestamp
FSL\B36402 15:990a8b5664e1 482 *
FSL\B36402 15:990a8b5664e1 483 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 484 phyTimeTimestamp_t PhyTime_GetTimestamp(void)
FSL\B36402 15:990a8b5664e1 485 {
FSL\B36402 15:990a8b5664e1 486 phyTimeTimestamp_t time = 0;
FSL\B36402 15:990a8b5664e1 487
FSL\B36402 15:990a8b5664e1 488 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 489 PhyTimeReadClock( (uint32_t*)&time );
FSL\B36402 15:990a8b5664e1 490 time |= (gPhyTimerOverflow << gPhyTimeShift_c);
FSL\B36402 15:990a8b5664e1 491 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 492
FSL\B36402 15:990a8b5664e1 493 return time;
FSL\B36402 15:990a8b5664e1 494 }
FSL\B36402 15:990a8b5664e1 495
FSL\B36402 15:990a8b5664e1 496 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 497 * \brief Schedules an event
FSL\B36402 15:990a8b5664e1 498 *
FSL\B36402 15:990a8b5664e1 499 * \param[in] pEvent event to be scheduled
FSL\B36402 15:990a8b5664e1 500 *
FSL\B36402 15:990a8b5664e1 501 * \return phyTimeTimerId_t the id of the alocated timer
FSL\B36402 15:990a8b5664e1 502 *
FSL\B36402 15:990a8b5664e1 503 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 504 phyTimeTimerId_t PhyTime_ScheduleEvent( phyTimeEvent_t *pEvent )
FSL\B36402 15:990a8b5664e1 505 {
FSL\B36402 15:990a8b5664e1 506 phyTimeTimerId_t tmr;
FSL\B36402 15:990a8b5664e1 507
FSL\B36402 15:990a8b5664e1 508 /* Parameter validation */
FSL\B36402 15:990a8b5664e1 509 if( NULL == pEvent->callback )
FSL\B36402 15:990a8b5664e1 510 {
FSL\B36402 15:990a8b5664e1 511 return gInvalidTimerId_c;
FSL\B36402 15:990a8b5664e1 512 }
FSL\B36402 15:990a8b5664e1 513
FSL\B36402 15:990a8b5664e1 514 /* Search for a free slot (slot 0 is reserved for the Overflow calback) */
FSL\B36402 15:990a8b5664e1 515 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 516 for( tmr=1; tmr<gMaxPhyTimers_c; tmr++ )
FSL\B36402 15:990a8b5664e1 517 {
FSL\B36402 15:990a8b5664e1 518 if( mPhyTimers[tmr].callback == NULL )
FSL\B36402 15:990a8b5664e1 519 {
FSL\B36402 15:990a8b5664e1 520 mPhyTimers[tmr] = *pEvent;
FSL\B36402 15:990a8b5664e1 521 break;
FSL\B36402 15:990a8b5664e1 522 }
FSL\B36402 15:990a8b5664e1 523 }
FSL\B36402 15:990a8b5664e1 524 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 525
FSL\B36402 15:990a8b5664e1 526 if( tmr >= gMaxPhyTimers_c )
FSL\B36402 15:990a8b5664e1 527 return gInvalidTimerId_c;
FSL\B36402 15:990a8b5664e1 528
FSL\B36402 15:990a8b5664e1 529 /* Program the next event */
FSL\B36402 15:990a8b5664e1 530 if((NULL == pNextEvent) ||
FSL\B36402 15:990a8b5664e1 531 (NULL != pNextEvent && mPhyTimers[tmr].timestamp < pNextEvent->timestamp))
FSL\B36402 15:990a8b5664e1 532 {
FSL\B36402 15:990a8b5664e1 533 PhyTime_Maintenance();
FSL\B36402 15:990a8b5664e1 534 }
FSL\B36402 15:990a8b5664e1 535
FSL\B36402 15:990a8b5664e1 536 return tmr;
FSL\B36402 15:990a8b5664e1 537 }
FSL\B36402 15:990a8b5664e1 538
FSL\B36402 15:990a8b5664e1 539 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 540 * \brief Cancel an event
FSL\B36402 15:990a8b5664e1 541 *
FSL\B36402 15:990a8b5664e1 542 * \param[in] timerId the Id of the timer
FSL\B36402 15:990a8b5664e1 543 *
FSL\B36402 15:990a8b5664e1 544 * \return phyTimeStatus_t
FSL\B36402 15:990a8b5664e1 545 *
FSL\B36402 15:990a8b5664e1 546 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 547 phyTimeStatus_t PhyTime_CancelEvent( phyTimeTimerId_t timerId )
FSL\B36402 15:990a8b5664e1 548 {
FSL\B36402 15:990a8b5664e1 549 if( (timerId == 0) || (timerId >= gMaxPhyTimers_c) || (NULL == mPhyTimers[timerId].callback) )
FSL\B36402 15:990a8b5664e1 550 {
FSL\B36402 15:990a8b5664e1 551 return gPhyTimeNotFound_c;
FSL\B36402 15:990a8b5664e1 552 }
FSL\B36402 15:990a8b5664e1 553
FSL\B36402 15:990a8b5664e1 554 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 555 if( pNextEvent == &mPhyTimers[timerId] )
FSL\B36402 15:990a8b5664e1 556 pNextEvent = NULL;
FSL\B36402 15:990a8b5664e1 557
FSL\B36402 15:990a8b5664e1 558 mPhyTimers[timerId].callback = NULL;
FSL\B36402 15:990a8b5664e1 559 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 560
FSL\B36402 15:990a8b5664e1 561 return gPhyTimeOk_c;
FSL\B36402 15:990a8b5664e1 562 }
FSL\B36402 15:990a8b5664e1 563
FSL\B36402 15:990a8b5664e1 564 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 565 * \brief Cancel all event with the specified paameter
FSL\B36402 15:990a8b5664e1 566 *
FSL\B36402 15:990a8b5664e1 567 * \param[in] param event parameter
FSL\B36402 15:990a8b5664e1 568 *
FSL\B36402 15:990a8b5664e1 569 * \return phyTimeStatus_t
FSL\B36402 15:990a8b5664e1 570 *
FSL\B36402 15:990a8b5664e1 571 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 572 phyTimeStatus_t PhyTime_CancelEventsWithParam ( uint32_t param )
FSL\B36402 15:990a8b5664e1 573 {
FSL\B36402 15:990a8b5664e1 574 uint32_t i;
FSL\B36402 15:990a8b5664e1 575 phyTimeStatus_t status = gPhyTimeNotFound_c;
FSL\B36402 15:990a8b5664e1 576
FSL\B36402 15:990a8b5664e1 577 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 578 for( i=1; i<gMaxPhyTimers_c; i++ )
FSL\B36402 15:990a8b5664e1 579 {
FSL\B36402 15:990a8b5664e1 580 if( mPhyTimers[i].callback && (param == mPhyTimers[i].parameter) )
FSL\B36402 15:990a8b5664e1 581 {
FSL\B36402 15:990a8b5664e1 582 status = gPhyTimeOk_c;
FSL\B36402 15:990a8b5664e1 583 mPhyTimers[i].callback = NULL;
FSL\B36402 15:990a8b5664e1 584 if( pNextEvent == &mPhyTimers[i] )
FSL\B36402 15:990a8b5664e1 585 pNextEvent = NULL;
FSL\B36402 15:990a8b5664e1 586 }
FSL\B36402 15:990a8b5664e1 587 }
FSL\B36402 15:990a8b5664e1 588 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 589
FSL\B36402 15:990a8b5664e1 590 return status;
FSL\B36402 15:990a8b5664e1 591 }
FSL\B36402 15:990a8b5664e1 592
FSL\B36402 15:990a8b5664e1 593 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 594 * \brief Run the callback for the recently expired event
FSL\B36402 15:990a8b5664e1 595 *
FSL\B36402 15:990a8b5664e1 596 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 597 void PhyTime_RunCallback( void )
FSL\B36402 15:990a8b5664e1 598 {
FSL\B36402 15:990a8b5664e1 599 uint32_t param;
FSL\B36402 15:990a8b5664e1 600 phyTimeCallback_t cb;
FSL\B36402 15:990a8b5664e1 601
FSL\B36402 15:990a8b5664e1 602 if( pNextEvent )
FSL\B36402 15:990a8b5664e1 603 {
FSL\B36402 15:990a8b5664e1 604 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 605
FSL\B36402 15:990a8b5664e1 606 param = pNextEvent->parameter;
FSL\B36402 15:990a8b5664e1 607 cb = pNextEvent->callback;
FSL\B36402 15:990a8b5664e1 608 pNextEvent->callback = NULL;
FSL\B36402 15:990a8b5664e1 609 pNextEvent = NULL;
FSL\B36402 15:990a8b5664e1 610
FSL\B36402 15:990a8b5664e1 611 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 612
FSL\B36402 15:990a8b5664e1 613 cb(param);
FSL\B36402 15:990a8b5664e1 614 }
FSL\B36402 15:990a8b5664e1 615 }
FSL\B36402 15:990a8b5664e1 616
FSL\B36402 15:990a8b5664e1 617 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 618 * \brief Expire events too close to be scheduled.
FSL\B36402 15:990a8b5664e1 619 * Program the next event
FSL\B36402 15:990a8b5664e1 620 *
FSL\B36402 15:990a8b5664e1 621 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 622 void PhyTime_Maintenance( void )
FSL\B36402 15:990a8b5664e1 623 {
FSL\B36402 15:990a8b5664e1 624 phyTimeTimestamp_t currentTime;
FSL\B36402 15:990a8b5664e1 625 phyTimeEvent_t *pEv;
FSL\B36402 15:990a8b5664e1 626
FSL\B36402 15:990a8b5664e1 627 PhyTimeDisableWaitTimeout();
FSL\B36402 15:990a8b5664e1 628
FSL\B36402 15:990a8b5664e1 629 while(1)
FSL\B36402 15:990a8b5664e1 630 {
FSL\B36402 15:990a8b5664e1 631 arm_enter_critical();
FSL\B36402 15:990a8b5664e1 632
FSL\B36402 15:990a8b5664e1 633 pEv = PhyTime_GetNextEvent();
FSL\B36402 15:990a8b5664e1 634 currentTime = PhyTime_GetTimestamp();
FSL\B36402 15:990a8b5664e1 635
FSL\B36402 15:990a8b5664e1 636 /* Program next event if exists */
FSL\B36402 15:990a8b5664e1 637 if( pEv )
FSL\B36402 15:990a8b5664e1 638 {
FSL\B36402 15:990a8b5664e1 639 pNextEvent = pEv;
FSL\B36402 15:990a8b5664e1 640
FSL\B36402 15:990a8b5664e1 641 if( pEv->timestamp > (currentTime + gPhyTimeMinSetupTime_c) )
FSL\B36402 15:990a8b5664e1 642 {
FSL\B36402 15:990a8b5664e1 643 PhyTimeSetWaitTimeout( (uint32_t*)&pEv->timestamp );
FSL\B36402 15:990a8b5664e1 644 pEv = NULL;
FSL\B36402 15:990a8b5664e1 645 }
FSL\B36402 15:990a8b5664e1 646 }
FSL\B36402 15:990a8b5664e1 647
FSL\B36402 15:990a8b5664e1 648 arm_exit_critical();
FSL\B36402 15:990a8b5664e1 649
FSL\B36402 15:990a8b5664e1 650 if( !pEv )
FSL\B36402 15:990a8b5664e1 651 break;
FSL\B36402 15:990a8b5664e1 652
FSL\B36402 15:990a8b5664e1 653 PhyTime_RunCallback();
FSL\B36402 15:990a8b5664e1 654 }
FSL\B36402 15:990a8b5664e1 655
FSL\B36402 15:990a8b5664e1 656 }
FSL\B36402 15:990a8b5664e1 657
FSL\B36402 15:990a8b5664e1 658
FSL\B36402 15:990a8b5664e1 659 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 660 * \brief Timer Overflow callback
FSL\B36402 15:990a8b5664e1 661 *
FSL\B36402 15:990a8b5664e1 662 * \param[in] param
FSL\B36402 15:990a8b5664e1 663 *
FSL\B36402 15:990a8b5664e1 664 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 665 static void PhyTime_OverflowCB( uint32_t param )
FSL\B36402 15:990a8b5664e1 666 {
FSL\B36402 15:990a8b5664e1 667 (void)param;
FSL\B36402 15:990a8b5664e1 668
FSL\B36402 15:990a8b5664e1 669 /* Reprogram the next overflow callback */
FSL\B36402 15:990a8b5664e1 670 mPhyTimers[0].callback = PhyTime_OverflowCB;
FSL\B36402 15:990a8b5664e1 671 mPhyTimers[0].timestamp = (gPhyTimerOverflow+1) << 24;
FSL\B36402 15:990a8b5664e1 672 }
FSL\B36402 15:990a8b5664e1 673
FSL\B36402 15:990a8b5664e1 674 /*! *********************************************************************************
FSL\B36402 15:990a8b5664e1 675 * \brief Search for the next event to be scheduled
FSL\B36402 15:990a8b5664e1 676 *
FSL\B36402 15:990a8b5664e1 677 * \return phyTimeEvent_t pointer to the next event to be scheduled
FSL\B36402 15:990a8b5664e1 678 *
FSL\B36402 15:990a8b5664e1 679 ********************************************************************************** */
FSL\B36402 15:990a8b5664e1 680 static phyTimeEvent_t* PhyTime_GetNextEvent( void )
FSL\B36402 15:990a8b5664e1 681 {
FSL\B36402 15:990a8b5664e1 682 phyTimeEvent_t *pEv = NULL;
FSL\B36402 15:990a8b5664e1 683 uint32_t i;
FSL\B36402 15:990a8b5664e1 684
FSL\B36402 15:990a8b5664e1 685 /* Search for the next event to be serviced */
FSL\B36402 15:990a8b5664e1 686 for( i=0; i<gMaxPhyTimers_c; i++ )
FSL\B36402 15:990a8b5664e1 687 {
FSL\B36402 15:990a8b5664e1 688 if( NULL != mPhyTimers[i].callback )
FSL\B36402 15:990a8b5664e1 689 {
FSL\B36402 15:990a8b5664e1 690 if( NULL == pEv )
FSL\B36402 15:990a8b5664e1 691 {
FSL\B36402 15:990a8b5664e1 692 pEv = &mPhyTimers[i];
FSL\B36402 15:990a8b5664e1 693 }
FSL\B36402 15:990a8b5664e1 694 /* Check which event expires first */
FSL\B36402 15:990a8b5664e1 695 else if( mPhyTimers[i].timestamp < pEv->timestamp )
FSL\B36402 15:990a8b5664e1 696 {
FSL\B36402 15:990a8b5664e1 697 pEv = &mPhyTimers[i];
FSL\B36402 15:990a8b5664e1 698 }
FSL\B36402 15:990a8b5664e1 699 }
FSL\B36402 15:990a8b5664e1 700 }
FSL\B36402 15:990a8b5664e1 701
FSL\B36402 15:990a8b5664e1 702 return pEv;
FSL\B36402 15:990a8b5664e1 703 }