NXP / Mbed 2 deprecated mcr20_wireless_uart

The MCR20A Wireless UART application functions as an wireless UART bridge between two (one-to-one) or several (one to many) boards. The application can be used with both a TERM, or with software that is capable of opening a serial port and writing to or reading from it. The characters sent or received are not necessarily ASCII printable characters.

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

RF_Drivers_Atmel/driverAtmelRFInterface_c.txt@16:549f2f246ece, 2015-03-15 (annotated)

Committer:
cotigac
Date:
Sun Mar 15 06:08:30 2015 +0000
Revision:
16:549f2f246ece
Parent:
RF_Drivers_Atmel/driverAtmelRFInterface.c@13:4fa8e504061f 
Minor updates to compile also online

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 2:3e7685cfb2a7 1 /*
sam_grove 2:3e7685cfb2a7 2 * driverAtmelRFInterface.c
sam_grove 2:3e7685cfb2a7 3 *
sam_grove 2:3e7685cfb2a7 4 * Created on: 14 July 2014
sam_grove 2:3e7685cfb2a7 5 * Author: mBed Team
sam_grove 2:3e7685cfb2a7 6 */
sam_grove 2:3e7685cfb2a7 7
sam_grove 2:3e7685cfb2a7 8 #include "arm_hal_interrupt.h"
sam_grove 2:3e7685cfb2a7 9 #include "arm_hal_phy.h"
sam_grove 2:3e7685cfb2a7 10 #include "driverRFPhy.h"
sam_grove 2:3e7685cfb2a7 11 #include "driverAtmelRFInterface.h"
sam_grove 2:3e7685cfb2a7 12 #include "low_level_RF.h"
sam_grove 2:3e7685cfb2a7 13
sam_grove 2:3e7685cfb2a7 14 #include <stdio.h>
sam_grove 2:3e7685cfb2a7 15
sam_grove 2:3e7685cfb2a7 16 void (*app_rf_settings_cb)(void) = 0;
sam_grove 2:3e7685cfb2a7 17 static uint8_t rf_part_num = 0;
sam_grove 2:3e7685cfb2a7 18 static uint8_t rf_irq_port = 0;
sam_grove 2:3e7685cfb2a7 19 static uint8_t rf_irq_pin = 0;
sam_grove 2:3e7685cfb2a7 20 static uint8_t rf_slp_tr_port = 0;
sam_grove 2:3e7685cfb2a7 21 static uint8_t rf_slp_tr_pin = 0;
sam_grove 2:3e7685cfb2a7 22 static uint8_t rf_reset_port = 0;
sam_grove 2:3e7685cfb2a7 23 static uint8_t rf_reset_pin = 0;
sam_grove 2:3e7685cfb2a7 24 static uint8_t rf_spi_if = 0;
sam_grove 2:3e7685cfb2a7 25 static uint8_t rf_spi_cs = 0;
sam_grove 2:3e7685cfb2a7 26 static uint8_t rf_spi_cs_port = 0;
sam_grove 2:3e7685cfb2a7 27 static uint8_t rf_spi_cs_pin = 0;
sam_grove 2:3e7685cfb2a7 28 static uint8_t rf_spi_port = 0;
sam_grove 2:3e7685cfb2a7 29 static uint8_t rf_spi_mosi_pin = 0;
sam_grove 2:3e7685cfb2a7 30 static uint8_t rf_spi_miso_pin = 0;
sam_grove 2:3e7685cfb2a7 31 static uint8_t rf_spi_sclk_pin = 0;
sam_grove 2:3e7685cfb2a7 32 static uint8_t rf_rx_lqi;
sam_grove 2:3e7685cfb2a7 33 static int8_t rf_rx_rssi;
sam_grove 2:3e7685cfb2a7 34 /*TODO: RSSI Base value setting*/
sam_grove 2:3e7685cfb2a7 35 static int8_t rf_rssi_base_val = -91;
sam_grove 2:3e7685cfb2a7 36 static uint8_t phy_timers_enabled = 0;
sam_grove 2:3e7685cfb2a7 37
sam_grove 2:3e7685cfb2a7 38 /*
sam_grove 2:3e7685cfb2a7 39 * \brief Delay function for RF interface.
sam_grove 2:3e7685cfb2a7 40 *
sam_grove 2:3e7685cfb2a7 41 * \param ticks Number of delay ticks
sam_grove 2:3e7685cfb2a7 42 *
sam_grove 2:3e7685cfb2a7 43 * \return none
sam_grove 2:3e7685cfb2a7 44 */
sam_grove 2:3e7685cfb2a7 45 void rf_if_delay_function(uint16_t ticks)
sam_grove 2:3e7685cfb2a7 46 {
sam_grove 2:3e7685cfb2a7 47 while(ticks--);
sam_grove 2:3e7685cfb2a7 48 }
sam_grove 2:3e7685cfb2a7 49
sam_grove 2:3e7685cfb2a7 50 /*
sam_grove 2:3e7685cfb2a7 51 * \brief Function initialises the RF timer for ACK wait and calibration.
sam_grove 2:3e7685cfb2a7 52 *
sam_grove 2:3e7685cfb2a7 53 * \param none
sam_grove 2:3e7685cfb2a7 54 *
sam_grove 2:3e7685cfb2a7 55 * \return none
sam_grove 2:3e7685cfb2a7 56 */
sam_grove 2:3e7685cfb2a7 57 void rf_if_timer_init(void)
sam_grove 2:3e7685cfb2a7 58 {
sam_grove 2:3e7685cfb2a7 59 /* TODO */
sam_grove 2:3e7685cfb2a7 60 }
sam_grove 2:3e7685cfb2a7 61
sam_grove 2:3e7685cfb2a7 62 /*
sam_grove 2:3e7685cfb2a7 63 * \brief Function starts the ACK wait timeout.
sam_grove 2:3e7685cfb2a7 64 *
sam_grove 2:3e7685cfb2a7 65 * \param slots Given slots, resolution 50us
sam_grove 2:3e7685cfb2a7 66 *
sam_grove 2:3e7685cfb2a7 67 * \return none
sam_grove 2:3e7685cfb2a7 68 */
sam_grove 2:3e7685cfb2a7 69 void rf_if_ack_wait_timer_start(uint16_t slots)
sam_grove 2:3e7685cfb2a7 70 {
sam_grove 2:3e7685cfb2a7 71 /* TODO */
sam_grove 2:3e7685cfb2a7 72 }
sam_grove 2:3e7685cfb2a7 73
sam_grove 2:3e7685cfb2a7 74 /*
sam_grove 2:3e7685cfb2a7 75 * \brief Function starts the calibration interval.
sam_grove 2:3e7685cfb2a7 76 *
sam_grove 2:3e7685cfb2a7 77 * \param slots Given slots, resolution 50us
sam_grove 2:3e7685cfb2a7 78 *
sam_grove 2:3e7685cfb2a7 79 * \return none
sam_grove 2:3e7685cfb2a7 80 */
sam_grove 2:3e7685cfb2a7 81 void rf_if_calibration_timer_start(uint32_t slots)
sam_grove 2:3e7685cfb2a7 82 {
sam_grove 2:3e7685cfb2a7 83 /* TODO */
sam_grove 2:3e7685cfb2a7 84 }
sam_grove 2:3e7685cfb2a7 85
sam_grove 2:3e7685cfb2a7 86 /*
sam_grove 2:3e7685cfb2a7 87 * \brief Function stops the ACK wait timeout.
sam_grove 2:3e7685cfb2a7 88 *
sam_grove 2:3e7685cfb2a7 89 * \param none
sam_grove 2:3e7685cfb2a7 90 *
sam_grove 2:3e7685cfb2a7 91 * \return none
sam_grove 2:3e7685cfb2a7 92 */
sam_grove 2:3e7685cfb2a7 93 void rf_if_ack_wait_timer_stop(void)
sam_grove 2:3e7685cfb2a7 94 {
sam_grove 2:3e7685cfb2a7 95 phy_timers_enabled &= ~PHY_ACK_WAIT_TIMER;
sam_grove 2:3e7685cfb2a7 96 }
sam_grove 2:3e7685cfb2a7 97
sam_grove 2:3e7685cfb2a7 98 /*
sam_grove 2:3e7685cfb2a7 99 * \brief Function is a call back for ACK wait timeout.
sam_grove 2:3e7685cfb2a7 100 *
sam_grove 2:3e7685cfb2a7 101 * \param none
sam_grove 2:3e7685cfb2a7 102 *
sam_grove 2:3e7685cfb2a7 103 * \return none
sam_grove 2:3e7685cfb2a7 104 */
sam_grove 2:3e7685cfb2a7 105 void rf_if_ack_wait_timer_interrupt(void)
sam_grove 2:3e7685cfb2a7 106 {
sam_grove 2:3e7685cfb2a7 107 /* TODO */
sam_grove 2:3e7685cfb2a7 108 }
sam_grove 2:3e7685cfb2a7 109
sam_grove 2:3e7685cfb2a7 110 /*
sam_grove 2:3e7685cfb2a7 111 * \brief Function is a call back for calibration interval timer.
sam_grove 2:3e7685cfb2a7 112 *
sam_grove 2:3e7685cfb2a7 113 * \param none
sam_grove 2:3e7685cfb2a7 114 *
sam_grove 2:3e7685cfb2a7 115 * \return none
sam_grove 2:3e7685cfb2a7 116 */
sam_grove 2:3e7685cfb2a7 117 void rf_if_calibration_timer_interrupt(void)
sam_grove 2:3e7685cfb2a7 118 {
sam_grove 2:3e7685cfb2a7 119 /* TODO */
sam_grove 2:3e7685cfb2a7 120 }
sam_grove 2:3e7685cfb2a7 121
sam_grove 2:3e7685cfb2a7 122 /*
sam_grove 2:3e7685cfb2a7 123 * \brief Function sets SLP_TR pin high in RF interface.
sam_grove 2:3e7685cfb2a7 124 *
sam_grove 2:3e7685cfb2a7 125 * \param none
sam_grove 2:3e7685cfb2a7 126 *
sam_grove 2:3e7685cfb2a7 127 * \return none
sam_grove 2:3e7685cfb2a7 128 */
sam_grove 2:3e7685cfb2a7 129 void rf_if_slp_tr_pin_high(void)
sam_grove 2:3e7685cfb2a7 130 {
sam_grove 2:3e7685cfb2a7 131 RF_SLP_TR_Set(1);
sam_grove 2:3e7685cfb2a7 132 }
sam_grove 2:3e7685cfb2a7 133
sam_grove 2:3e7685cfb2a7 134 /*
sam_grove 2:3e7685cfb2a7 135 * \brief Function sets SLP_TR pin low in RF interface.
sam_grove 2:3e7685cfb2a7 136 *
sam_grove 2:3e7685cfb2a7 137 * \param none
sam_grove 2:3e7685cfb2a7 138 *
sam_grove 2:3e7685cfb2a7 139 * \return none
sam_grove 2:3e7685cfb2a7 140 */
sam_grove 2:3e7685cfb2a7 141 void rf_if_slp_tr_pin_low(void)
sam_grove 2:3e7685cfb2a7 142 {
sam_grove 2:3e7685cfb2a7 143 RF_SLP_TR_Set(0);
sam_grove 2:3e7685cfb2a7 144 }
sam_grove 2:3e7685cfb2a7 145
sam_grove 2:3e7685cfb2a7 146 /*
sam_grove 2:3e7685cfb2a7 147 * \brief Function returns peripheral ID for SPI interface.
sam_grove 2:3e7685cfb2a7 148 *
sam_grove 2:3e7685cfb2a7 149 * \param none
sam_grove 2:3e7685cfb2a7 150 *
sam_grove 2:3e7685cfb2a7 151 * \return peripheral ID
sam_grove 2:3e7685cfb2a7 152 */
sam_grove 2:3e7685cfb2a7 153 uint8_t rf_if_get_rf_spi_periph(uint8_t spi_interface)
sam_grove 2:3e7685cfb2a7 154 {
sam_grove 2:3e7685cfb2a7 155 uint8_t ret_val = 19 + spi_interface;
sam_grove 2:3e7685cfb2a7 156 return ret_val;
sam_grove 2:3e7685cfb2a7 157 }
sam_grove 2:3e7685cfb2a7 158
sam_grove 2:3e7685cfb2a7 159 /*
sam_grove 2:3e7685cfb2a7 160 * \brief Function returns interrupt number for I/O port.
sam_grove 2:3e7685cfb2a7 161 *
sam_grove 2:3e7685cfb2a7 162 * \param none
sam_grove 2:3e7685cfb2a7 163 *
sam_grove 2:3e7685cfb2a7 164 * \return interrupt number
sam_grove 2:3e7685cfb2a7 165 */
sam_grove 2:3e7685cfb2a7 166 uint8_t rf_if_get_rf_irq_number(uint8_t port)
sam_grove 2:3e7685cfb2a7 167 {
sam_grove 2:3e7685cfb2a7 168 /* not needed in mBed */
sam_grove 2:3e7685cfb2a7 169 }
sam_grove 2:3e7685cfb2a7 170
sam_grove 2:3e7685cfb2a7 171
sam_grove 2:3e7685cfb2a7 172 /*
sam_grove 2:3e7685cfb2a7 173 * \brief Function enables RF irq pin interrupts in RF interface.
sam_grove 2:3e7685cfb2a7 174 *
sam_grove 2:3e7685cfb2a7 175 * \param none
sam_grove 2:3e7685cfb2a7 176 *
sam_grove 2:3e7685cfb2a7 177 * \return none
sam_grove 2:3e7685cfb2a7 178 */
sam_grove 2:3e7685cfb2a7 179 void rf_if_enable_irq(void)
sam_grove 2:3e7685cfb2a7 180 {
sam_grove 2:3e7685cfb2a7 181 /* not needed in mBed */
sam_grove 2:3e7685cfb2a7 182 }
sam_grove 2:3e7685cfb2a7 183
sam_grove 2:3e7685cfb2a7 184
sam_grove 2:3e7685cfb2a7 185 /*
sam_grove 2:3e7685cfb2a7 186 * \brief Function initialises RF interrupt pin in RF interface.
sam_grove 2:3e7685cfb2a7 187 *
sam_grove 2:3e7685cfb2a7 188 * \param none
sam_grove 2:3e7685cfb2a7 189 *
sam_grove 2:3e7685cfb2a7 190 * \return none
sam_grove 2:3e7685cfb2a7 191 */
sam_grove 2:3e7685cfb2a7 192 void rf_if_init_irq_delete(void)
sam_grove 2:3e7685cfb2a7 193 {
sam_grove 2:3e7685cfb2a7 194 RF_IRQ_Init();
sam_grove 2:3e7685cfb2a7 195 }
sam_grove 2:3e7685cfb2a7 196
sam_grove 2:3e7685cfb2a7 197 /*
sam_grove 2:3e7685cfb2a7 198 * \brief Function initialises the SPI interface for RF.
sam_grove 2:3e7685cfb2a7 199 *
sam_grove 2:3e7685cfb2a7 200 * \param none
sam_grove 2:3e7685cfb2a7 201 *
sam_grove 2:3e7685cfb2a7 202 * \return none
sam_grove 2:3e7685cfb2a7 203 */
sam_grove 2:3e7685cfb2a7 204 void rf_if_spi_init(void)
sam_grove 2:3e7685cfb2a7 205 {
sam_grove 2:3e7685cfb2a7 206 /* not needed in mBed */
sam_grove 2:3e7685cfb2a7 207 }
sam_grove 2:3e7685cfb2a7 208
sam_grove 2:3e7685cfb2a7 209 /*
sam_grove 2:3e7685cfb2a7 210 * \brief Function initialises SLP_TR pin in RF interface.
sam_grove 2:3e7685cfb2a7 211 *
sam_grove 2:3e7685cfb2a7 212 * \param none
sam_grove 2:3e7685cfb2a7 213 *
sam_grove 2:3e7685cfb2a7 214 * \return none
sam_grove 2:3e7685cfb2a7 215 */
sam_grove 2:3e7685cfb2a7 216 void rf_if_init_slp_tr_pin(void)
sam_grove 2:3e7685cfb2a7 217 {
sam_grove 2:3e7685cfb2a7 218 /*Chip select*/
sam_grove 2:3e7685cfb2a7 219 //RF_SLP_TR_Set(0); // moved to reset function
sam_grove 2:3e7685cfb2a7 220 }
sam_grove 2:3e7685cfb2a7 221
sam_grove 2:3e7685cfb2a7 222 /*
sam_grove 2:3e7685cfb2a7 223 * \brief Function returns peripheral ID for I/O port.
sam_grove 2:3e7685cfb2a7 224 *
sam_grove 2:3e7685cfb2a7 225 * \param none
sam_grove 2:3e7685cfb2a7 226 *
sam_grove 2:3e7685cfb2a7 227 * \return peripheral ID
sam_grove 2:3e7685cfb2a7 228 */
sam_grove 2:3e7685cfb2a7 229 uint8_t rf_if_get_port_peripheral_id(uint8_t port)
sam_grove 2:3e7685cfb2a7 230 {
sam_grove 2:3e7685cfb2a7 231 uint8_t ret_val = 9 + port;
sam_grove 2:3e7685cfb2a7 232 return ret_val;
sam_grove 2:3e7685cfb2a7 233 }
sam_grove 2:3e7685cfb2a7 234
sam_grove 2:3e7685cfb2a7 235 /*
sam_grove 2:3e7685cfb2a7 236 * \brief Function initialises I/O pins for RF interface.
sam_grove 2:3e7685cfb2a7 237 *
sam_grove 2:3e7685cfb2a7 238 * \param none
sam_grove 2:3e7685cfb2a7 239 *
sam_grove 2:3e7685cfb2a7 240 * \return peripheral ID
sam_grove 2:3e7685cfb2a7 241 */
sam_grove 2:3e7685cfb2a7 242 void rf_if_init_spi_pins(void)
sam_grove 2:3e7685cfb2a7 243 {
sam_grove 2:3e7685cfb2a7 244 /* not needed in mBed */
sam_grove 2:3e7685cfb2a7 245 }
sam_grove 2:3e7685cfb2a7 246
sam_grove 2:3e7685cfb2a7 247 /*
sam_grove 2:3e7685cfb2a7 248 * \brief Function reads data from the given RF SRAM address.
sam_grove 2:3e7685cfb2a7 249 *
sam_grove 2:3e7685cfb2a7 250 * \param ptr Read pointer
sam_grove 2:3e7685cfb2a7 251 * \param sram_address Read address in SRAM
sam_grove 2:3e7685cfb2a7 252 * \param len Length of the read
sam_grove 2:3e7685cfb2a7 253 *
sam_grove 2:3e7685cfb2a7 254 * \return none
sam_grove 2:3e7685cfb2a7 255 */
sam_grove 2:3e7685cfb2a7 256 void rf_if_read_payload(uint8_t *ptr, uint8_t sram_address, uint8_t len)
sam_grove 2:3e7685cfb2a7 257 {
sam_grove 2:3e7685cfb2a7 258 uint8_t i;
sam_grove 2:3e7685cfb2a7 259
sam_grove 2:3e7685cfb2a7 260 RF_CS_Set(0);
sam_grove 2:3e7685cfb2a7 261 spi_exchange(0x20);
sam_grove 2:3e7685cfb2a7 262 spi_exchange(sram_address);
sam_grove 2:3e7685cfb2a7 263 for(i=0; i<len; i++)
sam_grove 2:3e7685cfb2a7 264 *ptr++ = spi_exchange(0);
sam_grove 2:3e7685cfb2a7 265
sam_grove 2:3e7685cfb2a7 266 /*Read LQI and RSSI in variable*/
sam_grove 2:3e7685cfb2a7 267 rf_rx_lqi = spi_exchange(0);
sam_grove 2:3e7685cfb2a7 268 rf_rx_rssi = (rf_rssi_base_val + spi_exchange(0));
sam_grove 2:3e7685cfb2a7 269 RF_CS_Set(1);
sam_grove 2:3e7685cfb2a7 270 }
sam_grove 2:3e7685cfb2a7 271
sam_grove 2:3e7685cfb2a7 272 /*
sam_grove 2:3e7685cfb2a7 273 * \brief Function polls while the SPI chip select is active.
sam_grove 2:3e7685cfb2a7 274 *
sam_grove 2:3e7685cfb2a7 275 * \param none
sam_grove 2:3e7685cfb2a7 276 *
sam_grove 2:3e7685cfb2a7 277 * \return none
sam_grove 2:3e7685cfb2a7 278 */
sam_grove 2:3e7685cfb2a7 279 void rf_if_spi_poll_chip_select(void)
sam_grove 2:3e7685cfb2a7 280 {
sam_grove 2:3e7685cfb2a7 281 RF_CS_while_active();
sam_grove 2:3e7685cfb2a7 282 }
sam_grove 2:3e7685cfb2a7 283
sam_grove 2:3e7685cfb2a7 284 void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask)
sam_grove 2:3e7685cfb2a7 285 {
sam_grove 2:3e7685cfb2a7 286 uint8_t reg = rf_if_read_register(addr);
sam_grove 2:3e7685cfb2a7 287 reg &= ~bit_mask;
sam_grove 2:3e7685cfb2a7 288 reg |= bit;
sam_grove 2:3e7685cfb2a7 289 rf_if_write_register(addr, reg);
sam_grove 2:3e7685cfb2a7 290 }
sam_grove 2:3e7685cfb2a7 291
sam_grove 2:3e7685cfb2a7 292 /*
sam_grove 2:3e7685cfb2a7 293 * \brief Function clears bit(s) in given RF register.
sam_grove 2:3e7685cfb2a7 294 *
sam_grove 2:3e7685cfb2a7 295 * \param addr Address of the register to clear
sam_grove 2:3e7685cfb2a7 296 * \param bit Bit(s) to clear
sam_grove 2:3e7685cfb2a7 297 *
sam_grove 2:3e7685cfb2a7 298 * \return none
sam_grove 2:3e7685cfb2a7 299 */
sam_grove 2:3e7685cfb2a7 300 void rf_if_clear_bit(uint8_t addr, uint8_t bit)
sam_grove 2:3e7685cfb2a7 301 {
sam_grove 2:3e7685cfb2a7 302 uint8_t reg = rf_if_read_register(addr);
sam_grove 2:3e7685cfb2a7 303 reg &= ~bit;
sam_grove 2:3e7685cfb2a7 304 rf_if_write_register(addr, reg);
sam_grove 2:3e7685cfb2a7 305 }
sam_grove 2:3e7685cfb2a7 306
sam_grove 2:3e7685cfb2a7 307 /*
sam_grove 2:3e7685cfb2a7 308 * \brief Function writes register in RF.
sam_grove 2:3e7685cfb2a7 309 *
sam_grove 2:3e7685cfb2a7 310 * \param addr Address on the RF
sam_grove 2:3e7685cfb2a7 311 * \param data Written data
sam_grove 2:3e7685cfb2a7 312 *
sam_grove 2:3e7685cfb2a7 313 * \return none
sam_grove 2:3e7685cfb2a7 314 */
sam_grove 2:3e7685cfb2a7 315 void rf_if_write_register(uint8_t addr, uint8_t data)
sam_grove 2:3e7685cfb2a7 316 {
sam_grove 2:3e7685cfb2a7 317 uint8_t cmd = 0xC0;
sam_grove 2:3e7685cfb2a7 318 arm_enter_critical();
sam_grove 2:3e7685cfb2a7 319
sam_grove 2:3e7685cfb2a7 320 spi_write(cmd | addr, data);
sam_grove 2:3e7685cfb2a7 321
sam_grove 2:3e7685cfb2a7 322 arm_exit_critical();
sam_grove 2:3e7685cfb2a7 323 }
sam_grove 2:3e7685cfb2a7 324
sam_grove 2:3e7685cfb2a7 325 /*
sam_grove 2:3e7685cfb2a7 326 * \brief Function reads RF register.
sam_grove 2:3e7685cfb2a7 327 *
sam_grove 2:3e7685cfb2a7 328 * \param addr Address on the RF
sam_grove 2:3e7685cfb2a7 329 *
sam_grove 2:3e7685cfb2a7 330 * \return Read data
sam_grove 2:3e7685cfb2a7 331 */
sam_grove 2:3e7685cfb2a7 332 uint8_t rf_if_read_register(uint8_t addr)
sam_grove 2:3e7685cfb2a7 333 {
sam_grove 2:3e7685cfb2a7 334 uint8_t cmd = 0x80;
sam_grove 2:3e7685cfb2a7 335 uint8_t data;
sam_grove 2:3e7685cfb2a7 336 arm_enter_critical();
sam_grove 2:3e7685cfb2a7 337
sam_grove 2:3e7685cfb2a7 338 data = spi_read(cmd | addr);
sam_grove 2:3e7685cfb2a7 339 arm_exit_critical();
sam_grove 2:3e7685cfb2a7 340 return data;
sam_grove 2:3e7685cfb2a7 341 }
sam_grove 2:3e7685cfb2a7 342
sam_grove 2:3e7685cfb2a7 343 /*
sam_grove 2:3e7685cfb2a7 344 * \brief Function resets the RF.
sam_grove 2:3e7685cfb2a7 345 *
sam_grove 2:3e7685cfb2a7 346 * \param none
sam_grove 2:3e7685cfb2a7 347 *
sam_grove 2:3e7685cfb2a7 348 * \return none
sam_grove 2:3e7685cfb2a7 349 */
sam_grove 2:3e7685cfb2a7 350 void rf_if_reset_radio(void)
sam_grove 2:3e7685cfb2a7 351 {
sam_grove 2:3e7685cfb2a7 352 /* Reset and init RF_CS - chip select */
sam_grove 2:3e7685cfb2a7 353 RF_RST_Set(1);
sam_grove 2:3e7685cfb2a7 354 rf_if_delay_function(65000);
sam_grove 2:3e7685cfb2a7 355 RF_RST_Set(0);
sam_grove 2:3e7685cfb2a7 356 rf_if_delay_function(65000);
sam_grove 2:3e7685cfb2a7 357 /* Set default states */
sam_grove 2:3e7685cfb2a7 358 RF_CS_Set(1);
sam_grove 2:3e7685cfb2a7 359 RF_SLP_TR_Set(0);
sam_grove 2:3e7685cfb2a7 360 rf_if_delay_function(65000);
sam_grove 2:3e7685cfb2a7 361 RF_RST_Set(1);
sam_grove 2:3e7685cfb2a7 362 rf_if_delay_function(65000);
sam_grove 2:3e7685cfb2a7 363
sam_grove 2:3e7685cfb2a7 364 /*Initialise RF interrupt pin*/
sam_grove 2:3e7685cfb2a7 365 RF_IRQ_Init();
sam_grove 2:3e7685cfb2a7 366 }
sam_grove 2:3e7685cfb2a7 367
sam_grove 2:3e7685cfb2a7 368 /*
sam_grove 2:3e7685cfb2a7 369 * \brief Function enables the Front end usage.
sam_grove 2:3e7685cfb2a7 370 *
sam_grove 2:3e7685cfb2a7 371 * \param none
sam_grove 2:3e7685cfb2a7 372 *
sam_grove 2:3e7685cfb2a7 373 * \return none
sam_grove 2:3e7685cfb2a7 374 */
sam_grove 2:3e7685cfb2a7 375 void rf_if_enable_pa_ext(void)
sam_grove 2:3e7685cfb2a7 376 {
sam_grove 2:3e7685cfb2a7 377 /*Set PA_EXT_EN to enable controlling of external front end*/
sam_grove 2:3e7685cfb2a7 378 rf_if_set_bit(TRX_CTRL_1, PA_EXT_EN, PA_EXT_EN);
sam_grove 2:3e7685cfb2a7 379 }
sam_grove 2:3e7685cfb2a7 380
sam_grove 2:3e7685cfb2a7 381 /*
sam_grove 2:3e7685cfb2a7 382 * \brief Function disables the Front end usage.
sam_grove 2:3e7685cfb2a7 383 *
sam_grove 2:3e7685cfb2a7 384 * \param none
sam_grove 2:3e7685cfb2a7 385 *
sam_grove 2:3e7685cfb2a7 386 * \return none
sam_grove 2:3e7685cfb2a7 387 */
sam_grove 2:3e7685cfb2a7 388 void rf_if_disable_pa_ext(void)
sam_grove 2:3e7685cfb2a7 389 {
sam_grove 2:3e7685cfb2a7 390 /*Clear PA_EXT_EN to disable controlling of external front end*/
sam_grove 2:3e7685cfb2a7 391 rf_if_clear_bit(TRX_CTRL_1, PA_EXT_EN);
sam_grove 2:3e7685cfb2a7 392 }
sam_grove 2:3e7685cfb2a7 393
sam_grove 2:3e7685cfb2a7 394 /*
sam_grove 2:3e7685cfb2a7 395 * \brief Function enables the Antenna diversity usage.
sam_grove 2:3e7685cfb2a7 396 *
sam_grove 2:3e7685cfb2a7 397 * \param none
sam_grove 2:3e7685cfb2a7 398 *
sam_grove 2:3e7685cfb2a7 399 * \return none
sam_grove 2:3e7685cfb2a7 400 */
sam_grove 2:3e7685cfb2a7 401 void rf_if_enable_ant_div(void)
sam_grove 2:3e7685cfb2a7 402 {
sam_grove 2:3e7685cfb2a7 403 /*Set ANT_EXT_SW_EN to enable controlling of antenna diversity*/
sam_grove 2:3e7685cfb2a7 404 rf_if_set_bit(ANT_DIV, ANT_EXT_SW_EN, ANT_EXT_SW_EN);
sam_grove 2:3e7685cfb2a7 405 }
sam_grove 2:3e7685cfb2a7 406
sam_grove 2:3e7685cfb2a7 407 /*
sam_grove 2:3e7685cfb2a7 408 * \brief Function disables the Antenna diversity usage.
sam_grove 2:3e7685cfb2a7 409 *
sam_grove 2:3e7685cfb2a7 410 * \param none
sam_grove 2:3e7685cfb2a7 411 *
sam_grove 2:3e7685cfb2a7 412 * \return none
sam_grove 2:3e7685cfb2a7 413 */
sam_grove 2:3e7685cfb2a7 414 void rf_if_disable_ant_div(void)
sam_grove 2:3e7685cfb2a7 415 {
sam_grove 2:3e7685cfb2a7 416 rf_if_clear_bit(ANT_DIV, ANT_EXT_SW_EN);
sam_grove 2:3e7685cfb2a7 417 }
sam_grove 2:3e7685cfb2a7 418
sam_grove 2:3e7685cfb2a7 419 /*
sam_grove 2:3e7685cfb2a7 420 * \brief Function sets the SLP TR pin.
sam_grove 2:3e7685cfb2a7 421 *
sam_grove 2:3e7685cfb2a7 422 * \param none
sam_grove 2:3e7685cfb2a7 423 *
sam_grove 2:3e7685cfb2a7 424 * \return none
sam_grove 2:3e7685cfb2a7 425 */
sam_grove 2:3e7685cfb2a7 426 void rf_if_enable_slptr(void)
sam_grove 2:3e7685cfb2a7 427 {
sam_grove 2:3e7685cfb2a7 428 RF_SLP_TR_Set(1);
sam_grove 2:3e7685cfb2a7 429 }
sam_grove 2:3e7685cfb2a7 430
sam_grove 2:3e7685cfb2a7 431 /*
sam_grove 2:3e7685cfb2a7 432 * \brief Function clears the SLP TR pin.
sam_grove 2:3e7685cfb2a7 433 *
sam_grove 2:3e7685cfb2a7 434 * \param none
sam_grove 2:3e7685cfb2a7 435 *
sam_grove 2:3e7685cfb2a7 436 * \return none
sam_grove 2:3e7685cfb2a7 437 */
sam_grove 2:3e7685cfb2a7 438 void rf_if_disable_slptr(void)
sam_grove 2:3e7685cfb2a7 439 {
sam_grove 2:3e7685cfb2a7 440 RF_SLP_TR_Set(0);
sam_grove 2:3e7685cfb2a7 441 }
sam_grove 2:3e7685cfb2a7 442
sam_grove 2:3e7685cfb2a7 443 /*
sam_grove 2:3e7685cfb2a7 444 * \brief Function writes the antenna diversity settings.
sam_grove 2:3e7685cfb2a7 445 *
sam_grove 2:3e7685cfb2a7 446 * \param none
sam_grove 2:3e7685cfb2a7 447 *
sam_grove 2:3e7685cfb2a7 448 * \return none
sam_grove 2:3e7685cfb2a7 449 */
sam_grove 2:3e7685cfb2a7 450 void rf_if_write_antenna_diversity_settings(void)
sam_grove 2:3e7685cfb2a7 451 {
sam_grove 2:3e7685cfb2a7 452 /*Recommended setting of PDT_THRES is 3 when antenna diversity is used*/
sam_grove 2:3e7685cfb2a7 453 rf_if_set_bit(RX_CTRL, 0x03, 0x0f);
sam_grove 2:3e7685cfb2a7 454 rf_if_write_register(ANT_DIV, ANT_DIV_EN | ANT_EXT_SW_EN | ANT_CTRL_DEFAULT);
sam_grove 2:3e7685cfb2a7 455 }
sam_grove 2:3e7685cfb2a7 456
sam_grove 2:3e7685cfb2a7 457 /*
sam_grove 2:3e7685cfb2a7 458 * \brief Function writes the TX output power register.
sam_grove 2:3e7685cfb2a7 459 *
sam_grove 2:3e7685cfb2a7 460 * \param value Given register value
sam_grove 2:3e7685cfb2a7 461 *
sam_grove 2:3e7685cfb2a7 462 * \return none
sam_grove 2:3e7685cfb2a7 463 */
sam_grove 2:3e7685cfb2a7 464 void rf_if_write_set_tx_power_register(uint8_t value)
sam_grove 2:3e7685cfb2a7 465 {
sam_grove 2:3e7685cfb2a7 466 rf_if_write_register(PHY_TX_PWR, value);
sam_grove 2:3e7685cfb2a7 467 }
sam_grove 2:3e7685cfb2a7 468
sam_grove 2:3e7685cfb2a7 469 /*
sam_grove 2:3e7685cfb2a7 470 * \brief Function writes the RPC register.
sam_grove 2:3e7685cfb2a7 471 *
sam_grove 2:3e7685cfb2a7 472 * \param value Given register value
sam_grove 2:3e7685cfb2a7 473 *
sam_grove 2:3e7685cfb2a7 474 * \return none
sam_grove 2:3e7685cfb2a7 475 */
sam_grove 2:3e7685cfb2a7 476 void rf_if_write_set_trx_rpc_register(uint8_t value)
sam_grove 2:3e7685cfb2a7 477 {
sam_grove 2:3e7685cfb2a7 478 rf_if_write_register(TRX_RPC, value);
sam_grove 2:3e7685cfb2a7 479 }
sam_grove 2:3e7685cfb2a7 480
sam_grove 2:3e7685cfb2a7 481 /*
sam_grove 2:3e7685cfb2a7 482 * \brief Function returns the RF part number.
sam_grove 2:3e7685cfb2a7 483 *
sam_grove 2:3e7685cfb2a7 484 * \param none
sam_grove 2:3e7685cfb2a7 485 *
sam_grove 2:3e7685cfb2a7 486 * \return part number
sam_grove 2:3e7685cfb2a7 487 */
sam_grove 2:3e7685cfb2a7 488 uint8_t rf_if_read_part_num_delete(void)
sam_grove 2:3e7685cfb2a7 489 {
sam_grove 2:3e7685cfb2a7 490 return rf_if_read_register(PART_NUM);
sam_grove 2:3e7685cfb2a7 491 }
sam_grove 2:3e7685cfb2a7 492
sam_grove 2:3e7685cfb2a7 493 /*
sam_grove 2:3e7685cfb2a7 494 * \brief Function writes the RF settings and initialises SPI interface.
sam_grove 2:3e7685cfb2a7 495 *
sam_grove 2:3e7685cfb2a7 496 * \param none
sam_grove 2:3e7685cfb2a7 497 *
sam_grove 2:3e7685cfb2a7 498 * \return none
sam_grove 2:3e7685cfb2a7 499 */
sam_grove 2:3e7685cfb2a7 500 void rf_if_write_rf_settings(void)
sam_grove 2:3e7685cfb2a7 501 {
sam_grove 2:3e7685cfb2a7 502 int ret;
sam_grove 2:3e7685cfb2a7 503
sam_grove 2:3e7685cfb2a7 504 /* unslotted mode - max. frame & csma retries = 0 */
sam_grove 2:3e7685cfb2a7 505 rf_if_write_register(XAH_CTRL_0,0);
sam_grove 2:3e7685cfb2a7 506 if (rf_if_read_register(XAH_CTRL_0) != 0) {
sam_grove 2:3e7685cfb2a7 507 printf("Error: XAH_CTRL_0 reg. incorrect!\r\n");
sam_grove 2:3e7685cfb2a7 508 //while(1);
sam_grove 2:3e7685cfb2a7 509 }
sam_grove 2:3e7685cfb2a7 510
sam_grove 2:3e7685cfb2a7 511 /* TX_AUTO_CRC On - IRQ_Mask_Mode = 0 - IRQ_Polarity = 0 (Pin IRQ is active high) */
sam_grove 2:3e7685cfb2a7 512 rf_if_write_register(TRX_CTRL_1, 0x20);
sam_grove 2:3e7685cfb2a7 513 if (rf_if_read_register(TRX_CTRL_1) != 0x20) {
sam_grove 2:3e7685cfb2a7 514 printf("Error: TRX_CTRL_1 reg. incorrect!\r\n");
sam_grove 2:3e7685cfb2a7 515 //while(1);
sam_grove 2:3e7685cfb2a7 516 }
sam_grove 2:3e7685cfb2a7 517
sam_grove 2:3e7685cfb2a7 518 /*CCA Mode - Carrier sense OR energy above threshold. Channel list is set separately*/
sam_grove 2:3e7685cfb2a7 519 rf_if_write_register(PHY_CC_CCA, 0x05);
sam_grove 2:3e7685cfb2a7 520 if (rf_if_read_register(PHY_CC_CCA) != 0x05) {
sam_grove 2:3e7685cfb2a7 521 printf("Error: PHY_CC_CCA reg. incorrect!\r\n");
sam_grove 2:3e7685cfb2a7 522 //while(1);
sam_grove 2:3e7685cfb2a7 523 }
sam_grove 2:3e7685cfb2a7 524
sam_grove 2:3e7685cfb2a7 525 /*Read transceiver PART_NUM*/
sam_grove 2:3e7685cfb2a7 526 rf_part_num = rf_if_read_register(PART_NUM);
sam_grove 2:3e7685cfb2a7 527
sam_grove 2:3e7685cfb2a7 528 /*Sub-GHz RF settings*/
sam_grove 2:3e7685cfb2a7 529 if(rf_part_num == PART_AT86RF212)
sam_grove 2:3e7685cfb2a7 530 {
sam_grove 2:3e7685cfb2a7 531 /*GC_TX_OFFS mode-dependent setting - OQPSK*/
sam_grove 2:3e7685cfb2a7 532 rf_if_write_register(RF_CTRL_0, 0x32);
sam_grove 2:3e7685cfb2a7 533
sam_grove 2:3e7685cfb2a7 534 if(rf_if_read_register(VERSION_NUM) == VERSION_AT86RF212B)
sam_grove 2:3e7685cfb2a7 535 {
sam_grove 2:3e7685cfb2a7 536 /*TX Output Power setting - 0 dBm North American Band*/
sam_grove 2:3e7685cfb2a7 537 rf_if_write_register(PHY_TX_PWR, 0x03);
sam_grove 2:3e7685cfb2a7 538 }
sam_grove 2:3e7685cfb2a7 539 else
sam_grove 2:3e7685cfb2a7 540 {
sam_grove 2:3e7685cfb2a7 541 /*TX Output Power setting - 0 dBm North American Band*/
sam_grove 2:3e7685cfb2a7 542 rf_if_write_register(PHY_TX_PWR, 0x24);
sam_grove 2:3e7685cfb2a7 543 }
sam_grove 2:3e7685cfb2a7 544
sam_grove 2:3e7685cfb2a7 545 /*PHY Mode: IEEE 802.15.4-2006/2011 - OQPSK-SIN-250*/
sam_grove 2:3e7685cfb2a7 546 rf_if_write_register(TRX_CTRL_2, OQPSK_SIN_250);
sam_grove 2:3e7685cfb2a7 547 rf_rssi_base_val = -98;
sam_grove 2:3e7685cfb2a7 548 }
sam_grove 2:3e7685cfb2a7 549 /*2.4GHz RF settings*/
sam_grove 2:3e7685cfb2a7 550 else if (rf_part_num == PART_AT86RF233)
sam_grove 2:3e7685cfb2a7 551 {
sam_grove 2:3e7685cfb2a7 552 printf("Part detected: ATMEL AT86RF233\r\n");
sam_grove 2:3e7685cfb2a7 553 /*PHY Mode: IEEE 802.15.4 - Data Rate 250 kb/s*/
sam_grove 2:3e7685cfb2a7 554 rf_if_write_register(TRX_CTRL_2, 0);
sam_grove 2:3e7685cfb2a7 555 rf_rssi_base_val = -91;
sam_grove 2:3e7685cfb2a7 556 } else {
sam_grove 2:3e7685cfb2a7 557 // other module not yet defined
sam_grove 2:3e7685cfb2a7 558 printf("Error: RF Part Unknown!\r\n");
sam_grove 2:3e7685cfb2a7 559 }
sam_grove 2:3e7685cfb2a7 560 }
sam_grove 2:3e7685cfb2a7 561
sam_grove 2:3e7685cfb2a7 562
sam_grove 2:3e7685cfb2a7 563 /*
sam_grove 2:3e7685cfb2a7 564 * \brief Function checks the channel availability
sam_grove 2:3e7685cfb2a7 565 *
sam_grove 2:3e7685cfb2a7 566 * \param none
sam_grove 2:3e7685cfb2a7 567 *
sam_grove 2:3e7685cfb2a7 568 * \return 1 Channel clear
sam_grove 2:3e7685cfb2a7 569 * \return 0 Channel not clear
sam_grove 2:3e7685cfb2a7 570 */
sam_grove 2:3e7685cfb2a7 571 uint8_t rf_if_check_cca(void)
sam_grove 2:3e7685cfb2a7 572 {
sam_grove 2:3e7685cfb2a7 573 uint8_t retval = 0;
sam_grove 2:3e7685cfb2a7 574 if(rf_if_read_register(TRX_STATUS) & CCA_STATUS)
sam_grove 2:3e7685cfb2a7 575 {
sam_grove 2:3e7685cfb2a7 576 retval = 1;
sam_grove 2:3e7685cfb2a7 577 }
sam_grove 2:3e7685cfb2a7 578 return retval;
sam_grove 2:3e7685cfb2a7 579 }
sam_grove 2:3e7685cfb2a7 580
sam_grove 2:3e7685cfb2a7 581 /*
sam_grove 2:3e7685cfb2a7 582 * \brief Function checks if the CRC is valid in received frame
sam_grove 2:3e7685cfb2a7 583 *
sam_grove 2:3e7685cfb2a7 584 * \param none
sam_grove 2:3e7685cfb2a7 585 *
sam_grove 2:3e7685cfb2a7 586 * \return 1 CRC ok
sam_grove 2:3e7685cfb2a7 587 * \return 0 CRC failed
sam_grove 2:3e7685cfb2a7 588 */
sam_grove 2:3e7685cfb2a7 589 uint8_t rf_if_check_crc(void)
sam_grove 2:3e7685cfb2a7 590 {
sam_grove 2:3e7685cfb2a7 591 uint8_t retval = 0;
sam_grove 2:3e7685cfb2a7 592 if(rf_if_read_register(PHY_RSSI) & CRC_VALID)
sam_grove 2:3e7685cfb2a7 593 {
sam_grove 2:3e7685cfb2a7 594 retval = 1;
sam_grove 2:3e7685cfb2a7 595 }
sam_grove 2:3e7685cfb2a7 596 return retval;
sam_grove 2:3e7685cfb2a7 597 }
sam_grove 2:3e7685cfb2a7 598
sam_grove 2:3e7685cfb2a7 599 /*
sam_grove 2:3e7685cfb2a7 600 * \brief Function returns the RF state
sam_grove 2:3e7685cfb2a7 601 *
sam_grove 2:3e7685cfb2a7 602 * \param none
sam_grove 2:3e7685cfb2a7 603 *
sam_grove 2:3e7685cfb2a7 604 * \return RF state
sam_grove 2:3e7685cfb2a7 605 */
sam_grove 2:3e7685cfb2a7 606 uint8_t rf_if_read_trx_state(void)
sam_grove 2:3e7685cfb2a7 607 {
sam_grove 2:3e7685cfb2a7 608 return rf_if_read_register(TRX_STATUS) & 0x1F;
sam_grove 2:3e7685cfb2a7 609 }
sam_grove 2:3e7685cfb2a7 610
sam_grove 2:3e7685cfb2a7 611 /*
sam_grove 2:3e7685cfb2a7 612 * \brief Function reads data from RF SRAM.
sam_grove 2:3e7685cfb2a7 613 *
sam_grove 2:3e7685cfb2a7 614 * \param ptr Read pointer
sam_grove 2:3e7685cfb2a7 615 * \param len Length of the read
sam_grove 2:3e7685cfb2a7 616 *
sam_grove 2:3e7685cfb2a7 617 * \return none
sam_grove 2:3e7685cfb2a7 618 */
sam_grove 2:3e7685cfb2a7 619 void rf_if_read_packet(uint8_t *ptr, uint8_t len)
sam_grove 2:3e7685cfb2a7 620 {
sam_grove 2:3e7685cfb2a7 621 if(rf_part_num == PART_AT86RF231 || rf_part_num == PART_AT86RF212)
sam_grove 2:3e7685cfb2a7 622 rf_if_read_payload(ptr, 0, len);
sam_grove 2:3e7685cfb2a7 623 else if(rf_part_num == PART_AT86RF233)
sam_grove 2:3e7685cfb2a7 624 rf_if_read_payload(ptr, 1, len);
sam_grove 2:3e7685cfb2a7 625 }
sam_grove 2:3e7685cfb2a7 626
sam_grove 2:3e7685cfb2a7 627 /*
sam_grove 2:3e7685cfb2a7 628 * \brief Function writes RF short address registers
sam_grove 2:3e7685cfb2a7 629 *
sam_grove 2:3e7685cfb2a7 630 * \param short_address Given short address
sam_grove 2:3e7685cfb2a7 631 *
sam_grove 2:3e7685cfb2a7 632 * \return none
sam_grove 2:3e7685cfb2a7 633 */
sam_grove 2:3e7685cfb2a7 634 void rf_if_write_short_addr_registers(uint8_t *short_address)
sam_grove 2:3e7685cfb2a7 635 {
sam_grove 2:3e7685cfb2a7 636 rf_if_write_register(SHORT_ADDR_1, *short_address++);
sam_grove 2:3e7685cfb2a7 637 rf_if_write_register(SHORT_ADDR_0, *short_address);
sam_grove 2:3e7685cfb2a7 638 }
sam_grove 2:3e7685cfb2a7 639
sam_grove 2:3e7685cfb2a7 640 /*
sam_grove 2:3e7685cfb2a7 641 * \brief Function sets the frame pending in ACK message
sam_grove 2:3e7685cfb2a7 642 *
sam_grove 2:3e7685cfb2a7 643 * \param state Given frame pending state
sam_grove 2:3e7685cfb2a7 644 *
sam_grove 2:3e7685cfb2a7 645 * \return none
sam_grove 2:3e7685cfb2a7 646 */
sam_grove 2:3e7685cfb2a7 647 void rf_if_ack_pending_ctrl(uint8_t state)
sam_grove 2:3e7685cfb2a7 648 {
sam_grove 2:3e7685cfb2a7 649 arm_enter_critical();
sam_grove 2:3e7685cfb2a7 650 if(state)
sam_grove 2:3e7685cfb2a7 651 {
sam_grove 2:3e7685cfb2a7 652 rf_if_set_bit(CSMA_SEED_1, (1 << AACK_SET_PD), (1 << AACK_SET_PD));
sam_grove 2:3e7685cfb2a7 653 }
sam_grove 2:3e7685cfb2a7 654 else
sam_grove 2:3e7685cfb2a7 655 {
sam_grove 2:3e7685cfb2a7 656 rf_if_clear_bit(CSMA_SEED_1, (1 << AACK_SET_PD));
sam_grove 2:3e7685cfb2a7 657 }
sam_grove 2:3e7685cfb2a7 658 arm_exit_critical();
sam_grove 2:3e7685cfb2a7 659 }
sam_grove 2:3e7685cfb2a7 660
sam_grove 2:3e7685cfb2a7 661 /*
sam_grove 2:3e7685cfb2a7 662 * \brief Function returns the state of frame pending control
sam_grove 2:3e7685cfb2a7 663 *
sam_grove 2:3e7685cfb2a7 664 * \param none
sam_grove 2:3e7685cfb2a7 665 *
sam_grove 2:3e7685cfb2a7 666 * \return Frame pending state
sam_grove 2:3e7685cfb2a7 667 */
sam_grove 2:3e7685cfb2a7 668 uint8_t rf_if_last_acked_pending(void)
sam_grove 2:3e7685cfb2a7 669 {
sam_grove 2:3e7685cfb2a7 670 uint8_t last_acked_data_pending;
sam_grove 2:3e7685cfb2a7 671
sam_grove 2:3e7685cfb2a7 672 if(rf_if_read_register(CSMA_SEED_1) & 0x20)
sam_grove 2:3e7685cfb2a7 673 last_acked_data_pending = 1;
sam_grove 2:3e7685cfb2a7 674 else
sam_grove 2:3e7685cfb2a7 675 last_acked_data_pending = 0;
sam_grove 2:3e7685cfb2a7 676
sam_grove 2:3e7685cfb2a7 677 return last_acked_data_pending;
sam_grove 2:3e7685cfb2a7 678 }
sam_grove 2:3e7685cfb2a7 679
sam_grove 2:3e7685cfb2a7 680 /*
sam_grove 2:3e7685cfb2a7 681 * \brief Function calibrates the RF part.
sam_grove 2:3e7685cfb2a7 682 *
sam_grove 2:3e7685cfb2a7 683 * \param none
sam_grove 2:3e7685cfb2a7 684 *
sam_grove 2:3e7685cfb2a7 685 * \return none
sam_grove 2:3e7685cfb2a7 686 */
sam_grove 2:3e7685cfb2a7 687 void rf_if_calibration(void)
sam_grove 2:3e7685cfb2a7 688 {
sam_grove 2:3e7685cfb2a7 689 rf_if_set_bit(FTN_CTRL, FTN_START, FTN_START);
sam_grove 2:3e7685cfb2a7 690 /*Wait while calibration is running*/
sam_grove 2:3e7685cfb2a7 691 while(rf_if_read_register(FTN_CTRL) & FTN_START);
sam_grove 2:3e7685cfb2a7 692 }
sam_grove 2:3e7685cfb2a7 693
sam_grove 2:3e7685cfb2a7 694 /*
sam_grove 2:3e7685cfb2a7 695 * \brief Function writes RF PAN Id registers
sam_grove 2:3e7685cfb2a7 696 *
sam_grove 2:3e7685cfb2a7 697 * \param pan_id Given PAN Id
sam_grove 2:3e7685cfb2a7 698 *
sam_grove 2:3e7685cfb2a7 699 * \return none
sam_grove 2:3e7685cfb2a7 700 */
sam_grove 2:3e7685cfb2a7 701 void rf_if_write_pan_id_registers(uint8_t *pan_id)
sam_grove 2:3e7685cfb2a7 702 {
sam_grove 2:3e7685cfb2a7 703 rf_if_write_register(PAN_ID_1, *pan_id++);
sam_grove 2:3e7685cfb2a7 704 rf_if_write_register(PAN_ID_0, *pan_id);
sam_grove 2:3e7685cfb2a7 705 }
sam_grove 2:3e7685cfb2a7 706
sam_grove 2:3e7685cfb2a7 707 /*
sam_grove 2:3e7685cfb2a7 708 * \brief Function writes RF IEEE Address registers
sam_grove 2:3e7685cfb2a7 709 *
sam_grove 2:3e7685cfb2a7 710 * \param address Given IEEE Address
sam_grove 2:3e7685cfb2a7 711 *
sam_grove 2:3e7685cfb2a7 712 * \return none
sam_grove 2:3e7685cfb2a7 713 */
sam_grove 2:3e7685cfb2a7 714 void rf_if_write_ieee_addr_registers(uint8_t *address)
sam_grove 2:3e7685cfb2a7 715 {
sam_grove 2:3e7685cfb2a7 716 uint8_t i;
sam_grove 2:3e7685cfb2a7 717 uint8_t temp = IEEE_ADDR_0;
sam_grove 2:3e7685cfb2a7 718
sam_grove 2:3e7685cfb2a7 719 for(i=0; i<8; i++)
sam_grove 2:3e7685cfb2a7 720 rf_if_write_register(temp++, address[7-i]);
sam_grove 2:3e7685cfb2a7 721 }
sam_grove 2:3e7685cfb2a7 722
sam_grove 2:3e7685cfb2a7 723 /*
sam_grove 2:3e7685cfb2a7 724 * \brief Function writes data in RF frame buffer.
sam_grove 2:3e7685cfb2a7 725 *
sam_grove 2:3e7685cfb2a7 726 * \param ptr Pointer to data
sam_grove 2:3e7685cfb2a7 727 * \param length Pointer to length
sam_grove 2:3e7685cfb2a7 728 *
sam_grove 2:3e7685cfb2a7 729 * \return none
sam_grove 2:3e7685cfb2a7 730 */
sam_grove 2:3e7685cfb2a7 731 void rf_if_write_frame_buffer(uint8_t *ptr, uint8_t length)
sam_grove 2:3e7685cfb2a7 732 {
sam_grove 2:3e7685cfb2a7 733 uint8_t i;
sam_grove 2:3e7685cfb2a7 734 uint8_t cmd = 0x60;
sam_grove 2:3e7685cfb2a7 735
sam_grove 2:3e7685cfb2a7 736 RF_CS_Set(0);
sam_grove 2:3e7685cfb2a7 737 spi_exchange(cmd);
sam_grove 2:3e7685cfb2a7 738 spi_exchange(length + 2);
sam_grove 2:3e7685cfb2a7 739 for(i=0; i<length; i++)
sam_grove 2:3e7685cfb2a7 740 spi_exchange(*ptr++);
sam_grove 2:3e7685cfb2a7 741
sam_grove 2:3e7685cfb2a7 742 rf_if_delay_function(10);
sam_grove 2:3e7685cfb2a7 743 RF_CS_Set(1);
sam_grove 2:3e7685cfb2a7 744 }
sam_grove 2:3e7685cfb2a7 745
sam_grove 2:3e7685cfb2a7 746 /*
sam_grove 2:3e7685cfb2a7 747 * \brief Function returns 8-bit random value.
sam_grove 2:3e7685cfb2a7 748 *
sam_grove 2:3e7685cfb2a7 749 * \param none
sam_grove 2:3e7685cfb2a7 750 *
sam_grove 2:3e7685cfb2a7 751 * \return random value
sam_grove 2:3e7685cfb2a7 752 */
sam_grove 2:3e7685cfb2a7 753 uint8_t rf_if_read_rnd(void)
sam_grove 2:3e7685cfb2a7 754 {
sam_grove 2:3e7685cfb2a7 755 uint8_t temp;
sam_grove 2:3e7685cfb2a7 756
sam_grove 2:3e7685cfb2a7 757 temp = ((rf_if_read_register(PHY_RSSI)>>5) << 6);
sam_grove 2:3e7685cfb2a7 758 temp |= ((rf_if_read_register(PHY_RSSI)>>5) << 4);
sam_grove 2:3e7685cfb2a7 759 temp |= ((rf_if_read_register(PHY_RSSI)>>5) << 2);
sam_grove 2:3e7685cfb2a7 760 temp |= ((rf_if_read_register(PHY_RSSI)>>5));
sam_grove 2:3e7685cfb2a7 761 return temp;
sam_grove 2:3e7685cfb2a7 762 }
sam_grove 2:3e7685cfb2a7 763
sam_grove 2:3e7685cfb2a7 764 /*
sam_grove 2:3e7685cfb2a7 765 * \brief Function changes the state of the RF.
sam_grove 2:3e7685cfb2a7 766 *
sam_grove 2:3e7685cfb2a7 767 * \param trx_state Given RF state
sam_grove 2:3e7685cfb2a7 768 *
sam_grove 2:3e7685cfb2a7 769 * \return none
sam_grove 2:3e7685cfb2a7 770 */
sam_grove 2:3e7685cfb2a7 771 void rf_if_change_trx_state(rf_trx_states_t trx_state)
sam_grove 2:3e7685cfb2a7 772 {
sam_grove 2:3e7685cfb2a7 773 arm_enter_critical();
sam_grove 2:3e7685cfb2a7 774 rf_if_write_register(TRX_STATE, trx_state);
sam_grove 2:3e7685cfb2a7 775 /*Wait while not in desired state*/
sam_grove 2:3e7685cfb2a7 776 rf_poll_trx_state_change(trx_state);
sam_grove 2:3e7685cfb2a7 777 arm_exit_critical();
sam_grove 2:3e7685cfb2a7 778 }
sam_grove 2:3e7685cfb2a7 779
sam_grove 2:3e7685cfb2a7 780 /*
sam_grove 2:3e7685cfb2a7 781 * \brief Function enables the TX END interrupt
sam_grove 2:3e7685cfb2a7 782 *
sam_grove 2:3e7685cfb2a7 783 * \param none
sam_grove 2:3e7685cfb2a7 784 *
sam_grove 2:3e7685cfb2a7 785 * \return none
sam_grove 2:3e7685cfb2a7 786 */
sam_grove 2:3e7685cfb2a7 787 void rf_if_enable_tx_end_interrupt(void)
sam_grove 2:3e7685cfb2a7 788 {
sam_grove 2:3e7685cfb2a7 789 rf_if_set_bit(IRQ_MASK, TRX_END, 0x08);
sam_grove 2:3e7685cfb2a7 790 }
sam_grove 2:3e7685cfb2a7 791
sam_grove 2:3e7685cfb2a7 792 /*
sam_grove 2:3e7685cfb2a7 793 * \brief Function enables the RX END interrupt
sam_grove 2:3e7685cfb2a7 794 *
sam_grove 2:3e7685cfb2a7 795 * \param none
sam_grove 2:3e7685cfb2a7 796 *
sam_grove 2:3e7685cfb2a7 797 * \return none
sam_grove 2:3e7685cfb2a7 798 */
sam_grove 2:3e7685cfb2a7 799 void rf_if_enable_rx_end_interrupt(void)
sam_grove 2:3e7685cfb2a7 800 {
sam_grove 2:3e7685cfb2a7 801 rf_if_set_bit(IRQ_MASK, TRX_END, 0x08);
sam_grove 2:3e7685cfb2a7 802 }
sam_grove 2:3e7685cfb2a7 803
sam_grove 2:3e7685cfb2a7 804 /*
sam_grove 2:3e7685cfb2a7 805 * \brief Function enables the RX START interrupt
sam_grove 2:3e7685cfb2a7 806 *
sam_grove 2:3e7685cfb2a7 807 * \param none
sam_grove 2:3e7685cfb2a7 808 *
sam_grove 2:3e7685cfb2a7 809 * \return none
sam_grove 2:3e7685cfb2a7 810 */
sam_grove 2:3e7685cfb2a7 811 void rf_if_enable_rx_start_interrupt(void)
sam_grove 2:3e7685cfb2a7 812 {
sam_grove 2:3e7685cfb2a7 813 rf_if_set_bit(IRQ_MASK, RX_START, 0x04);
sam_grove 2:3e7685cfb2a7 814 }
sam_grove 2:3e7685cfb2a7 815
sam_grove 2:3e7685cfb2a7 816 /*
sam_grove 2:3e7685cfb2a7 817 * \brief Function enables the CCA ED interrupt
sam_grove 2:3e7685cfb2a7 818 *
sam_grove 2:3e7685cfb2a7 819 * \param none
sam_grove 2:3e7685cfb2a7 820 *
sam_grove 2:3e7685cfb2a7 821 * \return none
sam_grove 2:3e7685cfb2a7 822 */
sam_grove 2:3e7685cfb2a7 823 void rf_if_enable_cca_ed_done_interrupt(void)
sam_grove 2:3e7685cfb2a7 824 {
sam_grove 2:3e7685cfb2a7 825 rf_if_set_bit(IRQ_MASK, CCA_ED_DONE, 0x10);
sam_grove 2:3e7685cfb2a7 826 }
sam_grove 2:3e7685cfb2a7 827
sam_grove 2:3e7685cfb2a7 828 /*
sam_grove 2:3e7685cfb2a7 829 * \brief Function starts the CCA process
sam_grove 2:3e7685cfb2a7 830 *
sam_grove 2:3e7685cfb2a7 831 * \param none
sam_grove 2:3e7685cfb2a7 832 *
sam_grove 2:3e7685cfb2a7 833 * \return none
sam_grove 2:3e7685cfb2a7 834 */
sam_grove 2:3e7685cfb2a7 835 void rf_if_start_cca_process(void)
sam_grove 2:3e7685cfb2a7 836 {
sam_grove 2:3e7685cfb2a7 837 rf_if_set_bit(PHY_CC_CCA, CCA_REQUEST, 0x80);
sam_grove 2:3e7685cfb2a7 838 }
sam_grove 2:3e7685cfb2a7 839
sam_grove 2:3e7685cfb2a7 840 /*
sam_grove 2:3e7685cfb2a7 841 * \brief Function returns the length of the received packet
sam_grove 2:3e7685cfb2a7 842 *
sam_grove 2:3e7685cfb2a7 843 * \param none
sam_grove 2:3e7685cfb2a7 844 *
sam_grove 2:3e7685cfb2a7 845 * \return packet length
sam_grove 2:3e7685cfb2a7 846 */
sam_grove 2:3e7685cfb2a7 847 uint8_t rf_if_read_received_frame_length(void)
sam_grove 2:3e7685cfb2a7 848 {
sam_grove 2:3e7685cfb2a7 849 uint8_t length;
sam_grove 2:3e7685cfb2a7 850
sam_grove 2:3e7685cfb2a7 851 RF_CS_Set(0);
sam_grove 2:3e7685cfb2a7 852 spi_exchange(0x20);
sam_grove 2:3e7685cfb2a7 853 length = spi_exchange(0);
sam_grove 2:3e7685cfb2a7 854 RF_CS_Set(1);
sam_grove 2:3e7685cfb2a7 855 return length;
sam_grove 2:3e7685cfb2a7 856 }
sam_grove 2:3e7685cfb2a7 857
sam_grove 2:3e7685cfb2a7 858 /*
sam_grove 2:3e7685cfb2a7 859 * \brief Function returns the LQI of the received packet
sam_grove 2:3e7685cfb2a7 860 *
sam_grove 2:3e7685cfb2a7 861 * \param none
sam_grove 2:3e7685cfb2a7 862 *
sam_grove 2:3e7685cfb2a7 863 * \return packet LQI
sam_grove 2:3e7685cfb2a7 864 */
sam_grove 2:3e7685cfb2a7 865 uint8_t rf_if_read_lqi(void)
sam_grove 2:3e7685cfb2a7 866 {
sam_grove 2:3e7685cfb2a7 867 return rf_rx_lqi;
sam_grove 2:3e7685cfb2a7 868 }
sam_grove 2:3e7685cfb2a7 869
sam_grove 2:3e7685cfb2a7 870 /*
sam_grove 2:3e7685cfb2a7 871 * \brief Function returns the RSSI of the received packet
sam_grove 2:3e7685cfb2a7 872 *
sam_grove 2:3e7685cfb2a7 873 * \param none
sam_grove 2:3e7685cfb2a7 874 *
sam_grove 2:3e7685cfb2a7 875 * \return packet RSSI
sam_grove 2:3e7685cfb2a7 876 */
sam_grove 2:3e7685cfb2a7 877 int8_t rf_if_read_rssi(void)
sam_grove 2:3e7685cfb2a7 878 {
sam_grove 2:3e7685cfb2a7 879 return rf_rx_rssi;
sam_grove 2:3e7685cfb2a7 880 }
sam_grove 2:3e7685cfb2a7 881
sam_grove 2:3e7685cfb2a7 882 /*
sam_grove 2:3e7685cfb2a7 883 * \brief Function sets the RF channel field
sam_grove 2:3e7685cfb2a7 884 *
sam_grove 2:3e7685cfb2a7 885 * \param Given channel
sam_grove 2:3e7685cfb2a7 886 *
sam_grove 2:3e7685cfb2a7 887 * \return none
sam_grove 2:3e7685cfb2a7 888 */
sam_grove 2:3e7685cfb2a7 889 void rf_if_set_channel_register(uint8_t channel)
sam_grove 2:3e7685cfb2a7 890 {
sam_grove 2:3e7685cfb2a7 891 rf_if_set_bit(PHY_CC_CCA, channel, 0x1f);
sam_grove 2:3e7685cfb2a7 892 }
sam_grove 2:3e7685cfb2a7 893
sam_grove 2:3e7685cfb2a7 894 /*
sam_grove 2:3e7685cfb2a7 895 * \brief Function returns the pointer to RF interrupt handler
sam_grove 2:3e7685cfb2a7 896 *
sam_grove 2:3e7685cfb2a7 897 * \param none
sam_grove 2:3e7685cfb2a7 898 *
sam_grove 2:3e7685cfb2a7 899 * \return RF interrupt handler function
sam_grove 2:3e7685cfb2a7 900 */
sam_grove 2:3e7685cfb2a7 901 void (*rf_if_get_rf_interrupt_function())(void)
sam_grove 2:3e7685cfb2a7 902 {
sam_grove 2:3e7685cfb2a7 903 return rf_if_interrupt_handler;
sam_grove 2:3e7685cfb2a7 904 }
sam_grove 2:3e7685cfb2a7 905
sam_grove 2:3e7685cfb2a7 906 /*
sam_grove 2:3e7685cfb2a7 907 * \brief Function is a RF interrupt vector. End of frame in RX and TX are handled here as well as CCA process interrupt.
sam_grove 2:3e7685cfb2a7 908 *
sam_grove 2:3e7685cfb2a7 909 * \param none
sam_grove 2:3e7685cfb2a7 910 *
sam_grove 2:3e7685cfb2a7 911 * \return none
sam_grove 2:3e7685cfb2a7 912 */
sam_grove 2:3e7685cfb2a7 913 void rf_if_interrupt_handler(void)
sam_grove 2:3e7685cfb2a7 914 {
sam_grove 2:3e7685cfb2a7 915 uint8_t irq_status;
sam_grove 2:3e7685cfb2a7 916
sam_grove 2:3e7685cfb2a7 917 /*Read interrupt flag*/
sam_grove 2:3e7685cfb2a7 918 irq_status = rf_if_read_register(IRQ_STATUS);
sam_grove 2:3e7685cfb2a7 919
sam_grove 2:3e7685cfb2a7 920 /*Disable interrupt on RF*/
sam_grove 2:3e7685cfb2a7 921 rf_if_clear_bit(IRQ_MASK, irq_status);
sam_grove 2:3e7685cfb2a7 922 /*RX start interrupt*/
sam_grove 2:3e7685cfb2a7 923 if(irq_status & RX_START)
sam_grove 2:3e7685cfb2a7 924 {
sam_grove 2:3e7685cfb2a7 925 }
sam_grove 2:3e7685cfb2a7 926 /*Address matching interrupt*/
sam_grove 2:3e7685cfb2a7 927 if(irq_status & AMI)
sam_grove 2:3e7685cfb2a7 928 {
sam_grove 2:3e7685cfb2a7 929 }
sam_grove 2:3e7685cfb2a7 930 if(irq_status & TRX_UR)
sam_grove 2:3e7685cfb2a7 931 {
sam_grove 2:3e7685cfb2a7 932 }
sam_grove 2:3e7685cfb2a7 933 /*Frame end interrupt (RX and TX)*/
sam_grove 2:3e7685cfb2a7 934 if(irq_status & TRX_END)
sam_grove 2:3e7685cfb2a7 935 {
sam_grove 2:3e7685cfb2a7 936 /*TX done interrupt*/
sam_grove 2:3e7685cfb2a7 937 if(rf_if_read_trx_state() == PLL_ON || rf_if_read_trx_state() == TX_ARET_ON)
sam_grove 2:3e7685cfb2a7 938 {
sam_grove 2:3e7685cfb2a7 939 rf_handle_tx_end();
sam_grove 2:3e7685cfb2a7 940 }
sam_grove 2:3e7685cfb2a7 941 /*Frame received interrupt*/
sam_grove 2:3e7685cfb2a7 942 else
sam_grove 2:3e7685cfb2a7 943 {
sam_grove 2:3e7685cfb2a7 944 rf_handle_rx_end();
sam_grove 2:3e7685cfb2a7 945 }
sam_grove 2:3e7685cfb2a7 946 }
sam_grove 2:3e7685cfb2a7 947 if(irq_status & CCA_ED_DONE)
sam_grove 2:3e7685cfb2a7 948 {
sam_grove 2:3e7685cfb2a7 949 rf_handle_cca_ed_done();
sam_grove 2:3e7685cfb2a7 950 }
sam_grove 2:3e7685cfb2a7 951 }
sam_grove 2:3e7685cfb2a7 952