NXP / Mbed 2 deprecated mcr20_wireless_uart

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Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

RF_Drivers_Freescale/MCR20Drv/MCR20Reg.h@13:4fa8e504061f, 2015-03-08 (annotated)

Committer:
cotigac
Date:
Sun Mar 08 04:18:09 2015 +0000
Revision:
13:4fa8e504061f
Parent:
RF_Drivers_Freescale/MCR20Reg.h@8:e4c9f2b7a9d2 
Temporary reverted back to Atmel RF Drivers

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 5:69f1634cd40b 1 /*!
FSL\B36402 5:69f1634cd40b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
FSL\B36402 5:69f1634cd40b 3 * All rights reserved.
FSL\B36402 5:69f1634cd40b 4 *
FSL\B36402 5:69f1634cd40b 5 * \file MCR20reg.h
FSL\B36402 5:69f1634cd40b 6 * MCR20 Registers
FSL\B36402 5:69f1634cd40b 7 *
FSL\B36402 5:69f1634cd40b 8 * Redistribution and use in source and binary forms, with or without modification,
FSL\B36402 5:69f1634cd40b 9 * are permitted provided that the following conditions are met:
FSL\B36402 5:69f1634cd40b 10 *
FSL\B36402 5:69f1634cd40b 11 * o Redistributions of source code must retain the above copyright notice, this list
FSL\B36402 5:69f1634cd40b 12 * of conditions and the following disclaimer.
FSL\B36402 5:69f1634cd40b 13 *
FSL\B36402 5:69f1634cd40b 14 * o Redistributions in binary form must reproduce the above copyright notice, this
FSL\B36402 5:69f1634cd40b 15 * list of conditions and the following disclaimer in the documentation and/or
FSL\B36402 5:69f1634cd40b 16 * other materials provided with the distribution.
FSL\B36402 5:69f1634cd40b 17 *
FSL\B36402 5:69f1634cd40b 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
FSL\B36402 5:69f1634cd40b 19 * contributors may be used to endorse or promote products derived from this
FSL\B36402 5:69f1634cd40b 20 * software without specific prior written permission.
FSL\B36402 5:69f1634cd40b 21 *
FSL\B36402 5:69f1634cd40b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
FSL\B36402 5:69f1634cd40b 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
FSL\B36402 5:69f1634cd40b 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
FSL\B36402 5:69f1634cd40b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
FSL\B36402 5:69f1634cd40b 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
FSL\B36402 5:69f1634cd40b 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
FSL\B36402 5:69f1634cd40b 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
FSL\B36402 5:69f1634cd40b 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
FSL\B36402 5:69f1634cd40b 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
FSL\B36402 5:69f1634cd40b 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
FSL\B36402 5:69f1634cd40b 32 */
FSL\B36402 5:69f1634cd40b 33
FSL\B36402 5:69f1634cd40b 34 #ifndef __MCR20_REG_H__
FSL\B36402 5:69f1634cd40b 35 #define __MCR20_REG_H__
FSL\B36402 5:69f1634cd40b 36 /*****************************************************************************
FSL\B36402 5:69f1634cd40b 37 * INCLUDED HEADERS *
FSL\B36402 5:69f1634cd40b 38 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 39 * Add to this section all the headers that this module needs to include. *
FSL\B36402 5:69f1634cd40b 40 * Note that it is not a good practice to include header files into header *
FSL\B36402 5:69f1634cd40b 41 * files, so use this section only if there is no other better solution. *
FSL\B36402 5:69f1634cd40b 42 *---------------------------------------------------------------------------*
FSL\B36402 5:69f1634cd40b 43 *****************************************************************************/
FSL\B36402 5:69f1634cd40b 44
FSL\B36402 5:69f1634cd40b 45 /****************************************************************************/
FSL\B36402 5:69f1634cd40b 46 /* Transceiver SPI Registers */
FSL\B36402 5:69f1634cd40b 47 /****************************************************************************/
FSL\B36402 5:69f1634cd40b 48
FSL\B36402 5:69f1634cd40b 49 #define TransceiverSPI_IARIndexReg (0x3E)
FSL\B36402 5:69f1634cd40b 50
FSL\B36402 5:69f1634cd40b 51 #define TransceiverSPI_ReadSelect (1<<7)
FSL\B36402 5:69f1634cd40b 52 #define TransceiverSPI_WriteSelect (0<<7)
FSL\B36402 5:69f1634cd40b 53 #define TransceiverSPI_RegisterAccessSelect (0<<6)
FSL\B36402 5:69f1634cd40b 54 #define TransceiverSPI_PacketBuffAccessSelect (1<<6)
FSL\B36402 5:69f1634cd40b 55 #define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
FSL\B36402 5:69f1634cd40b 56 #define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
FSL\B36402 5:69f1634cd40b 57
FSL\B36402 5:69f1634cd40b 58 #define TransceiverSPI_DirectRegisterAddressMask (0x3F)
FSL\B36402 5:69f1634cd40b 59
FSL\B36402 5:69f1634cd40b 60 #define IRQSTS1 0x00
FSL\B36402 5:69f1634cd40b 61 #define IRQSTS2 0x01
FSL\B36402 5:69f1634cd40b 62 #define IRQSTS3 0x02
FSL\B36402 5:69f1634cd40b 63 #define PHY_CTRL1 0x03
FSL\B36402 5:69f1634cd40b 64 #define PHY_CTRL2 0x04
FSL\B36402 5:69f1634cd40b 65 #define PHY_CTRL3 0x05
FSL\B36402 5:69f1634cd40b 66 #define RX_FRM_LEN 0x06
FSL\B36402 5:69f1634cd40b 67 #define PHY_CTRL4 0x07
FSL\B36402 5:69f1634cd40b 68 #define SRC_CTRL 0x08
FSL\B36402 5:69f1634cd40b 69 #define SRC_ADDRS_SUM_LSB 0x09
FSL\B36402 5:69f1634cd40b 70 #define SRC_ADDRS_SUM_MSB 0x0A
FSL\B36402 5:69f1634cd40b 71 #define CCA1_ED_FNL 0x0B
FSL\B36402 5:69f1634cd40b 72 #define EVENT_TMR_LSB 0x0C
FSL\B36402 5:69f1634cd40b 73 #define EVENT_TMR_MSB 0x0D
FSL\B36402 5:69f1634cd40b 74 #define EVENT_TMR_USB 0x0E
FSL\B36402 5:69f1634cd40b 75 #define TIMESTAMP_LSB 0x0F
FSL\B36402 5:69f1634cd40b 76 #define TIMESTAMP_MSB 0x10
FSL\B36402 5:69f1634cd40b 77 #define TIMESTAMP_USB 0x11
FSL\B36402 5:69f1634cd40b 78 #define T3CMP_LSB 0x12
FSL\B36402 5:69f1634cd40b 79 #define T3CMP_MSB 0x13
FSL\B36402 5:69f1634cd40b 80 #define T3CMP_USB 0x14
FSL\B36402 5:69f1634cd40b 81 #define T2PRIMECMP_LSB 0x15
FSL\B36402 5:69f1634cd40b 82 #define T2PRIMECMP_MSB 0x16
FSL\B36402 5:69f1634cd40b 83 #define T1CMP_LSB 0x17
FSL\B36402 5:69f1634cd40b 84 #define T1CMP_MSB 0x18
FSL\B36402 5:69f1634cd40b 85 #define T1CMP_USB 0x19
FSL\B36402 5:69f1634cd40b 86 #define T2CMP_LSB 0x1A
FSL\B36402 5:69f1634cd40b 87 #define T2CMP_MSB 0x1B
FSL\B36402 5:69f1634cd40b 88 #define T2CMP_USB 0x1C
FSL\B36402 5:69f1634cd40b 89 #define T4CMP_LSB 0x1D
FSL\B36402 5:69f1634cd40b 90 #define T4CMP_MSB 0x1E
FSL\B36402 5:69f1634cd40b 91 #define T4CMP_USB 0x1F
FSL\B36402 5:69f1634cd40b 92 #define PLL_INT0 0x20
FSL\B36402 5:69f1634cd40b 93 #define PLL_FRAC0_LSB 0x21
FSL\B36402 5:69f1634cd40b 94 #define PLL_FRAC0_MSB 0x22
FSL\B36402 5:69f1634cd40b 95 #define PA_PWR 0x23
FSL\B36402 5:69f1634cd40b 96 #define SEQ_STATE 0x24
FSL\B36402 5:69f1634cd40b 97 #define LQI_VALUE 0x25
FSL\B36402 5:69f1634cd40b 98 #define RSSI_CCA_CONT 0x26
FSL\B36402 5:69f1634cd40b 99 //-------------- 0x27
FSL\B36402 5:69f1634cd40b 100 #define ASM_CTRL1 0x28
FSL\B36402 5:69f1634cd40b 101 #define ASM_CTRL2 0x29
FSL\B36402 5:69f1634cd40b 102 #define ASM_DATA_0 0x2A
FSL\B36402 5:69f1634cd40b 103 #define ASM_DATA_1 0x2B
FSL\B36402 5:69f1634cd40b 104 #define ASM_DATA_2 0x2C
FSL\B36402 5:69f1634cd40b 105 #define ASM_DATA_3 0x2D
FSL\B36402 5:69f1634cd40b 106 #define ASM_DATA_4 0x2E
FSL\B36402 5:69f1634cd40b 107 #define ASM_DATA_5 0x2F
FSL\B36402 5:69f1634cd40b 108 #define ASM_DATA_6 0x30
FSL\B36402 5:69f1634cd40b 109 #define ASM_DATA_7 0x31
FSL\B36402 5:69f1634cd40b 110 #define ASM_DATA_8 0x32
FSL\B36402 5:69f1634cd40b 111 #define ASM_DATA_9 0x33
FSL\B36402 5:69f1634cd40b 112 #define ASM_DATA_A 0x34
FSL\B36402 5:69f1634cd40b 113 #define ASM_DATA_B 0x35
FSL\B36402 5:69f1634cd40b 114 #define ASM_DATA_C 0x36
FSL\B36402 5:69f1634cd40b 115 #define ASM_DATA_D 0x37
FSL\B36402 5:69f1634cd40b 116 #define ASM_DATA_E 0x38
FSL\B36402 5:69f1634cd40b 117 #define ASM_DATA_F 0x39
FSL\B36402 5:69f1634cd40b 118 //------------------- 0x3A
FSL\B36402 5:69f1634cd40b 119 #define OVERWRITE_VER 0x3B
FSL\B36402 5:69f1634cd40b 120 #define CLK_OUT_CTRL 0x3C
FSL\B36402 5:69f1634cd40b 121 #define PWR_MODES 0x3D
FSL\B36402 5:69f1634cd40b 122 #define IAR_INDEX 0x3E
FSL\B36402 5:69f1634cd40b 123 #define IAR_DATA 0x3F
FSL\B36402 5:69f1634cd40b 124
FSL\B36402 5:69f1634cd40b 125
FSL\B36402 5:69f1634cd40b 126 #define PART_ID 0x00
FSL\B36402 5:69f1634cd40b 127 #define XTAL_TRIM 0x01
FSL\B36402 5:69f1634cd40b 128 #define PMC_LP_TRIM 0x02
FSL\B36402 5:69f1634cd40b 129 #define MACPANID0_LSB 0x03
FSL\B36402 5:69f1634cd40b 130 #define MACPANID0_MSB 0x04
FSL\B36402 5:69f1634cd40b 131 #define MACSHORTADDRS0_LSB 0x05
FSL\B36402 5:69f1634cd40b 132 #define MACSHORTADDRS0_MSB 0x06
FSL\B36402 5:69f1634cd40b 133 #define MACLONGADDRS0_0 0x07
FSL\B36402 5:69f1634cd40b 134 #define MACLONGADDRS0_8 0x08
FSL\B36402 5:69f1634cd40b 135 #define MACLONGADDRS0_16 0x09
FSL\B36402 5:69f1634cd40b 136 #define MACLONGADDRS0_24 0x0A
FSL\B36402 5:69f1634cd40b 137 #define MACLONGADDRS0_32 0x0B
FSL\B36402 5:69f1634cd40b 138 #define MACLONGADDRS0_40 0x0C
FSL\B36402 5:69f1634cd40b 139 #define MACLONGADDRS0_48 0x0D
FSL\B36402 5:69f1634cd40b 140 #define MACLONGADDRS0_56 0x0E
FSL\B36402 5:69f1634cd40b 141 #define RX_FRAME_FILTER 0x0F
FSL\B36402 5:69f1634cd40b 142 #define PLL_INT1 0x10
FSL\B36402 5:69f1634cd40b 143 #define PLL_FRAC1_LSB 0x11
FSL\B36402 5:69f1634cd40b 144 #define PLL_FRAC1_MSB 0x12
FSL\B36402 5:69f1634cd40b 145 #define MACPANID1_LSB 0x13
FSL\B36402 5:69f1634cd40b 146 #define MACPANID1_MSB 0x14
FSL\B36402 5:69f1634cd40b 147 #define MACSHORTADDRS1_LSB 0x15
FSL\B36402 5:69f1634cd40b 148 #define MACSHORTADDRS1_MSB 0x16
FSL\B36402 5:69f1634cd40b 149 #define MACLONGADDRS1_0 0x17
FSL\B36402 5:69f1634cd40b 150 #define MACLONGADDRS1_8 0x18
FSL\B36402 5:69f1634cd40b 151 #define MACLONGADDRS1_16 0x19
FSL\B36402 5:69f1634cd40b 152 #define MACLONGADDRS1_24 0x1A
FSL\B36402 5:69f1634cd40b 153 #define MACLONGADDRS1_32 0x1B
FSL\B36402 5:69f1634cd40b 154 #define MACLONGADDRS1_40 0x1C
FSL\B36402 5:69f1634cd40b 155 #define MACLONGADDRS1_48 0x1D
FSL\B36402 5:69f1634cd40b 156 #define MACLONGADDRS1_56 0x1E
FSL\B36402 5:69f1634cd40b 157 #define DUAL_PAN_CTRL 0x1F
FSL\B36402 5:69f1634cd40b 158 #define DUAL_PAN_DWELL 0x20
FSL\B36402 5:69f1634cd40b 159 #define DUAL_PAN_STS 0x21
FSL\B36402 5:69f1634cd40b 160 #define CCA1_THRESH 0x22
FSL\B36402 5:69f1634cd40b 161 #define CCA1_ED_OFFSET_COMP 0x23
FSL\B36402 5:69f1634cd40b 162 #define LQI_OFFSET_COMP 0x24
FSL\B36402 5:69f1634cd40b 163 #define CCA_CTRL 0x25
FSL\B36402 5:69f1634cd40b 164 #define CCA2_CORR_PEAKS 0x26
FSL\B36402 5:69f1634cd40b 165 #define CCA2_CORR_THRESH 0x27
FSL\B36402 5:69f1634cd40b 166 #define TMR_PRESCALE 0x28
FSL\B36402 5:69f1634cd40b 167 //---------------- 0x29
FSL\B36402 5:69f1634cd40b 168 #define GPIO_DATA 0x2A
FSL\B36402 5:69f1634cd40b 169 #define GPIO_DIR 0x2B
FSL\B36402 5:69f1634cd40b 170 #define GPIO_PUL_EN 0x2C
FSL\B36402 5:69f1634cd40b 171 #define GPIO_PUL_SEL 0x2D
FSL\B36402 5:69f1634cd40b 172 #define GPIO_DS 0x2E
FSL\B36402 5:69f1634cd40b 173 //-------------- 0x2F
FSL\B36402 5:69f1634cd40b 174 #define ANT_PAD_CTRL 0x30
FSL\B36402 5:69f1634cd40b 175 #define MISC_PAD_CTRL 0x31
FSL\B36402 5:69f1634cd40b 176 #define BSM_CTRL 0x32
FSL\B36402 5:69f1634cd40b 177 //--------------- 0x33
FSL\B36402 5:69f1634cd40b 178 #define _RNG 0x34
FSL\B36402 5:69f1634cd40b 179 #define RX_BYTE_COUNT 0x35
FSL\B36402 5:69f1634cd40b 180 #define RX_WTR_MARK 0x36
FSL\B36402 5:69f1634cd40b 181 #define SOFT_RESET 0x37
FSL\B36402 5:69f1634cd40b 182 #define TXDELAY 0x38
FSL\B36402 5:69f1634cd40b 183 #define ACKDELAY 0x39
FSL\B36402 5:69f1634cd40b 184 #define SEQ_MGR_CTRL 0x3A
FSL\B36402 5:69f1634cd40b 185 #define SEQ_MGR_STS 0x3B
FSL\B36402 5:69f1634cd40b 186 #define SEQ_T_STS 0x3C
FSL\B36402 5:69f1634cd40b 187 #define ABORT_STS 0x3D
FSL\B36402 5:69f1634cd40b 188 #define CCCA_BUSY_CNT 0x3E
FSL\B36402 5:69f1634cd40b 189 #define SRC_ADDR_CHECKSUM1 0x3F
FSL\B36402 5:69f1634cd40b 190 #define SRC_ADDR_CHECKSUM2 0x40
FSL\B36402 5:69f1634cd40b 191 #define SRC_TBL_VALID1 0x41
FSL\B36402 5:69f1634cd40b 192 #define SRC_TBL_VALID2 0x42
FSL\B36402 5:69f1634cd40b 193 #define FILTERFAIL_CODE1 0x43
FSL\B36402 5:69f1634cd40b 194 #define FILTERFAIL_CODE2 0x44
FSL\B36402 5:69f1634cd40b 195 #define SLOT_PRELOAD 0x45
FSL\B36402 5:69f1634cd40b 196 //---------------- 0x46
FSL\B36402 5:69f1634cd40b 197 #define CORR_VT 0x47
FSL\B36402 5:69f1634cd40b 198 #define SYNC_CTRL 0x48
FSL\B36402 5:69f1634cd40b 199 #define PN_LSB_0 0x49
FSL\B36402 5:69f1634cd40b 200 #define PN_LSB_1 0x4A
FSL\B36402 5:69f1634cd40b 201 #define PN_MSB_0 0x4B
FSL\B36402 5:69f1634cd40b 202 #define PN_MSB_1 0x4C
FSL\B36402 5:69f1634cd40b 203 #define CORR_NVAL 0x4D
FSL\B36402 5:69f1634cd40b 204 #define TX_MODE_CTRL 0x4E
FSL\B36402 5:69f1634cd40b 205 #define SNF_THR 0x4F
FSL\B36402 5:69f1634cd40b 206 #define FAD_THR 0x50
FSL\B36402 5:69f1634cd40b 207 #define ANT_AGC_CTRL 0x51
FSL\B36402 5:69f1634cd40b 208 #define AGC_THR1 0x52
FSL\B36402 5:69f1634cd40b 209 #define AGC_THR2 0x53
FSL\B36402 5:69f1634cd40b 210 #define AGC_HYS 0x54
FSL\B36402 5:69f1634cd40b 211 #define AFC 0x55
FSL\B36402 5:69f1634cd40b 212 //--------------- 0x56
FSL\B36402 5:69f1634cd40b 213 //--------------- 0x57
FSL\B36402 5:69f1634cd40b 214 #define PHY_STS 0x58
FSL\B36402 5:69f1634cd40b 215 #define RX_MAX_CORR 0x59
FSL\B36402 5:69f1634cd40b 216 #define RX_MAX_PREAMBLE 0x5A
FSL\B36402 5:69f1634cd40b 217 #define RSSI 0x5B
FSL\B36402 5:69f1634cd40b 218 //--------------- 0x5C
FSL\B36402 5:69f1634cd40b 219 //--------------- 0x5D
FSL\B36402 5:69f1634cd40b 220 #define PLL_DIG_CTRL 0x5E
FSL\B36402 5:69f1634cd40b 221 #define VCO_CAL 0x5F
FSL\B36402 5:69f1634cd40b 222 #define VCO_BEST_DIFF 0x60
FSL\B36402 5:69f1634cd40b 223 #define VCO_BIAS 0x61
FSL\B36402 5:69f1634cd40b 224 #define KMOD_CTRL 0x62
FSL\B36402 5:69f1634cd40b 225 #define KMOD_CAL 0x63
FSL\B36402 5:69f1634cd40b 226 #define PA_CAL 0x64
FSL\B36402 5:69f1634cd40b 227 #define PA_PWRCAL 0x65
FSL\B36402 5:69f1634cd40b 228 #define ATT_RSSI1 0x66
FSL\B36402 5:69f1634cd40b 229 #define ATT_RSSI2 0x67
FSL\B36402 5:69f1634cd40b 230 #define RSSI_OFFSET 0x68
FSL\B36402 5:69f1634cd40b 231 #define RSSI_SLOPE 0x69
FSL\B36402 5:69f1634cd40b 232 #define RSSI_CAL1 0x6A
FSL\B36402 5:69f1634cd40b 233 #define RSSI_CAL2 0x6B
FSL\B36402 5:69f1634cd40b 234 //--------------- 0x6C
FSL\B36402 5:69f1634cd40b 235 //--------------- 0x6D
FSL\B36402 5:69f1634cd40b 236 #define XTAL_CTRL 0x6E
FSL\B36402 5:69f1634cd40b 237 #define XTAL_COMP_MIN 0x6F
FSL\B36402 5:69f1634cd40b 238 #define XTAL_COMP_MAX 0x70
FSL\B36402 5:69f1634cd40b 239 #define XTAL_GM 0x71
FSL\B36402 5:69f1634cd40b 240 //--------------- 0x72
FSL\B36402 5:69f1634cd40b 241 //--------------- 0x73
FSL\B36402 5:69f1634cd40b 242 #define LNA_TUNE 0x74
FSL\B36402 5:69f1634cd40b 243 #define LNA_AGCGAIN 0x75
FSL\B36402 5:69f1634cd40b 244 //--------------- 0x76
FSL\B36402 5:69f1634cd40b 245 //--------------- 0x77
FSL\B36402 5:69f1634cd40b 246 #define CHF_PMA_GAIN 0x78
FSL\B36402 5:69f1634cd40b 247 #define CHF_IBUF 0x79
FSL\B36402 5:69f1634cd40b 248 #define CHF_QBUF 0x7A
FSL\B36402 5:69f1634cd40b 249 #define CHF_IRIN 0x7B
FSL\B36402 5:69f1634cd40b 250 #define CHF_QRIN 0x7C
FSL\B36402 5:69f1634cd40b 251 #define CHF_IL 0x7D
FSL\B36402 5:69f1634cd40b 252 #define CHF_QL 0x7E
FSL\B36402 5:69f1634cd40b 253 #define CHF_CC1 0x7F
FSL\B36402 5:69f1634cd40b 254 #define CHF_CCL 0x80
FSL\B36402 5:69f1634cd40b 255 #define CHF_CC2 0x81
FSL\B36402 5:69f1634cd40b 256 #define CHF_IROUT 0x82
FSL\B36402 5:69f1634cd40b 257 #define CHF_QROUT 0x83
FSL\B36402 5:69f1634cd40b 258 //--------------- 0x84
FSL\B36402 5:69f1634cd40b 259 //--------------- 0x85
FSL\B36402 5:69f1634cd40b 260 #define RSSI_CTRL 0x86
FSL\B36402 5:69f1634cd40b 261 //--------------- 0x87
FSL\B36402 5:69f1634cd40b 262 //--------------- 0x88
FSL\B36402 5:69f1634cd40b 263 #define PA_BIAS 0x89
FSL\B36402 5:69f1634cd40b 264 #define PA_TUNING 0x8A
FSL\B36402 5:69f1634cd40b 265 //--------------- 0x8B
FSL\B36402 5:69f1634cd40b 266 //--------------- 0x8C
FSL\B36402 5:69f1634cd40b 267 #define PMC_HP_TRIM 0x8D
FSL\B36402 5:69f1634cd40b 268 #define VREGA_TRIM 0x8E
FSL\B36402 5:69f1634cd40b 269 //--------------- 0x8F
FSL\B36402 5:69f1634cd40b 270 //--------------- 0x90
FSL\B36402 5:69f1634cd40b 271 #define VCO_CTRL1 0x91
FSL\B36402 5:69f1634cd40b 272 #define VCO_CTRL2 0x92
FSL\B36402 5:69f1634cd40b 273 //--------------- 0x93
FSL\B36402 5:69f1634cd40b 274 //--------------- 0x94
FSL\B36402 5:69f1634cd40b 275 #define ANA_SPARE_OUT1 0x95
FSL\B36402 5:69f1634cd40b 276 #define ANA_SPARE_OUT2 0x96
FSL\B36402 5:69f1634cd40b 277 #define ANA_SPARE_IN 0x97
FSL\B36402 5:69f1634cd40b 278 #define MISCELLANEOUS 0x98
FSL\B36402 5:69f1634cd40b 279 //--------------- 0x99
FSL\B36402 5:69f1634cd40b 280 #define SEQ_MGR_OVRD0 0x9A
FSL\B36402 5:69f1634cd40b 281 #define SEQ_MGR_OVRD1 0x9B
FSL\B36402 5:69f1634cd40b 282 #define SEQ_MGR_OVRD2 0x9C
FSL\B36402 5:69f1634cd40b 283 #define SEQ_MGR_OVRD3 0x9D
FSL\B36402 5:69f1634cd40b 284 #define SEQ_MGR_OVRD4 0x9E
FSL\B36402 5:69f1634cd40b 285 #define SEQ_MGR_OVRD5 0x9F
FSL\B36402 5:69f1634cd40b 286 #define SEQ_MGR_OVRD6 0xA0
FSL\B36402 5:69f1634cd40b 287 #define SEQ_MGR_OVRD7 0xA1
FSL\B36402 5:69f1634cd40b 288 //--------------- 0xA2
FSL\B36402 5:69f1634cd40b 289 #define TESTMODE_CTRL 0xA3
FSL\B36402 5:69f1634cd40b 290 #define DTM_CTRL1 0xA4
FSL\B36402 5:69f1634cd40b 291 #define DTM_CTRL2 0xA5
FSL\B36402 5:69f1634cd40b 292 #define ATM_CTRL1 0xA6
FSL\B36402 5:69f1634cd40b 293 #define ATM_CTRL2 0xA7
FSL\B36402 5:69f1634cd40b 294 #define ATM_CTRL3 0xA8
FSL\B36402 5:69f1634cd40b 295 //--------------- 0xA9
FSL\B36402 5:69f1634cd40b 296 #define LIM_FE_TEST_CTRL 0xAA
FSL\B36402 5:69f1634cd40b 297 #define CHF_TEST_CTRL 0xAB
FSL\B36402 5:69f1634cd40b 298 #define VCO_TEST_CTRL 0xAC
FSL\B36402 5:69f1634cd40b 299 #define PLL_TEST_CTRL 0xAD
FSL\B36402 5:69f1634cd40b 300 #define PA_TEST_CTRL 0xAE
FSL\B36402 5:69f1634cd40b 301 #define PMC_TEST_CTRL 0xAF
FSL\B36402 5:69f1634cd40b 302 #define SCAN_DTM_PROTECT_1 0xFE
FSL\B36402 5:69f1634cd40b 303 #define SCAN_DTM_PROTECT_0 0xFF
FSL\B36402 5:69f1634cd40b 304
FSL\B36402 5:69f1634cd40b 305 // IRQSTS1 bits
FSL\B36402 5:69f1634cd40b 306 #define cIRQSTS1_RX_FRM_PEND (1<<7)
FSL\B36402 5:69f1634cd40b 307 #define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
FSL\B36402 5:69f1634cd40b 308 #define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
FSL\B36402 5:69f1634cd40b 309 #define cIRQSTS1_RXWTRMRKIRQ (1<<4)
FSL\B36402 5:69f1634cd40b 310 #define cIRQSTS1_CCAIRQ (1<<3)
FSL\B36402 5:69f1634cd40b 311 #define cIRQSTS1_RXIRQ (1<<2)
FSL\B36402 5:69f1634cd40b 312 #define cIRQSTS1_TXIRQ (1<<1)
FSL\B36402 5:69f1634cd40b 313 #define cIRQSTS1_SEQIRQ (1<<0)
FSL\B36402 5:69f1634cd40b 314
FSL\B36402 5:69f1634cd40b 315 typedef union regIRQSTS1_tag{
FSL\B36402 5:69f1634cd40b 316 uint8_t byte;
FSL\B36402 5:69f1634cd40b 317 struct{
FSL\B36402 5:69f1634cd40b 318 uint8_t SEQIRQ:1;
FSL\B36402 5:69f1634cd40b 319 uint8_t TXIRQ:1;
FSL\B36402 5:69f1634cd40b 320 uint8_t RXIRQ:1;
FSL\B36402 5:69f1634cd40b 321 uint8_t CCAIRQ:1;
FSL\B36402 5:69f1634cd40b 322 uint8_t RXWTRMRKIRQ:1;
FSL\B36402 5:69f1634cd40b 323 uint8_t FILTERFAIL_IRQ:1;
FSL\B36402 5:69f1634cd40b 324 uint8_t PLL_UNLOCK_IRQ:1;
FSL\B36402 5:69f1634cd40b 325 uint8_t RX_FRM_PEND:1;
FSL\B36402 5:69f1634cd40b 326 }bit;
FSL\B36402 5:69f1634cd40b 327 } regIRQSTS1_t;
FSL\B36402 5:69f1634cd40b 328
FSL\B36402 5:69f1634cd40b 329 // IRQSTS2 bits
FSL\B36402 5:69f1634cd40b 330 #define cIRQSTS2_CRCVALID (1<<7)
FSL\B36402 5:69f1634cd40b 331 #define cIRQSTS2_CCA (1<<6)
FSL\B36402 5:69f1634cd40b 332 #define cIRQSTS2_SRCADDR (1<<5)
FSL\B36402 5:69f1634cd40b 333 #define cIRQSTS2_PI (1<<4)
FSL\B36402 5:69f1634cd40b 334 #define cIRQSTS2_TMRSTATUS (1<<3)
FSL\B36402 5:69f1634cd40b 335 #define cIRQSTS2_ASM_IRQ (1<<2)
FSL\B36402 5:69f1634cd40b 336 #define cIRQSTS2_PB_ERR_IRQ (1<<1)
FSL\B36402 5:69f1634cd40b 337 #define cIRQSTS2_WAKE_IRQ (1<<0)
FSL\B36402 5:69f1634cd40b 338
FSL\B36402 5:69f1634cd40b 339 typedef union regIRQSTS2_tag{
FSL\B36402 5:69f1634cd40b 340 uint8_t byte;
FSL\B36402 5:69f1634cd40b 341 struct{
FSL\B36402 5:69f1634cd40b 342 uint8_t WAKE_IRQ:1;
FSL\B36402 5:69f1634cd40b 343 uint8_t PB_ERR_IRQ:1;
FSL\B36402 5:69f1634cd40b 344 uint8_t ASM_IRQ:1;
FSL\B36402 5:69f1634cd40b 345 uint8_t TMRSTATUS:1;
FSL\B36402 5:69f1634cd40b 346 uint8_t PI:1;
FSL\B36402 5:69f1634cd40b 347 uint8_t SRCADDR:1;
FSL\B36402 5:69f1634cd40b 348 uint8_t CCA:1;
FSL\B36402 5:69f1634cd40b 349 uint8_t CRCVALID:1;
FSL\B36402 5:69f1634cd40b 350 }bit;
FSL\B36402 5:69f1634cd40b 351 } regIRQSTS2_t;
FSL\B36402 5:69f1634cd40b 352
FSL\B36402 5:69f1634cd40b 353 // IRQSTS3 bits
FSL\B36402 5:69f1634cd40b 354 #define cIRQSTS3_TMR4MSK (1<<7)
FSL\B36402 5:69f1634cd40b 355 #define cIRQSTS3_TMR3MSK (1<<6)
FSL\B36402 5:69f1634cd40b 356 #define cIRQSTS3_TMR2MSK (1<<5)
FSL\B36402 5:69f1634cd40b 357 #define cIRQSTS3_TMR1MSK (1<<4)
FSL\B36402 5:69f1634cd40b 358 #define cIRQSTS3_TMR4IRQ (1<<3)
FSL\B36402 5:69f1634cd40b 359 #define cIRQSTS3_TMR3IRQ (1<<2)
FSL\B36402 5:69f1634cd40b 360 #define cIRQSTS3_TMR2IRQ (1<<1)
FSL\B36402 5:69f1634cd40b 361 #define cIRQSTS3_TMR1IRQ (1<<0)
FSL\B36402 5:69f1634cd40b 362
FSL\B36402 5:69f1634cd40b 363 typedef union regIRQSTS3_tag{
FSL\B36402 5:69f1634cd40b 364 uint8_t byte;
FSL\B36402 5:69f1634cd40b 365 struct{
FSL\B36402 5:69f1634cd40b 366 uint8_t TMR1IRQ:1;
FSL\B36402 5:69f1634cd40b 367 uint8_t TMR2IRQ:1;
FSL\B36402 5:69f1634cd40b 368 uint8_t TMR3IRQ:1;
FSL\B36402 5:69f1634cd40b 369 uint8_t TMR4IRQ:1;
FSL\B36402 5:69f1634cd40b 370 uint8_t TMR1MSK:1;
FSL\B36402 5:69f1634cd40b 371 uint8_t TMR2MSK:1;
FSL\B36402 5:69f1634cd40b 372 uint8_t TMR3MSK:1;
FSL\B36402 5:69f1634cd40b 373 uint8_t TMR4MSK:1;
FSL\B36402 5:69f1634cd40b 374 }bit;
FSL\B36402 5:69f1634cd40b 375 } regIRQSTS3_t;
FSL\B36402 5:69f1634cd40b 376
FSL\B36402 5:69f1634cd40b 377 // PHY_CTRL1 bits
FSL\B36402 5:69f1634cd40b 378 #define cPHY_CTRL1_TMRTRIGEN (1<<7)
FSL\B36402 5:69f1634cd40b 379 #define cPHY_CTRL1_SLOTTED (1<<6)
FSL\B36402 5:69f1634cd40b 380 #define cPHY_CTRL1_CCABFRTX (1<<5)
FSL\B36402 5:69f1634cd40b 381 #define cPHY_CTRL1_RXACKRQD (1<<4)
FSL\B36402 5:69f1634cd40b 382 #define cPHY_CTRL1_AUTOACK (1<<3)
FSL\B36402 5:69f1634cd40b 383 #define cPHY_CTRL1_XCVSEQ (7<<0)
FSL\B36402 5:69f1634cd40b 384
FSL\B36402 5:69f1634cd40b 385 typedef union regPHY_CTRL1_tag{
FSL\B36402 5:69f1634cd40b 386 uint8_t byte;
FSL\B36402 5:69f1634cd40b 387 struct{
FSL\B36402 5:69f1634cd40b 388 uint8_t XCVSEQ:3;
FSL\B36402 5:69f1634cd40b 389 uint8_t AUTOACK:1;
FSL\B36402 5:69f1634cd40b 390 uint8_t RXACKRQD:1;
FSL\B36402 5:69f1634cd40b 391 uint8_t CCABFRTX:1;
FSL\B36402 5:69f1634cd40b 392 uint8_t SLOTTED:1;
FSL\B36402 5:69f1634cd40b 393 uint8_t TMRTRIGEN:1;
FSL\B36402 5:69f1634cd40b 394 }bit;
FSL\B36402 5:69f1634cd40b 395 } regPHY_CTRL1_t;
FSL\B36402 5:69f1634cd40b 396
FSL\B36402 5:69f1634cd40b 397 // PHY_CTRL2 bits
FSL\B36402 5:69f1634cd40b 398 #define cPHY_CTRL2_CRC_MSK (1<<7)
FSL\B36402 5:69f1634cd40b 399 #define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
FSL\B36402 5:69f1634cd40b 400 #define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
FSL\B36402 5:69f1634cd40b 401 #define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
FSL\B36402 5:69f1634cd40b 402 #define cPHY_CTRL2_CCAMSK (1<<3)
FSL\B36402 5:69f1634cd40b 403 #define cPHY_CTRL2_RXMSK (1<<2)
FSL\B36402 5:69f1634cd40b 404 #define cPHY_CTRL2_TXMSK (1<<1)
FSL\B36402 5:69f1634cd40b 405 #define cPHY_CTRL2_SEQMSK (1<<0)
FSL\B36402 5:69f1634cd40b 406
FSL\B36402 5:69f1634cd40b 407 typedef union regPHY_CTRL2_tag{
FSL\B36402 5:69f1634cd40b 408 uint8_t byte;
FSL\B36402 5:69f1634cd40b 409 struct{
FSL\B36402 5:69f1634cd40b 410 uint8_t SEQMSK:1;
FSL\B36402 5:69f1634cd40b 411 uint8_t TXMSK:1;
FSL\B36402 5:69f1634cd40b 412 uint8_t RXMSK:1;
FSL\B36402 5:69f1634cd40b 413 uint8_t CCAMSK:1;
FSL\B36402 5:69f1634cd40b 414 uint8_t RX_WMRK_MSK:1;
FSL\B36402 5:69f1634cd40b 415 uint8_t FILTERFAIL_MSK:1;
FSL\B36402 5:69f1634cd40b 416 uint8_t PLL_UNLOCK_MSK:1;
FSL\B36402 5:69f1634cd40b 417 uint8_t CRC_MSK:1;
FSL\B36402 5:69f1634cd40b 418 }bit;
FSL\B36402 5:69f1634cd40b 419 } regPHY_CTRL2_t;
FSL\B36402 5:69f1634cd40b 420
FSL\B36402 5:69f1634cd40b 421 // PHY_CTRL3 bits
FSL\B36402 5:69f1634cd40b 422 #define cPHY_CTRL3_TMR4CMP_EN (1<<7)
FSL\B36402 5:69f1634cd40b 423 #define cPHY_CTRL3_TMR3CMP_EN (1<<6)
FSL\B36402 5:69f1634cd40b 424 #define cPHY_CTRL3_TMR2CMP_EN (1<<5)
FSL\B36402 5:69f1634cd40b 425 #define cPHY_CTRL3_TMR1CMP_EN (1<<4)
FSL\B36402 5:69f1634cd40b 426 #define cPHY_CTRL3_ASM_MSK (1<<2)
FSL\B36402 5:69f1634cd40b 427 #define cPHY_CTRL3_PB_ERR_MSK (1<<1)
FSL\B36402 5:69f1634cd40b 428 #define cPHY_CTRL3_WAKE_MSK (1<<0)
FSL\B36402 5:69f1634cd40b 429
FSL\B36402 5:69f1634cd40b 430 typedef union regPHY_CTRL3_tag{
FSL\B36402 5:69f1634cd40b 431 uint8_t byte;
FSL\B36402 5:69f1634cd40b 432 struct{
FSL\B36402 5:69f1634cd40b 433 uint8_t WAKE_MSK:1;
FSL\B36402 5:69f1634cd40b 434 uint8_t PB_ERR_MSK:1;
FSL\B36402 5:69f1634cd40b 435 uint8_t ASM_MSK:1;
FSL\B36402 5:69f1634cd40b 436 uint8_t RESERVED:1;
FSL\B36402 5:69f1634cd40b 437 uint8_t TMR1CMP_EN:1;
FSL\B36402 5:69f1634cd40b 438 uint8_t TMR2CMP_EN:1;
FSL\B36402 5:69f1634cd40b 439 uint8_t TMR3CMP_EN:1;
FSL\B36402 5:69f1634cd40b 440 uint8_t TMR4CMP_EN:1;
FSL\B36402 5:69f1634cd40b 441 }bit;
FSL\B36402 5:69f1634cd40b 442 } regPHY_CTRL3_t;
FSL\B36402 5:69f1634cd40b 443
FSL\B36402 5:69f1634cd40b 444 // RX_FRM_LEN bits
FSL\B36402 5:69f1634cd40b 445 #define cRX_FRAME_LENGTH (0x7F)
FSL\B36402 5:69f1634cd40b 446
FSL\B36402 5:69f1634cd40b 447 // PHY_CTRL4 bits
FSL\B36402 5:69f1634cd40b 448 #define cPHY_CTRL4_TRCV_MSK (1<<7)
FSL\B36402 5:69f1634cd40b 449 #define cPHY_CTRL4_TC3TMOUT (1<<6)
FSL\B36402 5:69f1634cd40b 450 #define cPHY_CTRL4_PANCORDNTR0 (1<<5)
FSL\B36402 5:69f1634cd40b 451 #define cPHY_CTRL4_CCATYPE (3<<0)
FSL\B36402 5:69f1634cd40b 452 #define cPHY_CTRL4_CCATYPE_Shift_c (3)
FSL\B36402 5:69f1634cd40b 453 #define cPHY_CTRL4_TMRLOAD (1<<2)
FSL\B36402 5:69f1634cd40b 454 #define cPHY_CTRL4_PROMISCUOUS (1<<1)
FSL\B36402 5:69f1634cd40b 455 #define cPHY_CTRL4_TC2PRIME_EN (1<<0)
FSL\B36402 5:69f1634cd40b 456
FSL\B36402 5:69f1634cd40b 457 typedef union regPHY_CTRL4_tag{
FSL\B36402 5:69f1634cd40b 458 uint8_t byte;
FSL\B36402 5:69f1634cd40b 459 struct{
FSL\B36402 5:69f1634cd40b 460 uint8_t TC2PRIME_EN:1;
FSL\B36402 5:69f1634cd40b 461 uint8_t PROMISCUOUS:1;
FSL\B36402 5:69f1634cd40b 462 uint8_t TMRLOAD:1;
FSL\B36402 5:69f1634cd40b 463 uint8_t CCATYPE:2;
FSL\B36402 5:69f1634cd40b 464 uint8_t PANCORDNTR0:1;
FSL\B36402 5:69f1634cd40b 465 uint8_t TC3TMOUT:1;
FSL\B36402 5:69f1634cd40b 466 uint8_t TRCV_MSK:1;
FSL\B36402 5:69f1634cd40b 467 }bit;
FSL\B36402 5:69f1634cd40b 468 } regPHY_CTRL4_t;
FSL\B36402 5:69f1634cd40b 469
FSL\B36402 5:69f1634cd40b 470 // SRC_CTRL bits
FSL\B36402 5:69f1634cd40b 471 #define cSRC_CTRL_INDEX (0x0F)
FSL\B36402 5:69f1634cd40b 472 #define cSRC_CTRL_INDEX_Shift_c (4)
FSL\B36402 5:69f1634cd40b 473 #define cSRC_CTRL_ACK_FRM_PND (1<<3)
FSL\B36402 5:69f1634cd40b 474 #define cSRC_CTRL_SRCADDR_EN (1<<2)
FSL\B36402 5:69f1634cd40b 475 #define cSRC_CTRL_INDEX_EN (1<<1)
FSL\B36402 5:69f1634cd40b 476 #define cSRC_CTRL_INDEX_DISABLE (1<<0)
FSL\B36402 5:69f1634cd40b 477
FSL\B36402 5:69f1634cd40b 478 typedef union regSRC_CTRL_tag{
FSL\B36402 5:69f1634cd40b 479 uint8_t byte;
FSL\B36402 5:69f1634cd40b 480 struct{
FSL\B36402 5:69f1634cd40b 481 uint8_t INDEX_DISABLE:1;
FSL\B36402 5:69f1634cd40b 482 uint8_t INDEX_EN:1;
FSL\B36402 5:69f1634cd40b 483 uint8_t SRCADDR_EN:1;
FSL\B36402 5:69f1634cd40b 484 uint8_t ACK_FRM_PND:1;
FSL\B36402 5:69f1634cd40b 485 uint8_t INDEX:4;
FSL\B36402 5:69f1634cd40b 486 }bit;
FSL\B36402 5:69f1634cd40b 487 } regSRC_CTRL_t;
FSL\B36402 5:69f1634cd40b 488
FSL\B36402 5:69f1634cd40b 489 // ASM_CTRL1 bits
FSL\B36402 5:69f1634cd40b 490 #define cASM_CTRL1_CLEAR (1<<7)
FSL\B36402 5:69f1634cd40b 491 #define cASM_CTRL1_START (1<<6)
FSL\B36402 5:69f1634cd40b 492 #define cASM_CTRL1_SELFTST (1<<5)
FSL\B36402 5:69f1634cd40b 493 #define cASM_CTRL1_CTR (1<<4)
FSL\B36402 5:69f1634cd40b 494 #define cASM_CTRL1_CBC (1<<3)
FSL\B36402 5:69f1634cd40b 495 #define cASM_CTRL1_AES (1<<2)
FSL\B36402 5:69f1634cd40b 496 #define cASM_CTRL1_LOAD_MAC (1<<1)
FSL\B36402 5:69f1634cd40b 497
FSL\B36402 5:69f1634cd40b 498 // ASM_CTRL2 bits
FSL\B36402 5:69f1634cd40b 499 #define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
FSL\B36402 5:69f1634cd40b 500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
FSL\B36402 5:69f1634cd40b 501 #define cASM_CTRL2_TSTPAS (1<<1)
FSL\B36402 5:69f1634cd40b 502
FSL\B36402 5:69f1634cd40b 503 // CLK_OUT_CTRL bits
FSL\B36402 5:69f1634cd40b 504 #define cCLK_OUT_CTRL_EXTEND (1<<7)
FSL\B36402 5:69f1634cd40b 505 #define cCLK_OUT_CTRL_HIZ (1<<6)
FSL\B36402 5:69f1634cd40b 506 #define cCLK_OUT_CTRL_SR (1<<5)
FSL\B36402 5:69f1634cd40b 507 #define cCLK_OUT_CTRL_DS (1<<4)
FSL\B36402 5:69f1634cd40b 508 #define cCLK_OUT_CTRL_EN (1<<3)
FSL\B36402 5:69f1634cd40b 509 #define cCLK_OUT_CTRL_DIV (7)
FSL\B36402 5:69f1634cd40b 510
FSL\B36402 5:69f1634cd40b 511 // PWR_MODES bits
FSL\B36402 5:69f1634cd40b 512 #define cPWR_MODES_XTAL_READY (1<<5)
FSL\B36402 5:69f1634cd40b 513 #define cPWR_MODES_XTALEN (1<<4)
FSL\B36402 5:69f1634cd40b 514 #define cPWR_MODES_ASM_CLK_EN (1<<3)
FSL\B36402 5:69f1634cd40b 515 #define cPWR_MODES_AUTODOZE (1<<1)
FSL\B36402 5:69f1634cd40b 516 #define cPWR_MODES_PMC_MODE (1<<0)
FSL\B36402 5:69f1634cd40b 517
FSL\B36402 5:69f1634cd40b 518 // RX_FRAME_FILTER bits
FSL\B36402 5:69f1634cd40b 519 #define cRX_FRAME_FLT_FRM_VER (0xC0)
FSL\B36402 5:69f1634cd40b 520 #define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
FSL\B36402 5:69f1634cd40b 521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
FSL\B36402 5:69f1634cd40b 522 #define cRX_FRAME_FLT_NS_FT (1<<4)
FSL\B36402 5:69f1634cd40b 523 #define cRX_FRAME_FLT_CMD_FT (1<<3)
FSL\B36402 5:69f1634cd40b 524 #define cRX_FRAME_FLT_ACK_FT (1<<2)
FSL\B36402 5:69f1634cd40b 525 #define cRX_FRAME_FLT_DATA_FT (1<<1)
FSL\B36402 5:69f1634cd40b 526 #define cRX_FRAME_FLT_BEACON_FT (1<<0)
FSL\B36402 5:69f1634cd40b 527
FSL\B36402 5:69f1634cd40b 528 typedef union regRX_FRAME_FILTER_tag{
FSL\B36402 5:69f1634cd40b 529 uint8_t byte;
FSL\B36402 5:69f1634cd40b 530 struct{
FSL\B36402 5:69f1634cd40b 531 uint8_t FRAME_FLT_BEACON_FT:1;
FSL\B36402 5:69f1634cd40b 532 uint8_t FRAME_FLT_DATA_FT:1;
FSL\B36402 5:69f1634cd40b 533 uint8_t FRAME_FLT_ACK_FT:1;
FSL\B36402 5:69f1634cd40b 534 uint8_t FRAME_FLT_CMD_FT:1;
FSL\B36402 5:69f1634cd40b 535 uint8_t FRAME_FLT_NS_FT:1;
FSL\B36402 5:69f1634cd40b 536 uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
FSL\B36402 5:69f1634cd40b 537 uint8_t FRAME_FLT_FRM_VER:2;
FSL\B36402 5:69f1634cd40b 538 }bit;
FSL\B36402 5:69f1634cd40b 539 } regRX_FRAME_FILTER_t;
FSL\B36402 5:69f1634cd40b 540
FSL\B36402 5:69f1634cd40b 541 // DUAL_PAN_CTRL bits
FSL\B36402 5:69f1634cd40b 542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
FSL\B36402 5:69f1634cd40b 543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
FSL\B36402 5:69f1634cd40b 544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
FSL\B36402 5:69f1634cd40b 545 #define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
FSL\B36402 5:69f1634cd40b 546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
FSL\B36402 5:69f1634cd40b 547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
FSL\B36402 5:69f1634cd40b 548
FSL\B36402 5:69f1634cd40b 549 // DUAL_PAN_STS bits
FSL\B36402 5:69f1634cd40b 550 #define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
FSL\B36402 5:69f1634cd40b 551 #define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
FSL\B36402 5:69f1634cd40b 552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
FSL\B36402 5:69f1634cd40b 553
FSL\B36402 5:69f1634cd40b 554 // CCA_CTRL bits
FSL\B36402 5:69f1634cd40b 555 #define cCCA_CTRL_AGC_FRZ_EN (1<<6)
FSL\B36402 5:69f1634cd40b 556 #define cCCA_CTRL_CONT_RSSI_EN (1<<5)
FSL\B36402 5:69f1634cd40b 557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
FSL\B36402 5:69f1634cd40b 558 #define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
FSL\B36402 5:69f1634cd40b 559 #define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
FSL\B36402 5:69f1634cd40b 560 #define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
FSL\B36402 5:69f1634cd40b 561 #define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
FSL\B36402 5:69f1634cd40b 562
FSL\B36402 5:69f1634cd40b 563 // GPIO_DATA bits
FSL\B36402 5:69f1634cd40b 564 #define cGPIO_DATA_7 (1<<7)
FSL\B36402 5:69f1634cd40b 565 #define cGPIO_DATA_6 (1<<6)
FSL\B36402 5:69f1634cd40b 566 #define cGPIO_DATA_5 (1<<5)
FSL\B36402 5:69f1634cd40b 567 #define cGPIO_DATA_4 (1<<4)
FSL\B36402 5:69f1634cd40b 568 #define cGPIO_DATA_3 (1<<3)
FSL\B36402 5:69f1634cd40b 569 #define cGPIO_DATA_2 (1<<2)
FSL\B36402 5:69f1634cd40b 570 #define cGPIO_DATA_1 (1<<1)
FSL\B36402 5:69f1634cd40b 571 #define cGPIO_DATA_0 (1<<0)
FSL\B36402 5:69f1634cd40b 572
FSL\B36402 5:69f1634cd40b 573 // GPIO_DIR bits
FSL\B36402 5:69f1634cd40b 574 #define cGPIO_DIR_7 (1<<7)
FSL\B36402 5:69f1634cd40b 575 #define cGPIO_DIR_6 (1<<6)
FSL\B36402 5:69f1634cd40b 576 #define cGPIO_DIR_5 (1<<5)
FSL\B36402 5:69f1634cd40b 577 #define cGPIO_DIR_4 (1<<4)
FSL\B36402 5:69f1634cd40b 578 #define cGPIO_DIR_3 (1<<3)
FSL\B36402 5:69f1634cd40b 579 #define cGPIO_DIR_2 (1<<2)
FSL\B36402 5:69f1634cd40b 580 #define cGPIO_DIR_1 (1<<1)
FSL\B36402 5:69f1634cd40b 581 #define cGPIO_DIR_0 (1<<0)
FSL\B36402 5:69f1634cd40b 582
FSL\B36402 5:69f1634cd40b 583 // GPIO_PUL_EN bits
FSL\B36402 5:69f1634cd40b 584 #define cGPIO_PUL_EN_7 (1<<7)
FSL\B36402 5:69f1634cd40b 585 #define cGPIO_PUL_EN_6 (1<<6)
FSL\B36402 5:69f1634cd40b 586 #define cGPIO_PUL_EN_5 (1<<5)
FSL\B36402 5:69f1634cd40b 587 #define cGPIO_PUL_EN_4 (1<<4)
FSL\B36402 5:69f1634cd40b 588 #define cGPIO_PUL_EN_3 (1<<3)
FSL\B36402 5:69f1634cd40b 589 #define cGPIO_PUL_EN_2 (1<<2)
FSL\B36402 5:69f1634cd40b 590 #define cGPIO_PUL_EN_1 (1<<1)
FSL\B36402 5:69f1634cd40b 591 #define cGPIO_PUL_EN_0 (1<<0)
FSL\B36402 5:69f1634cd40b 592
FSL\B36402 5:69f1634cd40b 593 // GPIO_PUL_SEL bits
FSL\B36402 5:69f1634cd40b 594 #define cGPIO_PUL_SEL_7 (1<<7)
FSL\B36402 5:69f1634cd40b 595 #define cGPIO_PUL_SEL_6 (1<<6)
FSL\B36402 5:69f1634cd40b 596 #define cGPIO_PUL_SEL_5 (1<<5)
FSL\B36402 5:69f1634cd40b 597 #define cGPIO_PUL_SEL_4 (1<<4)
FSL\B36402 5:69f1634cd40b 598 #define cGPIO_PUL_SEL_3 (1<<3)
FSL\B36402 5:69f1634cd40b 599 #define cGPIO_PUL_SEL_2 (1<<2)
FSL\B36402 5:69f1634cd40b 600 #define cGPIO_PUL_SEL_1 (1<<1)
FSL\B36402 5:69f1634cd40b 601 #define cGPIO_PUL_SEL_0 (1<<0)
FSL\B36402 5:69f1634cd40b 602
FSL\B36402 5:69f1634cd40b 603 // GPIO_DS bits
FSL\B36402 5:69f1634cd40b 604 #define cGPIO_DS_7 (1<<7)
FSL\B36402 5:69f1634cd40b 605 #define cGPIO_DS_6 (1<<6)
FSL\B36402 5:69f1634cd40b 606 #define cGPIO_DS_5 (1<<5)
FSL\B36402 5:69f1634cd40b 607 #define cGPIO_DS_4 (1<<4)
FSL\B36402 5:69f1634cd40b 608 #define cGPIO_DS_3 (1<<3)
FSL\B36402 5:69f1634cd40b 609 #define cGPIO_DS_2 (1<<2)
FSL\B36402 5:69f1634cd40b 610 #define cGPIO_DS_1 (1<<1)
FSL\B36402 5:69f1634cd40b 611 #define cGPIO_DS_0 (1<<0)
FSL\B36402 5:69f1634cd40b 612
FSL\B36402 5:69f1634cd40b 613 // SPI_CTRL bits
FSL\B36402 5:69f1634cd40b 614 //#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
FSL\B36402 5:69f1634cd40b 615 //#define cSPI_CTRL_PB_PROTECT (1<<0)
FSL\B36402 5:69f1634cd40b 616
FSL\B36402 5:69f1634cd40b 617 // ANT_PAD_CTRL bits
FSL\B36402 5:69f1634cd40b 618 #define cANT_PAD_CTRL_ANTX_POL (0x0F)
FSL\B36402 5:69f1634cd40b 619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
FSL\B36402 5:69f1634cd40b 620 #define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
FSL\B36402 5:69f1634cd40b 621 #define cANT_PAD_CTRL_ANTX_HZ (1<<2)
FSL\B36402 5:69f1634cd40b 622 #define cANT_PAD_CTRL_ANTX_EN (3)
FSL\B36402 5:69f1634cd40b 623
FSL\B36402 5:69f1634cd40b 624 // MISC_PAD_CTRL bits
FSL\B36402 5:69f1634cd40b 625 #define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
FSL\B36402 5:69f1634cd40b 626 #define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
FSL\B36402 5:69f1634cd40b 627 #define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
FSL\B36402 5:69f1634cd40b 628 #define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
FSL\B36402 5:69f1634cd40b 629
FSL\B36402 5:69f1634cd40b 630 // ANT_AGC_CTRL bits
FSL\B36402 5:69f1634cd40b 631 #define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
FSL\B36402 5:69f1634cd40b 632 #define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
FSL\B36402 5:69f1634cd40b 633 #define cANT_AGC_CTRL_ANTX_Shift_c (1)
FSL\B36402 5:69f1634cd40b 634 #define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
FSL\B36402 5:69f1634cd40b 635
FSL\B36402 5:69f1634cd40b 636 // BSM_CTRL bits
FSL\B36402 5:69f1634cd40b 637 #define cBSM_CTRL_BSM_EN (1<<0)
FSL\B36402 5:69f1634cd40b 638
FSL\B36402 5:69f1634cd40b 639 // SOFT_RESET bits
FSL\B36402 5:69f1634cd40b 640 #define cSOFT_RESET_SOG_RST (1<<7)
FSL\B36402 5:69f1634cd40b 641 #define cSOFT_RESET_REGS_RST (1<<4)
FSL\B36402 5:69f1634cd40b 642 #define cSOFT_RESET_PLL_RST (1<<3)
FSL\B36402 5:69f1634cd40b 643 #define cSOFT_RESET_TX_RST (1<<2)
FSL\B36402 5:69f1634cd40b 644 #define cSOFT_RESET_RX_RST (1<<1)
FSL\B36402 5:69f1634cd40b 645 #define cSOFT_RESET_SEQ_MGR_RST (1<<0)
FSL\B36402 5:69f1634cd40b 646
FSL\B36402 5:69f1634cd40b 647 // SEQ_MGR_CTRL bits
FSL\B36402 5:69f1634cd40b 648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
FSL\B36402 5:69f1634cd40b 649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
FSL\B36402 5:69f1634cd40b 650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
FSL\B36402 5:69f1634cd40b 651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
FSL\B36402 5:69f1634cd40b 652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
FSL\B36402 5:69f1634cd40b 653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
FSL\B36402 5:69f1634cd40b 654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
FSL\B36402 5:69f1634cd40b 655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
FSL\B36402 5:69f1634cd40b 656
FSL\B36402 5:69f1634cd40b 657 // SEQ_MGR_STS bits
FSL\B36402 5:69f1634cd40b 658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
FSL\B36402 5:69f1634cd40b 659 #define cSEQ_MGR_STS_RX_MODE (1<<6)
FSL\B36402 5:69f1634cd40b 660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
FSL\B36402 5:69f1634cd40b 661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
FSL\B36402 5:69f1634cd40b 662 #define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
FSL\B36402 5:69f1634cd40b 663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
FSL\B36402 5:69f1634cd40b 664
FSL\B36402 5:69f1634cd40b 665 // ABORT_STS bits
FSL\B36402 5:69f1634cd40b 666 #define cABORT_STS_PLL_ABORTED (1<<2)
FSL\B36402 5:69f1634cd40b 667 #define cABORT_STS_TC3_ABORTED (1<<1)
FSL\B36402 5:69f1634cd40b 668 #define cABORT_STS_SW_ABORTED (1<<0)
FSL\B36402 5:69f1634cd40b 669
FSL\B36402 5:69f1634cd40b 670 // FILTERFAIL_CODE2 bits
FSL\B36402 5:69f1634cd40b 671 #define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
FSL\B36402 5:69f1634cd40b 672 #define cFILTERFAIL_CODE2_9_8 (3)
FSL\B36402 5:69f1634cd40b 673
FSL\B36402 5:69f1634cd40b 674 // PHY_STS bits
FSL\B36402 5:69f1634cd40b 675 #define cPHY_STS_PLL_UNLOCK (1<<7)
FSL\B36402 5:69f1634cd40b 676 #define cPHY_STS_PLL_LOCK_ERR (1<<6)
FSL\B36402 5:69f1634cd40b 677 #define cPHY_STS_PLL_LOCK (1<<5)
FSL\B36402 5:69f1634cd40b 678 #define cPHY_STS_CRCVALID (1<<3)
FSL\B36402 5:69f1634cd40b 679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
FSL\B36402 5:69f1634cd40b 680 #define cPHY_STS_SFD_DET (1<<1)
FSL\B36402 5:69f1634cd40b 681 #define cPHY_STS_PREAMBLE_DET (1<<0)
FSL\B36402 5:69f1634cd40b 682
FSL\B36402 5:69f1634cd40b 683 // TESTMODE_CTRL bits
FSL\B36402 5:69f1634cd40b 684 #define cTEST_MODE_CTRL_HOT_ANT (1<<4)
FSL\B36402 5:69f1634cd40b 685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
FSL\B36402 5:69f1634cd40b 686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
FSL\B36402 5:69f1634cd40b 687 #define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
FSL\B36402 5:69f1634cd40b 688 #define cTEST_MODE_CTRL_FPGA_EN (1<<0)
FSL\B36402 5:69f1634cd40b 689
FSL\B36402 5:69f1634cd40b 690 // DTM_CTRL1 bits
FSL\B36402 5:69f1634cd40b 691 #define cDTM_CTRL1_ATM_LOCKED (1<<7)
FSL\B36402 5:69f1634cd40b 692 #define cDTM_CTRL1_DTM_EN (1<<6)
FSL\B36402 5:69f1634cd40b 693 #define cDTM_CTRL1_PAGE5 (1<<5)
FSL\B36402 5:69f1634cd40b 694 #define cDTM_CTRL1_PAGE4 (1<<4)
FSL\B36402 5:69f1634cd40b 695 #define cDTM_CTRL1_PAGE3 (1<<3)
FSL\B36402 5:69f1634cd40b 696 #define cDTM_CTRL1_PAGE2 (1<<2)
FSL\B36402 5:69f1634cd40b 697 #define cDTM_CTRL1_PAGE1 (1<<1)
FSL\B36402 5:69f1634cd40b 698 #define cDTM_CTRL1_PAGE0 (1<<0)
FSL\B36402 5:69f1634cd40b 699
FSL\B36402 5:69f1634cd40b 700 // TX_MODE_CTRL
FSL\B36402 5:69f1634cd40b 701 #define cTX_MODE_CTRL_TX_INV (1<<4)
FSL\B36402 5:69f1634cd40b 702 #define cTX_MODE_CTRL_BT_EN (1<<3)
FSL\B36402 5:69f1634cd40b 703 #define cTX_MODE_CTRL_DTS2 (1<<2)
FSL\B36402 5:69f1634cd40b 704 #define cTX_MODE_CTRL_DTS1 (1<<1)
FSL\B36402 5:69f1634cd40b 705 #define cTX_MODE_CTRL_DTS0 (1<<0)
FSL\B36402 5:69f1634cd40b 706
FSL\B36402 5:69f1634cd40b 707 #define cTX_MODE_CTRL_DTS_MASK (7)
FSL\B36402 5:69f1634cd40b 708
FSL\B36402 5:69f1634cd40b 709 // CLK_OUT_CTRL bits
FSL\B36402 5:69f1634cd40b 710 #define cCLK_OUT_EXTEND (1<<7)
FSL\B36402 5:69f1634cd40b 711 #define cCLK_OUT_HIZ (1<<6)
FSL\B36402 5:69f1634cd40b 712 #define cCLK_OUT_SR (1<<5)
FSL\B36402 5:69f1634cd40b 713 #define cCLK_OUT_DS (1<<4)
FSL\B36402 5:69f1634cd40b 714 #define cCLK_OUT_EN (1<<3)
FSL\B36402 5:69f1634cd40b 715 #define cCLK_OUT_DIV_Mask (7<<0)
FSL\B36402 5:69f1634cd40b 716
FSL\B36402 5:69f1634cd40b 717 #define gCLK_OUT_FREQ_32_MHz (0)
FSL\B36402 5:69f1634cd40b 718 #define gCLK_OUT_FREQ_16_MHz (1)
FSL\B36402 5:69f1634cd40b 719 #define gCLK_OUT_FREQ_8_MHz (2)
FSL\B36402 5:69f1634cd40b 720 #define gCLK_OUT_FREQ_4_MHz (3)
FSL\B36402 5:69f1634cd40b 721 #define gCLK_OUT_FREQ_1_MHz (4)
FSL\B36402 5:69f1634cd40b 722 #define gCLK_OUT_FREQ_250_KHz (5)
FSL\B36402 5:69f1634cd40b 723 #define gCLK_OUT_FREQ_62_5_KHz (6)
FSL\B36402 5:69f1634cd40b 724 #define gCLK_OUT_FREQ_32_78_KHz (7)
FSL\B36402 5:69f1634cd40b 725 #define gCLK_OUT_FREQ_DISABLE (8)
FSL\B36402 5:69f1634cd40b 726
FSL\B36402 5:69f1634cd40b 727
FSL\B36402 5:69f1634cd40b 728
FSL\B36402 5:69f1634cd40b 729
FSL\B36402 5:69f1634cd40b 730 #endif /* __MCR20_REG_H__ */