NXP / Mbed 2 deprecated mcr20_wireless_uart

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by Freescale

By default, the application uses broadcast addresses for OTA communication. This way, the application can be directly downloaded and run without any user intervention. The following use case assumes no changes have been done to the project.

  • Two (or more) MCR20A platforms (plugged into the FRDM-K64F Freescale Freedom Development platform) have to be connected to the PC using the mini/micro-USB cables.
  • The code must be downloaded on the platforms via CMSIS-DAP (or other means).
  • After that, two or more TERM applications must be opened, and the serial ports must be configured with the same baud rate as the one in the project (default baud rate is 115200). Other necessary serial configurations are 8 bit, no parity, and 1 stop bit.
  • To start the setup, each platform must be reset, and one of the (user) push buttons found on the MCR20A platform must be pressed. The user can press any of the non-reset buttons on the FRDM-K64F Freescale Freedom Development platform as well. *This initiates the state machine of the application so user can start.

Documentation

SMAC Demo Applications User Guide

FXOS8700Q_TapDetector/FXOS8700Q_TD.cpp@2:3e7685cfb2a7, 2015-03-05 (annotated)

Committer:
sam_grove
Date:
Thu Mar 05 15:47:08 2015 +0000
Revision:
2:3e7685cfb2a7
Updating to techcon demo program

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 2:3e7685cfb2a7 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
sam_grove 2:3e7685cfb2a7 2 *
sam_grove 2:3e7685cfb2a7 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
sam_grove 2:3e7685cfb2a7 4 * and associated documentation files (the "Software"), to deal in the Software without
sam_grove 2:3e7685cfb2a7 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
sam_grove 2:3e7685cfb2a7 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
sam_grove 2:3e7685cfb2a7 7 * Software is furnished to do so, subject to the following conditions:
sam_grove 2:3e7685cfb2a7 8 *
sam_grove 2:3e7685cfb2a7 9 * The above copyright notice and this permission notice shall be included in all copies or
sam_grove 2:3e7685cfb2a7 10 * substantial portions of the Software.
sam_grove 2:3e7685cfb2a7 11 *
sam_grove 2:3e7685cfb2a7 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
sam_grove 2:3e7685cfb2a7 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
sam_grove 2:3e7685cfb2a7 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
sam_grove 2:3e7685cfb2a7 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
sam_grove 2:3e7685cfb2a7 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
sam_grove 2:3e7685cfb2a7 17 */
sam_grove 2:3e7685cfb2a7 18
sam_grove 2:3e7685cfb2a7 19 #include "FXOS8700Q_TD.h"
sam_grove 2:3e7685cfb2a7 20 #define UINT14_MAX 16383
sam_grove 2:3e7685cfb2a7 21
sam_grove 2:3e7685cfb2a7 22
sam_grove 2:3e7685cfb2a7 23 FXOS8700Q::FXOS8700Q(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr) {
sam_grove 2:3e7685cfb2a7 24
sam_grove 2:3e7685cfb2a7 25 //Step 1: Go to Standby Mode to change configuration settings.
sam_grove 2:3e7685cfb2a7 26 uint8_t data[2] = {0x2A, 0x10}; //200 Hz, Standby Mode
sam_grove 2:3e7685cfb2a7 27 m_i2c.frequency(400000);
sam_grove 2:3e7685cfb2a7 28 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 29
sam_grove 2:3e7685cfb2a7 30 //Step 2: Enable X, Y, Z Single Pulse and X, Y and Z Double Pulse with DPA = 0 no double pulse abort
sam_grove 2:3e7685cfb2a7 31 data[0] = 0x21;
sam_grove 2:3e7685cfb2a7 32 data[1] = 0x3F;
sam_grove 2:3e7685cfb2a7 33 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 34
sam_grove 2:3e7685cfb2a7 35 //Step 3: Set Threshold 2g on X and Y and 4g on Z
sam_grove 2:3e7685cfb2a7 36 //Note: Every step is 0.063g
sam_grove 2:3e7685cfb2a7 37 //2g / 0.063g = 32 counts
sam_grove 2:3e7685cfb2a7 38 //4g/ 0.063g = 64 counts
sam_grove 2:3e7685cfb2a7 39 data[0] = 0x23; //Set X Threshold to 2g
sam_grove 2:3e7685cfb2a7 40 data[1] = 0x20;
sam_grove 2:3e7685cfb2a7 41 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 42
sam_grove 2:3e7685cfb2a7 43 data[0] = 0x24; //Set Y Threshold to 2g
sam_grove 2:3e7685cfb2a7 44 data[1] = 0x20;
sam_grove 2:3e7685cfb2a7 45 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 46
sam_grove 2:3e7685cfb2a7 47 data[0] = 0x25; //Set Z Threshold to 4g
sam_grove 2:3e7685cfb2a7 48 data[1] = 0x40;
sam_grove 2:3e7685cfb2a7 49 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 50
sam_grove 2:3e7685cfb2a7 51 //Step 4: Set Time Limit for Tap Detection to 60 ms (LP Mode, 200 Hz ODR, No LPF)
sam_grove 2:3e7685cfb2a7 52 //Note: 200 Hz ODR LP Mode, Time step is 2.5 ms per step
sam_grove 2:3e7685cfb2a7 53 //60 ms /2.5 ms = 24 counts
sam_grove 2:3e7685cfb2a7 54 data[0] = 0x26; //60 ms
sam_grove 2:3e7685cfb2a7 55 data[1] = 0x18;
sam_grove 2:3e7685cfb2a7 56 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 57
sam_grove 2:3e7685cfb2a7 58 //Step 5: Set Latency Timer to 200 ms
sam_grove 2:3e7685cfb2a7 59 //Note: 200 Hz ODR LP Mode, Time step is 5 ms per step
sam_grove 2:3e7685cfb2a7 60 //200 ms/ 5 ms = 40 counts
sam_grove 2:3e7685cfb2a7 61 data[0] = 0x27; //200 ms
sam_grove 2:3e7685cfb2a7 62 data[1] = 0x28;
sam_grove 2:3e7685cfb2a7 63 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 64
sam_grove 2:3e7685cfb2a7 65 //Step 6: Set Time Window for Second Tap to 300 ms
sam_grove 2:3e7685cfb2a7 66 //Note: 200 Hz ODR LP Mode, Time step is 5 ms per step
sam_grove 2:3e7685cfb2a7 67 //00 ms/5 ms = 60 counts
sam_grove 2:3e7685cfb2a7 68 data[0] = 0x28; //300 ms
sam_grove 2:3e7685cfb2a7 69 data[1] = 0x3C;
sam_grove 2:3e7685cfb2a7 70 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 71
sam_grove 2:3e7685cfb2a7 72 //Step 7: Route INT1 to System Interrupt
sam_grove 2:3e7685cfb2a7 73 data[0] = 0x2D; //Enable Pulse Interrupt Block in System CTRL_REG4
sam_grove 2:3e7685cfb2a7 74 data[1] = 0x08;
sam_grove 2:3e7685cfb2a7 75 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 76
sam_grove 2:3e7685cfb2a7 77 data[0] = 0x2E; //Route Pulse Interrupt Block to INT1 hardware Pin CTRL_REG5
sam_grove 2:3e7685cfb2a7 78 data[1] = 0x08;
sam_grove 2:3e7685cfb2a7 79 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 80
sam_grove 2:3e7685cfb2a7 81 data[0] = 0x2C; //Pulse function is enabled in Sleep mode and can generate an interrupt to wake the system
sam_grove 2:3e7685cfb2a7 82 data[1] = 0x10;
sam_grove 2:3e7685cfb2a7 83 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 84
sam_grove 2:3e7685cfb2a7 85 //Step 8: Active Mode
sam_grove 2:3e7685cfb2a7 86 //Read out the contents of the register
sam_grove 2:3e7685cfb2a7 87 uint8_t value = 0;
sam_grove 2:3e7685cfb2a7 88 readRegs(0x2A, &value, 1);
sam_grove 2:3e7685cfb2a7 89 //Change the value in the register to Active Mode.
sam_grove 2:3e7685cfb2a7 90 value |= 0x01;
sam_grove 2:3e7685cfb2a7 91 //Write in the updated value to put the device in Active Mode
sam_grove 2:3e7685cfb2a7 92 data[0] = 0x2A;
sam_grove 2:3e7685cfb2a7 93 data[1] = value;
sam_grove 2:3e7685cfb2a7 94 writeRegs(data, 2);
sam_grove 2:3e7685cfb2a7 95
sam_grove 2:3e7685cfb2a7 96 }
sam_grove 2:3e7685cfb2a7 97
sam_grove 2:3e7685cfb2a7 98
sam_grove 2:3e7685cfb2a7 99 FXOS8700Q::~FXOS8700Q() { }
sam_grove 2:3e7685cfb2a7 100
sam_grove 2:3e7685cfb2a7 101 uint8_t FXOS8700Q::getWhoAmI() {
sam_grove 2:3e7685cfb2a7 102 uint8_t who_am_i = 0;
sam_grove 2:3e7685cfb2a7 103 readRegs(FXOS8700Q_WHOAMI, &who_am_i, 1);
sam_grove 2:3e7685cfb2a7 104 return who_am_i;
sam_grove 2:3e7685cfb2a7 105 }
sam_grove 2:3e7685cfb2a7 106
sam_grove 2:3e7685cfb2a7 107 float FXOS8700Q::getAccX() {
sam_grove 2:3e7685cfb2a7 108 return (float(getAccAxis(FXOS8700Q_OUT_X_MSB))/4096.0f);
sam_grove 2:3e7685cfb2a7 109 }
sam_grove 2:3e7685cfb2a7 110
sam_grove 2:3e7685cfb2a7 111 float FXOS8700Q::getAccY() {
sam_grove 2:3e7685cfb2a7 112 return (float(getAccAxis(FXOS8700Q_OUT_Y_MSB))/4096.0f);
sam_grove 2:3e7685cfb2a7 113 }
sam_grove 2:3e7685cfb2a7 114
sam_grove 2:3e7685cfb2a7 115 float FXOS8700Q::getAccZ() {
sam_grove 2:3e7685cfb2a7 116 return (float(getAccAxis(FXOS8700Q_OUT_Z_MSB))/4096.0f);
sam_grove 2:3e7685cfb2a7 117 }
sam_grove 2:3e7685cfb2a7 118
sam_grove 2:3e7685cfb2a7 119
sam_grove 2:3e7685cfb2a7 120 void FXOS8700Q::getAccAllAxis(float * res) {
sam_grove 2:3e7685cfb2a7 121 res[0] = getAccX();
sam_grove 2:3e7685cfb2a7 122 res[1] = getAccY();
sam_grove 2:3e7685cfb2a7 123 res[2] = getAccZ();
sam_grove 2:3e7685cfb2a7 124 }
sam_grove 2:3e7685cfb2a7 125
sam_grove 2:3e7685cfb2a7 126 void FXOS8700Q::AccXYZraw(int16_t * d) {
sam_grove 2:3e7685cfb2a7 127 int16_t acc;
sam_grove 2:3e7685cfb2a7 128 uint8_t res[6];
sam_grove 2:3e7685cfb2a7 129 readRegs(FXOS8700Q_OUT_X_MSB, res, 6);
sam_grove 2:3e7685cfb2a7 130
sam_grove 2:3e7685cfb2a7 131 acc = (res[0] << 6) | (res[1] >> 2);
sam_grove 2:3e7685cfb2a7 132 if (acc > UINT14_MAX/2)
sam_grove 2:3e7685cfb2a7 133 acc -= UINT14_MAX;
sam_grove 2:3e7685cfb2a7 134 d[0] = acc;
sam_grove 2:3e7685cfb2a7 135 acc = (res[2] << 6) | (res[3] >> 2);
sam_grove 2:3e7685cfb2a7 136 if (acc > UINT14_MAX/2)
sam_grove 2:3e7685cfb2a7 137 acc -= UINT14_MAX;
sam_grove 2:3e7685cfb2a7 138 d[1] = acc;
sam_grove 2:3e7685cfb2a7 139 acc = (res[4] << 6) | (res[5] >> 2);
sam_grove 2:3e7685cfb2a7 140 if (acc > UINT14_MAX/2)
sam_grove 2:3e7685cfb2a7 141 acc -= UINT14_MAX;
sam_grove 2:3e7685cfb2a7 142 d[2] = acc;
sam_grove 2:3e7685cfb2a7 143 }
sam_grove 2:3e7685cfb2a7 144
sam_grove 2:3e7685cfb2a7 145 void FXOS8700Q::MagXYZraw(int16_t * d) {
sam_grove 2:3e7685cfb2a7 146 uint8_t res[6];
sam_grove 2:3e7685cfb2a7 147 readRegs(FXOS8700Q_M_OUT_X_MSB, res, 6);
sam_grove 2:3e7685cfb2a7 148
sam_grove 2:3e7685cfb2a7 149 d[0] = (res[0] << 8) | res[1];
sam_grove 2:3e7685cfb2a7 150 d[1] = (res[2] << 8) | res[3];
sam_grove 2:3e7685cfb2a7 151 d[2] = (res[4] << 8) | res[5];
sam_grove 2:3e7685cfb2a7 152 }
sam_grove 2:3e7685cfb2a7 153
sam_grove 2:3e7685cfb2a7 154 void FXOS8700Q::getMagAllAxis(float * res) {
sam_grove 2:3e7685cfb2a7 155 int16_t raw[3];
sam_grove 2:3e7685cfb2a7 156 MagXYZraw( raw);
sam_grove 2:3e7685cfb2a7 157 res[0] = (float) raw[0] * 0.1f;
sam_grove 2:3e7685cfb2a7 158 res[1] = (float) raw[1] * 0.1f;
sam_grove 2:3e7685cfb2a7 159 res[2] = (float) raw[2] * 0.1f;
sam_grove 2:3e7685cfb2a7 160 }
sam_grove 2:3e7685cfb2a7 161
sam_grove 2:3e7685cfb2a7 162 int16_t FXOS8700Q::getAccAxis(uint8_t addr) {
sam_grove 2:3e7685cfb2a7 163 int16_t acc;
sam_grove 2:3e7685cfb2a7 164 uint8_t res[2];
sam_grove 2:3e7685cfb2a7 165 readRegs(addr, res, 2);
sam_grove 2:3e7685cfb2a7 166
sam_grove 2:3e7685cfb2a7 167 acc = (res[0] << 6) | (res[1] >> 2);
sam_grove 2:3e7685cfb2a7 168 if (acc > UINT14_MAX/2)
sam_grove 2:3e7685cfb2a7 169 acc -= UINT14_MAX;
sam_grove 2:3e7685cfb2a7 170
sam_grove 2:3e7685cfb2a7 171 return acc;
sam_grove 2:3e7685cfb2a7 172 }
sam_grove 2:3e7685cfb2a7 173
sam_grove 2:3e7685cfb2a7 174 void FXOS8700Q::readRegs(int addr, uint8_t * data, int len) {
sam_grove 2:3e7685cfb2a7 175 char t[1] = {addr};
sam_grove 2:3e7685cfb2a7 176 m_i2c.write(m_addr, t, 1, true);
sam_grove 2:3e7685cfb2a7 177 m_i2c.read(m_addr, (char *)data, len);
sam_grove 2:3e7685cfb2a7 178 }
sam_grove 2:3e7685cfb2a7 179
sam_grove 2:3e7685cfb2a7 180 void FXOS8700Q::writeRegs(uint8_t * data, int len) {
sam_grove 2:3e7685cfb2a7 181 m_i2c.write(m_addr, (char *)data, len);
sam_grove 2:3e7685cfb2a7 182 }
sam_grove 2:3e7685cfb2a7 183
sam_grove 2:3e7685cfb2a7 184