NXP / fsl_phy_mcr20a

A library implementing IEEE 802.15.4 PHY functionality for the MCR20A transceiver. The PHY sublayer provides two services: the PHY data service and the PHY management service interfacing to the PHY sublayer management entity (PLME) service access point (SAP) (known as PLME-SAP). The PHY data service enables the transmission and reception of PHY protocol data units (PSDUs) over the media (radio).

Fork of fsl_phy_mcr20a by Freescale

The Freescale PHY Layer deals with the physical burst which is to be sent and/or received. It performs modulation and demodulation, transmitter and receiver switching, fragmentation, scrambling, interleaving, and error correction coding. The communication to the upper protocol layers is carried out through the Layer 1 Interface.

The PHY Layer is capable of executing the following sequences:

  • I (Idle)
  • R (Receive Sequence conditionally followed by a TxAck)
  • T (Transmit Sequence)
  • C (Standalone CCA)
  • CCCA (Continuous CCA)
  • TR (Transmit/Receive Sequence - transmit unconditionally followed by either an R or RxAck)

In addition to these sequences the PHY Layer also integrates a packet processor which determines whether the packet is MAC-compliant, and if it is, whether it is addressed to the end device. Another feature of the packet processor is Source Address Matching which can be viewed as an extension of packet filtering; however its function is very specific to its intended application (data-polling and indirect queue management by a PAN Coordinator).

Documentation

MCR20A PHY Reference Manual

PHY/PhyDebug.h@0:764779eedf2d, 2015-08-18 (annotated)

Committer:
andreikovacs
Date:
Tue Aug 18 12:41:42 2015 +0000
Revision:
0:764779eedf2d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andreikovacs 0:764779eedf2d 1 /*!
andreikovacs 0:764779eedf2d 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
andreikovacs 0:764779eedf2d 3 * All rights reserved.
andreikovacs 0:764779eedf2d 4 *
andreikovacs 0:764779eedf2d 5 * \file PhyDebug.h
andreikovacs 0:764779eedf2d 6 *
andreikovacs 0:764779eedf2d 7 * Redistribution and use in source and binary forms, with or without modification,
andreikovacs 0:764779eedf2d 8 * are permitted provided that the following conditions are met:
andreikovacs 0:764779eedf2d 9 *
andreikovacs 0:764779eedf2d 10 * o Redistributions of source code must retain the above copyright notice, this list
andreikovacs 0:764779eedf2d 11 * of conditions and the following disclaimer.
andreikovacs 0:764779eedf2d 12 *
andreikovacs 0:764779eedf2d 13 * o Redistributions in binary form must reproduce the above copyright notice, this
andreikovacs 0:764779eedf2d 14 * list of conditions and the following disclaimer in the documentation and/or
andreikovacs 0:764779eedf2d 15 * other materials provided with the distribution.
andreikovacs 0:764779eedf2d 16 *
andreikovacs 0:764779eedf2d 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
andreikovacs 0:764779eedf2d 18 * contributors may be used to endorse or promote products derived from this
andreikovacs 0:764779eedf2d 19 * software without specific prior written permission.
andreikovacs 0:764779eedf2d 20 *
andreikovacs 0:764779eedf2d 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
andreikovacs 0:764779eedf2d 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
andreikovacs 0:764779eedf2d 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
andreikovacs 0:764779eedf2d 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
andreikovacs 0:764779eedf2d 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
andreikovacs 0:764779eedf2d 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
andreikovacs 0:764779eedf2d 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
andreikovacs 0:764779eedf2d 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
andreikovacs 0:764779eedf2d 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
andreikovacs 0:764779eedf2d 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
andreikovacs 0:764779eedf2d 31 */
andreikovacs 0:764779eedf2d 32
andreikovacs 0:764779eedf2d 33 #ifndef _PHY_DEBUG_H_
andreikovacs 0:764779eedf2d 34 #define _PHY_DEBUG_H_
andreikovacs 0:764779eedf2d 35
andreikovacs 0:764779eedf2d 36
andreikovacs 0:764779eedf2d 37 /************************************************************************************
andreikovacs 0:764779eedf2d 38 *************************************************************************************
andreikovacs 0:764779eedf2d 39 * Includes
andreikovacs 0:764779eedf2d 40 *************************************************************************************
andreikovacs 0:764779eedf2d 41 ************************************************************************************/
andreikovacs 0:764779eedf2d 42 //#include "MacPhyDebug.h"
andreikovacs 0:764779eedf2d 43
andreikovacs 0:764779eedf2d 44
andreikovacs 0:764779eedf2d 45 // a value of zero disables the logging of that event
andreikovacs 0:764779eedf2d 46 #define PDBG_SET_EVENT_TRIGGER 0x01 // 2 parameters
andreikovacs 0:764779eedf2d 47 #define PDBG_SET_EVENT_TIMEOUT 0x02 // 3 parameters
andreikovacs 0:764779eedf2d 48 #define PDBG_DISABLE_EVENT_TIMEOUT 0x03
andreikovacs 0:764779eedf2d 49 #define PDBG_READ_CLOCK 0x04
andreikovacs 0:764779eedf2d 50 #define PDBG_INIT_EVENT_TIMER 0
andreikovacs 0:764779eedf2d 51
andreikovacs 0:764779eedf2d 52 #define PDBG_WTRMRK_VECT_INTERRUPT 0x06
andreikovacs 0:764779eedf2d 53 #define PDBG_TIMERS_VECT_INTERRUPT 0x07
andreikovacs 0:764779eedf2d 54 #define PDBG_TX_VECT_INTERRUPT 0x08
andreikovacs 0:764779eedf2d 55 #define PDBG_RX_VECT_INTERRUPT 0x09
andreikovacs 0:764779eedf2d 56
andreikovacs 0:764779eedf2d 57 #define PDBG_CCA_CONFIRM_IDLE 0x0A
andreikovacs 0:764779eedf2d 58 #define PDBG_CCA_CONFIRM_BUSY 0x0B
andreikovacs 0:764779eedf2d 59 #define PDBG_DATA_CONFIRM 0x0C
andreikovacs 0:764779eedf2d 60 #define PDBG_DATA_INDICATION 0x0D
andreikovacs 0:764779eedf2d 61 #define PDBG_ED_CONFIRM 0x0E
andreikovacs 0:764779eedf2d 62 #define PDBG_SYNC_LOSS_INDICATION 0x0F
andreikovacs 0:764779eedf2d 63
andreikovacs 0:764779eedf2d 64 #define PDBG_UNLOCK_IRQ 0x10
andreikovacs 0:764779eedf2d 65 #define PDBG_WTRMARK_IRQ 0x11
andreikovacs 0:764779eedf2d 66 #define PDBG_START_INDICATION 0x12
andreikovacs 0:764779eedf2d 67 #define PDBG_TIMEOUT_INDICATION 0x13
andreikovacs 0:764779eedf2d 68 #define PDBG_TMR1_IRQ 0x14
andreikovacs 0:764779eedf2d 69 #define PDBG_TMR4_IRQ 0x15
andreikovacs 0:764779eedf2d 70 #define PDBG_FILTER_FAIL_IRQ 0x16
andreikovacs 0:764779eedf2d 71 #define PDBG_TX_IRQ 0x17
andreikovacs 0:764779eedf2d 72 #define PDBG_RX_IRQ 0x18 // 1 parameter
andreikovacs 0:764779eedf2d 73 #define PDBG_CCA_IRQ 0x19
andreikovacs 0:764779eedf2d 74 #define PDBG_SEQ_IRQ 0x1A // 1 parameter
andreikovacs 0:764779eedf2d 75
andreikovacs 0:764779eedf2d 76 #define PDBG_PHY_INIT 0x20
andreikovacs 0:764779eedf2d 77 #define PDBG_PHY_ABORT 0x21
andreikovacs 0:764779eedf2d 78 #define PDBG_PP_SET_PROMISC 0
andreikovacs 0:764779eedf2d 79 #define PDBG_PP_SET_PANID_PAN0 0x23
andreikovacs 0:764779eedf2d 80 #define PDBG_PP_SET_SHORTADDR_PAN0 0x24
andreikovacs 0:764779eedf2d 81 #define PDBG_PP_SET_LONGADDR_PAN0 0x25
andreikovacs 0:764779eedf2d 82 #define PDBG_PP_SET_MACROLE_PAN0 0x26
andreikovacs 0:764779eedf2d 83 #define PDBG_PP_ADD_INDIRECT 0x27 // 1 parameter
andreikovacs 0:764779eedf2d 84 #define PDBG_PP_REMOVE_INDIRECT 0x28 // 1 parameter
andreikovacs 0:764779eedf2d 85 #define PDBG_PP_READ_LATEST_INDEX 0x29 // 1 parameter
andreikovacs 0:764779eedf2d 86
andreikovacs 0:764779eedf2d 87 #define PDBG_DATA_REQUEST 0x30
andreikovacs 0:764779eedf2d 88 #define PDBG_PLME_RX_REQUEST 0x31
andreikovacs 0:764779eedf2d 89 #define PDBG_PLME_CCA_ED_REQUEST 0x32
andreikovacs 0:764779eedf2d 90 #define PDBG_PLME_SET_CHAN_REQUEST 0x33
andreikovacs 0:764779eedf2d 91 #define PDBG_PLME_SET_POWER_REQUEST 0x34
andreikovacs 0:764779eedf2d 92 #define PDBG_PLME_WAIT_REQUEST 0x35
andreikovacs 0:764779eedf2d 93
andreikovacs 0:764779eedf2d 94 #define PDBG_PP_SET_PANID_PAN1 0x36
andreikovacs 0:764779eedf2d 95 #define PDBG_PP_SET_SHORTADDR_PAN1 0x37
andreikovacs 0:764779eedf2d 96 #define PDBG_PP_SET_LONGADDR_PAN1 0x38
andreikovacs 0:764779eedf2d 97 #define PDBG_PP_SET_MACROLE_PAN1 0x39
andreikovacs 0:764779eedf2d 98
andreikovacs 0:764779eedf2d 99 //simple events - without timestamp
andreikovacs 0:764779eedf2d 100 //***** PDBG_MAC_FUNCTION_CALL PDBG_SIMPLE_EVENT // 3 parameters
andreikovacs 0:764779eedf2d 101 #define PDBG_READ_FSM PDBG_SIMPLE_EVENT + 0x01 // 1 parameter
andreikovacs 0:764779eedf2d 102 #define PDBG_FILTER_FAIL_CODE PDBG_SIMPLE_EVENT + 0x02 // 2 parameters
andreikovacs 0:764779eedf2d 103
andreikovacs 0:764779eedf2d 104
andreikovacs 0:764779eedf2d 105 #ifdef MAC_PHY_DEBUG
andreikovacs 0:764779eedf2d 106
andreikovacs 0:764779eedf2d 107 #define DEBUG_LOG_ENTRIES 768
andreikovacs 0:764779eedf2d 108
andreikovacs 0:764779eedf2d 109 #define PHY_DEBUG_LOG(item) if(PDBG_RESERVED_EVENT!=item){PhyDebugLogTime(item);}
andreikovacs 0:764779eedf2d 110 #define PHY_DEBUG_LOG1(item,param) if(PDBG_RESERVED_EVENT!=item){PhyDebugLogTime(PDBG_EXTENDED_EVENT | item);PhyDebugLogParam1(item,param);}
andreikovacs 0:764779eedf2d 111 #define PHY_DEBUG_LOG2(item,param1,param2) if(PDBG_RESERVED_EVENT!=item){PhyDebugLogTime(PDBG_EXTENDED_EVENT | item);PhyDebugLogParam2(item,param1,param2);}
andreikovacs 0:764779eedf2d 112 #define PHY_DEBUG_LOG3(item,param1,param2,param3) if(PDBG_RESERVED_EVENT!=item){PhyDebugLogTime(PDBG_EXTENDED_EVENT | item);PhyDebugLogParam3(item,param1,param2,param3);}
andreikovacs 0:764779eedf2d 113
andreikovacs 0:764779eedf2d 114 #define PHY_DEBUG_LOG_SIMPLE1(item,param) if(PDBG_RESERVED_EVENT!=item){PhyDebugLogParam1(item,param);}
andreikovacs 0:764779eedf2d 115 #define PHY_DEBUG_LOG_SIMPLE2(item,param1,param2) if(PDBG_RESERVED_EVENT!=item){PhyDebugLogParam2(item,param1,param2);}
andreikovacs 0:764779eedf2d 116 #define PHY_DEBUG_LOG_SIMPLE3(item,param1,param2,param3) if(PDBG_RESERVED_EVENT!=item){PhyDebugLogParam3(item,param1,param2,param3);}
andreikovacs 0:764779eedf2d 117
andreikovacs 0:764779eedf2d 118 void PhyUnexpectedTransceiverReset(void);
andreikovacs 0:764779eedf2d 119
andreikovacs 0:764779eedf2d 120 void PhyDebugLogTime(uint8_t item);
andreikovacs 0:764779eedf2d 121 void PhyDebugLogParam1(uint8_t item, uint8_t param1);
andreikovacs 0:764779eedf2d 122 void PhyDebugLogParam2(uint8_t item, uint8_t param1, uint8_t param2);
andreikovacs 0:764779eedf2d 123 void PhyDebugLogParam3(uint8_t item, uint8_t param1, uint8_t param2, uint8_t param3);
andreikovacs 0:764779eedf2d 124
andreikovacs 0:764779eedf2d 125
andreikovacs 0:764779eedf2d 126 #else /* not def MAC_PHY_DEBUG */
andreikovacs 0:764779eedf2d 127
andreikovacs 0:764779eedf2d 128 #define PhyUnexpectedTransceiverReset()
andreikovacs 0:764779eedf2d 129
andreikovacs 0:764779eedf2d 130 #define PHY_DEBUG_LOG(item)
andreikovacs 0:764779eedf2d 131 #define PHY_DEBUG_LOG1(item,param)
andreikovacs 0:764779eedf2d 132 #define PHY_DEBUG_LOG2(item,param1,param2)
andreikovacs 0:764779eedf2d 133 #define PHY_DEBUG_LOG3(item,param1,param2,param3)
andreikovacs 0:764779eedf2d 134
andreikovacs 0:764779eedf2d 135 #define PHY_DEBUG_LOG_SIMPLE1(item,param)
andreikovacs 0:764779eedf2d 136 #define PHY_DEBUG_LOG_SIMPLE2(item,param1,param2)
andreikovacs 0:764779eedf2d 137 #define PHY_DEBUG_LOG_SIMPLE3(item,param1,param2,param3)
andreikovacs 0:764779eedf2d 138
andreikovacs 0:764779eedf2d 139 #endif /* MAC_PHY_DEBUG */
andreikovacs 0:764779eedf2d 140
andreikovacs 0:764779eedf2d 141
andreikovacs 0:764779eedf2d 142 #endif /* _PHY_DEBUG_H_ */
andreikovacs 0:764779eedf2d 143
andreikovacs 0:764779eedf2d 144
andreikovacs 0:764779eedf2d 145