A library implementing IEEE 802.15.4 PHY functionality for the MCR20A transceiver. The PHY sublayer provides two services: the PHY data service and the PHY management service interfacing to the PHY sublayer management entity (PLME) service access point (SAP) (known as PLME-SAP). The PHY data service enables the transmission and reception of PHY protocol data units (PSDUs) over the media (radio).

Fork of fsl_phy_mcr20a by Freescale

The Freescale PHY Layer deals with the physical burst which is to be sent and/or received. It performs modulation and demodulation, transmitter and receiver switching, fragmentation, scrambling, interleaving, and error correction coding. The communication to the upper protocol layers is carried out through the Layer 1 Interface.

The PHY Layer is capable of executing the following sequences:

  • I (Idle)
  • R (Receive Sequence conditionally followed by a TxAck)
  • T (Transmit Sequence)
  • C (Standalone CCA)
  • CCCA (Continuous CCA)
  • TR (Transmit/Receive Sequence - transmit unconditionally followed by either an R or RxAck)

In addition to these sequences the PHY Layer also integrates a packet processor which determines whether the packet is MAC-compliant, and if it is, whether it is addressed to the end device. Another feature of the packet processor is Source Address Matching which can be viewed as an extension of packet filtering; however its function is very specific to its intended application (data-polling and indirect queue management by a PAN Coordinator).

Documentation

MCR20A PHY Reference Manual

Committer:
andreikovacs
Date:
Tue Aug 18 12:41:42 2015 +0000
Revision:
0:764779eedf2d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andreikovacs 0:764779eedf2d 1 /*!
andreikovacs 0:764779eedf2d 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
andreikovacs 0:764779eedf2d 3 * All rights reserved.
andreikovacs 0:764779eedf2d 4 *
andreikovacs 0:764779eedf2d 5 * \file MCR20Drv.h
andreikovacs 0:764779eedf2d 6 *
andreikovacs 0:764779eedf2d 7 * Redistribution and use in source and binary forms, with or without modification,
andreikovacs 0:764779eedf2d 8 * are permitted provided that the following conditions are met:
andreikovacs 0:764779eedf2d 9 *
andreikovacs 0:764779eedf2d 10 * o Redistributions of source code must retain the above copyright notice, this list
andreikovacs 0:764779eedf2d 11 * of conditions and the following disclaimer.
andreikovacs 0:764779eedf2d 12 *
andreikovacs 0:764779eedf2d 13 * o Redistributions in binary form must reproduce the above copyright notice, this
andreikovacs 0:764779eedf2d 14 * list of conditions and the following disclaimer in the documentation and/or
andreikovacs 0:764779eedf2d 15 * other materials provided with the distribution.
andreikovacs 0:764779eedf2d 16 *
andreikovacs 0:764779eedf2d 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
andreikovacs 0:764779eedf2d 18 * contributors may be used to endorse or promote products derived from this
andreikovacs 0:764779eedf2d 19 * software without specific prior written permission.
andreikovacs 0:764779eedf2d 20 *
andreikovacs 0:764779eedf2d 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
andreikovacs 0:764779eedf2d 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
andreikovacs 0:764779eedf2d 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
andreikovacs 0:764779eedf2d 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
andreikovacs 0:764779eedf2d 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
andreikovacs 0:764779eedf2d 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
andreikovacs 0:764779eedf2d 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
andreikovacs 0:764779eedf2d 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
andreikovacs 0:764779eedf2d 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
andreikovacs 0:764779eedf2d 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
andreikovacs 0:764779eedf2d 31 */
andreikovacs 0:764779eedf2d 32
andreikovacs 0:764779eedf2d 33 #ifndef __MCR20_DRV_H__
andreikovacs 0:764779eedf2d 34 #define __MCR20_DRV_H__
andreikovacs 0:764779eedf2d 35
andreikovacs 0:764779eedf2d 36
andreikovacs 0:764779eedf2d 37 /*****************************************************************************
andreikovacs 0:764779eedf2d 38 * INCLUDED HEADERS *
andreikovacs 0:764779eedf2d 39 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 40 * Add to this section all the headers that this module needs to include. *
andreikovacs 0:764779eedf2d 41 * Note that it is not a good practice to include header files into header *
andreikovacs 0:764779eedf2d 42 * files, so use this section only if there is no other better solution. *
andreikovacs 0:764779eedf2d 43 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 44 *****************************************************************************/
andreikovacs 0:764779eedf2d 45
andreikovacs 0:764779eedf2d 46 #include "EmbeddedTypes.h"
andreikovacs 0:764779eedf2d 47 #include "mbedAbstraction.h"
andreikovacs 0:764779eedf2d 48
andreikovacs 0:764779eedf2d 49 /*****************************************************************************
andreikovacs 0:764779eedf2d 50 * PRIVATE MACROS *
andreikovacs 0:764779eedf2d 51 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 52 * Add to this section all the access macros, registers mappings, bit access *
andreikovacs 0:764779eedf2d 53 * macros, masks, flags etc ...
andreikovacs 0:764779eedf2d 54 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 55 *****************************************************************************/
andreikovacs 0:764779eedf2d 56 #ifndef gMCR20_ClkOutFreq_d
andreikovacs 0:764779eedf2d 57 #define gMCR20_ClkOutFreq_d gCLK_OUT_FREQ_4_MHz
andreikovacs 0:764779eedf2d 58 #endif
andreikovacs 0:764779eedf2d 59
andreikovacs 0:764779eedf2d 60 /*****************************************************************************
andreikovacs 0:764779eedf2d 61 * PUBLIC FUNCTIONS *
andreikovacs 0:764779eedf2d 62 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 63 * Add to this section all the global functions prototype preceded (as a *
andreikovacs 0:764779eedf2d 64 * good practice) by the keyword 'extern' *
andreikovacs 0:764779eedf2d 65 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 66 *****************************************************************************/
andreikovacs 0:764779eedf2d 67
andreikovacs 0:764779eedf2d 68 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 69 * Name: MCR20Drv_Init
andreikovacs 0:764779eedf2d 70 * Description: -
andreikovacs 0:764779eedf2d 71 * Parameters: -
andreikovacs 0:764779eedf2d 72 * Return: -
andreikovacs 0:764779eedf2d 73 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 74 extern void MCR20Drv_Init
andreikovacs 0:764779eedf2d 75 (
andreikovacs 0:764779eedf2d 76 void
andreikovacs 0:764779eedf2d 77 );
andreikovacs 0:764779eedf2d 78
andreikovacs 0:764779eedf2d 79 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 80 * Name: MCR20Drv_SPI_DMA_Init
andreikovacs 0:764779eedf2d 81 * Description: -
andreikovacs 0:764779eedf2d 82 * Parameters: -
andreikovacs 0:764779eedf2d 83 * Return: -
andreikovacs 0:764779eedf2d 84 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 85 void MCR20Drv_SPI_DMA_Init
andreikovacs 0:764779eedf2d 86 (
andreikovacs 0:764779eedf2d 87 void
andreikovacs 0:764779eedf2d 88 );
andreikovacs 0:764779eedf2d 89
andreikovacs 0:764779eedf2d 90 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 91 * Name: MCR20Drv_Start_PB_DMA_SPI_Write
andreikovacs 0:764779eedf2d 92 * Description: -
andreikovacs 0:764779eedf2d 93 * Parameters: -
andreikovacs 0:764779eedf2d 94 * Return: -
andreikovacs 0:764779eedf2d 95 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 96 void MCR20Drv_Start_PB_DMA_SPI_Write
andreikovacs 0:764779eedf2d 97 (
andreikovacs 0:764779eedf2d 98 uint8_t * srcAddress,
andreikovacs 0:764779eedf2d 99 uint8_t numOfBytes
andreikovacs 0:764779eedf2d 100 );
andreikovacs 0:764779eedf2d 101
andreikovacs 0:764779eedf2d 102 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 103 * Name: MCR20Drv_Start_PB_DMA_SPI_Read
andreikovacs 0:764779eedf2d 104 * Description: -
andreikovacs 0:764779eedf2d 105 * Parameters: -
andreikovacs 0:764779eedf2d 106 * Return: -
andreikovacs 0:764779eedf2d 107 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 108 void MCR20Drv_Start_PB_DMA_SPI_Read
andreikovacs 0:764779eedf2d 109 (
andreikovacs 0:764779eedf2d 110 uint8_t * dstAddress,
andreikovacs 0:764779eedf2d 111 uint8_t numOfBytes
andreikovacs 0:764779eedf2d 112 );
andreikovacs 0:764779eedf2d 113
andreikovacs 0:764779eedf2d 114 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 115 * Name: MCR20Drv_DirectAccessSPIWrite
andreikovacs 0:764779eedf2d 116 * Description: -
andreikovacs 0:764779eedf2d 117 * Parameters: -
andreikovacs 0:764779eedf2d 118 * Return: -
andreikovacs 0:764779eedf2d 119 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 120 void MCR20Drv_DirectAccessSPIWrite
andreikovacs 0:764779eedf2d 121 (
andreikovacs 0:764779eedf2d 122 uint8_t address,
andreikovacs 0:764779eedf2d 123 uint8_t value
andreikovacs 0:764779eedf2d 124 );
andreikovacs 0:764779eedf2d 125
andreikovacs 0:764779eedf2d 126 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 127 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
andreikovacs 0:764779eedf2d 128 * Description: -
andreikovacs 0:764779eedf2d 129 * Parameters: -
andreikovacs 0:764779eedf2d 130 * Return: -
andreikovacs 0:764779eedf2d 131 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 132 void MCR20Drv_DirectAccessSPIMultiByteWrite
andreikovacs 0:764779eedf2d 133 (
andreikovacs 0:764779eedf2d 134 uint8_t startAddress,
andreikovacs 0:764779eedf2d 135 uint8_t * byteArray,
andreikovacs 0:764779eedf2d 136 uint8_t numOfBytes
andreikovacs 0:764779eedf2d 137 );
andreikovacs 0:764779eedf2d 138
andreikovacs 0:764779eedf2d 139 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 140 * Name: MCR20Drv_PB_SPIBurstWrite
andreikovacs 0:764779eedf2d 141 * Description: -
andreikovacs 0:764779eedf2d 142 * Parameters: -
andreikovacs 0:764779eedf2d 143 * Return: -
andreikovacs 0:764779eedf2d 144 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 145 void MCR20Drv_PB_SPIBurstWrite
andreikovacs 0:764779eedf2d 146 (
andreikovacs 0:764779eedf2d 147 uint8_t * byteArray,
andreikovacs 0:764779eedf2d 148 uint8_t numOfBytes
andreikovacs 0:764779eedf2d 149 );
andreikovacs 0:764779eedf2d 150
andreikovacs 0:764779eedf2d 151 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 152 * Name: MCR20Drv_DirectAccessSPIRead
andreikovacs 0:764779eedf2d 153 * Description: -
andreikovacs 0:764779eedf2d 154 * Parameters: -
andreikovacs 0:764779eedf2d 155 * Return: -
andreikovacs 0:764779eedf2d 156 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 157 uint8_t MCR20Drv_DirectAccessSPIRead
andreikovacs 0:764779eedf2d 158 (
andreikovacs 0:764779eedf2d 159 uint8_t address
andreikovacs 0:764779eedf2d 160 );
andreikovacs 0:764779eedf2d 161
andreikovacs 0:764779eedf2d 162 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 163 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
andreikovacs 0:764779eedf2d 164 * Description: -
andreikovacs 0:764779eedf2d 165 * Parameters: -
andreikovacs 0:764779eedf2d 166 * Return: -
andreikovacs 0:764779eedf2d 167 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 168
andreikovacs 0:764779eedf2d 169 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
andreikovacs 0:764779eedf2d 170 (
andreikovacs 0:764779eedf2d 171 uint8_t startAddress,
andreikovacs 0:764779eedf2d 172 uint8_t * byteArray,
andreikovacs 0:764779eedf2d 173 uint8_t numOfBytes
andreikovacs 0:764779eedf2d 174 );
andreikovacs 0:764779eedf2d 175
andreikovacs 0:764779eedf2d 176 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 177 * Name: MCR20Drv_PB_SPIByteWrite
andreikovacs 0:764779eedf2d 178 * Description: -
andreikovacs 0:764779eedf2d 179 * Parameters: -
andreikovacs 0:764779eedf2d 180 * Return: -
andreikovacs 0:764779eedf2d 181 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 182 void MCR20Drv_PB_SPIByteWrite
andreikovacs 0:764779eedf2d 183 (
andreikovacs 0:764779eedf2d 184 uint8_t address,
andreikovacs 0:764779eedf2d 185 uint8_t value
andreikovacs 0:764779eedf2d 186 );
andreikovacs 0:764779eedf2d 187
andreikovacs 0:764779eedf2d 188 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 189 * Name: MCR20Drv_PB_SPIBurstRead
andreikovacs 0:764779eedf2d 190 * Description: -
andreikovacs 0:764779eedf2d 191 * Parameters: -
andreikovacs 0:764779eedf2d 192 * Return: -
andreikovacs 0:764779eedf2d 193 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 194 uint8_t MCR20Drv_PB_SPIBurstRead
andreikovacs 0:764779eedf2d 195 (
andreikovacs 0:764779eedf2d 196 uint8_t * byteArray,
andreikovacs 0:764779eedf2d 197 uint8_t numOfBytes
andreikovacs 0:764779eedf2d 198 );
andreikovacs 0:764779eedf2d 199
andreikovacs 0:764779eedf2d 200 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 201 * Name: MCR20Drv_IndirectAccessSPIWrite
andreikovacs 0:764779eedf2d 202 * Description: -
andreikovacs 0:764779eedf2d 203 * Parameters: -
andreikovacs 0:764779eedf2d 204 * Return: -
andreikovacs 0:764779eedf2d 205 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 206 void MCR20Drv_IndirectAccessSPIWrite
andreikovacs 0:764779eedf2d 207 (
andreikovacs 0:764779eedf2d 208 uint8_t address,
andreikovacs 0:764779eedf2d 209 uint8_t value
andreikovacs 0:764779eedf2d 210 );
andreikovacs 0:764779eedf2d 211
andreikovacs 0:764779eedf2d 212 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 213 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
andreikovacs 0:764779eedf2d 214 * Description: -
andreikovacs 0:764779eedf2d 215 * Parameters: -
andreikovacs 0:764779eedf2d 216 * Return: -
andreikovacs 0:764779eedf2d 217 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 218 void MCR20Drv_IndirectAccessSPIMultiByteWrite
andreikovacs 0:764779eedf2d 219 (
andreikovacs 0:764779eedf2d 220 uint8_t startAddress,
andreikovacs 0:764779eedf2d 221 uint8_t * byteArray,
andreikovacs 0:764779eedf2d 222 uint8_t numOfBytes
andreikovacs 0:764779eedf2d 223 );
andreikovacs 0:764779eedf2d 224
andreikovacs 0:764779eedf2d 225 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 226 * Name: MCR20Drv_IndirectAccessSPIRead
andreikovacs 0:764779eedf2d 227 * Description: -
andreikovacs 0:764779eedf2d 228 * Parameters: -
andreikovacs 0:764779eedf2d 229 * Return: -
andreikovacs 0:764779eedf2d 230 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 231 uint8_t MCR20Drv_IndirectAccessSPIRead
andreikovacs 0:764779eedf2d 232 (
andreikovacs 0:764779eedf2d 233 uint8_t address
andreikovacs 0:764779eedf2d 234 );
andreikovacs 0:764779eedf2d 235 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 236 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
andreikovacs 0:764779eedf2d 237 * Description: -
andreikovacs 0:764779eedf2d 238 * Parameters: -
andreikovacs 0:764779eedf2d 239 * Return: -
andreikovacs 0:764779eedf2d 240 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 241 void MCR20Drv_IndirectAccessSPIMultiByteRead
andreikovacs 0:764779eedf2d 242 (
andreikovacs 0:764779eedf2d 243 uint8_t startAddress,
andreikovacs 0:764779eedf2d 244 uint8_t * byteArray,
andreikovacs 0:764779eedf2d 245 uint8_t numOfBytes
andreikovacs 0:764779eedf2d 246 );
andreikovacs 0:764779eedf2d 247
andreikovacs 0:764779eedf2d 248 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 249 * Name: MCR20Drv_IRQ_PortConfig
andreikovacs 0:764779eedf2d 250 * Description: -
andreikovacs 0:764779eedf2d 251 * Parameters: -
andreikovacs 0:764779eedf2d 252 * Return: -
andreikovacs 0:764779eedf2d 253 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 254 void MCR20Drv_IRQ_PortConfig
andreikovacs 0:764779eedf2d 255 (
andreikovacs 0:764779eedf2d 256 void
andreikovacs 0:764779eedf2d 257 );
andreikovacs 0:764779eedf2d 258
andreikovacs 0:764779eedf2d 259 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 260 * Name: MCR20Drv_IsIrqPending
andreikovacs 0:764779eedf2d 261 * Description: -
andreikovacs 0:764779eedf2d 262 * Parameters: -
andreikovacs 0:764779eedf2d 263 * Return: -
andreikovacs 0:764779eedf2d 264 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 265 uint32_t MCR20Drv_IsIrqPending
andreikovacs 0:764779eedf2d 266 (
andreikovacs 0:764779eedf2d 267 void
andreikovacs 0:764779eedf2d 268 );
andreikovacs 0:764779eedf2d 269
andreikovacs 0:764779eedf2d 270 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 271 * Name: MCR20Drv_IRQ_Disable
andreikovacs 0:764779eedf2d 272 * Description: -
andreikovacs 0:764779eedf2d 273 * Parameters: -
andreikovacs 0:764779eedf2d 274 * Return: -
andreikovacs 0:764779eedf2d 275 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 276 void MCR20Drv_IRQ_Disable
andreikovacs 0:764779eedf2d 277 (
andreikovacs 0:764779eedf2d 278 void
andreikovacs 0:764779eedf2d 279 );
andreikovacs 0:764779eedf2d 280
andreikovacs 0:764779eedf2d 281 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 282 * Name: MCR20Drv_IRQ_Enable
andreikovacs 0:764779eedf2d 283 * Description: -
andreikovacs 0:764779eedf2d 284 * Parameters: -
andreikovacs 0:764779eedf2d 285 * Return: -
andreikovacs 0:764779eedf2d 286 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 287 void MCR20Drv_IRQ_Enable
andreikovacs 0:764779eedf2d 288 (
andreikovacs 0:764779eedf2d 289 void
andreikovacs 0:764779eedf2d 290 );
andreikovacs 0:764779eedf2d 291
andreikovacs 0:764779eedf2d 292 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 293 * Name: MCR20Drv_IRQ_IsEnabled
andreikovacs 0:764779eedf2d 294 * Description: -
andreikovacs 0:764779eedf2d 295 * Parameters: -
andreikovacs 0:764779eedf2d 296 * Return: -
andreikovacs 0:764779eedf2d 297 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 298 uint32_t MCR20Drv_IRQ_IsEnabled
andreikovacs 0:764779eedf2d 299 (
andreikovacs 0:764779eedf2d 300 void
andreikovacs 0:764779eedf2d 301 );
andreikovacs 0:764779eedf2d 302
andreikovacs 0:764779eedf2d 303 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 304 * Name: MCR20Drv_IRQ_Clear
andreikovacs 0:764779eedf2d 305 * Description: -
andreikovacs 0:764779eedf2d 306 * Parameters: -
andreikovacs 0:764779eedf2d 307 * Return: -
andreikovacs 0:764779eedf2d 308 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 309 void MCR20Drv_IRQ_Clear
andreikovacs 0:764779eedf2d 310 (
andreikovacs 0:764779eedf2d 311 void
andreikovacs 0:764779eedf2d 312 );
andreikovacs 0:764779eedf2d 313
andreikovacs 0:764779eedf2d 314 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 315 * Name: MCR20Drv_RST_PortConfig
andreikovacs 0:764779eedf2d 316 * Description: -
andreikovacs 0:764779eedf2d 317 * Parameters: -
andreikovacs 0:764779eedf2d 318 * Return: -
andreikovacs 0:764779eedf2d 319 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 320 void MCR20Drv_RST_B_PortConfig
andreikovacs 0:764779eedf2d 321 (
andreikovacs 0:764779eedf2d 322 void
andreikovacs 0:764779eedf2d 323 );
andreikovacs 0:764779eedf2d 324
andreikovacs 0:764779eedf2d 325 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 326 * Name: MCR20Drv_RST_Assert
andreikovacs 0:764779eedf2d 327 * Description: -
andreikovacs 0:764779eedf2d 328 * Parameters: -
andreikovacs 0:764779eedf2d 329 * Return: -
andreikovacs 0:764779eedf2d 330 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 331 void MCR20Drv_RST_B_Assert
andreikovacs 0:764779eedf2d 332 (
andreikovacs 0:764779eedf2d 333 void
andreikovacs 0:764779eedf2d 334 );
andreikovacs 0:764779eedf2d 335
andreikovacs 0:764779eedf2d 336 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 337 * Name: MCR20Drv_RST_Deassert
andreikovacs 0:764779eedf2d 338 * Description: -
andreikovacs 0:764779eedf2d 339 * Parameters: -
andreikovacs 0:764779eedf2d 340 * Return: -
andreikovacs 0:764779eedf2d 341 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 342 void MCR20Drv_RST_B_Deassert
andreikovacs 0:764779eedf2d 343 (
andreikovacs 0:764779eedf2d 344 void
andreikovacs 0:764779eedf2d 345 );
andreikovacs 0:764779eedf2d 346
andreikovacs 0:764779eedf2d 347 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 348 * Name: MCR20Drv_SoftRST_Assert
andreikovacs 0:764779eedf2d 349 * Description: -
andreikovacs 0:764779eedf2d 350 * Parameters: -
andreikovacs 0:764779eedf2d 351 * Return: -
andreikovacs 0:764779eedf2d 352 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 353 void MCR20Drv_SoftRST_Assert
andreikovacs 0:764779eedf2d 354 (
andreikovacs 0:764779eedf2d 355 void
andreikovacs 0:764779eedf2d 356 );
andreikovacs 0:764779eedf2d 357
andreikovacs 0:764779eedf2d 358 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 359 * Name: MCR20Drv_SoftRST_Deassert
andreikovacs 0:764779eedf2d 360 * Description: -
andreikovacs 0:764779eedf2d 361 * Parameters: -
andreikovacs 0:764779eedf2d 362 * Return: -
andreikovacs 0:764779eedf2d 363 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 364 void MCR20Drv_SoftRST_Deassert
andreikovacs 0:764779eedf2d 365 (
andreikovacs 0:764779eedf2d 366 void
andreikovacs 0:764779eedf2d 367 );
andreikovacs 0:764779eedf2d 368
andreikovacs 0:764779eedf2d 369
andreikovacs 0:764779eedf2d 370 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 371 * Name: MCR20Drv_RESET
andreikovacs 0:764779eedf2d 372 * Description: -
andreikovacs 0:764779eedf2d 373 * Parameters: -
andreikovacs 0:764779eedf2d 374 * Return: -
andreikovacs 0:764779eedf2d 375 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 376 void MCR20Drv_RESET
andreikovacs 0:764779eedf2d 377 (
andreikovacs 0:764779eedf2d 378 void
andreikovacs 0:764779eedf2d 379 );
andreikovacs 0:764779eedf2d 380
andreikovacs 0:764779eedf2d 381 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 382 * Name: MCR20Drv_Soft_RESET
andreikovacs 0:764779eedf2d 383 * Description: -
andreikovacs 0:764779eedf2d 384 * Parameters: -
andreikovacs 0:764779eedf2d 385 * Return: -
andreikovacs 0:764779eedf2d 386 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 387 void MCR20Drv_Soft_RESET
andreikovacs 0:764779eedf2d 388 (
andreikovacs 0:764779eedf2d 389 void
andreikovacs 0:764779eedf2d 390 );
andreikovacs 0:764779eedf2d 391
andreikovacs 0:764779eedf2d 392 /*---------------------------------------------------------------------------
andreikovacs 0:764779eedf2d 393 * Name: MCR20Drv_Set_CLK_OUT_Freq
andreikovacs 0:764779eedf2d 394 * Description: -
andreikovacs 0:764779eedf2d 395 * Parameters: -
andreikovacs 0:764779eedf2d 396 * Return: -
andreikovacs 0:764779eedf2d 397 *---------------------------------------------------------------------------*/
andreikovacs 0:764779eedf2d 398 void MCR20Drv_Set_CLK_OUT_Freq
andreikovacs 0:764779eedf2d 399 (
andreikovacs 0:764779eedf2d 400 uint8_t freqDiv
andreikovacs 0:764779eedf2d 401 );
andreikovacs 0:764779eedf2d 402
andreikovacs 0:764779eedf2d 403 #define ProtectFromMCR20Interrupt() MCR20Drv_IRQ_Disable()
andreikovacs 0:764779eedf2d 404 #define UnprotectFromMCR20Interrupt() MCR20Drv_IRQ_Enable()
andreikovacs 0:764779eedf2d 405
andreikovacs 0:764779eedf2d 406 #endif /* __MCR20_DRV_H__ */