NXP
A library implementing IEEE 802.15.4 PHY functionality for the MCR20A transceiver. The PHY sublayer provides two services: the PHY data service and the PHY management service interfacing to the PHY sublayer management entity (PLME) service access point (SAP) (known as PLME-SAP). The PHY data service enables the transmission and reception of PHY protocol data units (PSDUs) over the media (radio).
Fork of
fsl_phy_mcr20a
by 
Freescale
The Freescale PHY Layer deals with the physical burst which is to be sent and/or received. It performs modulation and demodulation, transmitter and receiver switching, fragmentation, scrambling, interleaving, and error correction coding. The communication to the upper protocol layers is carried out through the Layer 1 Interface.
The PHY Layer is capable of executing the following sequences:
- I (Idle)
- R (Receive Sequence conditionally followed by a TxAck)
- T (Transmit Sequence)
- C (Standalone CCA)
- CCCA (Continuous CCA)
- TR (Transmit/Receive Sequence - transmit unconditionally followed by either an R or RxAck)
In addition to these sequences the PHY Layer also integrates a packet processor which determines whether the packet is MAC-compliant, and if it is, whether it is addressed to the end device. Another feature of the packet processor is Source Address Matching which can be viewed as an extension of packet filtering; however its function is very specific to its intended application (data-polling and indirect queue management by a PAN Coordinator).
Documentation
PHY/MCR20Drv/MCR20Drv.c@0:764779eedf2d, 2015-08-18 (annotated)
- Committer:
- andreikovacs
- Date:
- Tue Aug 18 12:41:42 2015 +0000
- Revision:
- 0:764779eedf2d
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| andreikovacs | 0:764779eedf2d | 1 | /*! |
| andreikovacs | 0:764779eedf2d | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| andreikovacs | 0:764779eedf2d | 3 | * All rights reserved. |
| andreikovacs | 0:764779eedf2d | 4 | * |
| andreikovacs | 0:764779eedf2d | 5 | * \file MCR20Drv.c |
| andreikovacs | 0:764779eedf2d | 6 | * |
| andreikovacs | 0:764779eedf2d | 7 | * Redistribution and use in source and binary forms, with or without modification, |
| andreikovacs | 0:764779eedf2d | 8 | * are permitted provided that the following conditions are met: |
| andreikovacs | 0:764779eedf2d | 9 | * |
| andreikovacs | 0:764779eedf2d | 10 | * o Redistributions of source code must retain the above copyright notice, this list |
| andreikovacs | 0:764779eedf2d | 11 | * of conditions and the following disclaimer. |
| andreikovacs | 0:764779eedf2d | 12 | * |
| andreikovacs | 0:764779eedf2d | 13 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| andreikovacs | 0:764779eedf2d | 14 | * list of conditions and the following disclaimer in the documentation and/or |
| andreikovacs | 0:764779eedf2d | 15 | * other materials provided with the distribution. |
| andreikovacs | 0:764779eedf2d | 16 | * |
| andreikovacs | 0:764779eedf2d | 17 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| andreikovacs | 0:764779eedf2d | 18 | * contributors may be used to endorse or promote products derived from this |
| andreikovacs | 0:764779eedf2d | 19 | * software without specific prior written permission. |
| andreikovacs | 0:764779eedf2d | 20 | * |
| andreikovacs | 0:764779eedf2d | 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| andreikovacs | 0:764779eedf2d | 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| andreikovacs | 0:764779eedf2d | 23 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| andreikovacs | 0:764779eedf2d | 24 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| andreikovacs | 0:764779eedf2d | 25 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| andreikovacs | 0:764779eedf2d | 26 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| andreikovacs | 0:764779eedf2d | 27 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| andreikovacs | 0:764779eedf2d | 28 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| andreikovacs | 0:764779eedf2d | 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| andreikovacs | 0:764779eedf2d | 30 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| andreikovacs | 0:764779eedf2d | 31 | */ |
| andreikovacs | 0:764779eedf2d | 32 | |
| andreikovacs | 0:764779eedf2d | 33 | |
| andreikovacs | 0:764779eedf2d | 34 | /***************************************************************************** |
| andreikovacs | 0:764779eedf2d | 35 | * INCLUDED HEADERS * |
| andreikovacs | 0:764779eedf2d | 36 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 37 | * Add to this section all the headers that this module needs to include. * |
| andreikovacs | 0:764779eedf2d | 38 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 39 | *****************************************************************************/ |
| andreikovacs | 0:764779eedf2d | 40 | |
| andreikovacs | 0:764779eedf2d | 41 | #include "MCR20Drv.h" |
| andreikovacs | 0:764779eedf2d | 42 | #include "MCR20Reg.h" |
| andreikovacs | 0:764779eedf2d | 43 | |
| andreikovacs | 0:764779eedf2d | 44 | #include "XcvrSpi.h" |
| andreikovacs | 0:764779eedf2d | 45 | |
| andreikovacs | 0:764779eedf2d | 46 | /***************************************************************************** |
| andreikovacs | 0:764779eedf2d | 47 | * PRIVATE VARIABLES * |
| andreikovacs | 0:764779eedf2d | 48 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 49 | * Add to this section all the variables and constants that have local * |
| andreikovacs | 0:764779eedf2d | 50 | * (file) scope. * |
| andreikovacs | 0:764779eedf2d | 51 | * Each of this declarations shall be preceded by the 'static' keyword. * |
| andreikovacs | 0:764779eedf2d | 52 | * These variables / constants cannot be accessed outside this module. * |
| andreikovacs | 0:764779eedf2d | 53 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 54 | *****************************************************************************/ |
| andreikovacs | 0:764779eedf2d | 55 | static uint32_t mPhyIrqDisableCnt = 1; |
| andreikovacs | 0:764779eedf2d | 56 | |
| andreikovacs | 0:764779eedf2d | 57 | /***************************************************************************** |
| andreikovacs | 0:764779eedf2d | 58 | * PUBLIC VARIABLES * |
| andreikovacs | 0:764779eedf2d | 59 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 60 | * Add to this section all the variables and constants that have global * |
| andreikovacs | 0:764779eedf2d | 61 | * (project) scope. * |
| andreikovacs | 0:764779eedf2d | 62 | * These variables / constants can be accessed outside this module. * |
| andreikovacs | 0:764779eedf2d | 63 | * These variables / constants shall be preceded by the 'extern' keyword in * |
| andreikovacs | 0:764779eedf2d | 64 | * the interface header. * |
| andreikovacs | 0:764779eedf2d | 65 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 66 | *****************************************************************************/ |
| andreikovacs | 0:764779eedf2d | 67 | |
| andreikovacs | 0:764779eedf2d | 68 | /***************************************************************************** |
| andreikovacs | 0:764779eedf2d | 69 | * PRIVATE FUNCTIONS PROTOTYPES * |
| andreikovacs | 0:764779eedf2d | 70 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 71 | * Add to this section all the functions prototypes that have local (file) * |
| andreikovacs | 0:764779eedf2d | 72 | * scope. * |
| andreikovacs | 0:764779eedf2d | 73 | * These functions cannot be accessed outside this module. * |
| andreikovacs | 0:764779eedf2d | 74 | * These declarations shall be preceded by the 'static' keyword. * |
| andreikovacs | 0:764779eedf2d | 75 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 76 | *****************************************************************************/ |
| andreikovacs | 0:764779eedf2d | 77 | |
| andreikovacs | 0:764779eedf2d | 78 | /***************************************************************************** |
| andreikovacs | 0:764779eedf2d | 79 | * PRIVATE FUNCTIONS * |
| andreikovacs | 0:764779eedf2d | 80 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 81 | * Add to this section all the functions that have local (file) scope. * |
| andreikovacs | 0:764779eedf2d | 82 | * These functions cannot be accessed outside this module. * |
| andreikovacs | 0:764779eedf2d | 83 | * These definitions shall be preceded by the 'static' keyword. * |
| andreikovacs | 0:764779eedf2d | 84 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 85 | *****************************************************************************/ |
| andreikovacs | 0:764779eedf2d | 86 | |
| andreikovacs | 0:764779eedf2d | 87 | |
| andreikovacs | 0:764779eedf2d | 88 | /***************************************************************************** |
| andreikovacs | 0:764779eedf2d | 89 | * PUBLIC FUNCTIONS * |
| andreikovacs | 0:764779eedf2d | 90 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 91 | * Add to this section all the functions that have global (project) scope. * |
| andreikovacs | 0:764779eedf2d | 92 | * These functions can be accessed outside this module. * |
| andreikovacs | 0:764779eedf2d | 93 | * These functions shall have their declarations (prototypes) within the * |
| andreikovacs | 0:764779eedf2d | 94 | * interface header file and shall be preceded by the 'extern' keyword. * |
| andreikovacs | 0:764779eedf2d | 95 | *---------------------------------------------------------------------------* |
| andreikovacs | 0:764779eedf2d | 96 | *****************************************************************************/ |
| andreikovacs | 0:764779eedf2d | 97 | |
| andreikovacs | 0:764779eedf2d | 98 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 99 | * Name: MCR20Drv_Init |
| andreikovacs | 0:764779eedf2d | 100 | * Description: - |
| andreikovacs | 0:764779eedf2d | 101 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 102 | * Return: - |
| andreikovacs | 0:764779eedf2d | 103 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 104 | void MCR20Drv_Init |
| andreikovacs | 0:764779eedf2d | 105 | ( |
| andreikovacs | 0:764779eedf2d | 106 | void |
| andreikovacs | 0:764779eedf2d | 107 | ) |
| andreikovacs | 0:764779eedf2d | 108 | { |
| andreikovacs | 0:764779eedf2d | 109 | spi_master_init(gXcvrSpiInstance_c); |
| andreikovacs | 0:764779eedf2d | 110 | spi_master_configure_speed(gXcvrSpiInstance_c, 8000000); |
| andreikovacs | 0:764779eedf2d | 111 | |
| andreikovacs | 0:764779eedf2d | 112 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 113 | MCR20Drv_RST_B_Deassert(); |
| andreikovacs | 0:764779eedf2d | 114 | //MCR20Drv_RESET(); |
| andreikovacs | 0:764779eedf2d | 115 | } |
| andreikovacs | 0:764779eedf2d | 116 | |
| andreikovacs | 0:764779eedf2d | 117 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 118 | * Name: MCR20Drv_DirectAccessSPIWrite |
| andreikovacs | 0:764779eedf2d | 119 | * Description: - |
| andreikovacs | 0:764779eedf2d | 120 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 121 | * Return: - |
| andreikovacs | 0:764779eedf2d | 122 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 123 | void MCR20Drv_DirectAccessSPIWrite |
| andreikovacs | 0:764779eedf2d | 124 | ( |
| andreikovacs | 0:764779eedf2d | 125 | uint8_t address, |
| andreikovacs | 0:764779eedf2d | 126 | uint8_t value |
| andreikovacs | 0:764779eedf2d | 127 | ) |
| andreikovacs | 0:764779eedf2d | 128 | { |
| andreikovacs | 0:764779eedf2d | 129 | uint16_t txData; |
| andreikovacs | 0:764779eedf2d | 130 | |
| andreikovacs | 0:764779eedf2d | 131 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 132 | |
| andreikovacs | 0:764779eedf2d | 133 | spi_master_configure_speed(gXcvrSpiInstance_c, 16000000); |
| andreikovacs | 0:764779eedf2d | 134 | |
| andreikovacs | 0:764779eedf2d | 135 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 136 | |
| andreikovacs | 0:764779eedf2d | 137 | txData = (address & TransceiverSPI_DirectRegisterAddressMask); |
| andreikovacs | 0:764779eedf2d | 138 | txData |= value << 8; |
| andreikovacs | 0:764779eedf2d | 139 | |
| andreikovacs | 0:764779eedf2d | 140 | spi_master_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, NULL, sizeof(txData)); |
| andreikovacs | 0:764779eedf2d | 141 | |
| andreikovacs | 0:764779eedf2d | 142 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 143 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 144 | } |
| andreikovacs | 0:764779eedf2d | 145 | |
| andreikovacs | 0:764779eedf2d | 146 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 147 | * Name: MCR20Drv_DirectAccessSPIMultiByteWrite |
| andreikovacs | 0:764779eedf2d | 148 | * Description: - |
| andreikovacs | 0:764779eedf2d | 149 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 150 | * Return: - |
| andreikovacs | 0:764779eedf2d | 151 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 152 | void MCR20Drv_DirectAccessSPIMultiByteWrite |
| andreikovacs | 0:764779eedf2d | 153 | ( |
| andreikovacs | 0:764779eedf2d | 154 | uint8_t startAddress, |
| andreikovacs | 0:764779eedf2d | 155 | uint8_t * byteArray, |
| andreikovacs | 0:764779eedf2d | 156 | uint8_t numOfBytes |
| andreikovacs | 0:764779eedf2d | 157 | ) |
| andreikovacs | 0:764779eedf2d | 158 | { |
| andreikovacs | 0:764779eedf2d | 159 | uint8_t txData; |
| andreikovacs | 0:764779eedf2d | 160 | |
| andreikovacs | 0:764779eedf2d | 161 | if( (numOfBytes == 0) || (byteArray == NULL) ) |
| andreikovacs | 0:764779eedf2d | 162 | { |
| andreikovacs | 0:764779eedf2d | 163 | return; |
| andreikovacs | 0:764779eedf2d | 164 | } |
| andreikovacs | 0:764779eedf2d | 165 | |
| andreikovacs | 0:764779eedf2d | 166 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 167 | |
| andreikovacs | 0:764779eedf2d | 168 | spi_master_configure_speed(gXcvrSpiInstance_c, 16000000); |
| andreikovacs | 0:764779eedf2d | 169 | |
| andreikovacs | 0:764779eedf2d | 170 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 171 | |
| andreikovacs | 0:764779eedf2d | 172 | txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask); |
| andreikovacs | 0:764779eedf2d | 173 | |
| andreikovacs | 0:764779eedf2d | 174 | spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, sizeof(txData)); |
| andreikovacs | 0:764779eedf2d | 175 | spi_master_transfer(gXcvrSpiInstance_c, byteArray, NULL, numOfBytes); |
| andreikovacs | 0:764779eedf2d | 176 | |
| andreikovacs | 0:764779eedf2d | 177 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 178 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 179 | } |
| andreikovacs | 0:764779eedf2d | 180 | |
| andreikovacs | 0:764779eedf2d | 181 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 182 | * Name: MCR20Drv_PB_SPIByteWrite |
| andreikovacs | 0:764779eedf2d | 183 | * Description: - |
| andreikovacs | 0:764779eedf2d | 184 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 185 | * Return: - |
| andreikovacs | 0:764779eedf2d | 186 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 187 | void MCR20Drv_PB_SPIByteWrite |
| andreikovacs | 0:764779eedf2d | 188 | ( |
| andreikovacs | 0:764779eedf2d | 189 | uint8_t address, |
| andreikovacs | 0:764779eedf2d | 190 | uint8_t value |
| andreikovacs | 0:764779eedf2d | 191 | ) |
| andreikovacs | 0:764779eedf2d | 192 | { |
| andreikovacs | 0:764779eedf2d | 193 | uint32_t txData; |
| andreikovacs | 0:764779eedf2d | 194 | |
| andreikovacs | 0:764779eedf2d | 195 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 196 | |
| andreikovacs | 0:764779eedf2d | 197 | spi_master_configure_speed(gXcvrSpiInstance_c, 16000000); |
| andreikovacs | 0:764779eedf2d | 198 | |
| andreikovacs | 0:764779eedf2d | 199 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 200 | |
| andreikovacs | 0:764779eedf2d | 201 | txData = TransceiverSPI_WriteSelect | |
| andreikovacs | 0:764779eedf2d | 202 | TransceiverSPI_PacketBuffAccessSelect | |
| andreikovacs | 0:764779eedf2d | 203 | TransceiverSPI_PacketBuffByteModeSelect; |
| andreikovacs | 0:764779eedf2d | 204 | txData |= (address) << 8; |
| andreikovacs | 0:764779eedf2d | 205 | txData |= (value) << 16; |
| andreikovacs | 0:764779eedf2d | 206 | |
| andreikovacs | 0:764779eedf2d | 207 | spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, 3); |
| andreikovacs | 0:764779eedf2d | 208 | |
| andreikovacs | 0:764779eedf2d | 209 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 210 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 211 | } |
| andreikovacs | 0:764779eedf2d | 212 | |
| andreikovacs | 0:764779eedf2d | 213 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 214 | * Name: MCR20Drv_PB_SPIBurstWrite |
| andreikovacs | 0:764779eedf2d | 215 | * Description: - |
| andreikovacs | 0:764779eedf2d | 216 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 217 | * Return: - |
| andreikovacs | 0:764779eedf2d | 218 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 219 | void MCR20Drv_PB_SPIBurstWrite |
| andreikovacs | 0:764779eedf2d | 220 | ( |
| andreikovacs | 0:764779eedf2d | 221 | uint8_t * byteArray, |
| andreikovacs | 0:764779eedf2d | 222 | uint8_t numOfBytes |
| andreikovacs | 0:764779eedf2d | 223 | ) |
| andreikovacs | 0:764779eedf2d | 224 | { |
| andreikovacs | 0:764779eedf2d | 225 | uint8_t txData; |
| andreikovacs | 0:764779eedf2d | 226 | |
| andreikovacs | 0:764779eedf2d | 227 | if( (numOfBytes == 0) || (byteArray == NULL) ) |
| andreikovacs | 0:764779eedf2d | 228 | { |
| andreikovacs | 0:764779eedf2d | 229 | return; |
| andreikovacs | 0:764779eedf2d | 230 | } |
| andreikovacs | 0:764779eedf2d | 231 | |
| andreikovacs | 0:764779eedf2d | 232 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 233 | |
| andreikovacs | 0:764779eedf2d | 234 | spi_master_configure_speed(gXcvrSpiInstance_c, 16000000); |
| andreikovacs | 0:764779eedf2d | 235 | |
| andreikovacs | 0:764779eedf2d | 236 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 237 | |
| andreikovacs | 0:764779eedf2d | 238 | txData = TransceiverSPI_WriteSelect | |
| andreikovacs | 0:764779eedf2d | 239 | TransceiverSPI_PacketBuffAccessSelect | |
| andreikovacs | 0:764779eedf2d | 240 | TransceiverSPI_PacketBuffBurstModeSelect; |
| andreikovacs | 0:764779eedf2d | 241 | |
| andreikovacs | 0:764779eedf2d | 242 | spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, 1); |
| andreikovacs | 0:764779eedf2d | 243 | spi_master_transfer(gXcvrSpiInstance_c, byteArray, NULL, numOfBytes); |
| andreikovacs | 0:764779eedf2d | 244 | |
| andreikovacs | 0:764779eedf2d | 245 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 246 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 247 | } |
| andreikovacs | 0:764779eedf2d | 248 | |
| andreikovacs | 0:764779eedf2d | 249 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 250 | * Name: MCR20Drv_DirectAccessSPIRead |
| andreikovacs | 0:764779eedf2d | 251 | * Description: - |
| andreikovacs | 0:764779eedf2d | 252 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 253 | * Return: - |
| andreikovacs | 0:764779eedf2d | 254 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 255 | |
| andreikovacs | 0:764779eedf2d | 256 | uint8_t MCR20Drv_DirectAccessSPIRead |
| andreikovacs | 0:764779eedf2d | 257 | ( |
| andreikovacs | 0:764779eedf2d | 258 | uint8_t address |
| andreikovacs | 0:764779eedf2d | 259 | ) |
| andreikovacs | 0:764779eedf2d | 260 | { |
| andreikovacs | 0:764779eedf2d | 261 | uint8_t txData; |
| andreikovacs | 0:764779eedf2d | 262 | uint8_t rxData; |
| andreikovacs | 0:764779eedf2d | 263 | |
| andreikovacs | 0:764779eedf2d | 264 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 265 | |
| andreikovacs | 0:764779eedf2d | 266 | spi_master_configure_speed(gXcvrSpiInstance_c, 8000000); |
| andreikovacs | 0:764779eedf2d | 267 | |
| andreikovacs | 0:764779eedf2d | 268 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 269 | |
| andreikovacs | 0:764779eedf2d | 270 | txData = (address & TransceiverSPI_DirectRegisterAddressMask) | |
| andreikovacs | 0:764779eedf2d | 271 | TransceiverSPI_ReadSelect; |
| andreikovacs | 0:764779eedf2d | 272 | |
| andreikovacs | 0:764779eedf2d | 273 | spi_master_transfer(gXcvrSpiInstance_c, &txData, NULL, sizeof(txData)); |
| andreikovacs | 0:764779eedf2d | 274 | spi_master_transfer(gXcvrSpiInstance_c, NULL, &rxData, sizeof(rxData)); |
| andreikovacs | 0:764779eedf2d | 275 | |
| andreikovacs | 0:764779eedf2d | 276 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 277 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 278 | |
| andreikovacs | 0:764779eedf2d | 279 | return rxData; |
| andreikovacs | 0:764779eedf2d | 280 | |
| andreikovacs | 0:764779eedf2d | 281 | } |
| andreikovacs | 0:764779eedf2d | 282 | |
| andreikovacs | 0:764779eedf2d | 283 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 284 | * Name: MCR20Drv_DirectAccessSPIMultyByteRead |
| andreikovacs | 0:764779eedf2d | 285 | * Description: - |
| andreikovacs | 0:764779eedf2d | 286 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 287 | * Return: - |
| andreikovacs | 0:764779eedf2d | 288 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 289 | uint8_t MCR20Drv_DirectAccessSPIMultiByteRead |
| andreikovacs | 0:764779eedf2d | 290 | ( |
| andreikovacs | 0:764779eedf2d | 291 | uint8_t startAddress, |
| andreikovacs | 0:764779eedf2d | 292 | uint8_t * byteArray, |
| andreikovacs | 0:764779eedf2d | 293 | uint8_t numOfBytes |
| andreikovacs | 0:764779eedf2d | 294 | ) |
| andreikovacs | 0:764779eedf2d | 295 | { |
| andreikovacs | 0:764779eedf2d | 296 | uint8_t txData; |
| andreikovacs | 0:764779eedf2d | 297 | uint8_t phyIRQSTS1; |
| andreikovacs | 0:764779eedf2d | 298 | |
| andreikovacs | 0:764779eedf2d | 299 | if( (numOfBytes == 0) || (byteArray == NULL) ) |
| andreikovacs | 0:764779eedf2d | 300 | { |
| andreikovacs | 0:764779eedf2d | 301 | return 0; |
| andreikovacs | 0:764779eedf2d | 302 | } |
| andreikovacs | 0:764779eedf2d | 303 | |
| andreikovacs | 0:764779eedf2d | 304 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 305 | |
| andreikovacs | 0:764779eedf2d | 306 | spi_master_configure_speed(gXcvrSpiInstance_c, 8000000); |
| andreikovacs | 0:764779eedf2d | 307 | |
| andreikovacs | 0:764779eedf2d | 308 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 309 | |
| andreikovacs | 0:764779eedf2d | 310 | txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) | |
| andreikovacs | 0:764779eedf2d | 311 | TransceiverSPI_ReadSelect; |
| andreikovacs | 0:764779eedf2d | 312 | |
| andreikovacs | 0:764779eedf2d | 313 | spi_master_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData)); |
| andreikovacs | 0:764779eedf2d | 314 | spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes); |
| andreikovacs | 0:764779eedf2d | 315 | |
| andreikovacs | 0:764779eedf2d | 316 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 317 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 318 | |
| andreikovacs | 0:764779eedf2d | 319 | return phyIRQSTS1; |
| andreikovacs | 0:764779eedf2d | 320 | } |
| andreikovacs | 0:764779eedf2d | 321 | |
| andreikovacs | 0:764779eedf2d | 322 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 323 | * Name: MCR20Drv_PB_SPIBurstRead |
| andreikovacs | 0:764779eedf2d | 324 | * Description: - |
| andreikovacs | 0:764779eedf2d | 325 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 326 | * Return: - |
| andreikovacs | 0:764779eedf2d | 327 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 328 | uint8_t MCR20Drv_PB_SPIBurstRead |
| andreikovacs | 0:764779eedf2d | 329 | ( |
| andreikovacs | 0:764779eedf2d | 330 | uint8_t * byteArray, |
| andreikovacs | 0:764779eedf2d | 331 | uint8_t numOfBytes |
| andreikovacs | 0:764779eedf2d | 332 | ) |
| andreikovacs | 0:764779eedf2d | 333 | { |
| andreikovacs | 0:764779eedf2d | 334 | uint8_t txData; |
| andreikovacs | 0:764779eedf2d | 335 | uint8_t phyIRQSTS1; |
| andreikovacs | 0:764779eedf2d | 336 | |
| andreikovacs | 0:764779eedf2d | 337 | if( (numOfBytes == 0) || (byteArray == NULL) ) |
| andreikovacs | 0:764779eedf2d | 338 | { |
| andreikovacs | 0:764779eedf2d | 339 | return 0; |
| andreikovacs | 0:764779eedf2d | 340 | } |
| andreikovacs | 0:764779eedf2d | 341 | |
| andreikovacs | 0:764779eedf2d | 342 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 343 | |
| andreikovacs | 0:764779eedf2d | 344 | spi_master_configure_speed(gXcvrSpiInstance_c, 8000000); |
| andreikovacs | 0:764779eedf2d | 345 | |
| andreikovacs | 0:764779eedf2d | 346 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 347 | |
| andreikovacs | 0:764779eedf2d | 348 | txData = TransceiverSPI_ReadSelect | |
| andreikovacs | 0:764779eedf2d | 349 | TransceiverSPI_PacketBuffAccessSelect | |
| andreikovacs | 0:764779eedf2d | 350 | TransceiverSPI_PacketBuffBurstModeSelect; |
| andreikovacs | 0:764779eedf2d | 351 | |
| andreikovacs | 0:764779eedf2d | 352 | spi_master_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData)); |
| andreikovacs | 0:764779eedf2d | 353 | spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes); |
| andreikovacs | 0:764779eedf2d | 354 | |
| andreikovacs | 0:764779eedf2d | 355 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 356 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 357 | |
| andreikovacs | 0:764779eedf2d | 358 | return phyIRQSTS1; |
| andreikovacs | 0:764779eedf2d | 359 | } |
| andreikovacs | 0:764779eedf2d | 360 | |
| andreikovacs | 0:764779eedf2d | 361 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 362 | * Name: MCR20Drv_IndirectAccessSPIWrite |
| andreikovacs | 0:764779eedf2d | 363 | * Description: - |
| andreikovacs | 0:764779eedf2d | 364 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 365 | * Return: - |
| andreikovacs | 0:764779eedf2d | 366 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 367 | void MCR20Drv_IndirectAccessSPIWrite |
| andreikovacs | 0:764779eedf2d | 368 | ( |
| andreikovacs | 0:764779eedf2d | 369 | uint8_t address, |
| andreikovacs | 0:764779eedf2d | 370 | uint8_t value |
| andreikovacs | 0:764779eedf2d | 371 | ) |
| andreikovacs | 0:764779eedf2d | 372 | { |
| andreikovacs | 0:764779eedf2d | 373 | uint32_t txData; |
| andreikovacs | 0:764779eedf2d | 374 | |
| andreikovacs | 0:764779eedf2d | 375 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 376 | |
| andreikovacs | 0:764779eedf2d | 377 | spi_master_configure_speed(gXcvrSpiInstance_c, 16000000); |
| andreikovacs | 0:764779eedf2d | 378 | |
| andreikovacs | 0:764779eedf2d | 379 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 380 | |
| andreikovacs | 0:764779eedf2d | 381 | txData = TransceiverSPI_IARIndexReg; |
| andreikovacs | 0:764779eedf2d | 382 | txData |= (address) << 8; |
| andreikovacs | 0:764779eedf2d | 383 | txData |= (value) << 16; |
| andreikovacs | 0:764779eedf2d | 384 | |
| andreikovacs | 0:764779eedf2d | 385 | spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, 3); |
| andreikovacs | 0:764779eedf2d | 386 | |
| andreikovacs | 0:764779eedf2d | 387 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 388 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 389 | } |
| andreikovacs | 0:764779eedf2d | 390 | |
| andreikovacs | 0:764779eedf2d | 391 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 392 | * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite |
| andreikovacs | 0:764779eedf2d | 393 | * Description: - |
| andreikovacs | 0:764779eedf2d | 394 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 395 | * Return: - |
| andreikovacs | 0:764779eedf2d | 396 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 397 | void MCR20Drv_IndirectAccessSPIMultiByteWrite |
| andreikovacs | 0:764779eedf2d | 398 | ( |
| andreikovacs | 0:764779eedf2d | 399 | uint8_t startAddress, |
| andreikovacs | 0:764779eedf2d | 400 | uint8_t * byteArray, |
| andreikovacs | 0:764779eedf2d | 401 | uint8_t numOfBytes |
| andreikovacs | 0:764779eedf2d | 402 | ) |
| andreikovacs | 0:764779eedf2d | 403 | { |
| andreikovacs | 0:764779eedf2d | 404 | uint16_t txData; |
| andreikovacs | 0:764779eedf2d | 405 | |
| andreikovacs | 0:764779eedf2d | 406 | if( (numOfBytes == 0) || (byteArray == NULL) ) |
| andreikovacs | 0:764779eedf2d | 407 | { |
| andreikovacs | 0:764779eedf2d | 408 | return; |
| andreikovacs | 0:764779eedf2d | 409 | } |
| andreikovacs | 0:764779eedf2d | 410 | |
| andreikovacs | 0:764779eedf2d | 411 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 412 | |
| andreikovacs | 0:764779eedf2d | 413 | spi_master_configure_speed(gXcvrSpiInstance_c, 16000000); |
| andreikovacs | 0:764779eedf2d | 414 | |
| andreikovacs | 0:764779eedf2d | 415 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 416 | |
| andreikovacs | 0:764779eedf2d | 417 | txData = TransceiverSPI_IARIndexReg; |
| andreikovacs | 0:764779eedf2d | 418 | txData |= (startAddress) << 8; |
| andreikovacs | 0:764779eedf2d | 419 | |
| andreikovacs | 0:764779eedf2d | 420 | spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData)); |
| andreikovacs | 0:764779eedf2d | 421 | spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, NULL, numOfBytes); |
| andreikovacs | 0:764779eedf2d | 422 | |
| andreikovacs | 0:764779eedf2d | 423 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 424 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 425 | } |
| andreikovacs | 0:764779eedf2d | 426 | |
| andreikovacs | 0:764779eedf2d | 427 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 428 | * Name: MCR20Drv_IndirectAccessSPIRead |
| andreikovacs | 0:764779eedf2d | 429 | * Description: - |
| andreikovacs | 0:764779eedf2d | 430 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 431 | * Return: - |
| andreikovacs | 0:764779eedf2d | 432 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 433 | uint8_t MCR20Drv_IndirectAccessSPIRead |
| andreikovacs | 0:764779eedf2d | 434 | ( |
| andreikovacs | 0:764779eedf2d | 435 | uint8_t address |
| andreikovacs | 0:764779eedf2d | 436 | ) |
| andreikovacs | 0:764779eedf2d | 437 | { |
| andreikovacs | 0:764779eedf2d | 438 | uint16_t txData; |
| andreikovacs | 0:764779eedf2d | 439 | uint8_t rxData; |
| andreikovacs | 0:764779eedf2d | 440 | |
| andreikovacs | 0:764779eedf2d | 441 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 442 | |
| andreikovacs | 0:764779eedf2d | 443 | spi_master_configure_speed(gXcvrSpiInstance_c, 8000000); |
| andreikovacs | 0:764779eedf2d | 444 | |
| andreikovacs | 0:764779eedf2d | 445 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 446 | |
| andreikovacs | 0:764779eedf2d | 447 | txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect; |
| andreikovacs | 0:764779eedf2d | 448 | txData |= (address) << 8; |
| andreikovacs | 0:764779eedf2d | 449 | |
| andreikovacs | 0:764779eedf2d | 450 | spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData)); |
| andreikovacs | 0:764779eedf2d | 451 | spi_master_transfer(gXcvrSpiInstance_c, NULL, &rxData, sizeof(rxData)); |
| andreikovacs | 0:764779eedf2d | 452 | |
| andreikovacs | 0:764779eedf2d | 453 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 454 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 455 | |
| andreikovacs | 0:764779eedf2d | 456 | return rxData; |
| andreikovacs | 0:764779eedf2d | 457 | } |
| andreikovacs | 0:764779eedf2d | 458 | |
| andreikovacs | 0:764779eedf2d | 459 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 460 | * Name: MCR20Drv_IndirectAccessSPIMultiByteRead |
| andreikovacs | 0:764779eedf2d | 461 | * Description: - |
| andreikovacs | 0:764779eedf2d | 462 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 463 | * Return: - |
| andreikovacs | 0:764779eedf2d | 464 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 465 | void MCR20Drv_IndirectAccessSPIMultiByteRead |
| andreikovacs | 0:764779eedf2d | 466 | ( |
| andreikovacs | 0:764779eedf2d | 467 | uint8_t startAddress, |
| andreikovacs | 0:764779eedf2d | 468 | uint8_t * byteArray, |
| andreikovacs | 0:764779eedf2d | 469 | uint8_t numOfBytes |
| andreikovacs | 0:764779eedf2d | 470 | ) |
| andreikovacs | 0:764779eedf2d | 471 | { |
| andreikovacs | 0:764779eedf2d | 472 | uint16_t txData; |
| andreikovacs | 0:764779eedf2d | 473 | |
| andreikovacs | 0:764779eedf2d | 474 | if( (numOfBytes == 0) || (byteArray == NULL) ) |
| andreikovacs | 0:764779eedf2d | 475 | { |
| andreikovacs | 0:764779eedf2d | 476 | return; |
| andreikovacs | 0:764779eedf2d | 477 | } |
| andreikovacs | 0:764779eedf2d | 478 | |
| andreikovacs | 0:764779eedf2d | 479 | ProtectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 480 | |
| andreikovacs | 0:764779eedf2d | 481 | spi_master_configure_speed(gXcvrSpiInstance_c, 8000000); |
| andreikovacs | 0:764779eedf2d | 482 | |
| andreikovacs | 0:764779eedf2d | 483 | gXcvrAssertCS_d(); |
| andreikovacs | 0:764779eedf2d | 484 | |
| andreikovacs | 0:764779eedf2d | 485 | txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect); |
| andreikovacs | 0:764779eedf2d | 486 | txData |= (startAddress) << 8; |
| andreikovacs | 0:764779eedf2d | 487 | |
| andreikovacs | 0:764779eedf2d | 488 | spi_master_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, NULL, sizeof(txData)); |
| andreikovacs | 0:764779eedf2d | 489 | spi_master_transfer(gXcvrSpiInstance_c, NULL, byteArray, numOfBytes); |
| andreikovacs | 0:764779eedf2d | 490 | |
| andreikovacs | 0:764779eedf2d | 491 | gXcvrDeassertCS_d(); |
| andreikovacs | 0:764779eedf2d | 492 | UnprotectFromMCR20Interrupt(); |
| andreikovacs | 0:764779eedf2d | 493 | } |
| andreikovacs | 0:764779eedf2d | 494 | |
| andreikovacs | 0:764779eedf2d | 495 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 496 | * Name: MCR20Drv_IRQ_PortConfig |
| andreikovacs | 0:764779eedf2d | 497 | * Description: - |
| andreikovacs | 0:764779eedf2d | 498 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 499 | * Return: - |
| andreikovacs | 0:764779eedf2d | 500 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 501 | void MCR20Drv_IRQ_PortConfig |
| andreikovacs | 0:764779eedf2d | 502 | ( |
| andreikovacs | 0:764779eedf2d | 503 | void |
| andreikovacs | 0:764779eedf2d | 504 | ) |
| andreikovacs | 0:764779eedf2d | 505 | { |
| andreikovacs | 0:764779eedf2d | 506 | #if 0 |
| andreikovacs | 0:764779eedf2d | 507 | PORT_HAL_SetMuxMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)], |
| andreikovacs | 0:764779eedf2d | 508 | GPIO_EXTRACT_PIN(kGpioXcvrIrqPin), |
| andreikovacs | 0:764779eedf2d | 509 | kPortMuxAsGpio); |
| andreikovacs | 0:764779eedf2d | 510 | GPIO_DRV_InputPinInit(&mXcvrIrqPinCfg); |
| andreikovacs | 0:764779eedf2d | 511 | #endif |
| andreikovacs | 0:764779eedf2d | 512 | } |
| andreikovacs | 0:764779eedf2d | 513 | |
| andreikovacs | 0:764779eedf2d | 514 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 515 | * Name: MCR20Drv_IsIrqPending |
| andreikovacs | 0:764779eedf2d | 516 | * Description: - |
| andreikovacs | 0:764779eedf2d | 517 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 518 | * Return: - |
| andreikovacs | 0:764779eedf2d | 519 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 520 | uint32_t MCR20Drv_IsIrqPending |
| andreikovacs | 0:764779eedf2d | 521 | ( |
| andreikovacs | 0:764779eedf2d | 522 | void |
| andreikovacs | 0:764779eedf2d | 523 | ) |
| andreikovacs | 0:764779eedf2d | 524 | { |
| andreikovacs | 0:764779eedf2d | 525 | if( !RF_isIRQ_Pending() ) |
| andreikovacs | 0:764779eedf2d | 526 | { |
| andreikovacs | 0:764779eedf2d | 527 | return TRUE; |
| andreikovacs | 0:764779eedf2d | 528 | } |
| andreikovacs | 0:764779eedf2d | 529 | |
| andreikovacs | 0:764779eedf2d | 530 | return FALSE; |
| andreikovacs | 0:764779eedf2d | 531 | } |
| andreikovacs | 0:764779eedf2d | 532 | |
| andreikovacs | 0:764779eedf2d | 533 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 534 | * Name: MCR20Drv_IRQ_Disable |
| andreikovacs | 0:764779eedf2d | 535 | * Description: - |
| andreikovacs | 0:764779eedf2d | 536 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 537 | * Return: - |
| andreikovacs | 0:764779eedf2d | 538 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 539 | void MCR20Drv_IRQ_Disable |
| andreikovacs | 0:764779eedf2d | 540 | ( |
| andreikovacs | 0:764779eedf2d | 541 | void |
| andreikovacs | 0:764779eedf2d | 542 | ) |
| andreikovacs | 0:764779eedf2d | 543 | { |
| andreikovacs | 0:764779eedf2d | 544 | OSA_EnterCritical(kCriticalDisableInt); |
| andreikovacs | 0:764779eedf2d | 545 | |
| andreikovacs | 0:764779eedf2d | 546 | if( mPhyIrqDisableCnt == 0 ) |
| andreikovacs | 0:764779eedf2d | 547 | { |
| andreikovacs | 0:764779eedf2d | 548 | RF_IRQ_Disable(); |
| andreikovacs | 0:764779eedf2d | 549 | } |
| andreikovacs | 0:764779eedf2d | 550 | |
| andreikovacs | 0:764779eedf2d | 551 | mPhyIrqDisableCnt++; |
| andreikovacs | 0:764779eedf2d | 552 | |
| andreikovacs | 0:764779eedf2d | 553 | OSA_ExitCritical(kCriticalDisableInt); |
| andreikovacs | 0:764779eedf2d | 554 | } |
| andreikovacs | 0:764779eedf2d | 555 | |
| andreikovacs | 0:764779eedf2d | 556 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 557 | * Name: MCR20Drv_IRQ_Enable |
| andreikovacs | 0:764779eedf2d | 558 | * Description: - |
| andreikovacs | 0:764779eedf2d | 559 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 560 | * Return: - |
| andreikovacs | 0:764779eedf2d | 561 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 562 | void MCR20Drv_IRQ_Enable |
| andreikovacs | 0:764779eedf2d | 563 | ( |
| andreikovacs | 0:764779eedf2d | 564 | void |
| andreikovacs | 0:764779eedf2d | 565 | ) |
| andreikovacs | 0:764779eedf2d | 566 | { |
| andreikovacs | 0:764779eedf2d | 567 | OSA_EnterCritical(kCriticalDisableInt); |
| andreikovacs | 0:764779eedf2d | 568 | |
| andreikovacs | 0:764779eedf2d | 569 | if( mPhyIrqDisableCnt ) |
| andreikovacs | 0:764779eedf2d | 570 | { |
| andreikovacs | 0:764779eedf2d | 571 | mPhyIrqDisableCnt--; |
| andreikovacs | 0:764779eedf2d | 572 | |
| andreikovacs | 0:764779eedf2d | 573 | if( mPhyIrqDisableCnt == 0 ) |
| andreikovacs | 0:764779eedf2d | 574 | { |
| andreikovacs | 0:764779eedf2d | 575 | RF_IRQ_Enable(); |
| andreikovacs | 0:764779eedf2d | 576 | } |
| andreikovacs | 0:764779eedf2d | 577 | } |
| andreikovacs | 0:764779eedf2d | 578 | |
| andreikovacs | 0:764779eedf2d | 579 | OSA_ExitCritical(kCriticalDisableInt); |
| andreikovacs | 0:764779eedf2d | 580 | } |
| andreikovacs | 0:764779eedf2d | 581 | |
| andreikovacs | 0:764779eedf2d | 582 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 583 | * Name: MCR20Drv_IRQ_IsEnabled |
| andreikovacs | 0:764779eedf2d | 584 | * Description: - |
| andreikovacs | 0:764779eedf2d | 585 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 586 | * Return: - |
| andreikovacs | 0:764779eedf2d | 587 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 588 | uint32_t MCR20Drv_IRQ_IsEnabled |
| andreikovacs | 0:764779eedf2d | 589 | ( |
| andreikovacs | 0:764779eedf2d | 590 | void |
| andreikovacs | 0:764779eedf2d | 591 | ) |
| andreikovacs | 0:764779eedf2d | 592 | { |
| andreikovacs | 0:764779eedf2d | 593 | |
| andreikovacs | 0:764779eedf2d | 594 | #if 0 |
| andreikovacs | 0:764779eedf2d | 595 | port_interrupt_config_t mode; |
| andreikovacs | 0:764779eedf2d | 596 | |
| andreikovacs | 0:764779eedf2d | 597 | mode = PORT_HAL_GetPinIntMode(g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioXcvrIrqPin)], |
| andreikovacs | 0:764779eedf2d | 598 | GPIO_EXTRACT_PIN(kGpioXcvrIrqPin)); |
| andreikovacs | 0:764779eedf2d | 599 | return (mode != kPortIntDisabled); |
| andreikovacs | 0:764779eedf2d | 600 | #endif |
| andreikovacs | 0:764779eedf2d | 601 | return 1; |
| andreikovacs | 0:764779eedf2d | 602 | } |
| andreikovacs | 0:764779eedf2d | 603 | |
| andreikovacs | 0:764779eedf2d | 604 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 605 | * Name: MCR20Drv_IRQ_Clear |
| andreikovacs | 0:764779eedf2d | 606 | * Description: - |
| andreikovacs | 0:764779eedf2d | 607 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 608 | * Return: - |
| andreikovacs | 0:764779eedf2d | 609 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 610 | void MCR20Drv_IRQ_Clear |
| andreikovacs | 0:764779eedf2d | 611 | ( |
| andreikovacs | 0:764779eedf2d | 612 | void |
| andreikovacs | 0:764779eedf2d | 613 | ) |
| andreikovacs | 0:764779eedf2d | 614 | { |
| andreikovacs | 0:764779eedf2d | 615 | //GPIO_DRV_ClearPinIntFlag(kGpioXcvrIrqPin); |
| andreikovacs | 0:764779eedf2d | 616 | } |
| andreikovacs | 0:764779eedf2d | 617 | |
| andreikovacs | 0:764779eedf2d | 618 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 619 | * Name: MCR20Drv_RST_Assert |
| andreikovacs | 0:764779eedf2d | 620 | * Description: - |
| andreikovacs | 0:764779eedf2d | 621 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 622 | * Return: - |
| andreikovacs | 0:764779eedf2d | 623 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 624 | void MCR20Drv_RST_B_Assert |
| andreikovacs | 0:764779eedf2d | 625 | ( |
| andreikovacs | 0:764779eedf2d | 626 | void |
| andreikovacs | 0:764779eedf2d | 627 | ) |
| andreikovacs | 0:764779eedf2d | 628 | { |
| andreikovacs | 0:764779eedf2d | 629 | RF_RST_Set(0); |
| andreikovacs | 0:764779eedf2d | 630 | //GPIO_DRV_ClearPinOutput(kGpioXcvrResetPin); |
| andreikovacs | 0:764779eedf2d | 631 | } |
| andreikovacs | 0:764779eedf2d | 632 | |
| andreikovacs | 0:764779eedf2d | 633 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 634 | * Name: MCR20Drv_RST_Deassert |
| andreikovacs | 0:764779eedf2d | 635 | * Description: - |
| andreikovacs | 0:764779eedf2d | 636 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 637 | * Return: - |
| andreikovacs | 0:764779eedf2d | 638 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 639 | void MCR20Drv_RST_B_Deassert |
| andreikovacs | 0:764779eedf2d | 640 | ( |
| andreikovacs | 0:764779eedf2d | 641 | void |
| andreikovacs | 0:764779eedf2d | 642 | ) |
| andreikovacs | 0:764779eedf2d | 643 | { |
| andreikovacs | 0:764779eedf2d | 644 | RF_RST_Set(1); |
| andreikovacs | 0:764779eedf2d | 645 | //GPIO_DRV_SetPinOutput(kGpioXcvrResetPin); |
| andreikovacs | 0:764779eedf2d | 646 | } |
| andreikovacs | 0:764779eedf2d | 647 | |
| andreikovacs | 0:764779eedf2d | 648 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 649 | * Name: MCR20Drv_SoftRST_Assert |
| andreikovacs | 0:764779eedf2d | 650 | * Description: - |
| andreikovacs | 0:764779eedf2d | 651 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 652 | * Return: - |
| andreikovacs | 0:764779eedf2d | 653 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 654 | void MCR20Drv_SoftRST_Assert |
| andreikovacs | 0:764779eedf2d | 655 | ( |
| andreikovacs | 0:764779eedf2d | 656 | void |
| andreikovacs | 0:764779eedf2d | 657 | ) |
| andreikovacs | 0:764779eedf2d | 658 | { |
| andreikovacs | 0:764779eedf2d | 659 | MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80)); |
| andreikovacs | 0:764779eedf2d | 660 | } |
| andreikovacs | 0:764779eedf2d | 661 | |
| andreikovacs | 0:764779eedf2d | 662 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 663 | * Name: MCR20Drv_SoftRST_Deassert |
| andreikovacs | 0:764779eedf2d | 664 | * Description: - |
| andreikovacs | 0:764779eedf2d | 665 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 666 | * Return: - |
| andreikovacs | 0:764779eedf2d | 667 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 668 | void MCR20Drv_SoftRST_Deassert |
| andreikovacs | 0:764779eedf2d | 669 | ( |
| andreikovacs | 0:764779eedf2d | 670 | void |
| andreikovacs | 0:764779eedf2d | 671 | ) |
| andreikovacs | 0:764779eedf2d | 672 | { |
| andreikovacs | 0:764779eedf2d | 673 | MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00)); |
| andreikovacs | 0:764779eedf2d | 674 | } |
| andreikovacs | 0:764779eedf2d | 675 | |
| andreikovacs | 0:764779eedf2d | 676 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 677 | * Name: MCR20Drv_Soft_RESET |
| andreikovacs | 0:764779eedf2d | 678 | * Description: - |
| andreikovacs | 0:764779eedf2d | 679 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 680 | * Return: - |
| andreikovacs | 0:764779eedf2d | 681 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 682 | void MCR20Drv_Soft_RESET |
| andreikovacs | 0:764779eedf2d | 683 | ( |
| andreikovacs | 0:764779eedf2d | 684 | void |
| andreikovacs | 0:764779eedf2d | 685 | ) |
| andreikovacs | 0:764779eedf2d | 686 | { |
| andreikovacs | 0:764779eedf2d | 687 | //assert SOG_RST |
| andreikovacs | 0:764779eedf2d | 688 | MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80)); |
| andreikovacs | 0:764779eedf2d | 689 | |
| andreikovacs | 0:764779eedf2d | 690 | //deassert SOG_RST |
| andreikovacs | 0:764779eedf2d | 691 | MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00)); |
| andreikovacs | 0:764779eedf2d | 692 | } |
| andreikovacs | 0:764779eedf2d | 693 | |
| andreikovacs | 0:764779eedf2d | 694 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 695 | * Name: MCR20Drv_RESET |
| andreikovacs | 0:764779eedf2d | 696 | * Description: - |
| andreikovacs | 0:764779eedf2d | 697 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 698 | * Return: - |
| andreikovacs | 0:764779eedf2d | 699 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 700 | void MCR20Drv_RESET |
| andreikovacs | 0:764779eedf2d | 701 | ( |
| andreikovacs | 0:764779eedf2d | 702 | void |
| andreikovacs | 0:764779eedf2d | 703 | ) |
| andreikovacs | 0:764779eedf2d | 704 | { |
| andreikovacs | 0:764779eedf2d | 705 | volatile uint32_t delay = 1000; |
| andreikovacs | 0:764779eedf2d | 706 | //assert RST_B |
| andreikovacs | 0:764779eedf2d | 707 | MCR20Drv_RST_B_Assert(); |
| andreikovacs | 0:764779eedf2d | 708 | |
| andreikovacs | 0:764779eedf2d | 709 | // TODO |
| andreikovacs | 0:764779eedf2d | 710 | while(delay--); |
| andreikovacs | 0:764779eedf2d | 711 | |
| andreikovacs | 0:764779eedf2d | 712 | //deassert RST_B |
| andreikovacs | 0:764779eedf2d | 713 | MCR20Drv_RST_B_Deassert(); |
| andreikovacs | 0:764779eedf2d | 714 | } |
| andreikovacs | 0:764779eedf2d | 715 | |
| andreikovacs | 0:764779eedf2d | 716 | /*--------------------------------------------------------------------------- |
| andreikovacs | 0:764779eedf2d | 717 | * Name: MCR20Drv_Set_CLK_OUT_Freq |
| andreikovacs | 0:764779eedf2d | 718 | * Description: - |
| andreikovacs | 0:764779eedf2d | 719 | * Parameters: - |
| andreikovacs | 0:764779eedf2d | 720 | * Return: - |
| andreikovacs | 0:764779eedf2d | 721 | *---------------------------------------------------------------------------*/ |
| andreikovacs | 0:764779eedf2d | 722 | void MCR20Drv_Set_CLK_OUT_Freq |
| andreikovacs | 0:764779eedf2d | 723 | ( |
| andreikovacs | 0:764779eedf2d | 724 | uint8_t freqDiv |
| andreikovacs | 0:764779eedf2d | 725 | ) |
| andreikovacs | 0:764779eedf2d | 726 | { |
| andreikovacs | 0:764779eedf2d | 727 | uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND; |
| andreikovacs | 0:764779eedf2d | 728 | |
| andreikovacs | 0:764779eedf2d | 729 | if(freqDiv == gCLK_OUT_FREQ_DISABLE) |
| andreikovacs | 0:764779eedf2d | 730 | { |
| andreikovacs | 0:764779eedf2d | 731 | clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled |
| andreikovacs | 0:764779eedf2d | 732 | } |
| andreikovacs | 0:764779eedf2d | 733 | |
| andreikovacs | 0:764779eedf2d | 734 | MCR20Drv_DirectAccessSPIWrite((uint8_t) CLK_OUT_CTRL, clkOutCtrlReg); |
| andreikovacs | 0:764779eedf2d | 735 | } |