Morpheus / target-mcu-k64f

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cmsis/MK64F12.h@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Processors: MK64FN1M0VDC12
screamer 0:c5e2f793b59a 4 ** MK64FN1M0VLL12
screamer 0:c5e2f793b59a 5 ** MK64FN1M0VLQ12
screamer 0:c5e2f793b59a 6 ** MK64FN1M0VMD12
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 9 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 10 ** GNU C Compiler
screamer 0:c5e2f793b59a 11 ** GNU C Compiler - CodeSourcery Sourcery G++
screamer 0:c5e2f793b59a 12 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 13 **
screamer 0:c5e2f793b59a 14 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 15 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 16 ** Build: b140604
screamer 0:c5e2f793b59a 17 **
screamer 0:c5e2f793b59a 18 ** Abstract:
screamer 0:c5e2f793b59a 19 ** CMSIS Peripheral Access Layer for MK64F12
screamer 0:c5e2f793b59a 20 **
screamer 0:c5e2f793b59a 21 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 22 ** All rights reserved.
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 25 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 26 **
screamer 0:c5e2f793b59a 27 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 28 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 29 **
screamer 0:c5e2f793b59a 30 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 31 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 32 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 33 **
screamer 0:c5e2f793b59a 34 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 35 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 36 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 37 **
screamer 0:c5e2f793b59a 38 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 39 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 40 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 41 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 42 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 43 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 44 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 45 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 46 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 47 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 48 **
screamer 0:c5e2f793b59a 49 ** http: www.freescale.com
screamer 0:c5e2f793b59a 50 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 51 **
screamer 0:c5e2f793b59a 52 ** Revisions:
screamer 0:c5e2f793b59a 53 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 54 ** Initial version.
screamer 0:c5e2f793b59a 55 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 56 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 57 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 58 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 59 ** System initialization updated.
screamer 0:c5e2f793b59a 60 ** MCG - registers updated.
screamer 0:c5e2f793b59a 61 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 62 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 63 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 64 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 65 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 66 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 67 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 68 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 69 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 70 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 71 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 72 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 73 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 74 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 75 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 76 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 77 **
screamer 0:c5e2f793b59a 78 ** ###################################################################
screamer 0:c5e2f793b59a 79 */
screamer 0:c5e2f793b59a 80
screamer 0:c5e2f793b59a 81 /*!
screamer 0:c5e2f793b59a 82 * @file MK64F12.h
screamer 0:c5e2f793b59a 83 * @version 2.5
screamer 0:c5e2f793b59a 84 * @date 2014-02-10
screamer 0:c5e2f793b59a 85 * @brief CMSIS Peripheral Access Layer for MK64F12
screamer 0:c5e2f793b59a 86 *
screamer 0:c5e2f793b59a 87 * CMSIS Peripheral Access Layer for MK64F12
screamer 0:c5e2f793b59a 88 */
screamer 0:c5e2f793b59a 89
screamer 0:c5e2f793b59a 90
screamer 0:c5e2f793b59a 91 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 92 -- MCU activation
screamer 0:c5e2f793b59a 93 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 94
screamer 0:c5e2f793b59a 95 /* Prevention from multiple including the same memory map */
screamer 0:c5e2f793b59a 96 #if !defined(MK64F12_H_) /* Check if memory map has not been already included */
screamer 0:c5e2f793b59a 97 #define MK64F12_H_
screamer 0:c5e2f793b59a 98 #define MCU_MK64F12
screamer 0:c5e2f793b59a 99
screamer 0:c5e2f793b59a 100 /* Check if another memory map has not been also included */
screamer 0:c5e2f793b59a 101 #if (defined(MCU_ACTIVE))
screamer 0:c5e2f793b59a 102 #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
screamer 0:c5e2f793b59a 103 #endif /* (defined(MCU_ACTIVE)) */
screamer 0:c5e2f793b59a 104 #define MCU_ACTIVE
screamer 0:c5e2f793b59a 105
screamer 0:c5e2f793b59a 106 #include <stdint.h>
screamer 0:c5e2f793b59a 107
screamer 0:c5e2f793b59a 108 /** Memory map major version (memory maps with equal major version number are
screamer 0:c5e2f793b59a 109 * compatible) */
screamer 0:c5e2f793b59a 110 #define MCU_MEM_MAP_VERSION 0x0200u
screamer 0:c5e2f793b59a 111 /** Memory map minor version */
screamer 0:c5e2f793b59a 112 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
screamer 0:c5e2f793b59a 113
screamer 0:c5e2f793b59a 114 /**
screamer 0:c5e2f793b59a 115 * @brief Macro to calculate address of an aliased word in the peripheral
screamer 0:c5e2f793b59a 116 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
screamer 0:c5e2f793b59a 117 * 0x400FFFFF).
screamer 0:c5e2f793b59a 118 * @param Reg Register to access.
screamer 0:c5e2f793b59a 119 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 120 * @return Address of the aliased word in the peripheral bitband area.
screamer 0:c5e2f793b59a 121 */
screamer 0:c5e2f793b59a 122 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
screamer 0:c5e2f793b59a 123 /**
screamer 0:c5e2f793b59a 124 * @brief Macro to access a single bit of a peripheral register (bit band region
screamer 0:c5e2f793b59a 125 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
screamer 0:c5e2f793b59a 126 * be used for peripherals with 32bit access allowed.
screamer 0:c5e2f793b59a 127 * @param Reg Register to access.
screamer 0:c5e2f793b59a 128 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 129 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 130 */
screamer 0:c5e2f793b59a 131 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
screamer 0:c5e2f793b59a 132 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
screamer 0:c5e2f793b59a 133 /**
screamer 0:c5e2f793b59a 134 * @brief Macro to access a single bit of a peripheral register (bit band region
screamer 0:c5e2f793b59a 135 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
screamer 0:c5e2f793b59a 136 * be used for peripherals with 16bit access allowed.
screamer 0:c5e2f793b59a 137 * @param Reg Register to access.
screamer 0:c5e2f793b59a 138 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 139 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 140 */
screamer 0:c5e2f793b59a 141 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
screamer 0:c5e2f793b59a 142 /**
screamer 0:c5e2f793b59a 143 * @brief Macro to access a single bit of a peripheral register (bit band region
screamer 0:c5e2f793b59a 144 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
screamer 0:c5e2f793b59a 145 * be used for peripherals with 8bit access allowed.
screamer 0:c5e2f793b59a 146 * @param Reg Register to access.
screamer 0:c5e2f793b59a 147 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 148 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 149 */
screamer 0:c5e2f793b59a 150 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
screamer 0:c5e2f793b59a 151
screamer 0:c5e2f793b59a 152 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 153 -- Interrupt vector numbers
screamer 0:c5e2f793b59a 154 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 155
screamer 0:c5e2f793b59a 156 /*!
screamer 0:c5e2f793b59a 157 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
screamer 0:c5e2f793b59a 158 * @{
screamer 0:c5e2f793b59a 159 */
screamer 0:c5e2f793b59a 160
screamer 0:c5e2f793b59a 161 /** Interrupt Number Definitions */
screamer 0:c5e2f793b59a 162 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
screamer 0:c5e2f793b59a 163
screamer 0:c5e2f793b59a 164 typedef enum IRQn {
screamer 0:c5e2f793b59a 165 /* Core interrupts */
screamer 0:c5e2f793b59a 166 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
screamer 0:c5e2f793b59a 167 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
screamer 0:c5e2f793b59a 168 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
screamer 0:c5e2f793b59a 169 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
screamer 0:c5e2f793b59a 170 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
screamer 0:c5e2f793b59a 171 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
screamer 0:c5e2f793b59a 172 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
screamer 0:c5e2f793b59a 173 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
screamer 0:c5e2f793b59a 174 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
screamer 0:c5e2f793b59a 175
screamer 0:c5e2f793b59a 176 /* Device specific interrupts */
screamer 0:c5e2f793b59a 177 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
screamer 0:c5e2f793b59a 178 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
screamer 0:c5e2f793b59a 179 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
screamer 0:c5e2f793b59a 180 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
screamer 0:c5e2f793b59a 181 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
screamer 0:c5e2f793b59a 182 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
screamer 0:c5e2f793b59a 183 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
screamer 0:c5e2f793b59a 184 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
screamer 0:c5e2f793b59a 185 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
screamer 0:c5e2f793b59a 186 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
screamer 0:c5e2f793b59a 187 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
screamer 0:c5e2f793b59a 188 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
screamer 0:c5e2f793b59a 189 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
screamer 0:c5e2f793b59a 190 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
screamer 0:c5e2f793b59a 191 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
screamer 0:c5e2f793b59a 192 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
screamer 0:c5e2f793b59a 193 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
screamer 0:c5e2f793b59a 194 MCM_IRQn = 17, /**< Normal Interrupt */
screamer 0:c5e2f793b59a 195 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
screamer 0:c5e2f793b59a 196 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
screamer 0:c5e2f793b59a 197 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
screamer 0:c5e2f793b59a 198 LLW_IRQn = 21, /**< Low Leakage Wakeup */
screamer 0:c5e2f793b59a 199 Watchdog_IRQn = 22, /**< WDOG Interrupt */
screamer 0:c5e2f793b59a 200 RNG_IRQn = 23, /**< RNG Interrupt */
screamer 0:c5e2f793b59a 201 I2C0_IRQn = 24, /**< I2C0 interrupt */
screamer 0:c5e2f793b59a 202 I2C1_IRQn = 25, /**< I2C1 interrupt */
screamer 0:c5e2f793b59a 203 SPI0_IRQn = 26, /**< SPI0 Interrupt */
screamer 0:c5e2f793b59a 204 SPI1_IRQn = 27, /**< SPI1 Interrupt */
screamer 0:c5e2f793b59a 205 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
screamer 0:c5e2f793b59a 206 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
screamer 0:c5e2f793b59a 207 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
screamer 0:c5e2f793b59a 208 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 209 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
screamer 0:c5e2f793b59a 210 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 211 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
screamer 0:c5e2f793b59a 212 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 213 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
screamer 0:c5e2f793b59a 214 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 215 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
screamer 0:c5e2f793b59a 216 ADC0_IRQn = 39, /**< ADC0 interrupt */
screamer 0:c5e2f793b59a 217 CMP0_IRQn = 40, /**< CMP0 interrupt */
screamer 0:c5e2f793b59a 218 CMP1_IRQn = 41, /**< CMP1 interrupt */
screamer 0:c5e2f793b59a 219 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
screamer 0:c5e2f793b59a 220 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
screamer 0:c5e2f793b59a 221 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
screamer 0:c5e2f793b59a 222 CMT_IRQn = 45, /**< CMT interrupt */
screamer 0:c5e2f793b59a 223 RTC_IRQn = 46, /**< RTC interrupt */
screamer 0:c5e2f793b59a 224 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
screamer 0:c5e2f793b59a 225 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
screamer 0:c5e2f793b59a 226 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
screamer 0:c5e2f793b59a 227 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
screamer 0:c5e2f793b59a 228 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
screamer 0:c5e2f793b59a 229 PDB0_IRQn = 52, /**< PDB0 Interrupt */
screamer 0:c5e2f793b59a 230 USB0_IRQn = 53, /**< USB0 interrupt */
screamer 0:c5e2f793b59a 231 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
screamer 0:c5e2f793b59a 232 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
screamer 0:c5e2f793b59a 233 DAC0_IRQn = 56, /**< DAC0 interrupt */
screamer 0:c5e2f793b59a 234 MCG_IRQn = 57, /**< MCG Interrupt */
screamer 0:c5e2f793b59a 235 LPTimer_IRQn = 58, /**< LPTimer interrupt */
screamer 0:c5e2f793b59a 236 PORTA_IRQn = 59, /**< Port A interrupt */
screamer 0:c5e2f793b59a 237 PORTB_IRQn = 60, /**< Port B interrupt */
screamer 0:c5e2f793b59a 238 PORTC_IRQn = 61, /**< Port C interrupt */
screamer 0:c5e2f793b59a 239 PORTD_IRQn = 62, /**< Port D interrupt */
screamer 0:c5e2f793b59a 240 PORTE_IRQn = 63, /**< Port E interrupt */
screamer 0:c5e2f793b59a 241 SWI_IRQn = 64, /**< Software interrupt */
screamer 0:c5e2f793b59a 242 SPI2_IRQn = 65, /**< SPI2 Interrupt */
screamer 0:c5e2f793b59a 243 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 244 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
screamer 0:c5e2f793b59a 245 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 246 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
screamer 0:c5e2f793b59a 247 CMP2_IRQn = 70, /**< CMP2 interrupt */
screamer 0:c5e2f793b59a 248 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
screamer 0:c5e2f793b59a 249 DAC1_IRQn = 72, /**< DAC1 interrupt */
screamer 0:c5e2f793b59a 250 ADC1_IRQn = 73, /**< ADC1 interrupt */
screamer 0:c5e2f793b59a 251 I2C2_IRQn = 74, /**< I2C2 interrupt */
screamer 0:c5e2f793b59a 252 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
screamer 0:c5e2f793b59a 253 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
screamer 0:c5e2f793b59a 254 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
screamer 0:c5e2f793b59a 255 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
screamer 0:c5e2f793b59a 256 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
screamer 0:c5e2f793b59a 257 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
screamer 0:c5e2f793b59a 258 SDHC_IRQn = 81, /**< SDHC interrupt */
screamer 0:c5e2f793b59a 259 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
screamer 0:c5e2f793b59a 260 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
screamer 0:c5e2f793b59a 261 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
screamer 0:c5e2f793b59a 262 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
screamer 0:c5e2f793b59a 263 } IRQn_Type;
screamer 0:c5e2f793b59a 264
screamer 0:c5e2f793b59a 265 /*!
screamer 0:c5e2f793b59a 266 * @}
screamer 0:c5e2f793b59a 267 */ /* end of group Interrupt_vector_numbers */
screamer 0:c5e2f793b59a 268
screamer 0:c5e2f793b59a 269
screamer 0:c5e2f793b59a 270 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 271 -- Cortex M4 Core Configuration
screamer 0:c5e2f793b59a 272 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 273
screamer 0:c5e2f793b59a 274 /*!
screamer 0:c5e2f793b59a 275 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
screamer 0:c5e2f793b59a 276 * @{
screamer 0:c5e2f793b59a 277 */
screamer 0:c5e2f793b59a 278
screamer 0:c5e2f793b59a 279 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
screamer 0:c5e2f793b59a 280 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
screamer 0:c5e2f793b59a 281 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
screamer 0:c5e2f793b59a 282 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
screamer 0:c5e2f793b59a 283
screamer 0:c5e2f793b59a 284 #include "core_cm4.h" /* Core Peripheral Access Layer */
screamer 0:c5e2f793b59a 285 #include "system_MK64F12.h" /* Device specific configuration file */
screamer 0:c5e2f793b59a 286
screamer 0:c5e2f793b59a 287 /*!
screamer 0:c5e2f793b59a 288 * @}
screamer 0:c5e2f793b59a 289 */ /* end of group Cortex_Core_Configuration */
screamer 0:c5e2f793b59a 290
screamer 0:c5e2f793b59a 291
screamer 0:c5e2f793b59a 292 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 293 -- Device Peripheral Access Layer
screamer 0:c5e2f793b59a 294 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 295
screamer 0:c5e2f793b59a 296 /*!
screamer 0:c5e2f793b59a 297 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
screamer 0:c5e2f793b59a 298 * @{
screamer 0:c5e2f793b59a 299 */
screamer 0:c5e2f793b59a 300
screamer 0:c5e2f793b59a 301
screamer 0:c5e2f793b59a 302 /*
screamer 0:c5e2f793b59a 303 ** Start of section using anonymous unions
screamer 0:c5e2f793b59a 304 */
screamer 0:c5e2f793b59a 305
screamer 0:c5e2f793b59a 306 #if defined(__ARMCC_VERSION)
screamer 0:c5e2f793b59a 307 #pragma push
screamer 0:c5e2f793b59a 308 #pragma anon_unions
screamer 0:c5e2f793b59a 309 #elif defined(__CWCC__)
screamer 0:c5e2f793b59a 310 #pragma push
screamer 0:c5e2f793b59a 311 #pragma cpp_extensions on
screamer 0:c5e2f793b59a 312 #elif defined(__GNUC__)
screamer 0:c5e2f793b59a 313 /* anonymous unions are enabled by default */
screamer 0:c5e2f793b59a 314 #elif defined(__IAR_SYSTEMS_ICC__)
screamer 0:c5e2f793b59a 315 #pragma language=extended
screamer 0:c5e2f793b59a 316 #else
screamer 0:c5e2f793b59a 317 #error Not supported compiler type
screamer 0:c5e2f793b59a 318 #endif
screamer 0:c5e2f793b59a 319
screamer 0:c5e2f793b59a 320 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 321 -- ADC Peripheral Access Layer
screamer 0:c5e2f793b59a 322 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 323
screamer 0:c5e2f793b59a 324 /*!
screamer 0:c5e2f793b59a 325 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
screamer 0:c5e2f793b59a 326 * @{
screamer 0:c5e2f793b59a 327 */
screamer 0:c5e2f793b59a 328
screamer 0:c5e2f793b59a 329 /** ADC - Register Layout Typedef */
screamer 0:c5e2f793b59a 330 typedef struct {
screamer 0:c5e2f793b59a 331 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
screamer 0:c5e2f793b59a 332 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
screamer 0:c5e2f793b59a 333 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
screamer 0:c5e2f793b59a 334 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
screamer 0:c5e2f793b59a 335 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
screamer 0:c5e2f793b59a 336 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
screamer 0:c5e2f793b59a 337 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
screamer 0:c5e2f793b59a 338 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
screamer 0:c5e2f793b59a 339 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
screamer 0:c5e2f793b59a 340 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
screamer 0:c5e2f793b59a 341 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
screamer 0:c5e2f793b59a 342 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
screamer 0:c5e2f793b59a 343 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
screamer 0:c5e2f793b59a 344 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
screamer 0:c5e2f793b59a 345 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
screamer 0:c5e2f793b59a 346 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
screamer 0:c5e2f793b59a 347 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
screamer 0:c5e2f793b59a 348 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
screamer 0:c5e2f793b59a 349 uint8_t RESERVED_0[4];
screamer 0:c5e2f793b59a 350 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
screamer 0:c5e2f793b59a 351 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
screamer 0:c5e2f793b59a 352 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
screamer 0:c5e2f793b59a 353 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
screamer 0:c5e2f793b59a 354 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
screamer 0:c5e2f793b59a 355 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
screamer 0:c5e2f793b59a 356 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
screamer 0:c5e2f793b59a 357 } ADC_Type, *ADC_MemMapPtr;
screamer 0:c5e2f793b59a 358
screamer 0:c5e2f793b59a 359 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 360 -- ADC - Register accessor macros
screamer 0:c5e2f793b59a 361 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 362
screamer 0:c5e2f793b59a 363 /*!
screamer 0:c5e2f793b59a 364 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
screamer 0:c5e2f793b59a 365 * @{
screamer 0:c5e2f793b59a 366 */
screamer 0:c5e2f793b59a 367
screamer 0:c5e2f793b59a 368
screamer 0:c5e2f793b59a 369 /* ADC - Register accessors */
screamer 0:c5e2f793b59a 370 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
screamer 0:c5e2f793b59a 371 #define ADC_CFG1_REG(base) ((base)->CFG1)
screamer 0:c5e2f793b59a 372 #define ADC_CFG2_REG(base) ((base)->CFG2)
screamer 0:c5e2f793b59a 373 #define ADC_R_REG(base,index) ((base)->R[index])
screamer 0:c5e2f793b59a 374 #define ADC_CV1_REG(base) ((base)->CV1)
screamer 0:c5e2f793b59a 375 #define ADC_CV2_REG(base) ((base)->CV2)
screamer 0:c5e2f793b59a 376 #define ADC_SC2_REG(base) ((base)->SC2)
screamer 0:c5e2f793b59a 377 #define ADC_SC3_REG(base) ((base)->SC3)
screamer 0:c5e2f793b59a 378 #define ADC_OFS_REG(base) ((base)->OFS)
screamer 0:c5e2f793b59a 379 #define ADC_PG_REG(base) ((base)->PG)
screamer 0:c5e2f793b59a 380 #define ADC_MG_REG(base) ((base)->MG)
screamer 0:c5e2f793b59a 381 #define ADC_CLPD_REG(base) ((base)->CLPD)
screamer 0:c5e2f793b59a 382 #define ADC_CLPS_REG(base) ((base)->CLPS)
screamer 0:c5e2f793b59a 383 #define ADC_CLP4_REG(base) ((base)->CLP4)
screamer 0:c5e2f793b59a 384 #define ADC_CLP3_REG(base) ((base)->CLP3)
screamer 0:c5e2f793b59a 385 #define ADC_CLP2_REG(base) ((base)->CLP2)
screamer 0:c5e2f793b59a 386 #define ADC_CLP1_REG(base) ((base)->CLP1)
screamer 0:c5e2f793b59a 387 #define ADC_CLP0_REG(base) ((base)->CLP0)
screamer 0:c5e2f793b59a 388 #define ADC_CLMD_REG(base) ((base)->CLMD)
screamer 0:c5e2f793b59a 389 #define ADC_CLMS_REG(base) ((base)->CLMS)
screamer 0:c5e2f793b59a 390 #define ADC_CLM4_REG(base) ((base)->CLM4)
screamer 0:c5e2f793b59a 391 #define ADC_CLM3_REG(base) ((base)->CLM3)
screamer 0:c5e2f793b59a 392 #define ADC_CLM2_REG(base) ((base)->CLM2)
screamer 0:c5e2f793b59a 393 #define ADC_CLM1_REG(base) ((base)->CLM1)
screamer 0:c5e2f793b59a 394 #define ADC_CLM0_REG(base) ((base)->CLM0)
screamer 0:c5e2f793b59a 395
screamer 0:c5e2f793b59a 396 /*!
screamer 0:c5e2f793b59a 397 * @}
screamer 0:c5e2f793b59a 398 */ /* end of group ADC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 399
screamer 0:c5e2f793b59a 400
screamer 0:c5e2f793b59a 401 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 402 -- ADC Register Masks
screamer 0:c5e2f793b59a 403 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 404
screamer 0:c5e2f793b59a 405 /*!
screamer 0:c5e2f793b59a 406 * @addtogroup ADC_Register_Masks ADC Register Masks
screamer 0:c5e2f793b59a 407 * @{
screamer 0:c5e2f793b59a 408 */
screamer 0:c5e2f793b59a 409
screamer 0:c5e2f793b59a 410 /* SC1 Bit Fields */
screamer 0:c5e2f793b59a 411 #define ADC_SC1_ADCH_MASK 0x1Fu
screamer 0:c5e2f793b59a 412 #define ADC_SC1_ADCH_SHIFT 0
screamer 0:c5e2f793b59a 413 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
screamer 0:c5e2f793b59a 414 #define ADC_SC1_DIFF_MASK 0x20u
screamer 0:c5e2f793b59a 415 #define ADC_SC1_DIFF_SHIFT 5
screamer 0:c5e2f793b59a 416 #define ADC_SC1_AIEN_MASK 0x40u
screamer 0:c5e2f793b59a 417 #define ADC_SC1_AIEN_SHIFT 6
screamer 0:c5e2f793b59a 418 #define ADC_SC1_COCO_MASK 0x80u
screamer 0:c5e2f793b59a 419 #define ADC_SC1_COCO_SHIFT 7
screamer 0:c5e2f793b59a 420 /* CFG1 Bit Fields */
screamer 0:c5e2f793b59a 421 #define ADC_CFG1_ADICLK_MASK 0x3u
screamer 0:c5e2f793b59a 422 #define ADC_CFG1_ADICLK_SHIFT 0
screamer 0:c5e2f793b59a 423 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
screamer 0:c5e2f793b59a 424 #define ADC_CFG1_MODE_MASK 0xCu
screamer 0:c5e2f793b59a 425 #define ADC_CFG1_MODE_SHIFT 2
screamer 0:c5e2f793b59a 426 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
screamer 0:c5e2f793b59a 427 #define ADC_CFG1_ADLSMP_MASK 0x10u
screamer 0:c5e2f793b59a 428 #define ADC_CFG1_ADLSMP_SHIFT 4
screamer 0:c5e2f793b59a 429 #define ADC_CFG1_ADIV_MASK 0x60u
screamer 0:c5e2f793b59a 430 #define ADC_CFG1_ADIV_SHIFT 5
screamer 0:c5e2f793b59a 431 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
screamer 0:c5e2f793b59a 432 #define ADC_CFG1_ADLPC_MASK 0x80u
screamer 0:c5e2f793b59a 433 #define ADC_CFG1_ADLPC_SHIFT 7
screamer 0:c5e2f793b59a 434 /* CFG2 Bit Fields */
screamer 0:c5e2f793b59a 435 #define ADC_CFG2_ADLSTS_MASK 0x3u
screamer 0:c5e2f793b59a 436 #define ADC_CFG2_ADLSTS_SHIFT 0
screamer 0:c5e2f793b59a 437 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
screamer 0:c5e2f793b59a 438 #define ADC_CFG2_ADHSC_MASK 0x4u
screamer 0:c5e2f793b59a 439 #define ADC_CFG2_ADHSC_SHIFT 2
screamer 0:c5e2f793b59a 440 #define ADC_CFG2_ADACKEN_MASK 0x8u
screamer 0:c5e2f793b59a 441 #define ADC_CFG2_ADACKEN_SHIFT 3
screamer 0:c5e2f793b59a 442 #define ADC_CFG2_MUXSEL_MASK 0x10u
screamer 0:c5e2f793b59a 443 #define ADC_CFG2_MUXSEL_SHIFT 4
screamer 0:c5e2f793b59a 444 /* R Bit Fields */
screamer 0:c5e2f793b59a 445 #define ADC_R_D_MASK 0xFFFFu
screamer 0:c5e2f793b59a 446 #define ADC_R_D_SHIFT 0
screamer 0:c5e2f793b59a 447 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
screamer 0:c5e2f793b59a 448 /* CV1 Bit Fields */
screamer 0:c5e2f793b59a 449 #define ADC_CV1_CV_MASK 0xFFFFu
screamer 0:c5e2f793b59a 450 #define ADC_CV1_CV_SHIFT 0
screamer 0:c5e2f793b59a 451 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
screamer 0:c5e2f793b59a 452 /* CV2 Bit Fields */
screamer 0:c5e2f793b59a 453 #define ADC_CV2_CV_MASK 0xFFFFu
screamer 0:c5e2f793b59a 454 #define ADC_CV2_CV_SHIFT 0
screamer 0:c5e2f793b59a 455 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
screamer 0:c5e2f793b59a 456 /* SC2 Bit Fields */
screamer 0:c5e2f793b59a 457 #define ADC_SC2_REFSEL_MASK 0x3u
screamer 0:c5e2f793b59a 458 #define ADC_SC2_REFSEL_SHIFT 0
screamer 0:c5e2f793b59a 459 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
screamer 0:c5e2f793b59a 460 #define ADC_SC2_DMAEN_MASK 0x4u
screamer 0:c5e2f793b59a 461 #define ADC_SC2_DMAEN_SHIFT 2
screamer 0:c5e2f793b59a 462 #define ADC_SC2_ACREN_MASK 0x8u
screamer 0:c5e2f793b59a 463 #define ADC_SC2_ACREN_SHIFT 3
screamer 0:c5e2f793b59a 464 #define ADC_SC2_ACFGT_MASK 0x10u
screamer 0:c5e2f793b59a 465 #define ADC_SC2_ACFGT_SHIFT 4
screamer 0:c5e2f793b59a 466 #define ADC_SC2_ACFE_MASK 0x20u
screamer 0:c5e2f793b59a 467 #define ADC_SC2_ACFE_SHIFT 5
screamer 0:c5e2f793b59a 468 #define ADC_SC2_ADTRG_MASK 0x40u
screamer 0:c5e2f793b59a 469 #define ADC_SC2_ADTRG_SHIFT 6
screamer 0:c5e2f793b59a 470 #define ADC_SC2_ADACT_MASK 0x80u
screamer 0:c5e2f793b59a 471 #define ADC_SC2_ADACT_SHIFT 7
screamer 0:c5e2f793b59a 472 /* SC3 Bit Fields */
screamer 0:c5e2f793b59a 473 #define ADC_SC3_AVGS_MASK 0x3u
screamer 0:c5e2f793b59a 474 #define ADC_SC3_AVGS_SHIFT 0
screamer 0:c5e2f793b59a 475 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
screamer 0:c5e2f793b59a 476 #define ADC_SC3_AVGE_MASK 0x4u
screamer 0:c5e2f793b59a 477 #define ADC_SC3_AVGE_SHIFT 2
screamer 0:c5e2f793b59a 478 #define ADC_SC3_ADCO_MASK 0x8u
screamer 0:c5e2f793b59a 479 #define ADC_SC3_ADCO_SHIFT 3
screamer 0:c5e2f793b59a 480 #define ADC_SC3_CALF_MASK 0x40u
screamer 0:c5e2f793b59a 481 #define ADC_SC3_CALF_SHIFT 6
screamer 0:c5e2f793b59a 482 #define ADC_SC3_CAL_MASK 0x80u
screamer 0:c5e2f793b59a 483 #define ADC_SC3_CAL_SHIFT 7
screamer 0:c5e2f793b59a 484 /* OFS Bit Fields */
screamer 0:c5e2f793b59a 485 #define ADC_OFS_OFS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 486 #define ADC_OFS_OFS_SHIFT 0
screamer 0:c5e2f793b59a 487 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
screamer 0:c5e2f793b59a 488 /* PG Bit Fields */
screamer 0:c5e2f793b59a 489 #define ADC_PG_PG_MASK 0xFFFFu
screamer 0:c5e2f793b59a 490 #define ADC_PG_PG_SHIFT 0
screamer 0:c5e2f793b59a 491 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
screamer 0:c5e2f793b59a 492 /* MG Bit Fields */
screamer 0:c5e2f793b59a 493 #define ADC_MG_MG_MASK 0xFFFFu
screamer 0:c5e2f793b59a 494 #define ADC_MG_MG_SHIFT 0
screamer 0:c5e2f793b59a 495 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
screamer 0:c5e2f793b59a 496 /* CLPD Bit Fields */
screamer 0:c5e2f793b59a 497 #define ADC_CLPD_CLPD_MASK 0x3Fu
screamer 0:c5e2f793b59a 498 #define ADC_CLPD_CLPD_SHIFT 0
screamer 0:c5e2f793b59a 499 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
screamer 0:c5e2f793b59a 500 /* CLPS Bit Fields */
screamer 0:c5e2f793b59a 501 #define ADC_CLPS_CLPS_MASK 0x3Fu
screamer 0:c5e2f793b59a 502 #define ADC_CLPS_CLPS_SHIFT 0
screamer 0:c5e2f793b59a 503 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
screamer 0:c5e2f793b59a 504 /* CLP4 Bit Fields */
screamer 0:c5e2f793b59a 505 #define ADC_CLP4_CLP4_MASK 0x3FFu
screamer 0:c5e2f793b59a 506 #define ADC_CLP4_CLP4_SHIFT 0
screamer 0:c5e2f793b59a 507 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
screamer 0:c5e2f793b59a 508 /* CLP3 Bit Fields */
screamer 0:c5e2f793b59a 509 #define ADC_CLP3_CLP3_MASK 0x1FFu
screamer 0:c5e2f793b59a 510 #define ADC_CLP3_CLP3_SHIFT 0
screamer 0:c5e2f793b59a 511 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
screamer 0:c5e2f793b59a 512 /* CLP2 Bit Fields */
screamer 0:c5e2f793b59a 513 #define ADC_CLP2_CLP2_MASK 0xFFu
screamer 0:c5e2f793b59a 514 #define ADC_CLP2_CLP2_SHIFT 0
screamer 0:c5e2f793b59a 515 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
screamer 0:c5e2f793b59a 516 /* CLP1 Bit Fields */
screamer 0:c5e2f793b59a 517 #define ADC_CLP1_CLP1_MASK 0x7Fu
screamer 0:c5e2f793b59a 518 #define ADC_CLP1_CLP1_SHIFT 0
screamer 0:c5e2f793b59a 519 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
screamer 0:c5e2f793b59a 520 /* CLP0 Bit Fields */
screamer 0:c5e2f793b59a 521 #define ADC_CLP0_CLP0_MASK 0x3Fu
screamer 0:c5e2f793b59a 522 #define ADC_CLP0_CLP0_SHIFT 0
screamer 0:c5e2f793b59a 523 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
screamer 0:c5e2f793b59a 524 /* CLMD Bit Fields */
screamer 0:c5e2f793b59a 525 #define ADC_CLMD_CLMD_MASK 0x3Fu
screamer 0:c5e2f793b59a 526 #define ADC_CLMD_CLMD_SHIFT 0
screamer 0:c5e2f793b59a 527 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
screamer 0:c5e2f793b59a 528 /* CLMS Bit Fields */
screamer 0:c5e2f793b59a 529 #define ADC_CLMS_CLMS_MASK 0x3Fu
screamer 0:c5e2f793b59a 530 #define ADC_CLMS_CLMS_SHIFT 0
screamer 0:c5e2f793b59a 531 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
screamer 0:c5e2f793b59a 532 /* CLM4 Bit Fields */
screamer 0:c5e2f793b59a 533 #define ADC_CLM4_CLM4_MASK 0x3FFu
screamer 0:c5e2f793b59a 534 #define ADC_CLM4_CLM4_SHIFT 0
screamer 0:c5e2f793b59a 535 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
screamer 0:c5e2f793b59a 536 /* CLM3 Bit Fields */
screamer 0:c5e2f793b59a 537 #define ADC_CLM3_CLM3_MASK 0x1FFu
screamer 0:c5e2f793b59a 538 #define ADC_CLM3_CLM3_SHIFT 0
screamer 0:c5e2f793b59a 539 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
screamer 0:c5e2f793b59a 540 /* CLM2 Bit Fields */
screamer 0:c5e2f793b59a 541 #define ADC_CLM2_CLM2_MASK 0xFFu
screamer 0:c5e2f793b59a 542 #define ADC_CLM2_CLM2_SHIFT 0
screamer 0:c5e2f793b59a 543 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
screamer 0:c5e2f793b59a 544 /* CLM1 Bit Fields */
screamer 0:c5e2f793b59a 545 #define ADC_CLM1_CLM1_MASK 0x7Fu
screamer 0:c5e2f793b59a 546 #define ADC_CLM1_CLM1_SHIFT 0
screamer 0:c5e2f793b59a 547 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
screamer 0:c5e2f793b59a 548 /* CLM0 Bit Fields */
screamer 0:c5e2f793b59a 549 #define ADC_CLM0_CLM0_MASK 0x3Fu
screamer 0:c5e2f793b59a 550 #define ADC_CLM0_CLM0_SHIFT 0
screamer 0:c5e2f793b59a 551 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
screamer 0:c5e2f793b59a 552
screamer 0:c5e2f793b59a 553 /*!
screamer 0:c5e2f793b59a 554 * @}
screamer 0:c5e2f793b59a 555 */ /* end of group ADC_Register_Masks */
screamer 0:c5e2f793b59a 556
screamer 0:c5e2f793b59a 557
screamer 0:c5e2f793b59a 558 /* ADC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 559 /** Peripheral ADC0 base address */
screamer 0:c5e2f793b59a 560 #define ADC0_BASE (0x4003B000u)
screamer 0:c5e2f793b59a 561 /** Peripheral ADC0 base pointer */
screamer 0:c5e2f793b59a 562 #define ADC0 ((ADC_Type *)ADC0_BASE)
screamer 0:c5e2f793b59a 563 #define ADC0_BASE_PTR (ADC0)
screamer 0:c5e2f793b59a 564 /** Peripheral ADC1 base address */
screamer 0:c5e2f793b59a 565 #define ADC1_BASE (0x400BB000u)
screamer 0:c5e2f793b59a 566 /** Peripheral ADC1 base pointer */
screamer 0:c5e2f793b59a 567 #define ADC1 ((ADC_Type *)ADC1_BASE)
screamer 0:c5e2f793b59a 568 #define ADC1_BASE_PTR (ADC1)
screamer 0:c5e2f793b59a 569 /** Array initializer of ADC peripheral base addresses */
screamer 0:c5e2f793b59a 570 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
screamer 0:c5e2f793b59a 571 /** Array initializer of ADC peripheral base pointers */
screamer 0:c5e2f793b59a 572 #define ADC_BASE_PTRS { ADC0, ADC1 }
screamer 0:c5e2f793b59a 573 /** Interrupt vectors for the ADC peripheral type */
screamer 0:c5e2f793b59a 574 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
screamer 0:c5e2f793b59a 575
screamer 0:c5e2f793b59a 576 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 577 -- ADC - Register accessor macros
screamer 0:c5e2f793b59a 578 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 579
screamer 0:c5e2f793b59a 580 /*!
screamer 0:c5e2f793b59a 581 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
screamer 0:c5e2f793b59a 582 * @{
screamer 0:c5e2f793b59a 583 */
screamer 0:c5e2f793b59a 584
screamer 0:c5e2f793b59a 585
screamer 0:c5e2f793b59a 586 /* ADC - Register instance definitions */
screamer 0:c5e2f793b59a 587 /* ADC0 */
screamer 0:c5e2f793b59a 588 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
screamer 0:c5e2f793b59a 589 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
screamer 0:c5e2f793b59a 590 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
screamer 0:c5e2f793b59a 591 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
screamer 0:c5e2f793b59a 592 #define ADC0_RA ADC_R_REG(ADC0,0)
screamer 0:c5e2f793b59a 593 #define ADC0_RB ADC_R_REG(ADC0,1)
screamer 0:c5e2f793b59a 594 #define ADC0_CV1 ADC_CV1_REG(ADC0)
screamer 0:c5e2f793b59a 595 #define ADC0_CV2 ADC_CV2_REG(ADC0)
screamer 0:c5e2f793b59a 596 #define ADC0_SC2 ADC_SC2_REG(ADC0)
screamer 0:c5e2f793b59a 597 #define ADC0_SC3 ADC_SC3_REG(ADC0)
screamer 0:c5e2f793b59a 598 #define ADC0_OFS ADC_OFS_REG(ADC0)
screamer 0:c5e2f793b59a 599 #define ADC0_PG ADC_PG_REG(ADC0)
screamer 0:c5e2f793b59a 600 #define ADC0_MG ADC_MG_REG(ADC0)
screamer 0:c5e2f793b59a 601 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
screamer 0:c5e2f793b59a 602 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
screamer 0:c5e2f793b59a 603 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
screamer 0:c5e2f793b59a 604 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
screamer 0:c5e2f793b59a 605 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
screamer 0:c5e2f793b59a 606 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
screamer 0:c5e2f793b59a 607 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
screamer 0:c5e2f793b59a 608 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
screamer 0:c5e2f793b59a 609 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
screamer 0:c5e2f793b59a 610 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
screamer 0:c5e2f793b59a 611 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
screamer 0:c5e2f793b59a 612 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
screamer 0:c5e2f793b59a 613 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
screamer 0:c5e2f793b59a 614 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
screamer 0:c5e2f793b59a 615 /* ADC1 */
screamer 0:c5e2f793b59a 616 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
screamer 0:c5e2f793b59a 617 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
screamer 0:c5e2f793b59a 618 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
screamer 0:c5e2f793b59a 619 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
screamer 0:c5e2f793b59a 620 #define ADC1_RA ADC_R_REG(ADC1,0)
screamer 0:c5e2f793b59a 621 #define ADC1_RB ADC_R_REG(ADC1,1)
screamer 0:c5e2f793b59a 622 #define ADC1_CV1 ADC_CV1_REG(ADC1)
screamer 0:c5e2f793b59a 623 #define ADC1_CV2 ADC_CV2_REG(ADC1)
screamer 0:c5e2f793b59a 624 #define ADC1_SC2 ADC_SC2_REG(ADC1)
screamer 0:c5e2f793b59a 625 #define ADC1_SC3 ADC_SC3_REG(ADC1)
screamer 0:c5e2f793b59a 626 #define ADC1_OFS ADC_OFS_REG(ADC1)
screamer 0:c5e2f793b59a 627 #define ADC1_PG ADC_PG_REG(ADC1)
screamer 0:c5e2f793b59a 628 #define ADC1_MG ADC_MG_REG(ADC1)
screamer 0:c5e2f793b59a 629 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
screamer 0:c5e2f793b59a 630 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
screamer 0:c5e2f793b59a 631 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
screamer 0:c5e2f793b59a 632 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
screamer 0:c5e2f793b59a 633 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
screamer 0:c5e2f793b59a 634 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
screamer 0:c5e2f793b59a 635 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
screamer 0:c5e2f793b59a 636 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
screamer 0:c5e2f793b59a 637 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
screamer 0:c5e2f793b59a 638 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
screamer 0:c5e2f793b59a 639 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
screamer 0:c5e2f793b59a 640 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
screamer 0:c5e2f793b59a 641 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
screamer 0:c5e2f793b59a 642 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
screamer 0:c5e2f793b59a 643
screamer 0:c5e2f793b59a 644 /* ADC - Register array accessors */
screamer 0:c5e2f793b59a 645 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
screamer 0:c5e2f793b59a 646 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
screamer 0:c5e2f793b59a 647 #define ADC0_R(index) ADC_R_REG(ADC0,index)
screamer 0:c5e2f793b59a 648 #define ADC1_R(index) ADC_R_REG(ADC1,index)
screamer 0:c5e2f793b59a 649
screamer 0:c5e2f793b59a 650 /*!
screamer 0:c5e2f793b59a 651 * @}
screamer 0:c5e2f793b59a 652 */ /* end of group ADC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 653
screamer 0:c5e2f793b59a 654
screamer 0:c5e2f793b59a 655 /*!
screamer 0:c5e2f793b59a 656 * @}
screamer 0:c5e2f793b59a 657 */ /* end of group ADC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 658
screamer 0:c5e2f793b59a 659
screamer 0:c5e2f793b59a 660 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 661 -- AIPS Peripheral Access Layer
screamer 0:c5e2f793b59a 662 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 663
screamer 0:c5e2f793b59a 664 /*!
screamer 0:c5e2f793b59a 665 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
screamer 0:c5e2f793b59a 666 * @{
screamer 0:c5e2f793b59a 667 */
screamer 0:c5e2f793b59a 668
screamer 0:c5e2f793b59a 669 /** AIPS - Register Layout Typedef */
screamer 0:c5e2f793b59a 670 typedef struct {
screamer 0:c5e2f793b59a 671 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
screamer 0:c5e2f793b59a 672 uint8_t RESERVED_0[28];
screamer 0:c5e2f793b59a 673 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
screamer 0:c5e2f793b59a 674 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
screamer 0:c5e2f793b59a 675 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
screamer 0:c5e2f793b59a 676 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
screamer 0:c5e2f793b59a 677 uint8_t RESERVED_1[16];
screamer 0:c5e2f793b59a 678 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
screamer 0:c5e2f793b59a 679 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
screamer 0:c5e2f793b59a 680 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
screamer 0:c5e2f793b59a 681 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
screamer 0:c5e2f793b59a 682 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
screamer 0:c5e2f793b59a 683 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
screamer 0:c5e2f793b59a 684 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
screamer 0:c5e2f793b59a 685 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
screamer 0:c5e2f793b59a 686 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
screamer 0:c5e2f793b59a 687 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
screamer 0:c5e2f793b59a 688 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
screamer 0:c5e2f793b59a 689 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
screamer 0:c5e2f793b59a 690 uint8_t RESERVED_2[16];
screamer 0:c5e2f793b59a 691 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
screamer 0:c5e2f793b59a 692 } AIPS_Type, *AIPS_MemMapPtr;
screamer 0:c5e2f793b59a 693
screamer 0:c5e2f793b59a 694 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 695 -- AIPS - Register accessor macros
screamer 0:c5e2f793b59a 696 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 697
screamer 0:c5e2f793b59a 698 /*!
screamer 0:c5e2f793b59a 699 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
screamer 0:c5e2f793b59a 700 * @{
screamer 0:c5e2f793b59a 701 */
screamer 0:c5e2f793b59a 702
screamer 0:c5e2f793b59a 703
screamer 0:c5e2f793b59a 704 /* AIPS - Register accessors */
screamer 0:c5e2f793b59a 705 #define AIPS_MPRA_REG(base) ((base)->MPRA)
screamer 0:c5e2f793b59a 706 #define AIPS_PACRA_REG(base) ((base)->PACRA)
screamer 0:c5e2f793b59a 707 #define AIPS_PACRB_REG(base) ((base)->PACRB)
screamer 0:c5e2f793b59a 708 #define AIPS_PACRC_REG(base) ((base)->PACRC)
screamer 0:c5e2f793b59a 709 #define AIPS_PACRD_REG(base) ((base)->PACRD)
screamer 0:c5e2f793b59a 710 #define AIPS_PACRE_REG(base) ((base)->PACRE)
screamer 0:c5e2f793b59a 711 #define AIPS_PACRF_REG(base) ((base)->PACRF)
screamer 0:c5e2f793b59a 712 #define AIPS_PACRG_REG(base) ((base)->PACRG)
screamer 0:c5e2f793b59a 713 #define AIPS_PACRH_REG(base) ((base)->PACRH)
screamer 0:c5e2f793b59a 714 #define AIPS_PACRI_REG(base) ((base)->PACRI)
screamer 0:c5e2f793b59a 715 #define AIPS_PACRJ_REG(base) ((base)->PACRJ)
screamer 0:c5e2f793b59a 716 #define AIPS_PACRK_REG(base) ((base)->PACRK)
screamer 0:c5e2f793b59a 717 #define AIPS_PACRL_REG(base) ((base)->PACRL)
screamer 0:c5e2f793b59a 718 #define AIPS_PACRM_REG(base) ((base)->PACRM)
screamer 0:c5e2f793b59a 719 #define AIPS_PACRN_REG(base) ((base)->PACRN)
screamer 0:c5e2f793b59a 720 #define AIPS_PACRO_REG(base) ((base)->PACRO)
screamer 0:c5e2f793b59a 721 #define AIPS_PACRP_REG(base) ((base)->PACRP)
screamer 0:c5e2f793b59a 722 #define AIPS_PACRU_REG(base) ((base)->PACRU)
screamer 0:c5e2f793b59a 723
screamer 0:c5e2f793b59a 724 /*!
screamer 0:c5e2f793b59a 725 * @}
screamer 0:c5e2f793b59a 726 */ /* end of group AIPS_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 727
screamer 0:c5e2f793b59a 728
screamer 0:c5e2f793b59a 729 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 730 -- AIPS Register Masks
screamer 0:c5e2f793b59a 731 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 732
screamer 0:c5e2f793b59a 733 /*!
screamer 0:c5e2f793b59a 734 * @addtogroup AIPS_Register_Masks AIPS Register Masks
screamer 0:c5e2f793b59a 735 * @{
screamer 0:c5e2f793b59a 736 */
screamer 0:c5e2f793b59a 737
screamer 0:c5e2f793b59a 738 /* MPRA Bit Fields */
screamer 0:c5e2f793b59a 739 #define AIPS_MPRA_MPL5_MASK 0x100u
screamer 0:c5e2f793b59a 740 #define AIPS_MPRA_MPL5_SHIFT 8
screamer 0:c5e2f793b59a 741 #define AIPS_MPRA_MTW5_MASK 0x200u
screamer 0:c5e2f793b59a 742 #define AIPS_MPRA_MTW5_SHIFT 9
screamer 0:c5e2f793b59a 743 #define AIPS_MPRA_MTR5_MASK 0x400u
screamer 0:c5e2f793b59a 744 #define AIPS_MPRA_MTR5_SHIFT 10
screamer 0:c5e2f793b59a 745 #define AIPS_MPRA_MPL4_MASK 0x1000u
screamer 0:c5e2f793b59a 746 #define AIPS_MPRA_MPL4_SHIFT 12
screamer 0:c5e2f793b59a 747 #define AIPS_MPRA_MTW4_MASK 0x2000u
screamer 0:c5e2f793b59a 748 #define AIPS_MPRA_MTW4_SHIFT 13
screamer 0:c5e2f793b59a 749 #define AIPS_MPRA_MTR4_MASK 0x4000u
screamer 0:c5e2f793b59a 750 #define AIPS_MPRA_MTR4_SHIFT 14
screamer 0:c5e2f793b59a 751 #define AIPS_MPRA_MPL3_MASK 0x10000u
screamer 0:c5e2f793b59a 752 #define AIPS_MPRA_MPL3_SHIFT 16
screamer 0:c5e2f793b59a 753 #define AIPS_MPRA_MTW3_MASK 0x20000u
screamer 0:c5e2f793b59a 754 #define AIPS_MPRA_MTW3_SHIFT 17
screamer 0:c5e2f793b59a 755 #define AIPS_MPRA_MTR3_MASK 0x40000u
screamer 0:c5e2f793b59a 756 #define AIPS_MPRA_MTR3_SHIFT 18
screamer 0:c5e2f793b59a 757 #define AIPS_MPRA_MPL2_MASK 0x100000u
screamer 0:c5e2f793b59a 758 #define AIPS_MPRA_MPL2_SHIFT 20
screamer 0:c5e2f793b59a 759 #define AIPS_MPRA_MTW2_MASK 0x200000u
screamer 0:c5e2f793b59a 760 #define AIPS_MPRA_MTW2_SHIFT 21
screamer 0:c5e2f793b59a 761 #define AIPS_MPRA_MTR2_MASK 0x400000u
screamer 0:c5e2f793b59a 762 #define AIPS_MPRA_MTR2_SHIFT 22
screamer 0:c5e2f793b59a 763 #define AIPS_MPRA_MPL1_MASK 0x1000000u
screamer 0:c5e2f793b59a 764 #define AIPS_MPRA_MPL1_SHIFT 24
screamer 0:c5e2f793b59a 765 #define AIPS_MPRA_MTW1_MASK 0x2000000u
screamer 0:c5e2f793b59a 766 #define AIPS_MPRA_MTW1_SHIFT 25
screamer 0:c5e2f793b59a 767 #define AIPS_MPRA_MTR1_MASK 0x4000000u
screamer 0:c5e2f793b59a 768 #define AIPS_MPRA_MTR1_SHIFT 26
screamer 0:c5e2f793b59a 769 #define AIPS_MPRA_MPL0_MASK 0x10000000u
screamer 0:c5e2f793b59a 770 #define AIPS_MPRA_MPL0_SHIFT 28
screamer 0:c5e2f793b59a 771 #define AIPS_MPRA_MTW0_MASK 0x20000000u
screamer 0:c5e2f793b59a 772 #define AIPS_MPRA_MTW0_SHIFT 29
screamer 0:c5e2f793b59a 773 #define AIPS_MPRA_MTR0_MASK 0x40000000u
screamer 0:c5e2f793b59a 774 #define AIPS_MPRA_MTR0_SHIFT 30
screamer 0:c5e2f793b59a 775 /* PACRA Bit Fields */
screamer 0:c5e2f793b59a 776 #define AIPS_PACRA_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 777 #define AIPS_PACRA_TP7_SHIFT 0
screamer 0:c5e2f793b59a 778 #define AIPS_PACRA_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 779 #define AIPS_PACRA_WP7_SHIFT 1
screamer 0:c5e2f793b59a 780 #define AIPS_PACRA_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 781 #define AIPS_PACRA_SP7_SHIFT 2
screamer 0:c5e2f793b59a 782 #define AIPS_PACRA_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 783 #define AIPS_PACRA_TP6_SHIFT 4
screamer 0:c5e2f793b59a 784 #define AIPS_PACRA_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 785 #define AIPS_PACRA_WP6_SHIFT 5
screamer 0:c5e2f793b59a 786 #define AIPS_PACRA_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 787 #define AIPS_PACRA_SP6_SHIFT 6
screamer 0:c5e2f793b59a 788 #define AIPS_PACRA_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 789 #define AIPS_PACRA_TP5_SHIFT 8
screamer 0:c5e2f793b59a 790 #define AIPS_PACRA_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 791 #define AIPS_PACRA_WP5_SHIFT 9
screamer 0:c5e2f793b59a 792 #define AIPS_PACRA_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 793 #define AIPS_PACRA_SP5_SHIFT 10
screamer 0:c5e2f793b59a 794 #define AIPS_PACRA_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 795 #define AIPS_PACRA_TP4_SHIFT 12
screamer 0:c5e2f793b59a 796 #define AIPS_PACRA_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 797 #define AIPS_PACRA_WP4_SHIFT 13
screamer 0:c5e2f793b59a 798 #define AIPS_PACRA_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 799 #define AIPS_PACRA_SP4_SHIFT 14
screamer 0:c5e2f793b59a 800 #define AIPS_PACRA_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 801 #define AIPS_PACRA_TP3_SHIFT 16
screamer 0:c5e2f793b59a 802 #define AIPS_PACRA_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 803 #define AIPS_PACRA_WP3_SHIFT 17
screamer 0:c5e2f793b59a 804 #define AIPS_PACRA_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 805 #define AIPS_PACRA_SP3_SHIFT 18
screamer 0:c5e2f793b59a 806 #define AIPS_PACRA_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 807 #define AIPS_PACRA_TP2_SHIFT 20
screamer 0:c5e2f793b59a 808 #define AIPS_PACRA_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 809 #define AIPS_PACRA_WP2_SHIFT 21
screamer 0:c5e2f793b59a 810 #define AIPS_PACRA_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 811 #define AIPS_PACRA_SP2_SHIFT 22
screamer 0:c5e2f793b59a 812 #define AIPS_PACRA_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 813 #define AIPS_PACRA_TP1_SHIFT 24
screamer 0:c5e2f793b59a 814 #define AIPS_PACRA_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 815 #define AIPS_PACRA_WP1_SHIFT 25
screamer 0:c5e2f793b59a 816 #define AIPS_PACRA_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 817 #define AIPS_PACRA_SP1_SHIFT 26
screamer 0:c5e2f793b59a 818 #define AIPS_PACRA_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 819 #define AIPS_PACRA_TP0_SHIFT 28
screamer 0:c5e2f793b59a 820 #define AIPS_PACRA_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 821 #define AIPS_PACRA_WP0_SHIFT 29
screamer 0:c5e2f793b59a 822 #define AIPS_PACRA_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 823 #define AIPS_PACRA_SP0_SHIFT 30
screamer 0:c5e2f793b59a 824 /* PACRB Bit Fields */
screamer 0:c5e2f793b59a 825 #define AIPS_PACRB_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 826 #define AIPS_PACRB_TP7_SHIFT 0
screamer 0:c5e2f793b59a 827 #define AIPS_PACRB_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 828 #define AIPS_PACRB_WP7_SHIFT 1
screamer 0:c5e2f793b59a 829 #define AIPS_PACRB_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 830 #define AIPS_PACRB_SP7_SHIFT 2
screamer 0:c5e2f793b59a 831 #define AIPS_PACRB_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 832 #define AIPS_PACRB_TP6_SHIFT 4
screamer 0:c5e2f793b59a 833 #define AIPS_PACRB_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 834 #define AIPS_PACRB_WP6_SHIFT 5
screamer 0:c5e2f793b59a 835 #define AIPS_PACRB_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 836 #define AIPS_PACRB_SP6_SHIFT 6
screamer 0:c5e2f793b59a 837 #define AIPS_PACRB_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 838 #define AIPS_PACRB_TP5_SHIFT 8
screamer 0:c5e2f793b59a 839 #define AIPS_PACRB_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 840 #define AIPS_PACRB_WP5_SHIFT 9
screamer 0:c5e2f793b59a 841 #define AIPS_PACRB_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 842 #define AIPS_PACRB_SP5_SHIFT 10
screamer 0:c5e2f793b59a 843 #define AIPS_PACRB_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 844 #define AIPS_PACRB_TP4_SHIFT 12
screamer 0:c5e2f793b59a 845 #define AIPS_PACRB_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 846 #define AIPS_PACRB_WP4_SHIFT 13
screamer 0:c5e2f793b59a 847 #define AIPS_PACRB_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 848 #define AIPS_PACRB_SP4_SHIFT 14
screamer 0:c5e2f793b59a 849 #define AIPS_PACRB_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 850 #define AIPS_PACRB_TP3_SHIFT 16
screamer 0:c5e2f793b59a 851 #define AIPS_PACRB_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 852 #define AIPS_PACRB_WP3_SHIFT 17
screamer 0:c5e2f793b59a 853 #define AIPS_PACRB_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 854 #define AIPS_PACRB_SP3_SHIFT 18
screamer 0:c5e2f793b59a 855 #define AIPS_PACRB_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 856 #define AIPS_PACRB_TP2_SHIFT 20
screamer 0:c5e2f793b59a 857 #define AIPS_PACRB_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 858 #define AIPS_PACRB_WP2_SHIFT 21
screamer 0:c5e2f793b59a 859 #define AIPS_PACRB_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 860 #define AIPS_PACRB_SP2_SHIFT 22
screamer 0:c5e2f793b59a 861 #define AIPS_PACRB_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 862 #define AIPS_PACRB_TP1_SHIFT 24
screamer 0:c5e2f793b59a 863 #define AIPS_PACRB_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 864 #define AIPS_PACRB_WP1_SHIFT 25
screamer 0:c5e2f793b59a 865 #define AIPS_PACRB_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 866 #define AIPS_PACRB_SP1_SHIFT 26
screamer 0:c5e2f793b59a 867 #define AIPS_PACRB_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 868 #define AIPS_PACRB_TP0_SHIFT 28
screamer 0:c5e2f793b59a 869 #define AIPS_PACRB_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 870 #define AIPS_PACRB_WP0_SHIFT 29
screamer 0:c5e2f793b59a 871 #define AIPS_PACRB_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 872 #define AIPS_PACRB_SP0_SHIFT 30
screamer 0:c5e2f793b59a 873 /* PACRC Bit Fields */
screamer 0:c5e2f793b59a 874 #define AIPS_PACRC_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 875 #define AIPS_PACRC_TP7_SHIFT 0
screamer 0:c5e2f793b59a 876 #define AIPS_PACRC_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 877 #define AIPS_PACRC_WP7_SHIFT 1
screamer 0:c5e2f793b59a 878 #define AIPS_PACRC_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 879 #define AIPS_PACRC_SP7_SHIFT 2
screamer 0:c5e2f793b59a 880 #define AIPS_PACRC_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 881 #define AIPS_PACRC_TP6_SHIFT 4
screamer 0:c5e2f793b59a 882 #define AIPS_PACRC_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 883 #define AIPS_PACRC_WP6_SHIFT 5
screamer 0:c5e2f793b59a 884 #define AIPS_PACRC_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 885 #define AIPS_PACRC_SP6_SHIFT 6
screamer 0:c5e2f793b59a 886 #define AIPS_PACRC_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 887 #define AIPS_PACRC_TP5_SHIFT 8
screamer 0:c5e2f793b59a 888 #define AIPS_PACRC_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 889 #define AIPS_PACRC_WP5_SHIFT 9
screamer 0:c5e2f793b59a 890 #define AIPS_PACRC_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 891 #define AIPS_PACRC_SP5_SHIFT 10
screamer 0:c5e2f793b59a 892 #define AIPS_PACRC_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 893 #define AIPS_PACRC_TP4_SHIFT 12
screamer 0:c5e2f793b59a 894 #define AIPS_PACRC_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 895 #define AIPS_PACRC_WP4_SHIFT 13
screamer 0:c5e2f793b59a 896 #define AIPS_PACRC_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 897 #define AIPS_PACRC_SP4_SHIFT 14
screamer 0:c5e2f793b59a 898 #define AIPS_PACRC_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 899 #define AIPS_PACRC_TP3_SHIFT 16
screamer 0:c5e2f793b59a 900 #define AIPS_PACRC_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 901 #define AIPS_PACRC_WP3_SHIFT 17
screamer 0:c5e2f793b59a 902 #define AIPS_PACRC_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 903 #define AIPS_PACRC_SP3_SHIFT 18
screamer 0:c5e2f793b59a 904 #define AIPS_PACRC_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 905 #define AIPS_PACRC_TP2_SHIFT 20
screamer 0:c5e2f793b59a 906 #define AIPS_PACRC_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 907 #define AIPS_PACRC_WP2_SHIFT 21
screamer 0:c5e2f793b59a 908 #define AIPS_PACRC_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 909 #define AIPS_PACRC_SP2_SHIFT 22
screamer 0:c5e2f793b59a 910 #define AIPS_PACRC_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 911 #define AIPS_PACRC_TP1_SHIFT 24
screamer 0:c5e2f793b59a 912 #define AIPS_PACRC_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 913 #define AIPS_PACRC_WP1_SHIFT 25
screamer 0:c5e2f793b59a 914 #define AIPS_PACRC_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 915 #define AIPS_PACRC_SP1_SHIFT 26
screamer 0:c5e2f793b59a 916 #define AIPS_PACRC_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 917 #define AIPS_PACRC_TP0_SHIFT 28
screamer 0:c5e2f793b59a 918 #define AIPS_PACRC_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 919 #define AIPS_PACRC_WP0_SHIFT 29
screamer 0:c5e2f793b59a 920 #define AIPS_PACRC_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 921 #define AIPS_PACRC_SP0_SHIFT 30
screamer 0:c5e2f793b59a 922 /* PACRD Bit Fields */
screamer 0:c5e2f793b59a 923 #define AIPS_PACRD_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 924 #define AIPS_PACRD_TP7_SHIFT 0
screamer 0:c5e2f793b59a 925 #define AIPS_PACRD_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 926 #define AIPS_PACRD_WP7_SHIFT 1
screamer 0:c5e2f793b59a 927 #define AIPS_PACRD_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 928 #define AIPS_PACRD_SP7_SHIFT 2
screamer 0:c5e2f793b59a 929 #define AIPS_PACRD_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 930 #define AIPS_PACRD_TP6_SHIFT 4
screamer 0:c5e2f793b59a 931 #define AIPS_PACRD_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 932 #define AIPS_PACRD_WP6_SHIFT 5
screamer 0:c5e2f793b59a 933 #define AIPS_PACRD_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 934 #define AIPS_PACRD_SP6_SHIFT 6
screamer 0:c5e2f793b59a 935 #define AIPS_PACRD_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 936 #define AIPS_PACRD_TP5_SHIFT 8
screamer 0:c5e2f793b59a 937 #define AIPS_PACRD_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 938 #define AIPS_PACRD_WP5_SHIFT 9
screamer 0:c5e2f793b59a 939 #define AIPS_PACRD_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 940 #define AIPS_PACRD_SP5_SHIFT 10
screamer 0:c5e2f793b59a 941 #define AIPS_PACRD_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 942 #define AIPS_PACRD_TP4_SHIFT 12
screamer 0:c5e2f793b59a 943 #define AIPS_PACRD_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 944 #define AIPS_PACRD_WP4_SHIFT 13
screamer 0:c5e2f793b59a 945 #define AIPS_PACRD_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 946 #define AIPS_PACRD_SP4_SHIFT 14
screamer 0:c5e2f793b59a 947 #define AIPS_PACRD_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 948 #define AIPS_PACRD_TP3_SHIFT 16
screamer 0:c5e2f793b59a 949 #define AIPS_PACRD_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 950 #define AIPS_PACRD_WP3_SHIFT 17
screamer 0:c5e2f793b59a 951 #define AIPS_PACRD_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 952 #define AIPS_PACRD_SP3_SHIFT 18
screamer 0:c5e2f793b59a 953 #define AIPS_PACRD_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 954 #define AIPS_PACRD_TP2_SHIFT 20
screamer 0:c5e2f793b59a 955 #define AIPS_PACRD_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 956 #define AIPS_PACRD_WP2_SHIFT 21
screamer 0:c5e2f793b59a 957 #define AIPS_PACRD_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 958 #define AIPS_PACRD_SP2_SHIFT 22
screamer 0:c5e2f793b59a 959 #define AIPS_PACRD_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 960 #define AIPS_PACRD_TP1_SHIFT 24
screamer 0:c5e2f793b59a 961 #define AIPS_PACRD_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 962 #define AIPS_PACRD_WP1_SHIFT 25
screamer 0:c5e2f793b59a 963 #define AIPS_PACRD_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 964 #define AIPS_PACRD_SP1_SHIFT 26
screamer 0:c5e2f793b59a 965 #define AIPS_PACRD_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 966 #define AIPS_PACRD_TP0_SHIFT 28
screamer 0:c5e2f793b59a 967 #define AIPS_PACRD_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 968 #define AIPS_PACRD_WP0_SHIFT 29
screamer 0:c5e2f793b59a 969 #define AIPS_PACRD_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 970 #define AIPS_PACRD_SP0_SHIFT 30
screamer 0:c5e2f793b59a 971 /* PACRE Bit Fields */
screamer 0:c5e2f793b59a 972 #define AIPS_PACRE_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 973 #define AIPS_PACRE_TP7_SHIFT 0
screamer 0:c5e2f793b59a 974 #define AIPS_PACRE_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 975 #define AIPS_PACRE_WP7_SHIFT 1
screamer 0:c5e2f793b59a 976 #define AIPS_PACRE_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 977 #define AIPS_PACRE_SP7_SHIFT 2
screamer 0:c5e2f793b59a 978 #define AIPS_PACRE_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 979 #define AIPS_PACRE_TP6_SHIFT 4
screamer 0:c5e2f793b59a 980 #define AIPS_PACRE_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 981 #define AIPS_PACRE_WP6_SHIFT 5
screamer 0:c5e2f793b59a 982 #define AIPS_PACRE_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 983 #define AIPS_PACRE_SP6_SHIFT 6
screamer 0:c5e2f793b59a 984 #define AIPS_PACRE_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 985 #define AIPS_PACRE_TP5_SHIFT 8
screamer 0:c5e2f793b59a 986 #define AIPS_PACRE_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 987 #define AIPS_PACRE_WP5_SHIFT 9
screamer 0:c5e2f793b59a 988 #define AIPS_PACRE_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 989 #define AIPS_PACRE_SP5_SHIFT 10
screamer 0:c5e2f793b59a 990 #define AIPS_PACRE_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 991 #define AIPS_PACRE_TP4_SHIFT 12
screamer 0:c5e2f793b59a 992 #define AIPS_PACRE_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 993 #define AIPS_PACRE_WP4_SHIFT 13
screamer 0:c5e2f793b59a 994 #define AIPS_PACRE_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 995 #define AIPS_PACRE_SP4_SHIFT 14
screamer 0:c5e2f793b59a 996 #define AIPS_PACRE_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 997 #define AIPS_PACRE_TP3_SHIFT 16
screamer 0:c5e2f793b59a 998 #define AIPS_PACRE_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 999 #define AIPS_PACRE_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1000 #define AIPS_PACRE_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1001 #define AIPS_PACRE_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1002 #define AIPS_PACRE_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1003 #define AIPS_PACRE_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1004 #define AIPS_PACRE_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1005 #define AIPS_PACRE_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1006 #define AIPS_PACRE_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1007 #define AIPS_PACRE_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1008 #define AIPS_PACRE_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1009 #define AIPS_PACRE_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1010 #define AIPS_PACRE_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1011 #define AIPS_PACRE_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1012 #define AIPS_PACRE_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1013 #define AIPS_PACRE_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1014 #define AIPS_PACRE_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1015 #define AIPS_PACRE_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1016 #define AIPS_PACRE_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1017 #define AIPS_PACRE_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1018 #define AIPS_PACRE_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1019 #define AIPS_PACRE_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1020 /* PACRF Bit Fields */
screamer 0:c5e2f793b59a 1021 #define AIPS_PACRF_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1022 #define AIPS_PACRF_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1023 #define AIPS_PACRF_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1024 #define AIPS_PACRF_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1025 #define AIPS_PACRF_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1026 #define AIPS_PACRF_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1027 #define AIPS_PACRF_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1028 #define AIPS_PACRF_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1029 #define AIPS_PACRF_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1030 #define AIPS_PACRF_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1031 #define AIPS_PACRF_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1032 #define AIPS_PACRF_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1033 #define AIPS_PACRF_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1034 #define AIPS_PACRF_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1035 #define AIPS_PACRF_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1036 #define AIPS_PACRF_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1037 #define AIPS_PACRF_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1038 #define AIPS_PACRF_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1039 #define AIPS_PACRF_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1040 #define AIPS_PACRF_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1041 #define AIPS_PACRF_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1042 #define AIPS_PACRF_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1043 #define AIPS_PACRF_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1044 #define AIPS_PACRF_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1045 #define AIPS_PACRF_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1046 #define AIPS_PACRF_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1047 #define AIPS_PACRF_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1048 #define AIPS_PACRF_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1049 #define AIPS_PACRF_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1050 #define AIPS_PACRF_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1051 #define AIPS_PACRF_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1052 #define AIPS_PACRF_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1053 #define AIPS_PACRF_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1054 #define AIPS_PACRF_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1055 #define AIPS_PACRF_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1056 #define AIPS_PACRF_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1057 #define AIPS_PACRF_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1058 #define AIPS_PACRF_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1059 #define AIPS_PACRF_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1060 #define AIPS_PACRF_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1061 #define AIPS_PACRF_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1062 #define AIPS_PACRF_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1063 #define AIPS_PACRF_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1064 #define AIPS_PACRF_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1065 #define AIPS_PACRF_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1066 #define AIPS_PACRF_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1067 #define AIPS_PACRF_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1068 #define AIPS_PACRF_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1069 /* PACRG Bit Fields */
screamer 0:c5e2f793b59a 1070 #define AIPS_PACRG_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1071 #define AIPS_PACRG_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1072 #define AIPS_PACRG_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1073 #define AIPS_PACRG_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1074 #define AIPS_PACRG_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1075 #define AIPS_PACRG_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1076 #define AIPS_PACRG_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1077 #define AIPS_PACRG_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1078 #define AIPS_PACRG_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1079 #define AIPS_PACRG_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1080 #define AIPS_PACRG_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1081 #define AIPS_PACRG_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1082 #define AIPS_PACRG_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1083 #define AIPS_PACRG_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1084 #define AIPS_PACRG_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1085 #define AIPS_PACRG_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1086 #define AIPS_PACRG_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1087 #define AIPS_PACRG_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1088 #define AIPS_PACRG_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1089 #define AIPS_PACRG_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1090 #define AIPS_PACRG_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1091 #define AIPS_PACRG_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1092 #define AIPS_PACRG_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1093 #define AIPS_PACRG_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1094 #define AIPS_PACRG_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1095 #define AIPS_PACRG_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1096 #define AIPS_PACRG_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1097 #define AIPS_PACRG_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1098 #define AIPS_PACRG_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1099 #define AIPS_PACRG_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1100 #define AIPS_PACRG_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1101 #define AIPS_PACRG_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1102 #define AIPS_PACRG_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1103 #define AIPS_PACRG_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1104 #define AIPS_PACRG_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1105 #define AIPS_PACRG_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1106 #define AIPS_PACRG_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1107 #define AIPS_PACRG_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1108 #define AIPS_PACRG_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1109 #define AIPS_PACRG_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1110 #define AIPS_PACRG_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1111 #define AIPS_PACRG_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1112 #define AIPS_PACRG_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1113 #define AIPS_PACRG_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1114 #define AIPS_PACRG_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1115 #define AIPS_PACRG_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1116 #define AIPS_PACRG_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1117 #define AIPS_PACRG_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1118 /* PACRH Bit Fields */
screamer 0:c5e2f793b59a 1119 #define AIPS_PACRH_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1120 #define AIPS_PACRH_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1121 #define AIPS_PACRH_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1122 #define AIPS_PACRH_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1123 #define AIPS_PACRH_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1124 #define AIPS_PACRH_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1125 #define AIPS_PACRH_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1126 #define AIPS_PACRH_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1127 #define AIPS_PACRH_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1128 #define AIPS_PACRH_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1129 #define AIPS_PACRH_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1130 #define AIPS_PACRH_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1131 #define AIPS_PACRH_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1132 #define AIPS_PACRH_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1133 #define AIPS_PACRH_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1134 #define AIPS_PACRH_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1135 #define AIPS_PACRH_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1136 #define AIPS_PACRH_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1137 #define AIPS_PACRH_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1138 #define AIPS_PACRH_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1139 #define AIPS_PACRH_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1140 #define AIPS_PACRH_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1141 #define AIPS_PACRH_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1142 #define AIPS_PACRH_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1143 #define AIPS_PACRH_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1144 #define AIPS_PACRH_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1145 #define AIPS_PACRH_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1146 #define AIPS_PACRH_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1147 #define AIPS_PACRH_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1148 #define AIPS_PACRH_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1149 #define AIPS_PACRH_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1150 #define AIPS_PACRH_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1151 #define AIPS_PACRH_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1152 #define AIPS_PACRH_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1153 #define AIPS_PACRH_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1154 #define AIPS_PACRH_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1155 #define AIPS_PACRH_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1156 #define AIPS_PACRH_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1157 #define AIPS_PACRH_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1158 #define AIPS_PACRH_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1159 #define AIPS_PACRH_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1160 #define AIPS_PACRH_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1161 #define AIPS_PACRH_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1162 #define AIPS_PACRH_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1163 #define AIPS_PACRH_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1164 #define AIPS_PACRH_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1165 #define AIPS_PACRH_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1166 #define AIPS_PACRH_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1167 /* PACRI Bit Fields */
screamer 0:c5e2f793b59a 1168 #define AIPS_PACRI_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1169 #define AIPS_PACRI_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1170 #define AIPS_PACRI_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1171 #define AIPS_PACRI_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1172 #define AIPS_PACRI_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1173 #define AIPS_PACRI_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1174 #define AIPS_PACRI_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1175 #define AIPS_PACRI_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1176 #define AIPS_PACRI_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1177 #define AIPS_PACRI_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1178 #define AIPS_PACRI_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1179 #define AIPS_PACRI_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1180 #define AIPS_PACRI_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1181 #define AIPS_PACRI_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1182 #define AIPS_PACRI_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1183 #define AIPS_PACRI_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1184 #define AIPS_PACRI_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1185 #define AIPS_PACRI_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1186 #define AIPS_PACRI_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1187 #define AIPS_PACRI_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1188 #define AIPS_PACRI_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1189 #define AIPS_PACRI_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1190 #define AIPS_PACRI_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1191 #define AIPS_PACRI_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1192 #define AIPS_PACRI_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1193 #define AIPS_PACRI_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1194 #define AIPS_PACRI_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1195 #define AIPS_PACRI_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1196 #define AIPS_PACRI_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1197 #define AIPS_PACRI_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1198 #define AIPS_PACRI_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1199 #define AIPS_PACRI_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1200 #define AIPS_PACRI_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1201 #define AIPS_PACRI_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1202 #define AIPS_PACRI_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1203 #define AIPS_PACRI_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1204 #define AIPS_PACRI_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1205 #define AIPS_PACRI_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1206 #define AIPS_PACRI_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1207 #define AIPS_PACRI_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1208 #define AIPS_PACRI_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1209 #define AIPS_PACRI_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1210 #define AIPS_PACRI_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1211 #define AIPS_PACRI_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1212 #define AIPS_PACRI_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1213 #define AIPS_PACRI_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1214 #define AIPS_PACRI_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1215 #define AIPS_PACRI_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1216 /* PACRJ Bit Fields */
screamer 0:c5e2f793b59a 1217 #define AIPS_PACRJ_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1218 #define AIPS_PACRJ_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1219 #define AIPS_PACRJ_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1220 #define AIPS_PACRJ_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1221 #define AIPS_PACRJ_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1222 #define AIPS_PACRJ_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1223 #define AIPS_PACRJ_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1224 #define AIPS_PACRJ_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1225 #define AIPS_PACRJ_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1226 #define AIPS_PACRJ_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1227 #define AIPS_PACRJ_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1228 #define AIPS_PACRJ_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1229 #define AIPS_PACRJ_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1230 #define AIPS_PACRJ_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1231 #define AIPS_PACRJ_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1232 #define AIPS_PACRJ_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1233 #define AIPS_PACRJ_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1234 #define AIPS_PACRJ_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1235 #define AIPS_PACRJ_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1236 #define AIPS_PACRJ_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1237 #define AIPS_PACRJ_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1238 #define AIPS_PACRJ_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1239 #define AIPS_PACRJ_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1240 #define AIPS_PACRJ_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1241 #define AIPS_PACRJ_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1242 #define AIPS_PACRJ_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1243 #define AIPS_PACRJ_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1244 #define AIPS_PACRJ_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1245 #define AIPS_PACRJ_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1246 #define AIPS_PACRJ_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1247 #define AIPS_PACRJ_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1248 #define AIPS_PACRJ_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1249 #define AIPS_PACRJ_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1250 #define AIPS_PACRJ_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1251 #define AIPS_PACRJ_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1252 #define AIPS_PACRJ_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1253 #define AIPS_PACRJ_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1254 #define AIPS_PACRJ_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1255 #define AIPS_PACRJ_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1256 #define AIPS_PACRJ_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1257 #define AIPS_PACRJ_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1258 #define AIPS_PACRJ_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1259 #define AIPS_PACRJ_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1260 #define AIPS_PACRJ_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1261 #define AIPS_PACRJ_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1262 #define AIPS_PACRJ_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1263 #define AIPS_PACRJ_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1264 #define AIPS_PACRJ_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1265 /* PACRK Bit Fields */
screamer 0:c5e2f793b59a 1266 #define AIPS_PACRK_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1267 #define AIPS_PACRK_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1268 #define AIPS_PACRK_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1269 #define AIPS_PACRK_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1270 #define AIPS_PACRK_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1271 #define AIPS_PACRK_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1272 #define AIPS_PACRK_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1273 #define AIPS_PACRK_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1274 #define AIPS_PACRK_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1275 #define AIPS_PACRK_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1276 #define AIPS_PACRK_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1277 #define AIPS_PACRK_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1278 #define AIPS_PACRK_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1279 #define AIPS_PACRK_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1280 #define AIPS_PACRK_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1281 #define AIPS_PACRK_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1282 #define AIPS_PACRK_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1283 #define AIPS_PACRK_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1284 #define AIPS_PACRK_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1285 #define AIPS_PACRK_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1286 #define AIPS_PACRK_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1287 #define AIPS_PACRK_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1288 #define AIPS_PACRK_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1289 #define AIPS_PACRK_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1290 #define AIPS_PACRK_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1291 #define AIPS_PACRK_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1292 #define AIPS_PACRK_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1293 #define AIPS_PACRK_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1294 #define AIPS_PACRK_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1295 #define AIPS_PACRK_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1296 #define AIPS_PACRK_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1297 #define AIPS_PACRK_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1298 #define AIPS_PACRK_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1299 #define AIPS_PACRK_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1300 #define AIPS_PACRK_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1301 #define AIPS_PACRK_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1302 #define AIPS_PACRK_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1303 #define AIPS_PACRK_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1304 #define AIPS_PACRK_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1305 #define AIPS_PACRK_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1306 #define AIPS_PACRK_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1307 #define AIPS_PACRK_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1308 #define AIPS_PACRK_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1309 #define AIPS_PACRK_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1310 #define AIPS_PACRK_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1311 #define AIPS_PACRK_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1312 #define AIPS_PACRK_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1313 #define AIPS_PACRK_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1314 /* PACRL Bit Fields */
screamer 0:c5e2f793b59a 1315 #define AIPS_PACRL_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1316 #define AIPS_PACRL_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1317 #define AIPS_PACRL_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1318 #define AIPS_PACRL_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1319 #define AIPS_PACRL_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1320 #define AIPS_PACRL_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1321 #define AIPS_PACRL_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1322 #define AIPS_PACRL_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1323 #define AIPS_PACRL_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1324 #define AIPS_PACRL_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1325 #define AIPS_PACRL_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1326 #define AIPS_PACRL_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1327 #define AIPS_PACRL_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1328 #define AIPS_PACRL_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1329 #define AIPS_PACRL_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1330 #define AIPS_PACRL_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1331 #define AIPS_PACRL_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1332 #define AIPS_PACRL_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1333 #define AIPS_PACRL_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1334 #define AIPS_PACRL_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1335 #define AIPS_PACRL_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1336 #define AIPS_PACRL_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1337 #define AIPS_PACRL_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1338 #define AIPS_PACRL_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1339 #define AIPS_PACRL_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1340 #define AIPS_PACRL_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1341 #define AIPS_PACRL_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1342 #define AIPS_PACRL_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1343 #define AIPS_PACRL_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1344 #define AIPS_PACRL_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1345 #define AIPS_PACRL_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1346 #define AIPS_PACRL_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1347 #define AIPS_PACRL_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1348 #define AIPS_PACRL_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1349 #define AIPS_PACRL_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1350 #define AIPS_PACRL_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1351 #define AIPS_PACRL_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1352 #define AIPS_PACRL_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1353 #define AIPS_PACRL_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1354 #define AIPS_PACRL_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1355 #define AIPS_PACRL_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1356 #define AIPS_PACRL_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1357 #define AIPS_PACRL_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1358 #define AIPS_PACRL_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1359 #define AIPS_PACRL_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1360 #define AIPS_PACRL_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1361 #define AIPS_PACRL_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1362 #define AIPS_PACRL_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1363 /* PACRM Bit Fields */
screamer 0:c5e2f793b59a 1364 #define AIPS_PACRM_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1365 #define AIPS_PACRM_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1366 #define AIPS_PACRM_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1367 #define AIPS_PACRM_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1368 #define AIPS_PACRM_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1369 #define AIPS_PACRM_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1370 #define AIPS_PACRM_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1371 #define AIPS_PACRM_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1372 #define AIPS_PACRM_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1373 #define AIPS_PACRM_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1374 #define AIPS_PACRM_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1375 #define AIPS_PACRM_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1376 #define AIPS_PACRM_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1377 #define AIPS_PACRM_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1378 #define AIPS_PACRM_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1379 #define AIPS_PACRM_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1380 #define AIPS_PACRM_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1381 #define AIPS_PACRM_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1382 #define AIPS_PACRM_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1383 #define AIPS_PACRM_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1384 #define AIPS_PACRM_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1385 #define AIPS_PACRM_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1386 #define AIPS_PACRM_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1387 #define AIPS_PACRM_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1388 #define AIPS_PACRM_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1389 #define AIPS_PACRM_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1390 #define AIPS_PACRM_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1391 #define AIPS_PACRM_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1392 #define AIPS_PACRM_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1393 #define AIPS_PACRM_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1394 #define AIPS_PACRM_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1395 #define AIPS_PACRM_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1396 #define AIPS_PACRM_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1397 #define AIPS_PACRM_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1398 #define AIPS_PACRM_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1399 #define AIPS_PACRM_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1400 #define AIPS_PACRM_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1401 #define AIPS_PACRM_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1402 #define AIPS_PACRM_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1403 #define AIPS_PACRM_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1404 #define AIPS_PACRM_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1405 #define AIPS_PACRM_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1406 #define AIPS_PACRM_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1407 #define AIPS_PACRM_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1408 #define AIPS_PACRM_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1409 #define AIPS_PACRM_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1410 #define AIPS_PACRM_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1411 #define AIPS_PACRM_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1412 /* PACRN Bit Fields */
screamer 0:c5e2f793b59a 1413 #define AIPS_PACRN_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1414 #define AIPS_PACRN_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1415 #define AIPS_PACRN_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1416 #define AIPS_PACRN_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1417 #define AIPS_PACRN_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1418 #define AIPS_PACRN_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1419 #define AIPS_PACRN_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1420 #define AIPS_PACRN_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1421 #define AIPS_PACRN_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1422 #define AIPS_PACRN_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1423 #define AIPS_PACRN_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1424 #define AIPS_PACRN_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1425 #define AIPS_PACRN_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1426 #define AIPS_PACRN_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1427 #define AIPS_PACRN_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1428 #define AIPS_PACRN_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1429 #define AIPS_PACRN_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1430 #define AIPS_PACRN_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1431 #define AIPS_PACRN_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1432 #define AIPS_PACRN_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1433 #define AIPS_PACRN_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1434 #define AIPS_PACRN_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1435 #define AIPS_PACRN_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1436 #define AIPS_PACRN_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1437 #define AIPS_PACRN_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1438 #define AIPS_PACRN_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1439 #define AIPS_PACRN_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1440 #define AIPS_PACRN_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1441 #define AIPS_PACRN_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1442 #define AIPS_PACRN_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1443 #define AIPS_PACRN_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1444 #define AIPS_PACRN_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1445 #define AIPS_PACRN_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1446 #define AIPS_PACRN_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1447 #define AIPS_PACRN_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1448 #define AIPS_PACRN_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1449 #define AIPS_PACRN_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1450 #define AIPS_PACRN_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1451 #define AIPS_PACRN_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1452 #define AIPS_PACRN_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1453 #define AIPS_PACRN_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1454 #define AIPS_PACRN_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1455 #define AIPS_PACRN_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1456 #define AIPS_PACRN_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1457 #define AIPS_PACRN_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1458 #define AIPS_PACRN_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1459 #define AIPS_PACRN_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1460 #define AIPS_PACRN_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1461 /* PACRO Bit Fields */
screamer 0:c5e2f793b59a 1462 #define AIPS_PACRO_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1463 #define AIPS_PACRO_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1464 #define AIPS_PACRO_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1465 #define AIPS_PACRO_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1466 #define AIPS_PACRO_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1467 #define AIPS_PACRO_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1468 #define AIPS_PACRO_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1469 #define AIPS_PACRO_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1470 #define AIPS_PACRO_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1471 #define AIPS_PACRO_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1472 #define AIPS_PACRO_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1473 #define AIPS_PACRO_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1474 #define AIPS_PACRO_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1475 #define AIPS_PACRO_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1476 #define AIPS_PACRO_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1477 #define AIPS_PACRO_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1478 #define AIPS_PACRO_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1479 #define AIPS_PACRO_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1480 #define AIPS_PACRO_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1481 #define AIPS_PACRO_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1482 #define AIPS_PACRO_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1483 #define AIPS_PACRO_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1484 #define AIPS_PACRO_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1485 #define AIPS_PACRO_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1486 #define AIPS_PACRO_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1487 #define AIPS_PACRO_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1488 #define AIPS_PACRO_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1489 #define AIPS_PACRO_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1490 #define AIPS_PACRO_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1491 #define AIPS_PACRO_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1492 #define AIPS_PACRO_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1493 #define AIPS_PACRO_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1494 #define AIPS_PACRO_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1495 #define AIPS_PACRO_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1496 #define AIPS_PACRO_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1497 #define AIPS_PACRO_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1498 #define AIPS_PACRO_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1499 #define AIPS_PACRO_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1500 #define AIPS_PACRO_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1501 #define AIPS_PACRO_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1502 #define AIPS_PACRO_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1503 #define AIPS_PACRO_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1504 #define AIPS_PACRO_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1505 #define AIPS_PACRO_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1506 #define AIPS_PACRO_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1507 #define AIPS_PACRO_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1508 #define AIPS_PACRO_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1509 #define AIPS_PACRO_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1510 /* PACRP Bit Fields */
screamer 0:c5e2f793b59a 1511 #define AIPS_PACRP_TP7_MASK 0x1u
screamer 0:c5e2f793b59a 1512 #define AIPS_PACRP_TP7_SHIFT 0
screamer 0:c5e2f793b59a 1513 #define AIPS_PACRP_WP7_MASK 0x2u
screamer 0:c5e2f793b59a 1514 #define AIPS_PACRP_WP7_SHIFT 1
screamer 0:c5e2f793b59a 1515 #define AIPS_PACRP_SP7_MASK 0x4u
screamer 0:c5e2f793b59a 1516 #define AIPS_PACRP_SP7_SHIFT 2
screamer 0:c5e2f793b59a 1517 #define AIPS_PACRP_TP6_MASK 0x10u
screamer 0:c5e2f793b59a 1518 #define AIPS_PACRP_TP6_SHIFT 4
screamer 0:c5e2f793b59a 1519 #define AIPS_PACRP_WP6_MASK 0x20u
screamer 0:c5e2f793b59a 1520 #define AIPS_PACRP_WP6_SHIFT 5
screamer 0:c5e2f793b59a 1521 #define AIPS_PACRP_SP6_MASK 0x40u
screamer 0:c5e2f793b59a 1522 #define AIPS_PACRP_SP6_SHIFT 6
screamer 0:c5e2f793b59a 1523 #define AIPS_PACRP_TP5_MASK 0x100u
screamer 0:c5e2f793b59a 1524 #define AIPS_PACRP_TP5_SHIFT 8
screamer 0:c5e2f793b59a 1525 #define AIPS_PACRP_WP5_MASK 0x200u
screamer 0:c5e2f793b59a 1526 #define AIPS_PACRP_WP5_SHIFT 9
screamer 0:c5e2f793b59a 1527 #define AIPS_PACRP_SP5_MASK 0x400u
screamer 0:c5e2f793b59a 1528 #define AIPS_PACRP_SP5_SHIFT 10
screamer 0:c5e2f793b59a 1529 #define AIPS_PACRP_TP4_MASK 0x1000u
screamer 0:c5e2f793b59a 1530 #define AIPS_PACRP_TP4_SHIFT 12
screamer 0:c5e2f793b59a 1531 #define AIPS_PACRP_WP4_MASK 0x2000u
screamer 0:c5e2f793b59a 1532 #define AIPS_PACRP_WP4_SHIFT 13
screamer 0:c5e2f793b59a 1533 #define AIPS_PACRP_SP4_MASK 0x4000u
screamer 0:c5e2f793b59a 1534 #define AIPS_PACRP_SP4_SHIFT 14
screamer 0:c5e2f793b59a 1535 #define AIPS_PACRP_TP3_MASK 0x10000u
screamer 0:c5e2f793b59a 1536 #define AIPS_PACRP_TP3_SHIFT 16
screamer 0:c5e2f793b59a 1537 #define AIPS_PACRP_WP3_MASK 0x20000u
screamer 0:c5e2f793b59a 1538 #define AIPS_PACRP_WP3_SHIFT 17
screamer 0:c5e2f793b59a 1539 #define AIPS_PACRP_SP3_MASK 0x40000u
screamer 0:c5e2f793b59a 1540 #define AIPS_PACRP_SP3_SHIFT 18
screamer 0:c5e2f793b59a 1541 #define AIPS_PACRP_TP2_MASK 0x100000u
screamer 0:c5e2f793b59a 1542 #define AIPS_PACRP_TP2_SHIFT 20
screamer 0:c5e2f793b59a 1543 #define AIPS_PACRP_WP2_MASK 0x200000u
screamer 0:c5e2f793b59a 1544 #define AIPS_PACRP_WP2_SHIFT 21
screamer 0:c5e2f793b59a 1545 #define AIPS_PACRP_SP2_MASK 0x400000u
screamer 0:c5e2f793b59a 1546 #define AIPS_PACRP_SP2_SHIFT 22
screamer 0:c5e2f793b59a 1547 #define AIPS_PACRP_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1548 #define AIPS_PACRP_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1549 #define AIPS_PACRP_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1550 #define AIPS_PACRP_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1551 #define AIPS_PACRP_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1552 #define AIPS_PACRP_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1553 #define AIPS_PACRP_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1554 #define AIPS_PACRP_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1555 #define AIPS_PACRP_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1556 #define AIPS_PACRP_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1557 #define AIPS_PACRP_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1558 #define AIPS_PACRP_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1559 /* PACRU Bit Fields */
screamer 0:c5e2f793b59a 1560 #define AIPS_PACRU_TP1_MASK 0x1000000u
screamer 0:c5e2f793b59a 1561 #define AIPS_PACRU_TP1_SHIFT 24
screamer 0:c5e2f793b59a 1562 #define AIPS_PACRU_WP1_MASK 0x2000000u
screamer 0:c5e2f793b59a 1563 #define AIPS_PACRU_WP1_SHIFT 25
screamer 0:c5e2f793b59a 1564 #define AIPS_PACRU_SP1_MASK 0x4000000u
screamer 0:c5e2f793b59a 1565 #define AIPS_PACRU_SP1_SHIFT 26
screamer 0:c5e2f793b59a 1566 #define AIPS_PACRU_TP0_MASK 0x10000000u
screamer 0:c5e2f793b59a 1567 #define AIPS_PACRU_TP0_SHIFT 28
screamer 0:c5e2f793b59a 1568 #define AIPS_PACRU_WP0_MASK 0x20000000u
screamer 0:c5e2f793b59a 1569 #define AIPS_PACRU_WP0_SHIFT 29
screamer 0:c5e2f793b59a 1570 #define AIPS_PACRU_SP0_MASK 0x40000000u
screamer 0:c5e2f793b59a 1571 #define AIPS_PACRU_SP0_SHIFT 30
screamer 0:c5e2f793b59a 1572
screamer 0:c5e2f793b59a 1573 /*!
screamer 0:c5e2f793b59a 1574 * @}
screamer 0:c5e2f793b59a 1575 */ /* end of group AIPS_Register_Masks */
screamer 0:c5e2f793b59a 1576
screamer 0:c5e2f793b59a 1577
screamer 0:c5e2f793b59a 1578 /* AIPS - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 1579 /** Peripheral AIPS0 base address */
screamer 0:c5e2f793b59a 1580 #define AIPS0_BASE (0x40000000u)
screamer 0:c5e2f793b59a 1581 /** Peripheral AIPS0 base pointer */
screamer 0:c5e2f793b59a 1582 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
screamer 0:c5e2f793b59a 1583 #define AIPS0_BASE_PTR (AIPS0)
screamer 0:c5e2f793b59a 1584 /** Peripheral AIPS1 base address */
screamer 0:c5e2f793b59a 1585 #define AIPS1_BASE (0x40080000u)
screamer 0:c5e2f793b59a 1586 /** Peripheral AIPS1 base pointer */
screamer 0:c5e2f793b59a 1587 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
screamer 0:c5e2f793b59a 1588 #define AIPS1_BASE_PTR (AIPS1)
screamer 0:c5e2f793b59a 1589 /** Array initializer of AIPS peripheral base addresses */
screamer 0:c5e2f793b59a 1590 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
screamer 0:c5e2f793b59a 1591 /** Array initializer of AIPS peripheral base pointers */
screamer 0:c5e2f793b59a 1592 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
screamer 0:c5e2f793b59a 1593
screamer 0:c5e2f793b59a 1594 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 1595 -- AIPS - Register accessor macros
screamer 0:c5e2f793b59a 1596 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 1597
screamer 0:c5e2f793b59a 1598 /*!
screamer 0:c5e2f793b59a 1599 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
screamer 0:c5e2f793b59a 1600 * @{
screamer 0:c5e2f793b59a 1601 */
screamer 0:c5e2f793b59a 1602
screamer 0:c5e2f793b59a 1603
screamer 0:c5e2f793b59a 1604 /* AIPS - Register instance definitions */
screamer 0:c5e2f793b59a 1605 /* AIPS0 */
screamer 0:c5e2f793b59a 1606 #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
screamer 0:c5e2f793b59a 1607 #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
screamer 0:c5e2f793b59a 1608 #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
screamer 0:c5e2f793b59a 1609 #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
screamer 0:c5e2f793b59a 1610 #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
screamer 0:c5e2f793b59a 1611 #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
screamer 0:c5e2f793b59a 1612 #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
screamer 0:c5e2f793b59a 1613 #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
screamer 0:c5e2f793b59a 1614 #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
screamer 0:c5e2f793b59a 1615 #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
screamer 0:c5e2f793b59a 1616 #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
screamer 0:c5e2f793b59a 1617 #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
screamer 0:c5e2f793b59a 1618 #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
screamer 0:c5e2f793b59a 1619 #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
screamer 0:c5e2f793b59a 1620 #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
screamer 0:c5e2f793b59a 1621 #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
screamer 0:c5e2f793b59a 1622 #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
screamer 0:c5e2f793b59a 1623 #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
screamer 0:c5e2f793b59a 1624 /* AIPS1 */
screamer 0:c5e2f793b59a 1625 #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
screamer 0:c5e2f793b59a 1626 #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
screamer 0:c5e2f793b59a 1627 #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
screamer 0:c5e2f793b59a 1628 #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
screamer 0:c5e2f793b59a 1629 #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
screamer 0:c5e2f793b59a 1630 #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
screamer 0:c5e2f793b59a 1631 #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
screamer 0:c5e2f793b59a 1632 #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
screamer 0:c5e2f793b59a 1633 #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
screamer 0:c5e2f793b59a 1634 #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
screamer 0:c5e2f793b59a 1635 #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
screamer 0:c5e2f793b59a 1636 #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
screamer 0:c5e2f793b59a 1637 #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
screamer 0:c5e2f793b59a 1638 #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
screamer 0:c5e2f793b59a 1639 #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
screamer 0:c5e2f793b59a 1640 #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
screamer 0:c5e2f793b59a 1641 #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
screamer 0:c5e2f793b59a 1642 #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
screamer 0:c5e2f793b59a 1643
screamer 0:c5e2f793b59a 1644 /*!
screamer 0:c5e2f793b59a 1645 * @}
screamer 0:c5e2f793b59a 1646 */ /* end of group AIPS_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 1647
screamer 0:c5e2f793b59a 1648
screamer 0:c5e2f793b59a 1649 /*!
screamer 0:c5e2f793b59a 1650 * @}
screamer 0:c5e2f793b59a 1651 */ /* end of group AIPS_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 1652
screamer 0:c5e2f793b59a 1653
screamer 0:c5e2f793b59a 1654 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 1655 -- AXBS Peripheral Access Layer
screamer 0:c5e2f793b59a 1656 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 1657
screamer 0:c5e2f793b59a 1658 /*!
screamer 0:c5e2f793b59a 1659 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
screamer 0:c5e2f793b59a 1660 * @{
screamer 0:c5e2f793b59a 1661 */
screamer 0:c5e2f793b59a 1662
screamer 0:c5e2f793b59a 1663 /** AXBS - Register Layout Typedef */
screamer 0:c5e2f793b59a 1664 typedef struct {
screamer 0:c5e2f793b59a 1665 struct { /* offset: 0x0, array step: 0x100 */
screamer 0:c5e2f793b59a 1666 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
screamer 0:c5e2f793b59a 1667 uint8_t RESERVED_0[12];
screamer 0:c5e2f793b59a 1668 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
screamer 0:c5e2f793b59a 1669 uint8_t RESERVED_1[236];
screamer 0:c5e2f793b59a 1670 } SLAVE[5];
screamer 0:c5e2f793b59a 1671 uint8_t RESERVED_0[768];
screamer 0:c5e2f793b59a 1672 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
screamer 0:c5e2f793b59a 1673 uint8_t RESERVED_1[252];
screamer 0:c5e2f793b59a 1674 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
screamer 0:c5e2f793b59a 1675 uint8_t RESERVED_2[252];
screamer 0:c5e2f793b59a 1676 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
screamer 0:c5e2f793b59a 1677 uint8_t RESERVED_3[252];
screamer 0:c5e2f793b59a 1678 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
screamer 0:c5e2f793b59a 1679 uint8_t RESERVED_4[252];
screamer 0:c5e2f793b59a 1680 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
screamer 0:c5e2f793b59a 1681 uint8_t RESERVED_5[252];
screamer 0:c5e2f793b59a 1682 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
screamer 0:c5e2f793b59a 1683 } AXBS_Type, *AXBS_MemMapPtr;
screamer 0:c5e2f793b59a 1684
screamer 0:c5e2f793b59a 1685 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 1686 -- AXBS - Register accessor macros
screamer 0:c5e2f793b59a 1687 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 1688
screamer 0:c5e2f793b59a 1689 /*!
screamer 0:c5e2f793b59a 1690 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
screamer 0:c5e2f793b59a 1691 * @{
screamer 0:c5e2f793b59a 1692 */
screamer 0:c5e2f793b59a 1693
screamer 0:c5e2f793b59a 1694
screamer 0:c5e2f793b59a 1695 /* AXBS - Register accessors */
screamer 0:c5e2f793b59a 1696 #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
screamer 0:c5e2f793b59a 1697 #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
screamer 0:c5e2f793b59a 1698 #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
screamer 0:c5e2f793b59a 1699 #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
screamer 0:c5e2f793b59a 1700 #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
screamer 0:c5e2f793b59a 1701 #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
screamer 0:c5e2f793b59a 1702 #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
screamer 0:c5e2f793b59a 1703 #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
screamer 0:c5e2f793b59a 1704
screamer 0:c5e2f793b59a 1705 /*!
screamer 0:c5e2f793b59a 1706 * @}
screamer 0:c5e2f793b59a 1707 */ /* end of group AXBS_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 1708
screamer 0:c5e2f793b59a 1709
screamer 0:c5e2f793b59a 1710 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 1711 -- AXBS Register Masks
screamer 0:c5e2f793b59a 1712 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 1713
screamer 0:c5e2f793b59a 1714 /*!
screamer 0:c5e2f793b59a 1715 * @addtogroup AXBS_Register_Masks AXBS Register Masks
screamer 0:c5e2f793b59a 1716 * @{
screamer 0:c5e2f793b59a 1717 */
screamer 0:c5e2f793b59a 1718
screamer 0:c5e2f793b59a 1719 /* PRS Bit Fields */
screamer 0:c5e2f793b59a 1720 #define AXBS_PRS_M0_MASK 0x7u
screamer 0:c5e2f793b59a 1721 #define AXBS_PRS_M0_SHIFT 0
screamer 0:c5e2f793b59a 1722 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
screamer 0:c5e2f793b59a 1723 #define AXBS_PRS_M1_MASK 0x70u
screamer 0:c5e2f793b59a 1724 #define AXBS_PRS_M1_SHIFT 4
screamer 0:c5e2f793b59a 1725 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
screamer 0:c5e2f793b59a 1726 #define AXBS_PRS_M2_MASK 0x700u
screamer 0:c5e2f793b59a 1727 #define AXBS_PRS_M2_SHIFT 8
screamer 0:c5e2f793b59a 1728 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
screamer 0:c5e2f793b59a 1729 #define AXBS_PRS_M3_MASK 0x7000u
screamer 0:c5e2f793b59a 1730 #define AXBS_PRS_M3_SHIFT 12
screamer 0:c5e2f793b59a 1731 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
screamer 0:c5e2f793b59a 1732 #define AXBS_PRS_M4_MASK 0x70000u
screamer 0:c5e2f793b59a 1733 #define AXBS_PRS_M4_SHIFT 16
screamer 0:c5e2f793b59a 1734 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
screamer 0:c5e2f793b59a 1735 #define AXBS_PRS_M5_MASK 0x700000u
screamer 0:c5e2f793b59a 1736 #define AXBS_PRS_M5_SHIFT 20
screamer 0:c5e2f793b59a 1737 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
screamer 0:c5e2f793b59a 1738 /* CRS Bit Fields */
screamer 0:c5e2f793b59a 1739 #define AXBS_CRS_PARK_MASK 0x7u
screamer 0:c5e2f793b59a 1740 #define AXBS_CRS_PARK_SHIFT 0
screamer 0:c5e2f793b59a 1741 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
screamer 0:c5e2f793b59a 1742 #define AXBS_CRS_PCTL_MASK 0x30u
screamer 0:c5e2f793b59a 1743 #define AXBS_CRS_PCTL_SHIFT 4
screamer 0:c5e2f793b59a 1744 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
screamer 0:c5e2f793b59a 1745 #define AXBS_CRS_ARB_MASK 0x300u
screamer 0:c5e2f793b59a 1746 #define AXBS_CRS_ARB_SHIFT 8
screamer 0:c5e2f793b59a 1747 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
screamer 0:c5e2f793b59a 1748 #define AXBS_CRS_HLP_MASK 0x40000000u
screamer 0:c5e2f793b59a 1749 #define AXBS_CRS_HLP_SHIFT 30
screamer 0:c5e2f793b59a 1750 #define AXBS_CRS_RO_MASK 0x80000000u
screamer 0:c5e2f793b59a 1751 #define AXBS_CRS_RO_SHIFT 31
screamer 0:c5e2f793b59a 1752 /* MGPCR0 Bit Fields */
screamer 0:c5e2f793b59a 1753 #define AXBS_MGPCR0_AULB_MASK 0x7u
screamer 0:c5e2f793b59a 1754 #define AXBS_MGPCR0_AULB_SHIFT 0
screamer 0:c5e2f793b59a 1755 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
screamer 0:c5e2f793b59a 1756 /* MGPCR1 Bit Fields */
screamer 0:c5e2f793b59a 1757 #define AXBS_MGPCR1_AULB_MASK 0x7u
screamer 0:c5e2f793b59a 1758 #define AXBS_MGPCR1_AULB_SHIFT 0
screamer 0:c5e2f793b59a 1759 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
screamer 0:c5e2f793b59a 1760 /* MGPCR2 Bit Fields */
screamer 0:c5e2f793b59a 1761 #define AXBS_MGPCR2_AULB_MASK 0x7u
screamer 0:c5e2f793b59a 1762 #define AXBS_MGPCR2_AULB_SHIFT 0
screamer 0:c5e2f793b59a 1763 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
screamer 0:c5e2f793b59a 1764 /* MGPCR3 Bit Fields */
screamer 0:c5e2f793b59a 1765 #define AXBS_MGPCR3_AULB_MASK 0x7u
screamer 0:c5e2f793b59a 1766 #define AXBS_MGPCR3_AULB_SHIFT 0
screamer 0:c5e2f793b59a 1767 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
screamer 0:c5e2f793b59a 1768 /* MGPCR4 Bit Fields */
screamer 0:c5e2f793b59a 1769 #define AXBS_MGPCR4_AULB_MASK 0x7u
screamer 0:c5e2f793b59a 1770 #define AXBS_MGPCR4_AULB_SHIFT 0
screamer 0:c5e2f793b59a 1771 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
screamer 0:c5e2f793b59a 1772 /* MGPCR5 Bit Fields */
screamer 0:c5e2f793b59a 1773 #define AXBS_MGPCR5_AULB_MASK 0x7u
screamer 0:c5e2f793b59a 1774 #define AXBS_MGPCR5_AULB_SHIFT 0
screamer 0:c5e2f793b59a 1775 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
screamer 0:c5e2f793b59a 1776
screamer 0:c5e2f793b59a 1777 /*!
screamer 0:c5e2f793b59a 1778 * @}
screamer 0:c5e2f793b59a 1779 */ /* end of group AXBS_Register_Masks */
screamer 0:c5e2f793b59a 1780
screamer 0:c5e2f793b59a 1781
screamer 0:c5e2f793b59a 1782 /* AXBS - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 1783 /** Peripheral AXBS base address */
screamer 0:c5e2f793b59a 1784 #define AXBS_BASE (0x40004000u)
screamer 0:c5e2f793b59a 1785 /** Peripheral AXBS base pointer */
screamer 0:c5e2f793b59a 1786 #define AXBS ((AXBS_Type *)AXBS_BASE)
screamer 0:c5e2f793b59a 1787 #define AXBS_BASE_PTR (AXBS)
screamer 0:c5e2f793b59a 1788 /** Array initializer of AXBS peripheral base addresses */
screamer 0:c5e2f793b59a 1789 #define AXBS_BASE_ADDRS { AXBS_BASE }
screamer 0:c5e2f793b59a 1790 /** Array initializer of AXBS peripheral base pointers */
screamer 0:c5e2f793b59a 1791 #define AXBS_BASE_PTRS { AXBS }
screamer 0:c5e2f793b59a 1792
screamer 0:c5e2f793b59a 1793 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 1794 -- AXBS - Register accessor macros
screamer 0:c5e2f793b59a 1795 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 1796
screamer 0:c5e2f793b59a 1797 /*!
screamer 0:c5e2f793b59a 1798 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
screamer 0:c5e2f793b59a 1799 * @{
screamer 0:c5e2f793b59a 1800 */
screamer 0:c5e2f793b59a 1801
screamer 0:c5e2f793b59a 1802
screamer 0:c5e2f793b59a 1803 /* AXBS - Register instance definitions */
screamer 0:c5e2f793b59a 1804 /* AXBS */
screamer 0:c5e2f793b59a 1805 #define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
screamer 0:c5e2f793b59a 1806 #define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
screamer 0:c5e2f793b59a 1807 #define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
screamer 0:c5e2f793b59a 1808 #define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
screamer 0:c5e2f793b59a 1809 #define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
screamer 0:c5e2f793b59a 1810 #define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
screamer 0:c5e2f793b59a 1811 #define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
screamer 0:c5e2f793b59a 1812 #define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
screamer 0:c5e2f793b59a 1813 #define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
screamer 0:c5e2f793b59a 1814 #define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
screamer 0:c5e2f793b59a 1815 #define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
screamer 0:c5e2f793b59a 1816 #define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
screamer 0:c5e2f793b59a 1817 #define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
screamer 0:c5e2f793b59a 1818 #define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
screamer 0:c5e2f793b59a 1819 #define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
screamer 0:c5e2f793b59a 1820 #define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
screamer 0:c5e2f793b59a 1821
screamer 0:c5e2f793b59a 1822 /* AXBS - Register array accessors */
screamer 0:c5e2f793b59a 1823 #define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
screamer 0:c5e2f793b59a 1824 #define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
screamer 0:c5e2f793b59a 1825
screamer 0:c5e2f793b59a 1826 /*!
screamer 0:c5e2f793b59a 1827 * @}
screamer 0:c5e2f793b59a 1828 */ /* end of group AXBS_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 1829
screamer 0:c5e2f793b59a 1830
screamer 0:c5e2f793b59a 1831 /*!
screamer 0:c5e2f793b59a 1832 * @}
screamer 0:c5e2f793b59a 1833 */ /* end of group AXBS_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 1834
screamer 0:c5e2f793b59a 1835
screamer 0:c5e2f793b59a 1836 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 1837 -- CAN Peripheral Access Layer
screamer 0:c5e2f793b59a 1838 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 1839
screamer 0:c5e2f793b59a 1840 /*!
screamer 0:c5e2f793b59a 1841 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
screamer 0:c5e2f793b59a 1842 * @{
screamer 0:c5e2f793b59a 1843 */
screamer 0:c5e2f793b59a 1844
screamer 0:c5e2f793b59a 1845 /** CAN - Register Layout Typedef */
screamer 0:c5e2f793b59a 1846 typedef struct {
screamer 0:c5e2f793b59a 1847 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
screamer 0:c5e2f793b59a 1848 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
screamer 0:c5e2f793b59a 1849 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
screamer 0:c5e2f793b59a 1850 uint8_t RESERVED_0[4];
screamer 0:c5e2f793b59a 1851 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
screamer 0:c5e2f793b59a 1852 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
screamer 0:c5e2f793b59a 1853 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
screamer 0:c5e2f793b59a 1854 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
screamer 0:c5e2f793b59a 1855 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
screamer 0:c5e2f793b59a 1856 uint8_t RESERVED_1[4];
screamer 0:c5e2f793b59a 1857 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
screamer 0:c5e2f793b59a 1858 uint8_t RESERVED_2[4];
screamer 0:c5e2f793b59a 1859 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
screamer 0:c5e2f793b59a 1860 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
screamer 0:c5e2f793b59a 1861 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
screamer 0:c5e2f793b59a 1862 uint8_t RESERVED_3[8];
screamer 0:c5e2f793b59a 1863 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
screamer 0:c5e2f793b59a 1864 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
screamer 0:c5e2f793b59a 1865 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
screamer 0:c5e2f793b59a 1866 uint8_t RESERVED_4[48];
screamer 0:c5e2f793b59a 1867 struct { /* offset: 0x80, array step: 0x10 */
screamer 0:c5e2f793b59a 1868 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
screamer 0:c5e2f793b59a 1869 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
screamer 0:c5e2f793b59a 1870 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
screamer 0:c5e2f793b59a 1871 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
screamer 0:c5e2f793b59a 1872 } MB[16];
screamer 0:c5e2f793b59a 1873 uint8_t RESERVED_5[1792];
screamer 0:c5e2f793b59a 1874 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
screamer 0:c5e2f793b59a 1875 } CAN_Type, *CAN_MemMapPtr;
screamer 0:c5e2f793b59a 1876
screamer 0:c5e2f793b59a 1877 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 1878 -- CAN - Register accessor macros
screamer 0:c5e2f793b59a 1879 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 1880
screamer 0:c5e2f793b59a 1881 /*!
screamer 0:c5e2f793b59a 1882 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
screamer 0:c5e2f793b59a 1883 * @{
screamer 0:c5e2f793b59a 1884 */
screamer 0:c5e2f793b59a 1885
screamer 0:c5e2f793b59a 1886
screamer 0:c5e2f793b59a 1887 /* CAN - Register accessors */
screamer 0:c5e2f793b59a 1888 #define CAN_MCR_REG(base) ((base)->MCR)
screamer 0:c5e2f793b59a 1889 #define CAN_CTRL1_REG(base) ((base)->CTRL1)
screamer 0:c5e2f793b59a 1890 #define CAN_TIMER_REG(base) ((base)->TIMER)
screamer 0:c5e2f793b59a 1891 #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
screamer 0:c5e2f793b59a 1892 #define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
screamer 0:c5e2f793b59a 1893 #define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
screamer 0:c5e2f793b59a 1894 #define CAN_ECR_REG(base) ((base)->ECR)
screamer 0:c5e2f793b59a 1895 #define CAN_ESR1_REG(base) ((base)->ESR1)
screamer 0:c5e2f793b59a 1896 #define CAN_IMASK1_REG(base) ((base)->IMASK1)
screamer 0:c5e2f793b59a 1897 #define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
screamer 0:c5e2f793b59a 1898 #define CAN_CTRL2_REG(base) ((base)->CTRL2)
screamer 0:c5e2f793b59a 1899 #define CAN_ESR2_REG(base) ((base)->ESR2)
screamer 0:c5e2f793b59a 1900 #define CAN_CRCR_REG(base) ((base)->CRCR)
screamer 0:c5e2f793b59a 1901 #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
screamer 0:c5e2f793b59a 1902 #define CAN_RXFIR_REG(base) ((base)->RXFIR)
screamer 0:c5e2f793b59a 1903 #define CAN_CS_REG(base,index) ((base)->MB[index].CS)
screamer 0:c5e2f793b59a 1904 #define CAN_ID_REG(base,index) ((base)->MB[index].ID)
screamer 0:c5e2f793b59a 1905 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
screamer 0:c5e2f793b59a 1906 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
screamer 0:c5e2f793b59a 1907 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
screamer 0:c5e2f793b59a 1908
screamer 0:c5e2f793b59a 1909 /*!
screamer 0:c5e2f793b59a 1910 * @}
screamer 0:c5e2f793b59a 1911 */ /* end of group CAN_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 1912
screamer 0:c5e2f793b59a 1913
screamer 0:c5e2f793b59a 1914 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 1915 -- CAN Register Masks
screamer 0:c5e2f793b59a 1916 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 1917
screamer 0:c5e2f793b59a 1918 /*!
screamer 0:c5e2f793b59a 1919 * @addtogroup CAN_Register_Masks CAN Register Masks
screamer 0:c5e2f793b59a 1920 * @{
screamer 0:c5e2f793b59a 1921 */
screamer 0:c5e2f793b59a 1922
screamer 0:c5e2f793b59a 1923 /* MCR Bit Fields */
screamer 0:c5e2f793b59a 1924 #define CAN_MCR_MAXMB_MASK 0x7Fu
screamer 0:c5e2f793b59a 1925 #define CAN_MCR_MAXMB_SHIFT 0
screamer 0:c5e2f793b59a 1926 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
screamer 0:c5e2f793b59a 1927 #define CAN_MCR_IDAM_MASK 0x300u
screamer 0:c5e2f793b59a 1928 #define CAN_MCR_IDAM_SHIFT 8
screamer 0:c5e2f793b59a 1929 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
screamer 0:c5e2f793b59a 1930 #define CAN_MCR_AEN_MASK 0x1000u
screamer 0:c5e2f793b59a 1931 #define CAN_MCR_AEN_SHIFT 12
screamer 0:c5e2f793b59a 1932 #define CAN_MCR_LPRIOEN_MASK 0x2000u
screamer 0:c5e2f793b59a 1933 #define CAN_MCR_LPRIOEN_SHIFT 13
screamer 0:c5e2f793b59a 1934 #define CAN_MCR_IRMQ_MASK 0x10000u
screamer 0:c5e2f793b59a 1935 #define CAN_MCR_IRMQ_SHIFT 16
screamer 0:c5e2f793b59a 1936 #define CAN_MCR_SRXDIS_MASK 0x20000u
screamer 0:c5e2f793b59a 1937 #define CAN_MCR_SRXDIS_SHIFT 17
screamer 0:c5e2f793b59a 1938 #define CAN_MCR_WAKSRC_MASK 0x80000u
screamer 0:c5e2f793b59a 1939 #define CAN_MCR_WAKSRC_SHIFT 19
screamer 0:c5e2f793b59a 1940 #define CAN_MCR_LPMACK_MASK 0x100000u
screamer 0:c5e2f793b59a 1941 #define CAN_MCR_LPMACK_SHIFT 20
screamer 0:c5e2f793b59a 1942 #define CAN_MCR_WRNEN_MASK 0x200000u
screamer 0:c5e2f793b59a 1943 #define CAN_MCR_WRNEN_SHIFT 21
screamer 0:c5e2f793b59a 1944 #define CAN_MCR_SLFWAK_MASK 0x400000u
screamer 0:c5e2f793b59a 1945 #define CAN_MCR_SLFWAK_SHIFT 22
screamer 0:c5e2f793b59a 1946 #define CAN_MCR_SUPV_MASK 0x800000u
screamer 0:c5e2f793b59a 1947 #define CAN_MCR_SUPV_SHIFT 23
screamer 0:c5e2f793b59a 1948 #define CAN_MCR_FRZACK_MASK 0x1000000u
screamer 0:c5e2f793b59a 1949 #define CAN_MCR_FRZACK_SHIFT 24
screamer 0:c5e2f793b59a 1950 #define CAN_MCR_SOFTRST_MASK 0x2000000u
screamer 0:c5e2f793b59a 1951 #define CAN_MCR_SOFTRST_SHIFT 25
screamer 0:c5e2f793b59a 1952 #define CAN_MCR_WAKMSK_MASK 0x4000000u
screamer 0:c5e2f793b59a 1953 #define CAN_MCR_WAKMSK_SHIFT 26
screamer 0:c5e2f793b59a 1954 #define CAN_MCR_NOTRDY_MASK 0x8000000u
screamer 0:c5e2f793b59a 1955 #define CAN_MCR_NOTRDY_SHIFT 27
screamer 0:c5e2f793b59a 1956 #define CAN_MCR_HALT_MASK 0x10000000u
screamer 0:c5e2f793b59a 1957 #define CAN_MCR_HALT_SHIFT 28
screamer 0:c5e2f793b59a 1958 #define CAN_MCR_RFEN_MASK 0x20000000u
screamer 0:c5e2f793b59a 1959 #define CAN_MCR_RFEN_SHIFT 29
screamer 0:c5e2f793b59a 1960 #define CAN_MCR_FRZ_MASK 0x40000000u
screamer 0:c5e2f793b59a 1961 #define CAN_MCR_FRZ_SHIFT 30
screamer 0:c5e2f793b59a 1962 #define CAN_MCR_MDIS_MASK 0x80000000u
screamer 0:c5e2f793b59a 1963 #define CAN_MCR_MDIS_SHIFT 31
screamer 0:c5e2f793b59a 1964 /* CTRL1 Bit Fields */
screamer 0:c5e2f793b59a 1965 #define CAN_CTRL1_PROPSEG_MASK 0x7u
screamer 0:c5e2f793b59a 1966 #define CAN_CTRL1_PROPSEG_SHIFT 0
screamer 0:c5e2f793b59a 1967 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
screamer 0:c5e2f793b59a 1968 #define CAN_CTRL1_LOM_MASK 0x8u
screamer 0:c5e2f793b59a 1969 #define CAN_CTRL1_LOM_SHIFT 3
screamer 0:c5e2f793b59a 1970 #define CAN_CTRL1_LBUF_MASK 0x10u
screamer 0:c5e2f793b59a 1971 #define CAN_CTRL1_LBUF_SHIFT 4
screamer 0:c5e2f793b59a 1972 #define CAN_CTRL1_TSYN_MASK 0x20u
screamer 0:c5e2f793b59a 1973 #define CAN_CTRL1_TSYN_SHIFT 5
screamer 0:c5e2f793b59a 1974 #define CAN_CTRL1_BOFFREC_MASK 0x40u
screamer 0:c5e2f793b59a 1975 #define CAN_CTRL1_BOFFREC_SHIFT 6
screamer 0:c5e2f793b59a 1976 #define CAN_CTRL1_SMP_MASK 0x80u
screamer 0:c5e2f793b59a 1977 #define CAN_CTRL1_SMP_SHIFT 7
screamer 0:c5e2f793b59a 1978 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
screamer 0:c5e2f793b59a 1979 #define CAN_CTRL1_RWRNMSK_SHIFT 10
screamer 0:c5e2f793b59a 1980 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
screamer 0:c5e2f793b59a 1981 #define CAN_CTRL1_TWRNMSK_SHIFT 11
screamer 0:c5e2f793b59a 1982 #define CAN_CTRL1_LPB_MASK 0x1000u
screamer 0:c5e2f793b59a 1983 #define CAN_CTRL1_LPB_SHIFT 12
screamer 0:c5e2f793b59a 1984 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
screamer 0:c5e2f793b59a 1985 #define CAN_CTRL1_CLKSRC_SHIFT 13
screamer 0:c5e2f793b59a 1986 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
screamer 0:c5e2f793b59a 1987 #define CAN_CTRL1_ERRMSK_SHIFT 14
screamer 0:c5e2f793b59a 1988 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
screamer 0:c5e2f793b59a 1989 #define CAN_CTRL1_BOFFMSK_SHIFT 15
screamer 0:c5e2f793b59a 1990 #define CAN_CTRL1_PSEG2_MASK 0x70000u
screamer 0:c5e2f793b59a 1991 #define CAN_CTRL1_PSEG2_SHIFT 16
screamer 0:c5e2f793b59a 1992 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
screamer 0:c5e2f793b59a 1993 #define CAN_CTRL1_PSEG1_MASK 0x380000u
screamer 0:c5e2f793b59a 1994 #define CAN_CTRL1_PSEG1_SHIFT 19
screamer 0:c5e2f793b59a 1995 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
screamer 0:c5e2f793b59a 1996 #define CAN_CTRL1_RJW_MASK 0xC00000u
screamer 0:c5e2f793b59a 1997 #define CAN_CTRL1_RJW_SHIFT 22
screamer 0:c5e2f793b59a 1998 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
screamer 0:c5e2f793b59a 1999 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
screamer 0:c5e2f793b59a 2000 #define CAN_CTRL1_PRESDIV_SHIFT 24
screamer 0:c5e2f793b59a 2001 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
screamer 0:c5e2f793b59a 2002 /* TIMER Bit Fields */
screamer 0:c5e2f793b59a 2003 #define CAN_TIMER_TIMER_MASK 0xFFFFu
screamer 0:c5e2f793b59a 2004 #define CAN_TIMER_TIMER_SHIFT 0
screamer 0:c5e2f793b59a 2005 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
screamer 0:c5e2f793b59a 2006 /* RXMGMASK Bit Fields */
screamer 0:c5e2f793b59a 2007 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2008 #define CAN_RXMGMASK_MG_SHIFT 0
screamer 0:c5e2f793b59a 2009 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
screamer 0:c5e2f793b59a 2010 /* RX14MASK Bit Fields */
screamer 0:c5e2f793b59a 2011 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2012 #define CAN_RX14MASK_RX14M_SHIFT 0
screamer 0:c5e2f793b59a 2013 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
screamer 0:c5e2f793b59a 2014 /* RX15MASK Bit Fields */
screamer 0:c5e2f793b59a 2015 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2016 #define CAN_RX15MASK_RX15M_SHIFT 0
screamer 0:c5e2f793b59a 2017 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
screamer 0:c5e2f793b59a 2018 /* ECR Bit Fields */
screamer 0:c5e2f793b59a 2019 #define CAN_ECR_TXERRCNT_MASK 0xFFu
screamer 0:c5e2f793b59a 2020 #define CAN_ECR_TXERRCNT_SHIFT 0
screamer 0:c5e2f793b59a 2021 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
screamer 0:c5e2f793b59a 2022 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
screamer 0:c5e2f793b59a 2023 #define CAN_ECR_RXERRCNT_SHIFT 8
screamer 0:c5e2f793b59a 2024 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
screamer 0:c5e2f793b59a 2025 /* ESR1 Bit Fields */
screamer 0:c5e2f793b59a 2026 #define CAN_ESR1_WAKINT_MASK 0x1u
screamer 0:c5e2f793b59a 2027 #define CAN_ESR1_WAKINT_SHIFT 0
screamer 0:c5e2f793b59a 2028 #define CAN_ESR1_ERRINT_MASK 0x2u
screamer 0:c5e2f793b59a 2029 #define CAN_ESR1_ERRINT_SHIFT 1
screamer 0:c5e2f793b59a 2030 #define CAN_ESR1_BOFFINT_MASK 0x4u
screamer 0:c5e2f793b59a 2031 #define CAN_ESR1_BOFFINT_SHIFT 2
screamer 0:c5e2f793b59a 2032 #define CAN_ESR1_RX_MASK 0x8u
screamer 0:c5e2f793b59a 2033 #define CAN_ESR1_RX_SHIFT 3
screamer 0:c5e2f793b59a 2034 #define CAN_ESR1_FLTCONF_MASK 0x30u
screamer 0:c5e2f793b59a 2035 #define CAN_ESR1_FLTCONF_SHIFT 4
screamer 0:c5e2f793b59a 2036 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
screamer 0:c5e2f793b59a 2037 #define CAN_ESR1_TX_MASK 0x40u
screamer 0:c5e2f793b59a 2038 #define CAN_ESR1_TX_SHIFT 6
screamer 0:c5e2f793b59a 2039 #define CAN_ESR1_IDLE_MASK 0x80u
screamer 0:c5e2f793b59a 2040 #define CAN_ESR1_IDLE_SHIFT 7
screamer 0:c5e2f793b59a 2041 #define CAN_ESR1_RXWRN_MASK 0x100u
screamer 0:c5e2f793b59a 2042 #define CAN_ESR1_RXWRN_SHIFT 8
screamer 0:c5e2f793b59a 2043 #define CAN_ESR1_TXWRN_MASK 0x200u
screamer 0:c5e2f793b59a 2044 #define CAN_ESR1_TXWRN_SHIFT 9
screamer 0:c5e2f793b59a 2045 #define CAN_ESR1_STFERR_MASK 0x400u
screamer 0:c5e2f793b59a 2046 #define CAN_ESR1_STFERR_SHIFT 10
screamer 0:c5e2f793b59a 2047 #define CAN_ESR1_FRMERR_MASK 0x800u
screamer 0:c5e2f793b59a 2048 #define CAN_ESR1_FRMERR_SHIFT 11
screamer 0:c5e2f793b59a 2049 #define CAN_ESR1_CRCERR_MASK 0x1000u
screamer 0:c5e2f793b59a 2050 #define CAN_ESR1_CRCERR_SHIFT 12
screamer 0:c5e2f793b59a 2051 #define CAN_ESR1_ACKERR_MASK 0x2000u
screamer 0:c5e2f793b59a 2052 #define CAN_ESR1_ACKERR_SHIFT 13
screamer 0:c5e2f793b59a 2053 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
screamer 0:c5e2f793b59a 2054 #define CAN_ESR1_BIT0ERR_SHIFT 14
screamer 0:c5e2f793b59a 2055 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
screamer 0:c5e2f793b59a 2056 #define CAN_ESR1_BIT1ERR_SHIFT 15
screamer 0:c5e2f793b59a 2057 #define CAN_ESR1_RWRNINT_MASK 0x10000u
screamer 0:c5e2f793b59a 2058 #define CAN_ESR1_RWRNINT_SHIFT 16
screamer 0:c5e2f793b59a 2059 #define CAN_ESR1_TWRNINT_MASK 0x20000u
screamer 0:c5e2f793b59a 2060 #define CAN_ESR1_TWRNINT_SHIFT 17
screamer 0:c5e2f793b59a 2061 #define CAN_ESR1_SYNCH_MASK 0x40000u
screamer 0:c5e2f793b59a 2062 #define CAN_ESR1_SYNCH_SHIFT 18
screamer 0:c5e2f793b59a 2063 /* IMASK1 Bit Fields */
screamer 0:c5e2f793b59a 2064 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2065 #define CAN_IMASK1_BUFLM_SHIFT 0
screamer 0:c5e2f793b59a 2066 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
screamer 0:c5e2f793b59a 2067 /* IFLAG1 Bit Fields */
screamer 0:c5e2f793b59a 2068 #define CAN_IFLAG1_BUF0I_MASK 0x1u
screamer 0:c5e2f793b59a 2069 #define CAN_IFLAG1_BUF0I_SHIFT 0
screamer 0:c5e2f793b59a 2070 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
screamer 0:c5e2f793b59a 2071 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1
screamer 0:c5e2f793b59a 2072 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
screamer 0:c5e2f793b59a 2073 #define CAN_IFLAG1_BUF5I_MASK 0x20u
screamer 0:c5e2f793b59a 2074 #define CAN_IFLAG1_BUF5I_SHIFT 5
screamer 0:c5e2f793b59a 2075 #define CAN_IFLAG1_BUF6I_MASK 0x40u
screamer 0:c5e2f793b59a 2076 #define CAN_IFLAG1_BUF6I_SHIFT 6
screamer 0:c5e2f793b59a 2077 #define CAN_IFLAG1_BUF7I_MASK 0x80u
screamer 0:c5e2f793b59a 2078 #define CAN_IFLAG1_BUF7I_SHIFT 7
screamer 0:c5e2f793b59a 2079 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
screamer 0:c5e2f793b59a 2080 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
screamer 0:c5e2f793b59a 2081 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
screamer 0:c5e2f793b59a 2082 /* CTRL2 Bit Fields */
screamer 0:c5e2f793b59a 2083 #define CAN_CTRL2_EACEN_MASK 0x10000u
screamer 0:c5e2f793b59a 2084 #define CAN_CTRL2_EACEN_SHIFT 16
screamer 0:c5e2f793b59a 2085 #define CAN_CTRL2_RRS_MASK 0x20000u
screamer 0:c5e2f793b59a 2086 #define CAN_CTRL2_RRS_SHIFT 17
screamer 0:c5e2f793b59a 2087 #define CAN_CTRL2_MRP_MASK 0x40000u
screamer 0:c5e2f793b59a 2088 #define CAN_CTRL2_MRP_SHIFT 18
screamer 0:c5e2f793b59a 2089 #define CAN_CTRL2_TASD_MASK 0xF80000u
screamer 0:c5e2f793b59a 2090 #define CAN_CTRL2_TASD_SHIFT 19
screamer 0:c5e2f793b59a 2091 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
screamer 0:c5e2f793b59a 2092 #define CAN_CTRL2_RFFN_MASK 0xF000000u
screamer 0:c5e2f793b59a 2093 #define CAN_CTRL2_RFFN_SHIFT 24
screamer 0:c5e2f793b59a 2094 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
screamer 0:c5e2f793b59a 2095 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
screamer 0:c5e2f793b59a 2096 #define CAN_CTRL2_WRMFRZ_SHIFT 28
screamer 0:c5e2f793b59a 2097 /* ESR2 Bit Fields */
screamer 0:c5e2f793b59a 2098 #define CAN_ESR2_IMB_MASK 0x2000u
screamer 0:c5e2f793b59a 2099 #define CAN_ESR2_IMB_SHIFT 13
screamer 0:c5e2f793b59a 2100 #define CAN_ESR2_VPS_MASK 0x4000u
screamer 0:c5e2f793b59a 2101 #define CAN_ESR2_VPS_SHIFT 14
screamer 0:c5e2f793b59a 2102 #define CAN_ESR2_LPTM_MASK 0x7F0000u
screamer 0:c5e2f793b59a 2103 #define CAN_ESR2_LPTM_SHIFT 16
screamer 0:c5e2f793b59a 2104 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
screamer 0:c5e2f793b59a 2105 /* CRCR Bit Fields */
screamer 0:c5e2f793b59a 2106 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
screamer 0:c5e2f793b59a 2107 #define CAN_CRCR_TXCRC_SHIFT 0
screamer 0:c5e2f793b59a 2108 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
screamer 0:c5e2f793b59a 2109 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
screamer 0:c5e2f793b59a 2110 #define CAN_CRCR_MBCRC_SHIFT 16
screamer 0:c5e2f793b59a 2111 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
screamer 0:c5e2f793b59a 2112 /* RXFGMASK Bit Fields */
screamer 0:c5e2f793b59a 2113 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2114 #define CAN_RXFGMASK_FGM_SHIFT 0
screamer 0:c5e2f793b59a 2115 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
screamer 0:c5e2f793b59a 2116 /* RXFIR Bit Fields */
screamer 0:c5e2f793b59a 2117 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
screamer 0:c5e2f793b59a 2118 #define CAN_RXFIR_IDHIT_SHIFT 0
screamer 0:c5e2f793b59a 2119 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
screamer 0:c5e2f793b59a 2120 /* CS Bit Fields */
screamer 0:c5e2f793b59a 2121 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
screamer 0:c5e2f793b59a 2122 #define CAN_CS_TIME_STAMP_SHIFT 0
screamer 0:c5e2f793b59a 2123 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
screamer 0:c5e2f793b59a 2124 #define CAN_CS_DLC_MASK 0xF0000u
screamer 0:c5e2f793b59a 2125 #define CAN_CS_DLC_SHIFT 16
screamer 0:c5e2f793b59a 2126 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
screamer 0:c5e2f793b59a 2127 #define CAN_CS_RTR_MASK 0x100000u
screamer 0:c5e2f793b59a 2128 #define CAN_CS_RTR_SHIFT 20
screamer 0:c5e2f793b59a 2129 #define CAN_CS_IDE_MASK 0x200000u
screamer 0:c5e2f793b59a 2130 #define CAN_CS_IDE_SHIFT 21
screamer 0:c5e2f793b59a 2131 #define CAN_CS_SRR_MASK 0x400000u
screamer 0:c5e2f793b59a 2132 #define CAN_CS_SRR_SHIFT 22
screamer 0:c5e2f793b59a 2133 #define CAN_CS_CODE_MASK 0xF000000u
screamer 0:c5e2f793b59a 2134 #define CAN_CS_CODE_SHIFT 24
screamer 0:c5e2f793b59a 2135 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
screamer 0:c5e2f793b59a 2136 /* ID Bit Fields */
screamer 0:c5e2f793b59a 2137 #define CAN_ID_EXT_MASK 0x3FFFFu
screamer 0:c5e2f793b59a 2138 #define CAN_ID_EXT_SHIFT 0
screamer 0:c5e2f793b59a 2139 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
screamer 0:c5e2f793b59a 2140 #define CAN_ID_STD_MASK 0x1FFC0000u
screamer 0:c5e2f793b59a 2141 #define CAN_ID_STD_SHIFT 18
screamer 0:c5e2f793b59a 2142 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
screamer 0:c5e2f793b59a 2143 #define CAN_ID_PRIO_MASK 0xE0000000u
screamer 0:c5e2f793b59a 2144 #define CAN_ID_PRIO_SHIFT 29
screamer 0:c5e2f793b59a 2145 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
screamer 0:c5e2f793b59a 2146 /* WORD0 Bit Fields */
screamer 0:c5e2f793b59a 2147 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
screamer 0:c5e2f793b59a 2148 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
screamer 0:c5e2f793b59a 2149 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
screamer 0:c5e2f793b59a 2150 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
screamer 0:c5e2f793b59a 2151 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
screamer 0:c5e2f793b59a 2152 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
screamer 0:c5e2f793b59a 2153 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
screamer 0:c5e2f793b59a 2154 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
screamer 0:c5e2f793b59a 2155 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
screamer 0:c5e2f793b59a 2156 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
screamer 0:c5e2f793b59a 2157 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
screamer 0:c5e2f793b59a 2158 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
screamer 0:c5e2f793b59a 2159 /* WORD1 Bit Fields */
screamer 0:c5e2f793b59a 2160 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
screamer 0:c5e2f793b59a 2161 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
screamer 0:c5e2f793b59a 2162 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
screamer 0:c5e2f793b59a 2163 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
screamer 0:c5e2f793b59a 2164 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
screamer 0:c5e2f793b59a 2165 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
screamer 0:c5e2f793b59a 2166 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
screamer 0:c5e2f793b59a 2167 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
screamer 0:c5e2f793b59a 2168 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
screamer 0:c5e2f793b59a 2169 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
screamer 0:c5e2f793b59a 2170 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
screamer 0:c5e2f793b59a 2171 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
screamer 0:c5e2f793b59a 2172 /* RXIMR Bit Fields */
screamer 0:c5e2f793b59a 2173 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2174 #define CAN_RXIMR_MI_SHIFT 0
screamer 0:c5e2f793b59a 2175 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
screamer 0:c5e2f793b59a 2176
screamer 0:c5e2f793b59a 2177 /*!
screamer 0:c5e2f793b59a 2178 * @}
screamer 0:c5e2f793b59a 2179 */ /* end of group CAN_Register_Masks */
screamer 0:c5e2f793b59a 2180
screamer 0:c5e2f793b59a 2181
screamer 0:c5e2f793b59a 2182 /* CAN - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 2183 /** Peripheral CAN0 base address */
screamer 0:c5e2f793b59a 2184 #define CAN0_BASE (0x40024000u)
screamer 0:c5e2f793b59a 2185 /** Peripheral CAN0 base pointer */
screamer 0:c5e2f793b59a 2186 #define CAN0 ((CAN_Type *)CAN0_BASE)
screamer 0:c5e2f793b59a 2187 #define CAN0_BASE_PTR (CAN0)
screamer 0:c5e2f793b59a 2188 /** Array initializer of CAN peripheral base addresses */
screamer 0:c5e2f793b59a 2189 #define CAN_BASE_ADDRS { CAN0_BASE }
screamer 0:c5e2f793b59a 2190 /** Array initializer of CAN peripheral base pointers */
screamer 0:c5e2f793b59a 2191 #define CAN_BASE_PTRS { CAN0 }
screamer 0:c5e2f793b59a 2192 /** Interrupt vectors for the CAN peripheral type */
screamer 0:c5e2f793b59a 2193 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
screamer 0:c5e2f793b59a 2194 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
screamer 0:c5e2f793b59a 2195 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
screamer 0:c5e2f793b59a 2196 #define CAN_Error_IRQS { CAN0_Error_IRQn }
screamer 0:c5e2f793b59a 2197 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
screamer 0:c5e2f793b59a 2198 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
screamer 0:c5e2f793b59a 2199
screamer 0:c5e2f793b59a 2200 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 2201 -- CAN - Register accessor macros
screamer 0:c5e2f793b59a 2202 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 2203
screamer 0:c5e2f793b59a 2204 /*!
screamer 0:c5e2f793b59a 2205 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
screamer 0:c5e2f793b59a 2206 * @{
screamer 0:c5e2f793b59a 2207 */
screamer 0:c5e2f793b59a 2208
screamer 0:c5e2f793b59a 2209
screamer 0:c5e2f793b59a 2210 /* CAN - Register instance definitions */
screamer 0:c5e2f793b59a 2211 /* CAN0 */
screamer 0:c5e2f793b59a 2212 #define CAN0_MCR CAN_MCR_REG(CAN0)
screamer 0:c5e2f793b59a 2213 #define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
screamer 0:c5e2f793b59a 2214 #define CAN0_TIMER CAN_TIMER_REG(CAN0)
screamer 0:c5e2f793b59a 2215 #define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
screamer 0:c5e2f793b59a 2216 #define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
screamer 0:c5e2f793b59a 2217 #define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
screamer 0:c5e2f793b59a 2218 #define CAN0_ECR CAN_ECR_REG(CAN0)
screamer 0:c5e2f793b59a 2219 #define CAN0_ESR1 CAN_ESR1_REG(CAN0)
screamer 0:c5e2f793b59a 2220 #define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
screamer 0:c5e2f793b59a 2221 #define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
screamer 0:c5e2f793b59a 2222 #define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
screamer 0:c5e2f793b59a 2223 #define CAN0_ESR2 CAN_ESR2_REG(CAN0)
screamer 0:c5e2f793b59a 2224 #define CAN0_CRCR CAN_CRCR_REG(CAN0)
screamer 0:c5e2f793b59a 2225 #define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
screamer 0:c5e2f793b59a 2226 #define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
screamer 0:c5e2f793b59a 2227 #define CAN0_CS0 CAN_CS_REG(CAN0,0)
screamer 0:c5e2f793b59a 2228 #define CAN0_ID0 CAN_ID_REG(CAN0,0)
screamer 0:c5e2f793b59a 2229 #define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
screamer 0:c5e2f793b59a 2230 #define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
screamer 0:c5e2f793b59a 2231 #define CAN0_CS1 CAN_CS_REG(CAN0,1)
screamer 0:c5e2f793b59a 2232 #define CAN0_ID1 CAN_ID_REG(CAN0,1)
screamer 0:c5e2f793b59a 2233 #define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
screamer 0:c5e2f793b59a 2234 #define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
screamer 0:c5e2f793b59a 2235 #define CAN0_CS2 CAN_CS_REG(CAN0,2)
screamer 0:c5e2f793b59a 2236 #define CAN0_ID2 CAN_ID_REG(CAN0,2)
screamer 0:c5e2f793b59a 2237 #define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
screamer 0:c5e2f793b59a 2238 #define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
screamer 0:c5e2f793b59a 2239 #define CAN0_CS3 CAN_CS_REG(CAN0,3)
screamer 0:c5e2f793b59a 2240 #define CAN0_ID3 CAN_ID_REG(CAN0,3)
screamer 0:c5e2f793b59a 2241 #define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
screamer 0:c5e2f793b59a 2242 #define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
screamer 0:c5e2f793b59a 2243 #define CAN0_CS4 CAN_CS_REG(CAN0,4)
screamer 0:c5e2f793b59a 2244 #define CAN0_ID4 CAN_ID_REG(CAN0,4)
screamer 0:c5e2f793b59a 2245 #define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
screamer 0:c5e2f793b59a 2246 #define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
screamer 0:c5e2f793b59a 2247 #define CAN0_CS5 CAN_CS_REG(CAN0,5)
screamer 0:c5e2f793b59a 2248 #define CAN0_ID5 CAN_ID_REG(CAN0,5)
screamer 0:c5e2f793b59a 2249 #define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
screamer 0:c5e2f793b59a 2250 #define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
screamer 0:c5e2f793b59a 2251 #define CAN0_CS6 CAN_CS_REG(CAN0,6)
screamer 0:c5e2f793b59a 2252 #define CAN0_ID6 CAN_ID_REG(CAN0,6)
screamer 0:c5e2f793b59a 2253 #define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
screamer 0:c5e2f793b59a 2254 #define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
screamer 0:c5e2f793b59a 2255 #define CAN0_CS7 CAN_CS_REG(CAN0,7)
screamer 0:c5e2f793b59a 2256 #define CAN0_ID7 CAN_ID_REG(CAN0,7)
screamer 0:c5e2f793b59a 2257 #define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
screamer 0:c5e2f793b59a 2258 #define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
screamer 0:c5e2f793b59a 2259 #define CAN0_CS8 CAN_CS_REG(CAN0,8)
screamer 0:c5e2f793b59a 2260 #define CAN0_ID8 CAN_ID_REG(CAN0,8)
screamer 0:c5e2f793b59a 2261 #define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
screamer 0:c5e2f793b59a 2262 #define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
screamer 0:c5e2f793b59a 2263 #define CAN0_CS9 CAN_CS_REG(CAN0,9)
screamer 0:c5e2f793b59a 2264 #define CAN0_ID9 CAN_ID_REG(CAN0,9)
screamer 0:c5e2f793b59a 2265 #define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
screamer 0:c5e2f793b59a 2266 #define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
screamer 0:c5e2f793b59a 2267 #define CAN0_CS10 CAN_CS_REG(CAN0,10)
screamer 0:c5e2f793b59a 2268 #define CAN0_ID10 CAN_ID_REG(CAN0,10)
screamer 0:c5e2f793b59a 2269 #define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
screamer 0:c5e2f793b59a 2270 #define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
screamer 0:c5e2f793b59a 2271 #define CAN0_CS11 CAN_CS_REG(CAN0,11)
screamer 0:c5e2f793b59a 2272 #define CAN0_ID11 CAN_ID_REG(CAN0,11)
screamer 0:c5e2f793b59a 2273 #define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
screamer 0:c5e2f793b59a 2274 #define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
screamer 0:c5e2f793b59a 2275 #define CAN0_CS12 CAN_CS_REG(CAN0,12)
screamer 0:c5e2f793b59a 2276 #define CAN0_ID12 CAN_ID_REG(CAN0,12)
screamer 0:c5e2f793b59a 2277 #define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
screamer 0:c5e2f793b59a 2278 #define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
screamer 0:c5e2f793b59a 2279 #define CAN0_CS13 CAN_CS_REG(CAN0,13)
screamer 0:c5e2f793b59a 2280 #define CAN0_ID13 CAN_ID_REG(CAN0,13)
screamer 0:c5e2f793b59a 2281 #define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
screamer 0:c5e2f793b59a 2282 #define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
screamer 0:c5e2f793b59a 2283 #define CAN0_CS14 CAN_CS_REG(CAN0,14)
screamer 0:c5e2f793b59a 2284 #define CAN0_ID14 CAN_ID_REG(CAN0,14)
screamer 0:c5e2f793b59a 2285 #define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
screamer 0:c5e2f793b59a 2286 #define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
screamer 0:c5e2f793b59a 2287 #define CAN0_CS15 CAN_CS_REG(CAN0,15)
screamer 0:c5e2f793b59a 2288 #define CAN0_ID15 CAN_ID_REG(CAN0,15)
screamer 0:c5e2f793b59a 2289 #define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
screamer 0:c5e2f793b59a 2290 #define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
screamer 0:c5e2f793b59a 2291 #define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
screamer 0:c5e2f793b59a 2292 #define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
screamer 0:c5e2f793b59a 2293 #define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
screamer 0:c5e2f793b59a 2294 #define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
screamer 0:c5e2f793b59a 2295 #define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
screamer 0:c5e2f793b59a 2296 #define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
screamer 0:c5e2f793b59a 2297 #define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
screamer 0:c5e2f793b59a 2298 #define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
screamer 0:c5e2f793b59a 2299 #define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
screamer 0:c5e2f793b59a 2300 #define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
screamer 0:c5e2f793b59a 2301 #define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
screamer 0:c5e2f793b59a 2302 #define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
screamer 0:c5e2f793b59a 2303 #define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
screamer 0:c5e2f793b59a 2304 #define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
screamer 0:c5e2f793b59a 2305 #define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
screamer 0:c5e2f793b59a 2306 #define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
screamer 0:c5e2f793b59a 2307
screamer 0:c5e2f793b59a 2308 /* CAN - Register array accessors */
screamer 0:c5e2f793b59a 2309 #define CAN0_CS(index) CAN_CS_REG(CAN0,index)
screamer 0:c5e2f793b59a 2310 #define CAN0_ID(index) CAN_ID_REG(CAN0,index)
screamer 0:c5e2f793b59a 2311 #define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
screamer 0:c5e2f793b59a 2312 #define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
screamer 0:c5e2f793b59a 2313 #define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
screamer 0:c5e2f793b59a 2314
screamer 0:c5e2f793b59a 2315 /*!
screamer 0:c5e2f793b59a 2316 * @}
screamer 0:c5e2f793b59a 2317 */ /* end of group CAN_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 2318
screamer 0:c5e2f793b59a 2319
screamer 0:c5e2f793b59a 2320 /*!
screamer 0:c5e2f793b59a 2321 * @}
screamer 0:c5e2f793b59a 2322 */ /* end of group CAN_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 2323
screamer 0:c5e2f793b59a 2324
screamer 0:c5e2f793b59a 2325 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 2326 -- CAU Peripheral Access Layer
screamer 0:c5e2f793b59a 2327 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 2328
screamer 0:c5e2f793b59a 2329 /*!
screamer 0:c5e2f793b59a 2330 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
screamer 0:c5e2f793b59a 2331 * @{
screamer 0:c5e2f793b59a 2332 */
screamer 0:c5e2f793b59a 2333
screamer 0:c5e2f793b59a 2334 /** CAU - Register Layout Typedef */
screamer 0:c5e2f793b59a 2335 typedef struct {
screamer 0:c5e2f793b59a 2336 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
screamer 0:c5e2f793b59a 2337 uint8_t RESERVED_0[2048];
screamer 0:c5e2f793b59a 2338 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
screamer 0:c5e2f793b59a 2339 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
screamer 0:c5e2f793b59a 2340 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
screamer 0:c5e2f793b59a 2341 uint8_t RESERVED_1[20];
screamer 0:c5e2f793b59a 2342 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
screamer 0:c5e2f793b59a 2343 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
screamer 0:c5e2f793b59a 2344 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
screamer 0:c5e2f793b59a 2345 uint8_t RESERVED_2[20];
screamer 0:c5e2f793b59a 2346 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
screamer 0:c5e2f793b59a 2347 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
screamer 0:c5e2f793b59a 2348 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
screamer 0:c5e2f793b59a 2349 uint8_t RESERVED_3[20];
screamer 0:c5e2f793b59a 2350 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
screamer 0:c5e2f793b59a 2351 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
screamer 0:c5e2f793b59a 2352 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
screamer 0:c5e2f793b59a 2353 uint8_t RESERVED_4[84];
screamer 0:c5e2f793b59a 2354 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
screamer 0:c5e2f793b59a 2355 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
screamer 0:c5e2f793b59a 2356 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
screamer 0:c5e2f793b59a 2357 uint8_t RESERVED_5[20];
screamer 0:c5e2f793b59a 2358 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
screamer 0:c5e2f793b59a 2359 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
screamer 0:c5e2f793b59a 2360 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
screamer 0:c5e2f793b59a 2361 uint8_t RESERVED_6[276];
screamer 0:c5e2f793b59a 2362 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
screamer 0:c5e2f793b59a 2363 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
screamer 0:c5e2f793b59a 2364 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
screamer 0:c5e2f793b59a 2365 uint8_t RESERVED_7[20];
screamer 0:c5e2f793b59a 2366 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
screamer 0:c5e2f793b59a 2367 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
screamer 0:c5e2f793b59a 2368 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
screamer 0:c5e2f793b59a 2369 } CAU_Type, *CAU_MemMapPtr;
screamer 0:c5e2f793b59a 2370
screamer 0:c5e2f793b59a 2371 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 2372 -- CAU - Register accessor macros
screamer 0:c5e2f793b59a 2373 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 2374
screamer 0:c5e2f793b59a 2375 /*!
screamer 0:c5e2f793b59a 2376 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
screamer 0:c5e2f793b59a 2377 * @{
screamer 0:c5e2f793b59a 2378 */
screamer 0:c5e2f793b59a 2379
screamer 0:c5e2f793b59a 2380
screamer 0:c5e2f793b59a 2381 /* CAU - Register accessors */
screamer 0:c5e2f793b59a 2382 #define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
screamer 0:c5e2f793b59a 2383 #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
screamer 0:c5e2f793b59a 2384 #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
screamer 0:c5e2f793b59a 2385 #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
screamer 0:c5e2f793b59a 2386 #define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
screamer 0:c5e2f793b59a 2387 #define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
screamer 0:c5e2f793b59a 2388 #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
screamer 0:c5e2f793b59a 2389 #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
screamer 0:c5e2f793b59a 2390 #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
screamer 0:c5e2f793b59a 2391 #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
screamer 0:c5e2f793b59a 2392 #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
screamer 0:c5e2f793b59a 2393 #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
screamer 0:c5e2f793b59a 2394 #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
screamer 0:c5e2f793b59a 2395 #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
screamer 0:c5e2f793b59a 2396 #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
screamer 0:c5e2f793b59a 2397 #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
screamer 0:c5e2f793b59a 2398 #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
screamer 0:c5e2f793b59a 2399 #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
screamer 0:c5e2f793b59a 2400 #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
screamer 0:c5e2f793b59a 2401 #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
screamer 0:c5e2f793b59a 2402 #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
screamer 0:c5e2f793b59a 2403 #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
screamer 0:c5e2f793b59a 2404 #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
screamer 0:c5e2f793b59a 2405 #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
screamer 0:c5e2f793b59a 2406 #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
screamer 0:c5e2f793b59a 2407
screamer 0:c5e2f793b59a 2408 /*!
screamer 0:c5e2f793b59a 2409 * @}
screamer 0:c5e2f793b59a 2410 */ /* end of group CAU_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 2411
screamer 0:c5e2f793b59a 2412
screamer 0:c5e2f793b59a 2413 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 2414 -- CAU Register Masks
screamer 0:c5e2f793b59a 2415 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 2416
screamer 0:c5e2f793b59a 2417 /*!
screamer 0:c5e2f793b59a 2418 * @addtogroup CAU_Register_Masks CAU Register Masks
screamer 0:c5e2f793b59a 2419 * @{
screamer 0:c5e2f793b59a 2420 */
screamer 0:c5e2f793b59a 2421
screamer 0:c5e2f793b59a 2422 /* DIRECT Bit Fields */
screamer 0:c5e2f793b59a 2423 #define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2424 #define CAU_DIRECT_CAU_DIRECT0_SHIFT 0
screamer 0:c5e2f793b59a 2425 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
screamer 0:c5e2f793b59a 2426 #define CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2427 #define CAU_DIRECT_CAU_DIRECT1_SHIFT 0
screamer 0:c5e2f793b59a 2428 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
screamer 0:c5e2f793b59a 2429 #define CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2430 #define CAU_DIRECT_CAU_DIRECT2_SHIFT 0
screamer 0:c5e2f793b59a 2431 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
screamer 0:c5e2f793b59a 2432 #define CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2433 #define CAU_DIRECT_CAU_DIRECT3_SHIFT 0
screamer 0:c5e2f793b59a 2434 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
screamer 0:c5e2f793b59a 2435 #define CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2436 #define CAU_DIRECT_CAU_DIRECT4_SHIFT 0
screamer 0:c5e2f793b59a 2437 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
screamer 0:c5e2f793b59a 2438 #define CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2439 #define CAU_DIRECT_CAU_DIRECT5_SHIFT 0
screamer 0:c5e2f793b59a 2440 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
screamer 0:c5e2f793b59a 2441 #define CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2442 #define CAU_DIRECT_CAU_DIRECT6_SHIFT 0
screamer 0:c5e2f793b59a 2443 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
screamer 0:c5e2f793b59a 2444 #define CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2445 #define CAU_DIRECT_CAU_DIRECT7_SHIFT 0
screamer 0:c5e2f793b59a 2446 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
screamer 0:c5e2f793b59a 2447 #define CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2448 #define CAU_DIRECT_CAU_DIRECT8_SHIFT 0
screamer 0:c5e2f793b59a 2449 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
screamer 0:c5e2f793b59a 2450 #define CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2451 #define CAU_DIRECT_CAU_DIRECT9_SHIFT 0
screamer 0:c5e2f793b59a 2452 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
screamer 0:c5e2f793b59a 2453 #define CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2454 #define CAU_DIRECT_CAU_DIRECT10_SHIFT 0
screamer 0:c5e2f793b59a 2455 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
screamer 0:c5e2f793b59a 2456 #define CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2457 #define CAU_DIRECT_CAU_DIRECT11_SHIFT 0
screamer 0:c5e2f793b59a 2458 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
screamer 0:c5e2f793b59a 2459 #define CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2460 #define CAU_DIRECT_CAU_DIRECT12_SHIFT 0
screamer 0:c5e2f793b59a 2461 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
screamer 0:c5e2f793b59a 2462 #define CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2463 #define CAU_DIRECT_CAU_DIRECT13_SHIFT 0
screamer 0:c5e2f793b59a 2464 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
screamer 0:c5e2f793b59a 2465 #define CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2466 #define CAU_DIRECT_CAU_DIRECT14_SHIFT 0
screamer 0:c5e2f793b59a 2467 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
screamer 0:c5e2f793b59a 2468 #define CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2469 #define CAU_DIRECT_CAU_DIRECT15_SHIFT 0
screamer 0:c5e2f793b59a 2470 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
screamer 0:c5e2f793b59a 2471 /* LDR_CASR Bit Fields */
screamer 0:c5e2f793b59a 2472 #define CAU_LDR_CASR_IC_MASK 0x1u
screamer 0:c5e2f793b59a 2473 #define CAU_LDR_CASR_IC_SHIFT 0
screamer 0:c5e2f793b59a 2474 #define CAU_LDR_CASR_DPE_MASK 0x2u
screamer 0:c5e2f793b59a 2475 #define CAU_LDR_CASR_DPE_SHIFT 1
screamer 0:c5e2f793b59a 2476 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
screamer 0:c5e2f793b59a 2477 #define CAU_LDR_CASR_VER_SHIFT 28
screamer 0:c5e2f793b59a 2478 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
screamer 0:c5e2f793b59a 2479 /* LDR_CAA Bit Fields */
screamer 0:c5e2f793b59a 2480 #define CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2481 #define CAU_LDR_CAA_ACC_SHIFT 0
screamer 0:c5e2f793b59a 2482 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
screamer 0:c5e2f793b59a 2483 /* LDR_CA Bit Fields */
screamer 0:c5e2f793b59a 2484 #define CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2485 #define CAU_LDR_CA_CA0_SHIFT 0
screamer 0:c5e2f793b59a 2486 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
screamer 0:c5e2f793b59a 2487 #define CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2488 #define CAU_LDR_CA_CA1_SHIFT 0
screamer 0:c5e2f793b59a 2489 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
screamer 0:c5e2f793b59a 2490 #define CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2491 #define CAU_LDR_CA_CA2_SHIFT 0
screamer 0:c5e2f793b59a 2492 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
screamer 0:c5e2f793b59a 2493 #define CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2494 #define CAU_LDR_CA_CA3_SHIFT 0
screamer 0:c5e2f793b59a 2495 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
screamer 0:c5e2f793b59a 2496 #define CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2497 #define CAU_LDR_CA_CA4_SHIFT 0
screamer 0:c5e2f793b59a 2498 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
screamer 0:c5e2f793b59a 2499 #define CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2500 #define CAU_LDR_CA_CA5_SHIFT 0
screamer 0:c5e2f793b59a 2501 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
screamer 0:c5e2f793b59a 2502 #define CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2503 #define CAU_LDR_CA_CA6_SHIFT 0
screamer 0:c5e2f793b59a 2504 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
screamer 0:c5e2f793b59a 2505 #define CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2506 #define CAU_LDR_CA_CA7_SHIFT 0
screamer 0:c5e2f793b59a 2507 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
screamer 0:c5e2f793b59a 2508 #define CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2509 #define CAU_LDR_CA_CA8_SHIFT 0
screamer 0:c5e2f793b59a 2510 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
screamer 0:c5e2f793b59a 2511 /* STR_CASR Bit Fields */
screamer 0:c5e2f793b59a 2512 #define CAU_STR_CASR_IC_MASK 0x1u
screamer 0:c5e2f793b59a 2513 #define CAU_STR_CASR_IC_SHIFT 0
screamer 0:c5e2f793b59a 2514 #define CAU_STR_CASR_DPE_MASK 0x2u
screamer 0:c5e2f793b59a 2515 #define CAU_STR_CASR_DPE_SHIFT 1
screamer 0:c5e2f793b59a 2516 #define CAU_STR_CASR_VER_MASK 0xF0000000u
screamer 0:c5e2f793b59a 2517 #define CAU_STR_CASR_VER_SHIFT 28
screamer 0:c5e2f793b59a 2518 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
screamer 0:c5e2f793b59a 2519 /* STR_CAA Bit Fields */
screamer 0:c5e2f793b59a 2520 #define CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2521 #define CAU_STR_CAA_ACC_SHIFT 0
screamer 0:c5e2f793b59a 2522 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
screamer 0:c5e2f793b59a 2523 /* STR_CA Bit Fields */
screamer 0:c5e2f793b59a 2524 #define CAU_STR_CA_CA0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2525 #define CAU_STR_CA_CA0_SHIFT 0
screamer 0:c5e2f793b59a 2526 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
screamer 0:c5e2f793b59a 2527 #define CAU_STR_CA_CA1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2528 #define CAU_STR_CA_CA1_SHIFT 0
screamer 0:c5e2f793b59a 2529 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
screamer 0:c5e2f793b59a 2530 #define CAU_STR_CA_CA2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2531 #define CAU_STR_CA_CA2_SHIFT 0
screamer 0:c5e2f793b59a 2532 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
screamer 0:c5e2f793b59a 2533 #define CAU_STR_CA_CA3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2534 #define CAU_STR_CA_CA3_SHIFT 0
screamer 0:c5e2f793b59a 2535 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
screamer 0:c5e2f793b59a 2536 #define CAU_STR_CA_CA4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2537 #define CAU_STR_CA_CA4_SHIFT 0
screamer 0:c5e2f793b59a 2538 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
screamer 0:c5e2f793b59a 2539 #define CAU_STR_CA_CA5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2540 #define CAU_STR_CA_CA5_SHIFT 0
screamer 0:c5e2f793b59a 2541 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
screamer 0:c5e2f793b59a 2542 #define CAU_STR_CA_CA6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2543 #define CAU_STR_CA_CA6_SHIFT 0
screamer 0:c5e2f793b59a 2544 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
screamer 0:c5e2f793b59a 2545 #define CAU_STR_CA_CA7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2546 #define CAU_STR_CA_CA7_SHIFT 0
screamer 0:c5e2f793b59a 2547 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
screamer 0:c5e2f793b59a 2548 #define CAU_STR_CA_CA8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2549 #define CAU_STR_CA_CA8_SHIFT 0
screamer 0:c5e2f793b59a 2550 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
screamer 0:c5e2f793b59a 2551 /* ADR_CASR Bit Fields */
screamer 0:c5e2f793b59a 2552 #define CAU_ADR_CASR_IC_MASK 0x1u
screamer 0:c5e2f793b59a 2553 #define CAU_ADR_CASR_IC_SHIFT 0
screamer 0:c5e2f793b59a 2554 #define CAU_ADR_CASR_DPE_MASK 0x2u
screamer 0:c5e2f793b59a 2555 #define CAU_ADR_CASR_DPE_SHIFT 1
screamer 0:c5e2f793b59a 2556 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
screamer 0:c5e2f793b59a 2557 #define CAU_ADR_CASR_VER_SHIFT 28
screamer 0:c5e2f793b59a 2558 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
screamer 0:c5e2f793b59a 2559 /* ADR_CAA Bit Fields */
screamer 0:c5e2f793b59a 2560 #define CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2561 #define CAU_ADR_CAA_ACC_SHIFT 0
screamer 0:c5e2f793b59a 2562 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
screamer 0:c5e2f793b59a 2563 /* ADR_CA Bit Fields */
screamer 0:c5e2f793b59a 2564 #define CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2565 #define CAU_ADR_CA_CA0_SHIFT 0
screamer 0:c5e2f793b59a 2566 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
screamer 0:c5e2f793b59a 2567 #define CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2568 #define CAU_ADR_CA_CA1_SHIFT 0
screamer 0:c5e2f793b59a 2569 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
screamer 0:c5e2f793b59a 2570 #define CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2571 #define CAU_ADR_CA_CA2_SHIFT 0
screamer 0:c5e2f793b59a 2572 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
screamer 0:c5e2f793b59a 2573 #define CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2574 #define CAU_ADR_CA_CA3_SHIFT 0
screamer 0:c5e2f793b59a 2575 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
screamer 0:c5e2f793b59a 2576 #define CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2577 #define CAU_ADR_CA_CA4_SHIFT 0
screamer 0:c5e2f793b59a 2578 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
screamer 0:c5e2f793b59a 2579 #define CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2580 #define CAU_ADR_CA_CA5_SHIFT 0
screamer 0:c5e2f793b59a 2581 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
screamer 0:c5e2f793b59a 2582 #define CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2583 #define CAU_ADR_CA_CA6_SHIFT 0
screamer 0:c5e2f793b59a 2584 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
screamer 0:c5e2f793b59a 2585 #define CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2586 #define CAU_ADR_CA_CA7_SHIFT 0
screamer 0:c5e2f793b59a 2587 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
screamer 0:c5e2f793b59a 2588 #define CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2589 #define CAU_ADR_CA_CA8_SHIFT 0
screamer 0:c5e2f793b59a 2590 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
screamer 0:c5e2f793b59a 2591 /* RADR_CASR Bit Fields */
screamer 0:c5e2f793b59a 2592 #define CAU_RADR_CASR_IC_MASK 0x1u
screamer 0:c5e2f793b59a 2593 #define CAU_RADR_CASR_IC_SHIFT 0
screamer 0:c5e2f793b59a 2594 #define CAU_RADR_CASR_DPE_MASK 0x2u
screamer 0:c5e2f793b59a 2595 #define CAU_RADR_CASR_DPE_SHIFT 1
screamer 0:c5e2f793b59a 2596 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
screamer 0:c5e2f793b59a 2597 #define CAU_RADR_CASR_VER_SHIFT 28
screamer 0:c5e2f793b59a 2598 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
screamer 0:c5e2f793b59a 2599 /* RADR_CAA Bit Fields */
screamer 0:c5e2f793b59a 2600 #define CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2601 #define CAU_RADR_CAA_ACC_SHIFT 0
screamer 0:c5e2f793b59a 2602 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
screamer 0:c5e2f793b59a 2603 /* RADR_CA Bit Fields */
screamer 0:c5e2f793b59a 2604 #define CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2605 #define CAU_RADR_CA_CA0_SHIFT 0
screamer 0:c5e2f793b59a 2606 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
screamer 0:c5e2f793b59a 2607 #define CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2608 #define CAU_RADR_CA_CA1_SHIFT 0
screamer 0:c5e2f793b59a 2609 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
screamer 0:c5e2f793b59a 2610 #define CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2611 #define CAU_RADR_CA_CA2_SHIFT 0
screamer 0:c5e2f793b59a 2612 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
screamer 0:c5e2f793b59a 2613 #define CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2614 #define CAU_RADR_CA_CA3_SHIFT 0
screamer 0:c5e2f793b59a 2615 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
screamer 0:c5e2f793b59a 2616 #define CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2617 #define CAU_RADR_CA_CA4_SHIFT 0
screamer 0:c5e2f793b59a 2618 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
screamer 0:c5e2f793b59a 2619 #define CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2620 #define CAU_RADR_CA_CA5_SHIFT 0
screamer 0:c5e2f793b59a 2621 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
screamer 0:c5e2f793b59a 2622 #define CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2623 #define CAU_RADR_CA_CA6_SHIFT 0
screamer 0:c5e2f793b59a 2624 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
screamer 0:c5e2f793b59a 2625 #define CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2626 #define CAU_RADR_CA_CA7_SHIFT 0
screamer 0:c5e2f793b59a 2627 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
screamer 0:c5e2f793b59a 2628 #define CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2629 #define CAU_RADR_CA_CA8_SHIFT 0
screamer 0:c5e2f793b59a 2630 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
screamer 0:c5e2f793b59a 2631 /* XOR_CASR Bit Fields */
screamer 0:c5e2f793b59a 2632 #define CAU_XOR_CASR_IC_MASK 0x1u
screamer 0:c5e2f793b59a 2633 #define CAU_XOR_CASR_IC_SHIFT 0
screamer 0:c5e2f793b59a 2634 #define CAU_XOR_CASR_DPE_MASK 0x2u
screamer 0:c5e2f793b59a 2635 #define CAU_XOR_CASR_DPE_SHIFT 1
screamer 0:c5e2f793b59a 2636 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
screamer 0:c5e2f793b59a 2637 #define CAU_XOR_CASR_VER_SHIFT 28
screamer 0:c5e2f793b59a 2638 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
screamer 0:c5e2f793b59a 2639 /* XOR_CAA Bit Fields */
screamer 0:c5e2f793b59a 2640 #define CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2641 #define CAU_XOR_CAA_ACC_SHIFT 0
screamer 0:c5e2f793b59a 2642 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
screamer 0:c5e2f793b59a 2643 /* XOR_CA Bit Fields */
screamer 0:c5e2f793b59a 2644 #define CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2645 #define CAU_XOR_CA_CA0_SHIFT 0
screamer 0:c5e2f793b59a 2646 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
screamer 0:c5e2f793b59a 2647 #define CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2648 #define CAU_XOR_CA_CA1_SHIFT 0
screamer 0:c5e2f793b59a 2649 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
screamer 0:c5e2f793b59a 2650 #define CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2651 #define CAU_XOR_CA_CA2_SHIFT 0
screamer 0:c5e2f793b59a 2652 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
screamer 0:c5e2f793b59a 2653 #define CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2654 #define CAU_XOR_CA_CA3_SHIFT 0
screamer 0:c5e2f793b59a 2655 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
screamer 0:c5e2f793b59a 2656 #define CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2657 #define CAU_XOR_CA_CA4_SHIFT 0
screamer 0:c5e2f793b59a 2658 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
screamer 0:c5e2f793b59a 2659 #define CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2660 #define CAU_XOR_CA_CA5_SHIFT 0
screamer 0:c5e2f793b59a 2661 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
screamer 0:c5e2f793b59a 2662 #define CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2663 #define CAU_XOR_CA_CA6_SHIFT 0
screamer 0:c5e2f793b59a 2664 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
screamer 0:c5e2f793b59a 2665 #define CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2666 #define CAU_XOR_CA_CA7_SHIFT 0
screamer 0:c5e2f793b59a 2667 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
screamer 0:c5e2f793b59a 2668 #define CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2669 #define CAU_XOR_CA_CA8_SHIFT 0
screamer 0:c5e2f793b59a 2670 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
screamer 0:c5e2f793b59a 2671 /* ROTL_CASR Bit Fields */
screamer 0:c5e2f793b59a 2672 #define CAU_ROTL_CASR_IC_MASK 0x1u
screamer 0:c5e2f793b59a 2673 #define CAU_ROTL_CASR_IC_SHIFT 0
screamer 0:c5e2f793b59a 2674 #define CAU_ROTL_CASR_DPE_MASK 0x2u
screamer 0:c5e2f793b59a 2675 #define CAU_ROTL_CASR_DPE_SHIFT 1
screamer 0:c5e2f793b59a 2676 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
screamer 0:c5e2f793b59a 2677 #define CAU_ROTL_CASR_VER_SHIFT 28
screamer 0:c5e2f793b59a 2678 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
screamer 0:c5e2f793b59a 2679 /* ROTL_CAA Bit Fields */
screamer 0:c5e2f793b59a 2680 #define CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2681 #define CAU_ROTL_CAA_ACC_SHIFT 0
screamer 0:c5e2f793b59a 2682 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
screamer 0:c5e2f793b59a 2683 /* ROTL_CA Bit Fields */
screamer 0:c5e2f793b59a 2684 #define CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2685 #define CAU_ROTL_CA_CA0_SHIFT 0
screamer 0:c5e2f793b59a 2686 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
screamer 0:c5e2f793b59a 2687 #define CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2688 #define CAU_ROTL_CA_CA1_SHIFT 0
screamer 0:c5e2f793b59a 2689 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
screamer 0:c5e2f793b59a 2690 #define CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2691 #define CAU_ROTL_CA_CA2_SHIFT 0
screamer 0:c5e2f793b59a 2692 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
screamer 0:c5e2f793b59a 2693 #define CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2694 #define CAU_ROTL_CA_CA3_SHIFT 0
screamer 0:c5e2f793b59a 2695 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
screamer 0:c5e2f793b59a 2696 #define CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2697 #define CAU_ROTL_CA_CA4_SHIFT 0
screamer 0:c5e2f793b59a 2698 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
screamer 0:c5e2f793b59a 2699 #define CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2700 #define CAU_ROTL_CA_CA5_SHIFT 0
screamer 0:c5e2f793b59a 2701 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
screamer 0:c5e2f793b59a 2702 #define CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2703 #define CAU_ROTL_CA_CA6_SHIFT 0
screamer 0:c5e2f793b59a 2704 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
screamer 0:c5e2f793b59a 2705 #define CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2706 #define CAU_ROTL_CA_CA7_SHIFT 0
screamer 0:c5e2f793b59a 2707 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
screamer 0:c5e2f793b59a 2708 #define CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2709 #define CAU_ROTL_CA_CA8_SHIFT 0
screamer 0:c5e2f793b59a 2710 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
screamer 0:c5e2f793b59a 2711 /* AESC_CASR Bit Fields */
screamer 0:c5e2f793b59a 2712 #define CAU_AESC_CASR_IC_MASK 0x1u
screamer 0:c5e2f793b59a 2713 #define CAU_AESC_CASR_IC_SHIFT 0
screamer 0:c5e2f793b59a 2714 #define CAU_AESC_CASR_DPE_MASK 0x2u
screamer 0:c5e2f793b59a 2715 #define CAU_AESC_CASR_DPE_SHIFT 1
screamer 0:c5e2f793b59a 2716 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
screamer 0:c5e2f793b59a 2717 #define CAU_AESC_CASR_VER_SHIFT 28
screamer 0:c5e2f793b59a 2718 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
screamer 0:c5e2f793b59a 2719 /* AESC_CAA Bit Fields */
screamer 0:c5e2f793b59a 2720 #define CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2721 #define CAU_AESC_CAA_ACC_SHIFT 0
screamer 0:c5e2f793b59a 2722 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
screamer 0:c5e2f793b59a 2723 /* AESC_CA Bit Fields */
screamer 0:c5e2f793b59a 2724 #define CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2725 #define CAU_AESC_CA_CA0_SHIFT 0
screamer 0:c5e2f793b59a 2726 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
screamer 0:c5e2f793b59a 2727 #define CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2728 #define CAU_AESC_CA_CA1_SHIFT 0
screamer 0:c5e2f793b59a 2729 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
screamer 0:c5e2f793b59a 2730 #define CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2731 #define CAU_AESC_CA_CA2_SHIFT 0
screamer 0:c5e2f793b59a 2732 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
screamer 0:c5e2f793b59a 2733 #define CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2734 #define CAU_AESC_CA_CA3_SHIFT 0
screamer 0:c5e2f793b59a 2735 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
screamer 0:c5e2f793b59a 2736 #define CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2737 #define CAU_AESC_CA_CA4_SHIFT 0
screamer 0:c5e2f793b59a 2738 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
screamer 0:c5e2f793b59a 2739 #define CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2740 #define CAU_AESC_CA_CA5_SHIFT 0
screamer 0:c5e2f793b59a 2741 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
screamer 0:c5e2f793b59a 2742 #define CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2743 #define CAU_AESC_CA_CA6_SHIFT 0
screamer 0:c5e2f793b59a 2744 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
screamer 0:c5e2f793b59a 2745 #define CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2746 #define CAU_AESC_CA_CA7_SHIFT 0
screamer 0:c5e2f793b59a 2747 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
screamer 0:c5e2f793b59a 2748 #define CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2749 #define CAU_AESC_CA_CA8_SHIFT 0
screamer 0:c5e2f793b59a 2750 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
screamer 0:c5e2f793b59a 2751 /* AESIC_CASR Bit Fields */
screamer 0:c5e2f793b59a 2752 #define CAU_AESIC_CASR_IC_MASK 0x1u
screamer 0:c5e2f793b59a 2753 #define CAU_AESIC_CASR_IC_SHIFT 0
screamer 0:c5e2f793b59a 2754 #define CAU_AESIC_CASR_DPE_MASK 0x2u
screamer 0:c5e2f793b59a 2755 #define CAU_AESIC_CASR_DPE_SHIFT 1
screamer 0:c5e2f793b59a 2756 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
screamer 0:c5e2f793b59a 2757 #define CAU_AESIC_CASR_VER_SHIFT 28
screamer 0:c5e2f793b59a 2758 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
screamer 0:c5e2f793b59a 2759 /* AESIC_CAA Bit Fields */
screamer 0:c5e2f793b59a 2760 #define CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2761 #define CAU_AESIC_CAA_ACC_SHIFT 0
screamer 0:c5e2f793b59a 2762 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
screamer 0:c5e2f793b59a 2763 /* AESIC_CA Bit Fields */
screamer 0:c5e2f793b59a 2764 #define CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2765 #define CAU_AESIC_CA_CA0_SHIFT 0
screamer 0:c5e2f793b59a 2766 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
screamer 0:c5e2f793b59a 2767 #define CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2768 #define CAU_AESIC_CA_CA1_SHIFT 0
screamer 0:c5e2f793b59a 2769 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
screamer 0:c5e2f793b59a 2770 #define CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2771 #define CAU_AESIC_CA_CA2_SHIFT 0
screamer 0:c5e2f793b59a 2772 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
screamer 0:c5e2f793b59a 2773 #define CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2774 #define CAU_AESIC_CA_CA3_SHIFT 0
screamer 0:c5e2f793b59a 2775 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
screamer 0:c5e2f793b59a 2776 #define CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2777 #define CAU_AESIC_CA_CA4_SHIFT 0
screamer 0:c5e2f793b59a 2778 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
screamer 0:c5e2f793b59a 2779 #define CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2780 #define CAU_AESIC_CA_CA5_SHIFT 0
screamer 0:c5e2f793b59a 2781 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
screamer 0:c5e2f793b59a 2782 #define CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2783 #define CAU_AESIC_CA_CA6_SHIFT 0
screamer 0:c5e2f793b59a 2784 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
screamer 0:c5e2f793b59a 2785 #define CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2786 #define CAU_AESIC_CA_CA7_SHIFT 0
screamer 0:c5e2f793b59a 2787 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
screamer 0:c5e2f793b59a 2788 #define CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 2789 #define CAU_AESIC_CA_CA8_SHIFT 0
screamer 0:c5e2f793b59a 2790 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
screamer 0:c5e2f793b59a 2791
screamer 0:c5e2f793b59a 2792 /*!
screamer 0:c5e2f793b59a 2793 * @}
screamer 0:c5e2f793b59a 2794 */ /* end of group CAU_Register_Masks */
screamer 0:c5e2f793b59a 2795
screamer 0:c5e2f793b59a 2796
screamer 0:c5e2f793b59a 2797 /* CAU - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 2798 /** Peripheral CAU base address */
screamer 0:c5e2f793b59a 2799 #define CAU_BASE (0xE0081000u)
screamer 0:c5e2f793b59a 2800 /** Peripheral CAU base pointer */
screamer 0:c5e2f793b59a 2801 #define CAU ((CAU_Type *)CAU_BASE)
screamer 0:c5e2f793b59a 2802 #define CAU_BASE_PTR (CAU)
screamer 0:c5e2f793b59a 2803 /** Array initializer of CAU peripheral base addresses */
screamer 0:c5e2f793b59a 2804 #define CAU_BASE_ADDRS { CAU_BASE }
screamer 0:c5e2f793b59a 2805 /** Array initializer of CAU peripheral base pointers */
screamer 0:c5e2f793b59a 2806 #define CAU_BASE_PTRS { CAU }
screamer 0:c5e2f793b59a 2807
screamer 0:c5e2f793b59a 2808 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 2809 -- CAU - Register accessor macros
screamer 0:c5e2f793b59a 2810 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 2811
screamer 0:c5e2f793b59a 2812 /*!
screamer 0:c5e2f793b59a 2813 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
screamer 0:c5e2f793b59a 2814 * @{
screamer 0:c5e2f793b59a 2815 */
screamer 0:c5e2f793b59a 2816
screamer 0:c5e2f793b59a 2817
screamer 0:c5e2f793b59a 2818 /* CAU - Register instance definitions */
screamer 0:c5e2f793b59a 2819 /* CAU */
screamer 0:c5e2f793b59a 2820 #define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
screamer 0:c5e2f793b59a 2821 #define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
screamer 0:c5e2f793b59a 2822 #define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
screamer 0:c5e2f793b59a 2823 #define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
screamer 0:c5e2f793b59a 2824 #define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
screamer 0:c5e2f793b59a 2825 #define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
screamer 0:c5e2f793b59a 2826 #define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
screamer 0:c5e2f793b59a 2827 #define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
screamer 0:c5e2f793b59a 2828 #define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
screamer 0:c5e2f793b59a 2829 #define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
screamer 0:c5e2f793b59a 2830 #define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
screamer 0:c5e2f793b59a 2831 #define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
screamer 0:c5e2f793b59a 2832 #define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
screamer 0:c5e2f793b59a 2833 #define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
screamer 0:c5e2f793b59a 2834 #define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
screamer 0:c5e2f793b59a 2835 #define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
screamer 0:c5e2f793b59a 2836 #define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
screamer 0:c5e2f793b59a 2837 #define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
screamer 0:c5e2f793b59a 2838 #define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
screamer 0:c5e2f793b59a 2839 #define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
screamer 0:c5e2f793b59a 2840 #define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
screamer 0:c5e2f793b59a 2841 #define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
screamer 0:c5e2f793b59a 2842 #define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
screamer 0:c5e2f793b59a 2843 #define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
screamer 0:c5e2f793b59a 2844 #define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
screamer 0:c5e2f793b59a 2845 #define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
screamer 0:c5e2f793b59a 2846 #define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
screamer 0:c5e2f793b59a 2847 #define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
screamer 0:c5e2f793b59a 2848 #define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
screamer 0:c5e2f793b59a 2849 #define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
screamer 0:c5e2f793b59a 2850 #define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
screamer 0:c5e2f793b59a 2851 #define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
screamer 0:c5e2f793b59a 2852 #define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
screamer 0:c5e2f793b59a 2853 #define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
screamer 0:c5e2f793b59a 2854 #define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
screamer 0:c5e2f793b59a 2855 #define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
screamer 0:c5e2f793b59a 2856 #define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
screamer 0:c5e2f793b59a 2857 #define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
screamer 0:c5e2f793b59a 2858 #define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
screamer 0:c5e2f793b59a 2859 #define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
screamer 0:c5e2f793b59a 2860 #define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
screamer 0:c5e2f793b59a 2861 #define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
screamer 0:c5e2f793b59a 2862 #define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
screamer 0:c5e2f793b59a 2863 #define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
screamer 0:c5e2f793b59a 2864 #define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
screamer 0:c5e2f793b59a 2865 #define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
screamer 0:c5e2f793b59a 2866 #define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
screamer 0:c5e2f793b59a 2867 #define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
screamer 0:c5e2f793b59a 2868 #define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
screamer 0:c5e2f793b59a 2869 #define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
screamer 0:c5e2f793b59a 2870 #define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
screamer 0:c5e2f793b59a 2871 #define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
screamer 0:c5e2f793b59a 2872 #define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
screamer 0:c5e2f793b59a 2873 #define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
screamer 0:c5e2f793b59a 2874 #define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
screamer 0:c5e2f793b59a 2875 #define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
screamer 0:c5e2f793b59a 2876 #define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
screamer 0:c5e2f793b59a 2877 #define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
screamer 0:c5e2f793b59a 2878 #define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
screamer 0:c5e2f793b59a 2879 #define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
screamer 0:c5e2f793b59a 2880 #define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
screamer 0:c5e2f793b59a 2881 #define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
screamer 0:c5e2f793b59a 2882 #define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
screamer 0:c5e2f793b59a 2883 #define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
screamer 0:c5e2f793b59a 2884 #define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
screamer 0:c5e2f793b59a 2885 #define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
screamer 0:c5e2f793b59a 2886 #define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
screamer 0:c5e2f793b59a 2887 #define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
screamer 0:c5e2f793b59a 2888 #define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
screamer 0:c5e2f793b59a 2889 #define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
screamer 0:c5e2f793b59a 2890 #define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
screamer 0:c5e2f793b59a 2891 #define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
screamer 0:c5e2f793b59a 2892 #define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
screamer 0:c5e2f793b59a 2893 #define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
screamer 0:c5e2f793b59a 2894 #define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
screamer 0:c5e2f793b59a 2895 #define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
screamer 0:c5e2f793b59a 2896 #define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
screamer 0:c5e2f793b59a 2897 #define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
screamer 0:c5e2f793b59a 2898 #define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
screamer 0:c5e2f793b59a 2899 #define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
screamer 0:c5e2f793b59a 2900 #define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
screamer 0:c5e2f793b59a 2901 #define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
screamer 0:c5e2f793b59a 2902 #define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
screamer 0:c5e2f793b59a 2903 #define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
screamer 0:c5e2f793b59a 2904 #define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
screamer 0:c5e2f793b59a 2905 #define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
screamer 0:c5e2f793b59a 2906 #define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
screamer 0:c5e2f793b59a 2907 #define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
screamer 0:c5e2f793b59a 2908 #define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
screamer 0:c5e2f793b59a 2909 #define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
screamer 0:c5e2f793b59a 2910 #define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
screamer 0:c5e2f793b59a 2911 #define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
screamer 0:c5e2f793b59a 2912 #define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
screamer 0:c5e2f793b59a 2913 #define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
screamer 0:c5e2f793b59a 2914 #define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
screamer 0:c5e2f793b59a 2915 #define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
screamer 0:c5e2f793b59a 2916 #define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
screamer 0:c5e2f793b59a 2917 #define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
screamer 0:c5e2f793b59a 2918 #define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
screamer 0:c5e2f793b59a 2919 #define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
screamer 0:c5e2f793b59a 2920 #define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
screamer 0:c5e2f793b59a 2921 #define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
screamer 0:c5e2f793b59a 2922 #define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
screamer 0:c5e2f793b59a 2923 #define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
screamer 0:c5e2f793b59a 2924
screamer 0:c5e2f793b59a 2925 /* CAU - Register array accessors */
screamer 0:c5e2f793b59a 2926 #define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
screamer 0:c5e2f793b59a 2927 #define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
screamer 0:c5e2f793b59a 2928 #define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
screamer 0:c5e2f793b59a 2929 #define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
screamer 0:c5e2f793b59a 2930 #define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
screamer 0:c5e2f793b59a 2931 #define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
screamer 0:c5e2f793b59a 2932 #define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
screamer 0:c5e2f793b59a 2933 #define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
screamer 0:c5e2f793b59a 2934 #define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
screamer 0:c5e2f793b59a 2935
screamer 0:c5e2f793b59a 2936 /*!
screamer 0:c5e2f793b59a 2937 * @}
screamer 0:c5e2f793b59a 2938 */ /* end of group CAU_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 2939
screamer 0:c5e2f793b59a 2940
screamer 0:c5e2f793b59a 2941 /*!
screamer 0:c5e2f793b59a 2942 * @}
screamer 0:c5e2f793b59a 2943 */ /* end of group CAU_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 2944
screamer 0:c5e2f793b59a 2945
screamer 0:c5e2f793b59a 2946 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 2947 -- CMP Peripheral Access Layer
screamer 0:c5e2f793b59a 2948 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 2949
screamer 0:c5e2f793b59a 2950 /*!
screamer 0:c5e2f793b59a 2951 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
screamer 0:c5e2f793b59a 2952 * @{
screamer 0:c5e2f793b59a 2953 */
screamer 0:c5e2f793b59a 2954
screamer 0:c5e2f793b59a 2955 /** CMP - Register Layout Typedef */
screamer 0:c5e2f793b59a 2956 typedef struct {
screamer 0:c5e2f793b59a 2957 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
screamer 0:c5e2f793b59a 2958 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
screamer 0:c5e2f793b59a 2959 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
screamer 0:c5e2f793b59a 2960 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
screamer 0:c5e2f793b59a 2961 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
screamer 0:c5e2f793b59a 2962 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
screamer 0:c5e2f793b59a 2963 } CMP_Type, *CMP_MemMapPtr;
screamer 0:c5e2f793b59a 2964
screamer 0:c5e2f793b59a 2965 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 2966 -- CMP - Register accessor macros
screamer 0:c5e2f793b59a 2967 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 2968
screamer 0:c5e2f793b59a 2969 /*!
screamer 0:c5e2f793b59a 2970 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
screamer 0:c5e2f793b59a 2971 * @{
screamer 0:c5e2f793b59a 2972 */
screamer 0:c5e2f793b59a 2973
screamer 0:c5e2f793b59a 2974
screamer 0:c5e2f793b59a 2975 /* CMP - Register accessors */
screamer 0:c5e2f793b59a 2976 #define CMP_CR0_REG(base) ((base)->CR0)
screamer 0:c5e2f793b59a 2977 #define CMP_CR1_REG(base) ((base)->CR1)
screamer 0:c5e2f793b59a 2978 #define CMP_FPR_REG(base) ((base)->FPR)
screamer 0:c5e2f793b59a 2979 #define CMP_SCR_REG(base) ((base)->SCR)
screamer 0:c5e2f793b59a 2980 #define CMP_DACCR_REG(base) ((base)->DACCR)
screamer 0:c5e2f793b59a 2981 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
screamer 0:c5e2f793b59a 2982
screamer 0:c5e2f793b59a 2983 /*!
screamer 0:c5e2f793b59a 2984 * @}
screamer 0:c5e2f793b59a 2985 */ /* end of group CMP_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 2986
screamer 0:c5e2f793b59a 2987
screamer 0:c5e2f793b59a 2988 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 2989 -- CMP Register Masks
screamer 0:c5e2f793b59a 2990 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 2991
screamer 0:c5e2f793b59a 2992 /*!
screamer 0:c5e2f793b59a 2993 * @addtogroup CMP_Register_Masks CMP Register Masks
screamer 0:c5e2f793b59a 2994 * @{
screamer 0:c5e2f793b59a 2995 */
screamer 0:c5e2f793b59a 2996
screamer 0:c5e2f793b59a 2997 /* CR0 Bit Fields */
screamer 0:c5e2f793b59a 2998 #define CMP_CR0_HYSTCTR_MASK 0x3u
screamer 0:c5e2f793b59a 2999 #define CMP_CR0_HYSTCTR_SHIFT 0
screamer 0:c5e2f793b59a 3000 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
screamer 0:c5e2f793b59a 3001 #define CMP_CR0_FILTER_CNT_MASK 0x70u
screamer 0:c5e2f793b59a 3002 #define CMP_CR0_FILTER_CNT_SHIFT 4
screamer 0:c5e2f793b59a 3003 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
screamer 0:c5e2f793b59a 3004 /* CR1 Bit Fields */
screamer 0:c5e2f793b59a 3005 #define CMP_CR1_EN_MASK 0x1u
screamer 0:c5e2f793b59a 3006 #define CMP_CR1_EN_SHIFT 0
screamer 0:c5e2f793b59a 3007 #define CMP_CR1_OPE_MASK 0x2u
screamer 0:c5e2f793b59a 3008 #define CMP_CR1_OPE_SHIFT 1
screamer 0:c5e2f793b59a 3009 #define CMP_CR1_COS_MASK 0x4u
screamer 0:c5e2f793b59a 3010 #define CMP_CR1_COS_SHIFT 2
screamer 0:c5e2f793b59a 3011 #define CMP_CR1_INV_MASK 0x8u
screamer 0:c5e2f793b59a 3012 #define CMP_CR1_INV_SHIFT 3
screamer 0:c5e2f793b59a 3013 #define CMP_CR1_PMODE_MASK 0x10u
screamer 0:c5e2f793b59a 3014 #define CMP_CR1_PMODE_SHIFT 4
screamer 0:c5e2f793b59a 3015 #define CMP_CR1_WE_MASK 0x40u
screamer 0:c5e2f793b59a 3016 #define CMP_CR1_WE_SHIFT 6
screamer 0:c5e2f793b59a 3017 #define CMP_CR1_SE_MASK 0x80u
screamer 0:c5e2f793b59a 3018 #define CMP_CR1_SE_SHIFT 7
screamer 0:c5e2f793b59a 3019 /* FPR Bit Fields */
screamer 0:c5e2f793b59a 3020 #define CMP_FPR_FILT_PER_MASK 0xFFu
screamer 0:c5e2f793b59a 3021 #define CMP_FPR_FILT_PER_SHIFT 0
screamer 0:c5e2f793b59a 3022 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
screamer 0:c5e2f793b59a 3023 /* SCR Bit Fields */
screamer 0:c5e2f793b59a 3024 #define CMP_SCR_COUT_MASK 0x1u
screamer 0:c5e2f793b59a 3025 #define CMP_SCR_COUT_SHIFT 0
screamer 0:c5e2f793b59a 3026 #define CMP_SCR_CFF_MASK 0x2u
screamer 0:c5e2f793b59a 3027 #define CMP_SCR_CFF_SHIFT 1
screamer 0:c5e2f793b59a 3028 #define CMP_SCR_CFR_MASK 0x4u
screamer 0:c5e2f793b59a 3029 #define CMP_SCR_CFR_SHIFT 2
screamer 0:c5e2f793b59a 3030 #define CMP_SCR_IEF_MASK 0x8u
screamer 0:c5e2f793b59a 3031 #define CMP_SCR_IEF_SHIFT 3
screamer 0:c5e2f793b59a 3032 #define CMP_SCR_IER_MASK 0x10u
screamer 0:c5e2f793b59a 3033 #define CMP_SCR_IER_SHIFT 4
screamer 0:c5e2f793b59a 3034 #define CMP_SCR_DMAEN_MASK 0x40u
screamer 0:c5e2f793b59a 3035 #define CMP_SCR_DMAEN_SHIFT 6
screamer 0:c5e2f793b59a 3036 /* DACCR Bit Fields */
screamer 0:c5e2f793b59a 3037 #define CMP_DACCR_VOSEL_MASK 0x3Fu
screamer 0:c5e2f793b59a 3038 #define CMP_DACCR_VOSEL_SHIFT 0
screamer 0:c5e2f793b59a 3039 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
screamer 0:c5e2f793b59a 3040 #define CMP_DACCR_VRSEL_MASK 0x40u
screamer 0:c5e2f793b59a 3041 #define CMP_DACCR_VRSEL_SHIFT 6
screamer 0:c5e2f793b59a 3042 #define CMP_DACCR_DACEN_MASK 0x80u
screamer 0:c5e2f793b59a 3043 #define CMP_DACCR_DACEN_SHIFT 7
screamer 0:c5e2f793b59a 3044 /* MUXCR Bit Fields */
screamer 0:c5e2f793b59a 3045 #define CMP_MUXCR_MSEL_MASK 0x7u
screamer 0:c5e2f793b59a 3046 #define CMP_MUXCR_MSEL_SHIFT 0
screamer 0:c5e2f793b59a 3047 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
screamer 0:c5e2f793b59a 3048 #define CMP_MUXCR_PSEL_MASK 0x38u
screamer 0:c5e2f793b59a 3049 #define CMP_MUXCR_PSEL_SHIFT 3
screamer 0:c5e2f793b59a 3050 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
screamer 0:c5e2f793b59a 3051 #define CMP_MUXCR_PSTM_MASK 0x80u
screamer 0:c5e2f793b59a 3052 #define CMP_MUXCR_PSTM_SHIFT 7
screamer 0:c5e2f793b59a 3053
screamer 0:c5e2f793b59a 3054 /*!
screamer 0:c5e2f793b59a 3055 * @}
screamer 0:c5e2f793b59a 3056 */ /* end of group CMP_Register_Masks */
screamer 0:c5e2f793b59a 3057
screamer 0:c5e2f793b59a 3058
screamer 0:c5e2f793b59a 3059 /* CMP - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 3060 /** Peripheral CMP0 base address */
screamer 0:c5e2f793b59a 3061 #define CMP0_BASE (0x40073000u)
screamer 0:c5e2f793b59a 3062 /** Peripheral CMP0 base pointer */
screamer 0:c5e2f793b59a 3063 #define CMP0 ((CMP_Type *)CMP0_BASE)
screamer 0:c5e2f793b59a 3064 #define CMP0_BASE_PTR (CMP0)
screamer 0:c5e2f793b59a 3065 /** Peripheral CMP1 base address */
screamer 0:c5e2f793b59a 3066 #define CMP1_BASE (0x40073008u)
screamer 0:c5e2f793b59a 3067 /** Peripheral CMP1 base pointer */
screamer 0:c5e2f793b59a 3068 #define CMP1 ((CMP_Type *)CMP1_BASE)
screamer 0:c5e2f793b59a 3069 #define CMP1_BASE_PTR (CMP1)
screamer 0:c5e2f793b59a 3070 /** Peripheral CMP2 base address */
screamer 0:c5e2f793b59a 3071 #define CMP2_BASE (0x40073010u)
screamer 0:c5e2f793b59a 3072 /** Peripheral CMP2 base pointer */
screamer 0:c5e2f793b59a 3073 #define CMP2 ((CMP_Type *)CMP2_BASE)
screamer 0:c5e2f793b59a 3074 #define CMP2_BASE_PTR (CMP2)
screamer 0:c5e2f793b59a 3075 /** Array initializer of CMP peripheral base addresses */
screamer 0:c5e2f793b59a 3076 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
screamer 0:c5e2f793b59a 3077 /** Array initializer of CMP peripheral base pointers */
screamer 0:c5e2f793b59a 3078 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
screamer 0:c5e2f793b59a 3079 /** Interrupt vectors for the CMP peripheral type */
screamer 0:c5e2f793b59a 3080 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
screamer 0:c5e2f793b59a 3081
screamer 0:c5e2f793b59a 3082 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3083 -- CMP - Register accessor macros
screamer 0:c5e2f793b59a 3084 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3085
screamer 0:c5e2f793b59a 3086 /*!
screamer 0:c5e2f793b59a 3087 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
screamer 0:c5e2f793b59a 3088 * @{
screamer 0:c5e2f793b59a 3089 */
screamer 0:c5e2f793b59a 3090
screamer 0:c5e2f793b59a 3091
screamer 0:c5e2f793b59a 3092 /* CMP - Register instance definitions */
screamer 0:c5e2f793b59a 3093 /* CMP0 */
screamer 0:c5e2f793b59a 3094 #define CMP0_CR0 CMP_CR0_REG(CMP0)
screamer 0:c5e2f793b59a 3095 #define CMP0_CR1 CMP_CR1_REG(CMP0)
screamer 0:c5e2f793b59a 3096 #define CMP0_FPR CMP_FPR_REG(CMP0)
screamer 0:c5e2f793b59a 3097 #define CMP0_SCR CMP_SCR_REG(CMP0)
screamer 0:c5e2f793b59a 3098 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
screamer 0:c5e2f793b59a 3099 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
screamer 0:c5e2f793b59a 3100 /* CMP1 */
screamer 0:c5e2f793b59a 3101 #define CMP1_CR0 CMP_CR0_REG(CMP1)
screamer 0:c5e2f793b59a 3102 #define CMP1_CR1 CMP_CR1_REG(CMP1)
screamer 0:c5e2f793b59a 3103 #define CMP1_FPR CMP_FPR_REG(CMP1)
screamer 0:c5e2f793b59a 3104 #define CMP1_SCR CMP_SCR_REG(CMP1)
screamer 0:c5e2f793b59a 3105 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
screamer 0:c5e2f793b59a 3106 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
screamer 0:c5e2f793b59a 3107 /* CMP2 */
screamer 0:c5e2f793b59a 3108 #define CMP2_CR0 CMP_CR0_REG(CMP2)
screamer 0:c5e2f793b59a 3109 #define CMP2_CR1 CMP_CR1_REG(CMP2)
screamer 0:c5e2f793b59a 3110 #define CMP2_FPR CMP_FPR_REG(CMP2)
screamer 0:c5e2f793b59a 3111 #define CMP2_SCR CMP_SCR_REG(CMP2)
screamer 0:c5e2f793b59a 3112 #define CMP2_DACCR CMP_DACCR_REG(CMP2)
screamer 0:c5e2f793b59a 3113 #define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
screamer 0:c5e2f793b59a 3114
screamer 0:c5e2f793b59a 3115 /*!
screamer 0:c5e2f793b59a 3116 * @}
screamer 0:c5e2f793b59a 3117 */ /* end of group CMP_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 3118
screamer 0:c5e2f793b59a 3119
screamer 0:c5e2f793b59a 3120 /*!
screamer 0:c5e2f793b59a 3121 * @}
screamer 0:c5e2f793b59a 3122 */ /* end of group CMP_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 3123
screamer 0:c5e2f793b59a 3124
screamer 0:c5e2f793b59a 3125 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3126 -- CMT Peripheral Access Layer
screamer 0:c5e2f793b59a 3127 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3128
screamer 0:c5e2f793b59a 3129 /*!
screamer 0:c5e2f793b59a 3130 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
screamer 0:c5e2f793b59a 3131 * @{
screamer 0:c5e2f793b59a 3132 */
screamer 0:c5e2f793b59a 3133
screamer 0:c5e2f793b59a 3134 /** CMT - Register Layout Typedef */
screamer 0:c5e2f793b59a 3135 typedef struct {
screamer 0:c5e2f793b59a 3136 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
screamer 0:c5e2f793b59a 3137 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
screamer 0:c5e2f793b59a 3138 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
screamer 0:c5e2f793b59a 3139 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
screamer 0:c5e2f793b59a 3140 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
screamer 0:c5e2f793b59a 3141 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
screamer 0:c5e2f793b59a 3142 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
screamer 0:c5e2f793b59a 3143 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
screamer 0:c5e2f793b59a 3144 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
screamer 0:c5e2f793b59a 3145 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
screamer 0:c5e2f793b59a 3146 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
screamer 0:c5e2f793b59a 3147 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
screamer 0:c5e2f793b59a 3148 } CMT_Type, *CMT_MemMapPtr;
screamer 0:c5e2f793b59a 3149
screamer 0:c5e2f793b59a 3150 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3151 -- CMT - Register accessor macros
screamer 0:c5e2f793b59a 3152 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3153
screamer 0:c5e2f793b59a 3154 /*!
screamer 0:c5e2f793b59a 3155 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
screamer 0:c5e2f793b59a 3156 * @{
screamer 0:c5e2f793b59a 3157 */
screamer 0:c5e2f793b59a 3158
screamer 0:c5e2f793b59a 3159
screamer 0:c5e2f793b59a 3160 /* CMT - Register accessors */
screamer 0:c5e2f793b59a 3161 #define CMT_CGH1_REG(base) ((base)->CGH1)
screamer 0:c5e2f793b59a 3162 #define CMT_CGL1_REG(base) ((base)->CGL1)
screamer 0:c5e2f793b59a 3163 #define CMT_CGH2_REG(base) ((base)->CGH2)
screamer 0:c5e2f793b59a 3164 #define CMT_CGL2_REG(base) ((base)->CGL2)
screamer 0:c5e2f793b59a 3165 #define CMT_OC_REG(base) ((base)->OC)
screamer 0:c5e2f793b59a 3166 #define CMT_MSC_REG(base) ((base)->MSC)
screamer 0:c5e2f793b59a 3167 #define CMT_CMD1_REG(base) ((base)->CMD1)
screamer 0:c5e2f793b59a 3168 #define CMT_CMD2_REG(base) ((base)->CMD2)
screamer 0:c5e2f793b59a 3169 #define CMT_CMD3_REG(base) ((base)->CMD3)
screamer 0:c5e2f793b59a 3170 #define CMT_CMD4_REG(base) ((base)->CMD4)
screamer 0:c5e2f793b59a 3171 #define CMT_PPS_REG(base) ((base)->PPS)
screamer 0:c5e2f793b59a 3172 #define CMT_DMA_REG(base) ((base)->DMA)
screamer 0:c5e2f793b59a 3173
screamer 0:c5e2f793b59a 3174 /*!
screamer 0:c5e2f793b59a 3175 * @}
screamer 0:c5e2f793b59a 3176 */ /* end of group CMT_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 3177
screamer 0:c5e2f793b59a 3178
screamer 0:c5e2f793b59a 3179 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3180 -- CMT Register Masks
screamer 0:c5e2f793b59a 3181 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3182
screamer 0:c5e2f793b59a 3183 /*!
screamer 0:c5e2f793b59a 3184 * @addtogroup CMT_Register_Masks CMT Register Masks
screamer 0:c5e2f793b59a 3185 * @{
screamer 0:c5e2f793b59a 3186 */
screamer 0:c5e2f793b59a 3187
screamer 0:c5e2f793b59a 3188 /* CGH1 Bit Fields */
screamer 0:c5e2f793b59a 3189 #define CMT_CGH1_PH_MASK 0xFFu
screamer 0:c5e2f793b59a 3190 #define CMT_CGH1_PH_SHIFT 0
screamer 0:c5e2f793b59a 3191 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
screamer 0:c5e2f793b59a 3192 /* CGL1 Bit Fields */
screamer 0:c5e2f793b59a 3193 #define CMT_CGL1_PL_MASK 0xFFu
screamer 0:c5e2f793b59a 3194 #define CMT_CGL1_PL_SHIFT 0
screamer 0:c5e2f793b59a 3195 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
screamer 0:c5e2f793b59a 3196 /* CGH2 Bit Fields */
screamer 0:c5e2f793b59a 3197 #define CMT_CGH2_SH_MASK 0xFFu
screamer 0:c5e2f793b59a 3198 #define CMT_CGH2_SH_SHIFT 0
screamer 0:c5e2f793b59a 3199 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
screamer 0:c5e2f793b59a 3200 /* CGL2 Bit Fields */
screamer 0:c5e2f793b59a 3201 #define CMT_CGL2_SL_MASK 0xFFu
screamer 0:c5e2f793b59a 3202 #define CMT_CGL2_SL_SHIFT 0
screamer 0:c5e2f793b59a 3203 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
screamer 0:c5e2f793b59a 3204 /* OC Bit Fields */
screamer 0:c5e2f793b59a 3205 #define CMT_OC_IROPEN_MASK 0x20u
screamer 0:c5e2f793b59a 3206 #define CMT_OC_IROPEN_SHIFT 5
screamer 0:c5e2f793b59a 3207 #define CMT_OC_CMTPOL_MASK 0x40u
screamer 0:c5e2f793b59a 3208 #define CMT_OC_CMTPOL_SHIFT 6
screamer 0:c5e2f793b59a 3209 #define CMT_OC_IROL_MASK 0x80u
screamer 0:c5e2f793b59a 3210 #define CMT_OC_IROL_SHIFT 7
screamer 0:c5e2f793b59a 3211 /* MSC Bit Fields */
screamer 0:c5e2f793b59a 3212 #define CMT_MSC_MCGEN_MASK 0x1u
screamer 0:c5e2f793b59a 3213 #define CMT_MSC_MCGEN_SHIFT 0
screamer 0:c5e2f793b59a 3214 #define CMT_MSC_EOCIE_MASK 0x2u
screamer 0:c5e2f793b59a 3215 #define CMT_MSC_EOCIE_SHIFT 1
screamer 0:c5e2f793b59a 3216 #define CMT_MSC_FSK_MASK 0x4u
screamer 0:c5e2f793b59a 3217 #define CMT_MSC_FSK_SHIFT 2
screamer 0:c5e2f793b59a 3218 #define CMT_MSC_BASE_MASK 0x8u
screamer 0:c5e2f793b59a 3219 #define CMT_MSC_BASE_SHIFT 3
screamer 0:c5e2f793b59a 3220 #define CMT_MSC_EXSPC_MASK 0x10u
screamer 0:c5e2f793b59a 3221 #define CMT_MSC_EXSPC_SHIFT 4
screamer 0:c5e2f793b59a 3222 #define CMT_MSC_CMTDIV_MASK 0x60u
screamer 0:c5e2f793b59a 3223 #define CMT_MSC_CMTDIV_SHIFT 5
screamer 0:c5e2f793b59a 3224 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
screamer 0:c5e2f793b59a 3225 #define CMT_MSC_EOCF_MASK 0x80u
screamer 0:c5e2f793b59a 3226 #define CMT_MSC_EOCF_SHIFT 7
screamer 0:c5e2f793b59a 3227 /* CMD1 Bit Fields */
screamer 0:c5e2f793b59a 3228 #define CMT_CMD1_MB_MASK 0xFFu
screamer 0:c5e2f793b59a 3229 #define CMT_CMD1_MB_SHIFT 0
screamer 0:c5e2f793b59a 3230 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
screamer 0:c5e2f793b59a 3231 /* CMD2 Bit Fields */
screamer 0:c5e2f793b59a 3232 #define CMT_CMD2_MB_MASK 0xFFu
screamer 0:c5e2f793b59a 3233 #define CMT_CMD2_MB_SHIFT 0
screamer 0:c5e2f793b59a 3234 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
screamer 0:c5e2f793b59a 3235 /* CMD3 Bit Fields */
screamer 0:c5e2f793b59a 3236 #define CMT_CMD3_SB_MASK 0xFFu
screamer 0:c5e2f793b59a 3237 #define CMT_CMD3_SB_SHIFT 0
screamer 0:c5e2f793b59a 3238 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
screamer 0:c5e2f793b59a 3239 /* CMD4 Bit Fields */
screamer 0:c5e2f793b59a 3240 #define CMT_CMD4_SB_MASK 0xFFu
screamer 0:c5e2f793b59a 3241 #define CMT_CMD4_SB_SHIFT 0
screamer 0:c5e2f793b59a 3242 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
screamer 0:c5e2f793b59a 3243 /* PPS Bit Fields */
screamer 0:c5e2f793b59a 3244 #define CMT_PPS_PPSDIV_MASK 0xFu
screamer 0:c5e2f793b59a 3245 #define CMT_PPS_PPSDIV_SHIFT 0
screamer 0:c5e2f793b59a 3246 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
screamer 0:c5e2f793b59a 3247 /* DMA Bit Fields */
screamer 0:c5e2f793b59a 3248 #define CMT_DMA_DMA_MASK 0x1u
screamer 0:c5e2f793b59a 3249 #define CMT_DMA_DMA_SHIFT 0
screamer 0:c5e2f793b59a 3250
screamer 0:c5e2f793b59a 3251 /*!
screamer 0:c5e2f793b59a 3252 * @}
screamer 0:c5e2f793b59a 3253 */ /* end of group CMT_Register_Masks */
screamer 0:c5e2f793b59a 3254
screamer 0:c5e2f793b59a 3255
screamer 0:c5e2f793b59a 3256 /* CMT - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 3257 /** Peripheral CMT base address */
screamer 0:c5e2f793b59a 3258 #define CMT_BASE (0x40062000u)
screamer 0:c5e2f793b59a 3259 /** Peripheral CMT base pointer */
screamer 0:c5e2f793b59a 3260 #define CMT ((CMT_Type *)CMT_BASE)
screamer 0:c5e2f793b59a 3261 #define CMT_BASE_PTR (CMT)
screamer 0:c5e2f793b59a 3262 /** Array initializer of CMT peripheral base addresses */
screamer 0:c5e2f793b59a 3263 #define CMT_BASE_ADDRS { CMT_BASE }
screamer 0:c5e2f793b59a 3264 /** Array initializer of CMT peripheral base pointers */
screamer 0:c5e2f793b59a 3265 #define CMT_BASE_PTRS { CMT }
screamer 0:c5e2f793b59a 3266 /** Interrupt vectors for the CMT peripheral type */
screamer 0:c5e2f793b59a 3267 #define CMT_IRQS { CMT_IRQn }
screamer 0:c5e2f793b59a 3268
screamer 0:c5e2f793b59a 3269 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3270 -- CMT - Register accessor macros
screamer 0:c5e2f793b59a 3271 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3272
screamer 0:c5e2f793b59a 3273 /*!
screamer 0:c5e2f793b59a 3274 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
screamer 0:c5e2f793b59a 3275 * @{
screamer 0:c5e2f793b59a 3276 */
screamer 0:c5e2f793b59a 3277
screamer 0:c5e2f793b59a 3278
screamer 0:c5e2f793b59a 3279 /* CMT - Register instance definitions */
screamer 0:c5e2f793b59a 3280 /* CMT */
screamer 0:c5e2f793b59a 3281 #define CMT_CGH1 CMT_CGH1_REG(CMT)
screamer 0:c5e2f793b59a 3282 #define CMT_CGL1 CMT_CGL1_REG(CMT)
screamer 0:c5e2f793b59a 3283 #define CMT_CGH2 CMT_CGH2_REG(CMT)
screamer 0:c5e2f793b59a 3284 #define CMT_CGL2 CMT_CGL2_REG(CMT)
screamer 0:c5e2f793b59a 3285 #define CMT_OC CMT_OC_REG(CMT)
screamer 0:c5e2f793b59a 3286 #define CMT_MSC CMT_MSC_REG(CMT)
screamer 0:c5e2f793b59a 3287 #define CMT_CMD1 CMT_CMD1_REG(CMT)
screamer 0:c5e2f793b59a 3288 #define CMT_CMD2 CMT_CMD2_REG(CMT)
screamer 0:c5e2f793b59a 3289 #define CMT_CMD3 CMT_CMD3_REG(CMT)
screamer 0:c5e2f793b59a 3290 #define CMT_CMD4 CMT_CMD4_REG(CMT)
screamer 0:c5e2f793b59a 3291 #define CMT_PPS CMT_PPS_REG(CMT)
screamer 0:c5e2f793b59a 3292 #define CMT_DMA CMT_DMA_REG(CMT)
screamer 0:c5e2f793b59a 3293
screamer 0:c5e2f793b59a 3294 /*!
screamer 0:c5e2f793b59a 3295 * @}
screamer 0:c5e2f793b59a 3296 */ /* end of group CMT_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 3297
screamer 0:c5e2f793b59a 3298
screamer 0:c5e2f793b59a 3299 /*!
screamer 0:c5e2f793b59a 3300 * @}
screamer 0:c5e2f793b59a 3301 */ /* end of group CMT_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 3302
screamer 0:c5e2f793b59a 3303
screamer 0:c5e2f793b59a 3304 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3305 -- CRC Peripheral Access Layer
screamer 0:c5e2f793b59a 3306 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3307
screamer 0:c5e2f793b59a 3308 /*!
screamer 0:c5e2f793b59a 3309 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
screamer 0:c5e2f793b59a 3310 * @{
screamer 0:c5e2f793b59a 3311 */
screamer 0:c5e2f793b59a 3312
screamer 0:c5e2f793b59a 3313 /** CRC - Register Layout Typedef */
screamer 0:c5e2f793b59a 3314 typedef struct {
screamer 0:c5e2f793b59a 3315 union { /* offset: 0x0 */
screamer 0:c5e2f793b59a 3316 struct { /* offset: 0x0 */
screamer 0:c5e2f793b59a 3317 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
screamer 0:c5e2f793b59a 3318 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
screamer 0:c5e2f793b59a 3319 } ACCESS16BIT;
screamer 0:c5e2f793b59a 3320 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
screamer 0:c5e2f793b59a 3321 struct { /* offset: 0x0 */
screamer 0:c5e2f793b59a 3322 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
screamer 0:c5e2f793b59a 3323 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
screamer 0:c5e2f793b59a 3324 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
screamer 0:c5e2f793b59a 3325 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
screamer 0:c5e2f793b59a 3326 } ACCESS8BIT;
screamer 0:c5e2f793b59a 3327 };
screamer 0:c5e2f793b59a 3328 union { /* offset: 0x4 */
screamer 0:c5e2f793b59a 3329 struct { /* offset: 0x4 */
screamer 0:c5e2f793b59a 3330 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
screamer 0:c5e2f793b59a 3331 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
screamer 0:c5e2f793b59a 3332 } GPOLY_ACCESS16BIT;
screamer 0:c5e2f793b59a 3333 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
screamer 0:c5e2f793b59a 3334 struct { /* offset: 0x4 */
screamer 0:c5e2f793b59a 3335 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
screamer 0:c5e2f793b59a 3336 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
screamer 0:c5e2f793b59a 3337 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
screamer 0:c5e2f793b59a 3338 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
screamer 0:c5e2f793b59a 3339 } GPOLY_ACCESS8BIT;
screamer 0:c5e2f793b59a 3340 };
screamer 0:c5e2f793b59a 3341 union { /* offset: 0x8 */
screamer 0:c5e2f793b59a 3342 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
screamer 0:c5e2f793b59a 3343 struct { /* offset: 0x8 */
screamer 0:c5e2f793b59a 3344 uint8_t RESERVED_0[3];
screamer 0:c5e2f793b59a 3345 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
screamer 0:c5e2f793b59a 3346 } CTRL_ACCESS8BIT;
screamer 0:c5e2f793b59a 3347 };
screamer 0:c5e2f793b59a 3348 } CRC_Type, *CRC_MemMapPtr;
screamer 0:c5e2f793b59a 3349
screamer 0:c5e2f793b59a 3350 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3351 -- CRC - Register accessor macros
screamer 0:c5e2f793b59a 3352 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3353
screamer 0:c5e2f793b59a 3354 /*!
screamer 0:c5e2f793b59a 3355 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
screamer 0:c5e2f793b59a 3356 * @{
screamer 0:c5e2f793b59a 3357 */
screamer 0:c5e2f793b59a 3358
screamer 0:c5e2f793b59a 3359
screamer 0:c5e2f793b59a 3360 /* CRC - Register accessors */
screamer 0:c5e2f793b59a 3361 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
screamer 0:c5e2f793b59a 3362 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
screamer 0:c5e2f793b59a 3363 #define CRC_DATA_REG(base) ((base)->DATA)
screamer 0:c5e2f793b59a 3364 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
screamer 0:c5e2f793b59a 3365 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
screamer 0:c5e2f793b59a 3366 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
screamer 0:c5e2f793b59a 3367 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
screamer 0:c5e2f793b59a 3368 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
screamer 0:c5e2f793b59a 3369 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
screamer 0:c5e2f793b59a 3370 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
screamer 0:c5e2f793b59a 3371 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
screamer 0:c5e2f793b59a 3372 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
screamer 0:c5e2f793b59a 3373 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
screamer 0:c5e2f793b59a 3374 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
screamer 0:c5e2f793b59a 3375 #define CRC_CTRL_REG(base) ((base)->CTRL)
screamer 0:c5e2f793b59a 3376 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
screamer 0:c5e2f793b59a 3377
screamer 0:c5e2f793b59a 3378 /*!
screamer 0:c5e2f793b59a 3379 * @}
screamer 0:c5e2f793b59a 3380 */ /* end of group CRC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 3381
screamer 0:c5e2f793b59a 3382
screamer 0:c5e2f793b59a 3383 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3384 -- CRC Register Masks
screamer 0:c5e2f793b59a 3385 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3386
screamer 0:c5e2f793b59a 3387 /*!
screamer 0:c5e2f793b59a 3388 * @addtogroup CRC_Register_Masks CRC Register Masks
screamer 0:c5e2f793b59a 3389 * @{
screamer 0:c5e2f793b59a 3390 */
screamer 0:c5e2f793b59a 3391
screamer 0:c5e2f793b59a 3392 /* DATAL Bit Fields */
screamer 0:c5e2f793b59a 3393 #define CRC_DATAL_DATAL_MASK 0xFFFFu
screamer 0:c5e2f793b59a 3394 #define CRC_DATAL_DATAL_SHIFT 0
screamer 0:c5e2f793b59a 3395 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
screamer 0:c5e2f793b59a 3396 /* DATAH Bit Fields */
screamer 0:c5e2f793b59a 3397 #define CRC_DATAH_DATAH_MASK 0xFFFFu
screamer 0:c5e2f793b59a 3398 #define CRC_DATAH_DATAH_SHIFT 0
screamer 0:c5e2f793b59a 3399 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
screamer 0:c5e2f793b59a 3400 /* DATA Bit Fields */
screamer 0:c5e2f793b59a 3401 #define CRC_DATA_LL_MASK 0xFFu
screamer 0:c5e2f793b59a 3402 #define CRC_DATA_LL_SHIFT 0
screamer 0:c5e2f793b59a 3403 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
screamer 0:c5e2f793b59a 3404 #define CRC_DATA_LU_MASK 0xFF00u
screamer 0:c5e2f793b59a 3405 #define CRC_DATA_LU_SHIFT 8
screamer 0:c5e2f793b59a 3406 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
screamer 0:c5e2f793b59a 3407 #define CRC_DATA_HL_MASK 0xFF0000u
screamer 0:c5e2f793b59a 3408 #define CRC_DATA_HL_SHIFT 16
screamer 0:c5e2f793b59a 3409 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
screamer 0:c5e2f793b59a 3410 #define CRC_DATA_HU_MASK 0xFF000000u
screamer 0:c5e2f793b59a 3411 #define CRC_DATA_HU_SHIFT 24
screamer 0:c5e2f793b59a 3412 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
screamer 0:c5e2f793b59a 3413 /* DATALL Bit Fields */
screamer 0:c5e2f793b59a 3414 #define CRC_DATALL_DATALL_MASK 0xFFu
screamer 0:c5e2f793b59a 3415 #define CRC_DATALL_DATALL_SHIFT 0
screamer 0:c5e2f793b59a 3416 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
screamer 0:c5e2f793b59a 3417 /* DATALU Bit Fields */
screamer 0:c5e2f793b59a 3418 #define CRC_DATALU_DATALU_MASK 0xFFu
screamer 0:c5e2f793b59a 3419 #define CRC_DATALU_DATALU_SHIFT 0
screamer 0:c5e2f793b59a 3420 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
screamer 0:c5e2f793b59a 3421 /* DATAHL Bit Fields */
screamer 0:c5e2f793b59a 3422 #define CRC_DATAHL_DATAHL_MASK 0xFFu
screamer 0:c5e2f793b59a 3423 #define CRC_DATAHL_DATAHL_SHIFT 0
screamer 0:c5e2f793b59a 3424 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
screamer 0:c5e2f793b59a 3425 /* DATAHU Bit Fields */
screamer 0:c5e2f793b59a 3426 #define CRC_DATAHU_DATAHU_MASK 0xFFu
screamer 0:c5e2f793b59a 3427 #define CRC_DATAHU_DATAHU_SHIFT 0
screamer 0:c5e2f793b59a 3428 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
screamer 0:c5e2f793b59a 3429 /* GPOLYL Bit Fields */
screamer 0:c5e2f793b59a 3430 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
screamer 0:c5e2f793b59a 3431 #define CRC_GPOLYL_GPOLYL_SHIFT 0
screamer 0:c5e2f793b59a 3432 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
screamer 0:c5e2f793b59a 3433 /* GPOLYH Bit Fields */
screamer 0:c5e2f793b59a 3434 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
screamer 0:c5e2f793b59a 3435 #define CRC_GPOLYH_GPOLYH_SHIFT 0
screamer 0:c5e2f793b59a 3436 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
screamer 0:c5e2f793b59a 3437 /* GPOLY Bit Fields */
screamer 0:c5e2f793b59a 3438 #define CRC_GPOLY_LOW_MASK 0xFFFFu
screamer 0:c5e2f793b59a 3439 #define CRC_GPOLY_LOW_SHIFT 0
screamer 0:c5e2f793b59a 3440 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
screamer 0:c5e2f793b59a 3441 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 3442 #define CRC_GPOLY_HIGH_SHIFT 16
screamer 0:c5e2f793b59a 3443 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
screamer 0:c5e2f793b59a 3444 /* GPOLYLL Bit Fields */
screamer 0:c5e2f793b59a 3445 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
screamer 0:c5e2f793b59a 3446 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
screamer 0:c5e2f793b59a 3447 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
screamer 0:c5e2f793b59a 3448 /* GPOLYLU Bit Fields */
screamer 0:c5e2f793b59a 3449 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
screamer 0:c5e2f793b59a 3450 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
screamer 0:c5e2f793b59a 3451 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
screamer 0:c5e2f793b59a 3452 /* GPOLYHL Bit Fields */
screamer 0:c5e2f793b59a 3453 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
screamer 0:c5e2f793b59a 3454 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
screamer 0:c5e2f793b59a 3455 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
screamer 0:c5e2f793b59a 3456 /* GPOLYHU Bit Fields */
screamer 0:c5e2f793b59a 3457 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
screamer 0:c5e2f793b59a 3458 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
screamer 0:c5e2f793b59a 3459 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
screamer 0:c5e2f793b59a 3460 /* CTRL Bit Fields */
screamer 0:c5e2f793b59a 3461 #define CRC_CTRL_TCRC_MASK 0x1000000u
screamer 0:c5e2f793b59a 3462 #define CRC_CTRL_TCRC_SHIFT 24
screamer 0:c5e2f793b59a 3463 #define CRC_CTRL_WAS_MASK 0x2000000u
screamer 0:c5e2f793b59a 3464 #define CRC_CTRL_WAS_SHIFT 25
screamer 0:c5e2f793b59a 3465 #define CRC_CTRL_FXOR_MASK 0x4000000u
screamer 0:c5e2f793b59a 3466 #define CRC_CTRL_FXOR_SHIFT 26
screamer 0:c5e2f793b59a 3467 #define CRC_CTRL_TOTR_MASK 0x30000000u
screamer 0:c5e2f793b59a 3468 #define CRC_CTRL_TOTR_SHIFT 28
screamer 0:c5e2f793b59a 3469 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
screamer 0:c5e2f793b59a 3470 #define CRC_CTRL_TOT_MASK 0xC0000000u
screamer 0:c5e2f793b59a 3471 #define CRC_CTRL_TOT_SHIFT 30
screamer 0:c5e2f793b59a 3472 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
screamer 0:c5e2f793b59a 3473 /* CTRLHU Bit Fields */
screamer 0:c5e2f793b59a 3474 #define CRC_CTRLHU_TCRC_MASK 0x1u
screamer 0:c5e2f793b59a 3475 #define CRC_CTRLHU_TCRC_SHIFT 0
screamer 0:c5e2f793b59a 3476 #define CRC_CTRLHU_WAS_MASK 0x2u
screamer 0:c5e2f793b59a 3477 #define CRC_CTRLHU_WAS_SHIFT 1
screamer 0:c5e2f793b59a 3478 #define CRC_CTRLHU_FXOR_MASK 0x4u
screamer 0:c5e2f793b59a 3479 #define CRC_CTRLHU_FXOR_SHIFT 2
screamer 0:c5e2f793b59a 3480 #define CRC_CTRLHU_TOTR_MASK 0x30u
screamer 0:c5e2f793b59a 3481 #define CRC_CTRLHU_TOTR_SHIFT 4
screamer 0:c5e2f793b59a 3482 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
screamer 0:c5e2f793b59a 3483 #define CRC_CTRLHU_TOT_MASK 0xC0u
screamer 0:c5e2f793b59a 3484 #define CRC_CTRLHU_TOT_SHIFT 6
screamer 0:c5e2f793b59a 3485 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
screamer 0:c5e2f793b59a 3486
screamer 0:c5e2f793b59a 3487 /*!
screamer 0:c5e2f793b59a 3488 * @}
screamer 0:c5e2f793b59a 3489 */ /* end of group CRC_Register_Masks */
screamer 0:c5e2f793b59a 3490
screamer 0:c5e2f793b59a 3491
screamer 0:c5e2f793b59a 3492 /* CRC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 3493 /** Peripheral CRC base address */
screamer 0:c5e2f793b59a 3494 #define CRC_BASE (0x40032000u)
screamer 0:c5e2f793b59a 3495 /** Peripheral CRC base pointer */
screamer 0:c5e2f793b59a 3496 #define CRC0 ((CRC_Type *)CRC_BASE)
screamer 0:c5e2f793b59a 3497 #define CRC_BASE_PTR (CRC0)
screamer 0:c5e2f793b59a 3498 /** Array initializer of CRC peripheral base addresses */
screamer 0:c5e2f793b59a 3499 #define CRC_BASE_ADDRS { CRC_BASE }
screamer 0:c5e2f793b59a 3500 /** Array initializer of CRC peripheral base pointers */
screamer 0:c5e2f793b59a 3501 #define CRC_BASE_PTRS { CRC0 }
screamer 0:c5e2f793b59a 3502
screamer 0:c5e2f793b59a 3503 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3504 -- CRC - Register accessor macros
screamer 0:c5e2f793b59a 3505 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3506
screamer 0:c5e2f793b59a 3507 /*!
screamer 0:c5e2f793b59a 3508 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
screamer 0:c5e2f793b59a 3509 * @{
screamer 0:c5e2f793b59a 3510 */
screamer 0:c5e2f793b59a 3511
screamer 0:c5e2f793b59a 3512
screamer 0:c5e2f793b59a 3513 /* CRC - Register instance definitions */
screamer 0:c5e2f793b59a 3514 /* CRC */
screamer 0:c5e2f793b59a 3515 #define CRC_DATA CRC_DATA_REG(CRC0)
screamer 0:c5e2f793b59a 3516 #define CRC_DATAL CRC_DATAL_REG(CRC0)
screamer 0:c5e2f793b59a 3517 #define CRC_DATALL CRC_DATALL_REG(CRC0)
screamer 0:c5e2f793b59a 3518 #define CRC_DATALU CRC_DATALU_REG(CRC0)
screamer 0:c5e2f793b59a 3519 #define CRC_DATAH CRC_DATAH_REG(CRC0)
screamer 0:c5e2f793b59a 3520 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
screamer 0:c5e2f793b59a 3521 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
screamer 0:c5e2f793b59a 3522 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
screamer 0:c5e2f793b59a 3523 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
screamer 0:c5e2f793b59a 3524 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
screamer 0:c5e2f793b59a 3525 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
screamer 0:c5e2f793b59a 3526 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
screamer 0:c5e2f793b59a 3527 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
screamer 0:c5e2f793b59a 3528 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
screamer 0:c5e2f793b59a 3529 #define CRC_CTRL CRC_CTRL_REG(CRC0)
screamer 0:c5e2f793b59a 3530 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
screamer 0:c5e2f793b59a 3531
screamer 0:c5e2f793b59a 3532 /*!
screamer 0:c5e2f793b59a 3533 * @}
screamer 0:c5e2f793b59a 3534 */ /* end of group CRC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 3535
screamer 0:c5e2f793b59a 3536
screamer 0:c5e2f793b59a 3537 /*!
screamer 0:c5e2f793b59a 3538 * @}
screamer 0:c5e2f793b59a 3539 */ /* end of group CRC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 3540
screamer 0:c5e2f793b59a 3541
screamer 0:c5e2f793b59a 3542 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3543 -- DAC Peripheral Access Layer
screamer 0:c5e2f793b59a 3544 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3545
screamer 0:c5e2f793b59a 3546 /*!
screamer 0:c5e2f793b59a 3547 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
screamer 0:c5e2f793b59a 3548 * @{
screamer 0:c5e2f793b59a 3549 */
screamer 0:c5e2f793b59a 3550
screamer 0:c5e2f793b59a 3551 /** DAC - Register Layout Typedef */
screamer 0:c5e2f793b59a 3552 typedef struct {
screamer 0:c5e2f793b59a 3553 struct { /* offset: 0x0, array step: 0x2 */
screamer 0:c5e2f793b59a 3554 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
screamer 0:c5e2f793b59a 3555 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
screamer 0:c5e2f793b59a 3556 } DAT[16];
screamer 0:c5e2f793b59a 3557 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
screamer 0:c5e2f793b59a 3558 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
screamer 0:c5e2f793b59a 3559 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
screamer 0:c5e2f793b59a 3560 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
screamer 0:c5e2f793b59a 3561 } DAC_Type, *DAC_MemMapPtr;
screamer 0:c5e2f793b59a 3562
screamer 0:c5e2f793b59a 3563 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3564 -- DAC - Register accessor macros
screamer 0:c5e2f793b59a 3565 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3566
screamer 0:c5e2f793b59a 3567 /*!
screamer 0:c5e2f793b59a 3568 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
screamer 0:c5e2f793b59a 3569 * @{
screamer 0:c5e2f793b59a 3570 */
screamer 0:c5e2f793b59a 3571
screamer 0:c5e2f793b59a 3572
screamer 0:c5e2f793b59a 3573 /* DAC - Register accessors */
screamer 0:c5e2f793b59a 3574 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
screamer 0:c5e2f793b59a 3575 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
screamer 0:c5e2f793b59a 3576 #define DAC_SR_REG(base) ((base)->SR)
screamer 0:c5e2f793b59a 3577 #define DAC_C0_REG(base) ((base)->C0)
screamer 0:c5e2f793b59a 3578 #define DAC_C1_REG(base) ((base)->C1)
screamer 0:c5e2f793b59a 3579 #define DAC_C2_REG(base) ((base)->C2)
screamer 0:c5e2f793b59a 3580
screamer 0:c5e2f793b59a 3581 /*!
screamer 0:c5e2f793b59a 3582 * @}
screamer 0:c5e2f793b59a 3583 */ /* end of group DAC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 3584
screamer 0:c5e2f793b59a 3585
screamer 0:c5e2f793b59a 3586 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3587 -- DAC Register Masks
screamer 0:c5e2f793b59a 3588 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3589
screamer 0:c5e2f793b59a 3590 /*!
screamer 0:c5e2f793b59a 3591 * @addtogroup DAC_Register_Masks DAC Register Masks
screamer 0:c5e2f793b59a 3592 * @{
screamer 0:c5e2f793b59a 3593 */
screamer 0:c5e2f793b59a 3594
screamer 0:c5e2f793b59a 3595 /* DATL Bit Fields */
screamer 0:c5e2f793b59a 3596 #define DAC_DATL_DATA0_MASK 0xFFu
screamer 0:c5e2f793b59a 3597 #define DAC_DATL_DATA0_SHIFT 0
screamer 0:c5e2f793b59a 3598 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
screamer 0:c5e2f793b59a 3599 /* DATH Bit Fields */
screamer 0:c5e2f793b59a 3600 #define DAC_DATH_DATA1_MASK 0xFu
screamer 0:c5e2f793b59a 3601 #define DAC_DATH_DATA1_SHIFT 0
screamer 0:c5e2f793b59a 3602 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
screamer 0:c5e2f793b59a 3603 /* SR Bit Fields */
screamer 0:c5e2f793b59a 3604 #define DAC_SR_DACBFRPBF_MASK 0x1u
screamer 0:c5e2f793b59a 3605 #define DAC_SR_DACBFRPBF_SHIFT 0
screamer 0:c5e2f793b59a 3606 #define DAC_SR_DACBFRPTF_MASK 0x2u
screamer 0:c5e2f793b59a 3607 #define DAC_SR_DACBFRPTF_SHIFT 1
screamer 0:c5e2f793b59a 3608 #define DAC_SR_DACBFWMF_MASK 0x4u
screamer 0:c5e2f793b59a 3609 #define DAC_SR_DACBFWMF_SHIFT 2
screamer 0:c5e2f793b59a 3610 /* C0 Bit Fields */
screamer 0:c5e2f793b59a 3611 #define DAC_C0_DACBBIEN_MASK 0x1u
screamer 0:c5e2f793b59a 3612 #define DAC_C0_DACBBIEN_SHIFT 0
screamer 0:c5e2f793b59a 3613 #define DAC_C0_DACBTIEN_MASK 0x2u
screamer 0:c5e2f793b59a 3614 #define DAC_C0_DACBTIEN_SHIFT 1
screamer 0:c5e2f793b59a 3615 #define DAC_C0_DACBWIEN_MASK 0x4u
screamer 0:c5e2f793b59a 3616 #define DAC_C0_DACBWIEN_SHIFT 2
screamer 0:c5e2f793b59a 3617 #define DAC_C0_LPEN_MASK 0x8u
screamer 0:c5e2f793b59a 3618 #define DAC_C0_LPEN_SHIFT 3
screamer 0:c5e2f793b59a 3619 #define DAC_C0_DACSWTRG_MASK 0x10u
screamer 0:c5e2f793b59a 3620 #define DAC_C0_DACSWTRG_SHIFT 4
screamer 0:c5e2f793b59a 3621 #define DAC_C0_DACTRGSEL_MASK 0x20u
screamer 0:c5e2f793b59a 3622 #define DAC_C0_DACTRGSEL_SHIFT 5
screamer 0:c5e2f793b59a 3623 #define DAC_C0_DACRFS_MASK 0x40u
screamer 0:c5e2f793b59a 3624 #define DAC_C0_DACRFS_SHIFT 6
screamer 0:c5e2f793b59a 3625 #define DAC_C0_DACEN_MASK 0x80u
screamer 0:c5e2f793b59a 3626 #define DAC_C0_DACEN_SHIFT 7
screamer 0:c5e2f793b59a 3627 /* C1 Bit Fields */
screamer 0:c5e2f793b59a 3628 #define DAC_C1_DACBFEN_MASK 0x1u
screamer 0:c5e2f793b59a 3629 #define DAC_C1_DACBFEN_SHIFT 0
screamer 0:c5e2f793b59a 3630 #define DAC_C1_DACBFMD_MASK 0x6u
screamer 0:c5e2f793b59a 3631 #define DAC_C1_DACBFMD_SHIFT 1
screamer 0:c5e2f793b59a 3632 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
screamer 0:c5e2f793b59a 3633 #define DAC_C1_DACBFWM_MASK 0x18u
screamer 0:c5e2f793b59a 3634 #define DAC_C1_DACBFWM_SHIFT 3
screamer 0:c5e2f793b59a 3635 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
screamer 0:c5e2f793b59a 3636 #define DAC_C1_DMAEN_MASK 0x80u
screamer 0:c5e2f793b59a 3637 #define DAC_C1_DMAEN_SHIFT 7
screamer 0:c5e2f793b59a 3638 /* C2 Bit Fields */
screamer 0:c5e2f793b59a 3639 #define DAC_C2_DACBFUP_MASK 0xFu
screamer 0:c5e2f793b59a 3640 #define DAC_C2_DACBFUP_SHIFT 0
screamer 0:c5e2f793b59a 3641 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
screamer 0:c5e2f793b59a 3642 #define DAC_C2_DACBFRP_MASK 0xF0u
screamer 0:c5e2f793b59a 3643 #define DAC_C2_DACBFRP_SHIFT 4
screamer 0:c5e2f793b59a 3644 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
screamer 0:c5e2f793b59a 3645
screamer 0:c5e2f793b59a 3646 /*!
screamer 0:c5e2f793b59a 3647 * @}
screamer 0:c5e2f793b59a 3648 */ /* end of group DAC_Register_Masks */
screamer 0:c5e2f793b59a 3649
screamer 0:c5e2f793b59a 3650
screamer 0:c5e2f793b59a 3651 /* DAC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 3652 /** Peripheral DAC0 base address */
screamer 0:c5e2f793b59a 3653 #define DAC0_BASE (0x400CC000u)
screamer 0:c5e2f793b59a 3654 /** Peripheral DAC0 base pointer */
screamer 0:c5e2f793b59a 3655 #define DAC0 ((DAC_Type *)DAC0_BASE)
screamer 0:c5e2f793b59a 3656 #define DAC0_BASE_PTR (DAC0)
screamer 0:c5e2f793b59a 3657 /** Peripheral DAC1 base address */
screamer 0:c5e2f793b59a 3658 #define DAC1_BASE (0x400CD000u)
screamer 0:c5e2f793b59a 3659 /** Peripheral DAC1 base pointer */
screamer 0:c5e2f793b59a 3660 #define DAC1 ((DAC_Type *)DAC1_BASE)
screamer 0:c5e2f793b59a 3661 #define DAC1_BASE_PTR (DAC1)
screamer 0:c5e2f793b59a 3662 /** Array initializer of DAC peripheral base addresses */
screamer 0:c5e2f793b59a 3663 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
screamer 0:c5e2f793b59a 3664 /** Array initializer of DAC peripheral base pointers */
screamer 0:c5e2f793b59a 3665 #define DAC_BASE_PTRS { DAC0, DAC1 }
screamer 0:c5e2f793b59a 3666 /** Interrupt vectors for the DAC peripheral type */
screamer 0:c5e2f793b59a 3667 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
screamer 0:c5e2f793b59a 3668
screamer 0:c5e2f793b59a 3669 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3670 -- DAC - Register accessor macros
screamer 0:c5e2f793b59a 3671 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3672
screamer 0:c5e2f793b59a 3673 /*!
screamer 0:c5e2f793b59a 3674 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
screamer 0:c5e2f793b59a 3675 * @{
screamer 0:c5e2f793b59a 3676 */
screamer 0:c5e2f793b59a 3677
screamer 0:c5e2f793b59a 3678
screamer 0:c5e2f793b59a 3679 /* DAC - Register instance definitions */
screamer 0:c5e2f793b59a 3680 /* DAC0 */
screamer 0:c5e2f793b59a 3681 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
screamer 0:c5e2f793b59a 3682 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
screamer 0:c5e2f793b59a 3683 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
screamer 0:c5e2f793b59a 3684 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
screamer 0:c5e2f793b59a 3685 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
screamer 0:c5e2f793b59a 3686 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
screamer 0:c5e2f793b59a 3687 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
screamer 0:c5e2f793b59a 3688 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
screamer 0:c5e2f793b59a 3689 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
screamer 0:c5e2f793b59a 3690 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
screamer 0:c5e2f793b59a 3691 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
screamer 0:c5e2f793b59a 3692 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
screamer 0:c5e2f793b59a 3693 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
screamer 0:c5e2f793b59a 3694 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
screamer 0:c5e2f793b59a 3695 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
screamer 0:c5e2f793b59a 3696 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
screamer 0:c5e2f793b59a 3697 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
screamer 0:c5e2f793b59a 3698 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
screamer 0:c5e2f793b59a 3699 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
screamer 0:c5e2f793b59a 3700 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
screamer 0:c5e2f793b59a 3701 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
screamer 0:c5e2f793b59a 3702 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
screamer 0:c5e2f793b59a 3703 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
screamer 0:c5e2f793b59a 3704 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
screamer 0:c5e2f793b59a 3705 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
screamer 0:c5e2f793b59a 3706 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
screamer 0:c5e2f793b59a 3707 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
screamer 0:c5e2f793b59a 3708 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
screamer 0:c5e2f793b59a 3709 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
screamer 0:c5e2f793b59a 3710 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
screamer 0:c5e2f793b59a 3711 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
screamer 0:c5e2f793b59a 3712 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
screamer 0:c5e2f793b59a 3713 #define DAC0_SR DAC_SR_REG(DAC0)
screamer 0:c5e2f793b59a 3714 #define DAC0_C0 DAC_C0_REG(DAC0)
screamer 0:c5e2f793b59a 3715 #define DAC0_C1 DAC_C1_REG(DAC0)
screamer 0:c5e2f793b59a 3716 #define DAC0_C2 DAC_C2_REG(DAC0)
screamer 0:c5e2f793b59a 3717 /* DAC1 */
screamer 0:c5e2f793b59a 3718 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
screamer 0:c5e2f793b59a 3719 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
screamer 0:c5e2f793b59a 3720 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
screamer 0:c5e2f793b59a 3721 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
screamer 0:c5e2f793b59a 3722 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
screamer 0:c5e2f793b59a 3723 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
screamer 0:c5e2f793b59a 3724 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
screamer 0:c5e2f793b59a 3725 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
screamer 0:c5e2f793b59a 3726 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
screamer 0:c5e2f793b59a 3727 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
screamer 0:c5e2f793b59a 3728 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
screamer 0:c5e2f793b59a 3729 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
screamer 0:c5e2f793b59a 3730 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
screamer 0:c5e2f793b59a 3731 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
screamer 0:c5e2f793b59a 3732 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
screamer 0:c5e2f793b59a 3733 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
screamer 0:c5e2f793b59a 3734 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
screamer 0:c5e2f793b59a 3735 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
screamer 0:c5e2f793b59a 3736 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
screamer 0:c5e2f793b59a 3737 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
screamer 0:c5e2f793b59a 3738 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
screamer 0:c5e2f793b59a 3739 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
screamer 0:c5e2f793b59a 3740 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
screamer 0:c5e2f793b59a 3741 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
screamer 0:c5e2f793b59a 3742 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
screamer 0:c5e2f793b59a 3743 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
screamer 0:c5e2f793b59a 3744 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
screamer 0:c5e2f793b59a 3745 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
screamer 0:c5e2f793b59a 3746 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
screamer 0:c5e2f793b59a 3747 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
screamer 0:c5e2f793b59a 3748 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
screamer 0:c5e2f793b59a 3749 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
screamer 0:c5e2f793b59a 3750 #define DAC1_SR DAC_SR_REG(DAC1)
screamer 0:c5e2f793b59a 3751 #define DAC1_C0 DAC_C0_REG(DAC1)
screamer 0:c5e2f793b59a 3752 #define DAC1_C1 DAC_C1_REG(DAC1)
screamer 0:c5e2f793b59a 3753 #define DAC1_C2 DAC_C2_REG(DAC1)
screamer 0:c5e2f793b59a 3754
screamer 0:c5e2f793b59a 3755 /* DAC - Register array accessors */
screamer 0:c5e2f793b59a 3756 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
screamer 0:c5e2f793b59a 3757 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
screamer 0:c5e2f793b59a 3758 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
screamer 0:c5e2f793b59a 3759 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
screamer 0:c5e2f793b59a 3760
screamer 0:c5e2f793b59a 3761 /*!
screamer 0:c5e2f793b59a 3762 * @}
screamer 0:c5e2f793b59a 3763 */ /* end of group DAC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 3764
screamer 0:c5e2f793b59a 3765
screamer 0:c5e2f793b59a 3766 /*!
screamer 0:c5e2f793b59a 3767 * @}
screamer 0:c5e2f793b59a 3768 */ /* end of group DAC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 3769
screamer 0:c5e2f793b59a 3770
screamer 0:c5e2f793b59a 3771 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3772 -- DMA Peripheral Access Layer
screamer 0:c5e2f793b59a 3773 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3774
screamer 0:c5e2f793b59a 3775 /*!
screamer 0:c5e2f793b59a 3776 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
screamer 0:c5e2f793b59a 3777 * @{
screamer 0:c5e2f793b59a 3778 */
screamer 0:c5e2f793b59a 3779
screamer 0:c5e2f793b59a 3780 /** DMA - Register Layout Typedef */
screamer 0:c5e2f793b59a 3781 typedef struct {
screamer 0:c5e2f793b59a 3782 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
screamer 0:c5e2f793b59a 3783 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
screamer 0:c5e2f793b59a 3784 uint8_t RESERVED_0[4];
screamer 0:c5e2f793b59a 3785 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
screamer 0:c5e2f793b59a 3786 uint8_t RESERVED_1[4];
screamer 0:c5e2f793b59a 3787 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
screamer 0:c5e2f793b59a 3788 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
screamer 0:c5e2f793b59a 3789 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
screamer 0:c5e2f793b59a 3790 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
screamer 0:c5e2f793b59a 3791 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
screamer 0:c5e2f793b59a 3792 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
screamer 0:c5e2f793b59a 3793 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
screamer 0:c5e2f793b59a 3794 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
screamer 0:c5e2f793b59a 3795 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
screamer 0:c5e2f793b59a 3796 uint8_t RESERVED_2[4];
screamer 0:c5e2f793b59a 3797 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
screamer 0:c5e2f793b59a 3798 uint8_t RESERVED_3[4];
screamer 0:c5e2f793b59a 3799 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
screamer 0:c5e2f793b59a 3800 uint8_t RESERVED_4[4];
screamer 0:c5e2f793b59a 3801 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
screamer 0:c5e2f793b59a 3802 uint8_t RESERVED_5[200];
screamer 0:c5e2f793b59a 3803 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
screamer 0:c5e2f793b59a 3804 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
screamer 0:c5e2f793b59a 3805 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
screamer 0:c5e2f793b59a 3806 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
screamer 0:c5e2f793b59a 3807 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
screamer 0:c5e2f793b59a 3808 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
screamer 0:c5e2f793b59a 3809 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
screamer 0:c5e2f793b59a 3810 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
screamer 0:c5e2f793b59a 3811 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
screamer 0:c5e2f793b59a 3812 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
screamer 0:c5e2f793b59a 3813 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
screamer 0:c5e2f793b59a 3814 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
screamer 0:c5e2f793b59a 3815 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
screamer 0:c5e2f793b59a 3816 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
screamer 0:c5e2f793b59a 3817 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
screamer 0:c5e2f793b59a 3818 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
screamer 0:c5e2f793b59a 3819 uint8_t RESERVED_6[3824];
screamer 0:c5e2f793b59a 3820 struct { /* offset: 0x1000, array step: 0x20 */
screamer 0:c5e2f793b59a 3821 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
screamer 0:c5e2f793b59a 3822 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
screamer 0:c5e2f793b59a 3823 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
screamer 0:c5e2f793b59a 3824 union { /* offset: 0x1008, array step: 0x20 */
screamer 0:c5e2f793b59a 3825 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
screamer 0:c5e2f793b59a 3826 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
screamer 0:c5e2f793b59a 3827 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
screamer 0:c5e2f793b59a 3828 };
screamer 0:c5e2f793b59a 3829 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
screamer 0:c5e2f793b59a 3830 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
screamer 0:c5e2f793b59a 3831 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
screamer 0:c5e2f793b59a 3832 union { /* offset: 0x1016, array step: 0x20 */
screamer 0:c5e2f793b59a 3833 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
screamer 0:c5e2f793b59a 3834 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
screamer 0:c5e2f793b59a 3835 };
screamer 0:c5e2f793b59a 3836 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
screamer 0:c5e2f793b59a 3837 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
screamer 0:c5e2f793b59a 3838 union { /* offset: 0x101E, array step: 0x20 */
screamer 0:c5e2f793b59a 3839 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
screamer 0:c5e2f793b59a 3840 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
screamer 0:c5e2f793b59a 3841 };
screamer 0:c5e2f793b59a 3842 } TCD[16];
screamer 0:c5e2f793b59a 3843 } DMA_Type, *DMA_MemMapPtr;
screamer 0:c5e2f793b59a 3844
screamer 0:c5e2f793b59a 3845 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3846 -- DMA - Register accessor macros
screamer 0:c5e2f793b59a 3847 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3848
screamer 0:c5e2f793b59a 3849 /*!
screamer 0:c5e2f793b59a 3850 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
screamer 0:c5e2f793b59a 3851 * @{
screamer 0:c5e2f793b59a 3852 */
screamer 0:c5e2f793b59a 3853
screamer 0:c5e2f793b59a 3854
screamer 0:c5e2f793b59a 3855 /* DMA - Register accessors */
screamer 0:c5e2f793b59a 3856 #define DMA_CR_REG(base) ((base)->CR)
screamer 0:c5e2f793b59a 3857 #define DMA_ES_REG(base) ((base)->ES)
screamer 0:c5e2f793b59a 3858 #define DMA_ERQ_REG(base) ((base)->ERQ)
screamer 0:c5e2f793b59a 3859 #define DMA_EEI_REG(base) ((base)->EEI)
screamer 0:c5e2f793b59a 3860 #define DMA_CEEI_REG(base) ((base)->CEEI)
screamer 0:c5e2f793b59a 3861 #define DMA_SEEI_REG(base) ((base)->SEEI)
screamer 0:c5e2f793b59a 3862 #define DMA_CERQ_REG(base) ((base)->CERQ)
screamer 0:c5e2f793b59a 3863 #define DMA_SERQ_REG(base) ((base)->SERQ)
screamer 0:c5e2f793b59a 3864 #define DMA_CDNE_REG(base) ((base)->CDNE)
screamer 0:c5e2f793b59a 3865 #define DMA_SSRT_REG(base) ((base)->SSRT)
screamer 0:c5e2f793b59a 3866 #define DMA_CERR_REG(base) ((base)->CERR)
screamer 0:c5e2f793b59a 3867 #define DMA_CINT_REG(base) ((base)->CINT)
screamer 0:c5e2f793b59a 3868 #define DMA_INT_REG(base) ((base)->INT)
screamer 0:c5e2f793b59a 3869 #define DMA_ERR_REG(base) ((base)->ERR)
screamer 0:c5e2f793b59a 3870 #define DMA_HRS_REG(base) ((base)->HRS)
screamer 0:c5e2f793b59a 3871 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
screamer 0:c5e2f793b59a 3872 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
screamer 0:c5e2f793b59a 3873 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
screamer 0:c5e2f793b59a 3874 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
screamer 0:c5e2f793b59a 3875 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
screamer 0:c5e2f793b59a 3876 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
screamer 0:c5e2f793b59a 3877 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
screamer 0:c5e2f793b59a 3878 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
screamer 0:c5e2f793b59a 3879 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
screamer 0:c5e2f793b59a 3880 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
screamer 0:c5e2f793b59a 3881 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
screamer 0:c5e2f793b59a 3882 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
screamer 0:c5e2f793b59a 3883 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
screamer 0:c5e2f793b59a 3884 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
screamer 0:c5e2f793b59a 3885 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
screamer 0:c5e2f793b59a 3886 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
screamer 0:c5e2f793b59a 3887 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
screamer 0:c5e2f793b59a 3888 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
screamer 0:c5e2f793b59a 3889 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
screamer 0:c5e2f793b59a 3890 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
screamer 0:c5e2f793b59a 3891 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
screamer 0:c5e2f793b59a 3892 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
screamer 0:c5e2f793b59a 3893 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
screamer 0:c5e2f793b59a 3894 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
screamer 0:c5e2f793b59a 3895 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
screamer 0:c5e2f793b59a 3896 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
screamer 0:c5e2f793b59a 3897 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
screamer 0:c5e2f793b59a 3898 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
screamer 0:c5e2f793b59a 3899 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
screamer 0:c5e2f793b59a 3900 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
screamer 0:c5e2f793b59a 3901 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
screamer 0:c5e2f793b59a 3902
screamer 0:c5e2f793b59a 3903 /*!
screamer 0:c5e2f793b59a 3904 * @}
screamer 0:c5e2f793b59a 3905 */ /* end of group DMA_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 3906
screamer 0:c5e2f793b59a 3907
screamer 0:c5e2f793b59a 3908 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 3909 -- DMA Register Masks
screamer 0:c5e2f793b59a 3910 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 3911
screamer 0:c5e2f793b59a 3912 /*!
screamer 0:c5e2f793b59a 3913 * @addtogroup DMA_Register_Masks DMA Register Masks
screamer 0:c5e2f793b59a 3914 * @{
screamer 0:c5e2f793b59a 3915 */
screamer 0:c5e2f793b59a 3916
screamer 0:c5e2f793b59a 3917 /* CR Bit Fields */
screamer 0:c5e2f793b59a 3918 #define DMA_CR_EDBG_MASK 0x2u
screamer 0:c5e2f793b59a 3919 #define DMA_CR_EDBG_SHIFT 1
screamer 0:c5e2f793b59a 3920 #define DMA_CR_ERCA_MASK 0x4u
screamer 0:c5e2f793b59a 3921 #define DMA_CR_ERCA_SHIFT 2
screamer 0:c5e2f793b59a 3922 #define DMA_CR_HOE_MASK 0x10u
screamer 0:c5e2f793b59a 3923 #define DMA_CR_HOE_SHIFT 4
screamer 0:c5e2f793b59a 3924 #define DMA_CR_HALT_MASK 0x20u
screamer 0:c5e2f793b59a 3925 #define DMA_CR_HALT_SHIFT 5
screamer 0:c5e2f793b59a 3926 #define DMA_CR_CLM_MASK 0x40u
screamer 0:c5e2f793b59a 3927 #define DMA_CR_CLM_SHIFT 6
screamer 0:c5e2f793b59a 3928 #define DMA_CR_EMLM_MASK 0x80u
screamer 0:c5e2f793b59a 3929 #define DMA_CR_EMLM_SHIFT 7
screamer 0:c5e2f793b59a 3930 #define DMA_CR_ECX_MASK 0x10000u
screamer 0:c5e2f793b59a 3931 #define DMA_CR_ECX_SHIFT 16
screamer 0:c5e2f793b59a 3932 #define DMA_CR_CX_MASK 0x20000u
screamer 0:c5e2f793b59a 3933 #define DMA_CR_CX_SHIFT 17
screamer 0:c5e2f793b59a 3934 /* ES Bit Fields */
screamer 0:c5e2f793b59a 3935 #define DMA_ES_DBE_MASK 0x1u
screamer 0:c5e2f793b59a 3936 #define DMA_ES_DBE_SHIFT 0
screamer 0:c5e2f793b59a 3937 #define DMA_ES_SBE_MASK 0x2u
screamer 0:c5e2f793b59a 3938 #define DMA_ES_SBE_SHIFT 1
screamer 0:c5e2f793b59a 3939 #define DMA_ES_SGE_MASK 0x4u
screamer 0:c5e2f793b59a 3940 #define DMA_ES_SGE_SHIFT 2
screamer 0:c5e2f793b59a 3941 #define DMA_ES_NCE_MASK 0x8u
screamer 0:c5e2f793b59a 3942 #define DMA_ES_NCE_SHIFT 3
screamer 0:c5e2f793b59a 3943 #define DMA_ES_DOE_MASK 0x10u
screamer 0:c5e2f793b59a 3944 #define DMA_ES_DOE_SHIFT 4
screamer 0:c5e2f793b59a 3945 #define DMA_ES_DAE_MASK 0x20u
screamer 0:c5e2f793b59a 3946 #define DMA_ES_DAE_SHIFT 5
screamer 0:c5e2f793b59a 3947 #define DMA_ES_SOE_MASK 0x40u
screamer 0:c5e2f793b59a 3948 #define DMA_ES_SOE_SHIFT 6
screamer 0:c5e2f793b59a 3949 #define DMA_ES_SAE_MASK 0x80u
screamer 0:c5e2f793b59a 3950 #define DMA_ES_SAE_SHIFT 7
screamer 0:c5e2f793b59a 3951 #define DMA_ES_ERRCHN_MASK 0xF00u
screamer 0:c5e2f793b59a 3952 #define DMA_ES_ERRCHN_SHIFT 8
screamer 0:c5e2f793b59a 3953 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
screamer 0:c5e2f793b59a 3954 #define DMA_ES_CPE_MASK 0x4000u
screamer 0:c5e2f793b59a 3955 #define DMA_ES_CPE_SHIFT 14
screamer 0:c5e2f793b59a 3956 #define DMA_ES_ECX_MASK 0x10000u
screamer 0:c5e2f793b59a 3957 #define DMA_ES_ECX_SHIFT 16
screamer 0:c5e2f793b59a 3958 #define DMA_ES_VLD_MASK 0x80000000u
screamer 0:c5e2f793b59a 3959 #define DMA_ES_VLD_SHIFT 31
screamer 0:c5e2f793b59a 3960 /* ERQ Bit Fields */
screamer 0:c5e2f793b59a 3961 #define DMA_ERQ_ERQ0_MASK 0x1u
screamer 0:c5e2f793b59a 3962 #define DMA_ERQ_ERQ0_SHIFT 0
screamer 0:c5e2f793b59a 3963 #define DMA_ERQ_ERQ1_MASK 0x2u
screamer 0:c5e2f793b59a 3964 #define DMA_ERQ_ERQ1_SHIFT 1
screamer 0:c5e2f793b59a 3965 #define DMA_ERQ_ERQ2_MASK 0x4u
screamer 0:c5e2f793b59a 3966 #define DMA_ERQ_ERQ2_SHIFT 2
screamer 0:c5e2f793b59a 3967 #define DMA_ERQ_ERQ3_MASK 0x8u
screamer 0:c5e2f793b59a 3968 #define DMA_ERQ_ERQ3_SHIFT 3
screamer 0:c5e2f793b59a 3969 #define DMA_ERQ_ERQ4_MASK 0x10u
screamer 0:c5e2f793b59a 3970 #define DMA_ERQ_ERQ4_SHIFT 4
screamer 0:c5e2f793b59a 3971 #define DMA_ERQ_ERQ5_MASK 0x20u
screamer 0:c5e2f793b59a 3972 #define DMA_ERQ_ERQ5_SHIFT 5
screamer 0:c5e2f793b59a 3973 #define DMA_ERQ_ERQ6_MASK 0x40u
screamer 0:c5e2f793b59a 3974 #define DMA_ERQ_ERQ6_SHIFT 6
screamer 0:c5e2f793b59a 3975 #define DMA_ERQ_ERQ7_MASK 0x80u
screamer 0:c5e2f793b59a 3976 #define DMA_ERQ_ERQ7_SHIFT 7
screamer 0:c5e2f793b59a 3977 #define DMA_ERQ_ERQ8_MASK 0x100u
screamer 0:c5e2f793b59a 3978 #define DMA_ERQ_ERQ8_SHIFT 8
screamer 0:c5e2f793b59a 3979 #define DMA_ERQ_ERQ9_MASK 0x200u
screamer 0:c5e2f793b59a 3980 #define DMA_ERQ_ERQ9_SHIFT 9
screamer 0:c5e2f793b59a 3981 #define DMA_ERQ_ERQ10_MASK 0x400u
screamer 0:c5e2f793b59a 3982 #define DMA_ERQ_ERQ10_SHIFT 10
screamer 0:c5e2f793b59a 3983 #define DMA_ERQ_ERQ11_MASK 0x800u
screamer 0:c5e2f793b59a 3984 #define DMA_ERQ_ERQ11_SHIFT 11
screamer 0:c5e2f793b59a 3985 #define DMA_ERQ_ERQ12_MASK 0x1000u
screamer 0:c5e2f793b59a 3986 #define DMA_ERQ_ERQ12_SHIFT 12
screamer 0:c5e2f793b59a 3987 #define DMA_ERQ_ERQ13_MASK 0x2000u
screamer 0:c5e2f793b59a 3988 #define DMA_ERQ_ERQ13_SHIFT 13
screamer 0:c5e2f793b59a 3989 #define DMA_ERQ_ERQ14_MASK 0x4000u
screamer 0:c5e2f793b59a 3990 #define DMA_ERQ_ERQ14_SHIFT 14
screamer 0:c5e2f793b59a 3991 #define DMA_ERQ_ERQ15_MASK 0x8000u
screamer 0:c5e2f793b59a 3992 #define DMA_ERQ_ERQ15_SHIFT 15
screamer 0:c5e2f793b59a 3993 /* EEI Bit Fields */
screamer 0:c5e2f793b59a 3994 #define DMA_EEI_EEI0_MASK 0x1u
screamer 0:c5e2f793b59a 3995 #define DMA_EEI_EEI0_SHIFT 0
screamer 0:c5e2f793b59a 3996 #define DMA_EEI_EEI1_MASK 0x2u
screamer 0:c5e2f793b59a 3997 #define DMA_EEI_EEI1_SHIFT 1
screamer 0:c5e2f793b59a 3998 #define DMA_EEI_EEI2_MASK 0x4u
screamer 0:c5e2f793b59a 3999 #define DMA_EEI_EEI2_SHIFT 2
screamer 0:c5e2f793b59a 4000 #define DMA_EEI_EEI3_MASK 0x8u
screamer 0:c5e2f793b59a 4001 #define DMA_EEI_EEI3_SHIFT 3
screamer 0:c5e2f793b59a 4002 #define DMA_EEI_EEI4_MASK 0x10u
screamer 0:c5e2f793b59a 4003 #define DMA_EEI_EEI4_SHIFT 4
screamer 0:c5e2f793b59a 4004 #define DMA_EEI_EEI5_MASK 0x20u
screamer 0:c5e2f793b59a 4005 #define DMA_EEI_EEI5_SHIFT 5
screamer 0:c5e2f793b59a 4006 #define DMA_EEI_EEI6_MASK 0x40u
screamer 0:c5e2f793b59a 4007 #define DMA_EEI_EEI6_SHIFT 6
screamer 0:c5e2f793b59a 4008 #define DMA_EEI_EEI7_MASK 0x80u
screamer 0:c5e2f793b59a 4009 #define DMA_EEI_EEI7_SHIFT 7
screamer 0:c5e2f793b59a 4010 #define DMA_EEI_EEI8_MASK 0x100u
screamer 0:c5e2f793b59a 4011 #define DMA_EEI_EEI8_SHIFT 8
screamer 0:c5e2f793b59a 4012 #define DMA_EEI_EEI9_MASK 0x200u
screamer 0:c5e2f793b59a 4013 #define DMA_EEI_EEI9_SHIFT 9
screamer 0:c5e2f793b59a 4014 #define DMA_EEI_EEI10_MASK 0x400u
screamer 0:c5e2f793b59a 4015 #define DMA_EEI_EEI10_SHIFT 10
screamer 0:c5e2f793b59a 4016 #define DMA_EEI_EEI11_MASK 0x800u
screamer 0:c5e2f793b59a 4017 #define DMA_EEI_EEI11_SHIFT 11
screamer 0:c5e2f793b59a 4018 #define DMA_EEI_EEI12_MASK 0x1000u
screamer 0:c5e2f793b59a 4019 #define DMA_EEI_EEI12_SHIFT 12
screamer 0:c5e2f793b59a 4020 #define DMA_EEI_EEI13_MASK 0x2000u
screamer 0:c5e2f793b59a 4021 #define DMA_EEI_EEI13_SHIFT 13
screamer 0:c5e2f793b59a 4022 #define DMA_EEI_EEI14_MASK 0x4000u
screamer 0:c5e2f793b59a 4023 #define DMA_EEI_EEI14_SHIFT 14
screamer 0:c5e2f793b59a 4024 #define DMA_EEI_EEI15_MASK 0x8000u
screamer 0:c5e2f793b59a 4025 #define DMA_EEI_EEI15_SHIFT 15
screamer 0:c5e2f793b59a 4026 /* CEEI Bit Fields */
screamer 0:c5e2f793b59a 4027 #define DMA_CEEI_CEEI_MASK 0xFu
screamer 0:c5e2f793b59a 4028 #define DMA_CEEI_CEEI_SHIFT 0
screamer 0:c5e2f793b59a 4029 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
screamer 0:c5e2f793b59a 4030 #define DMA_CEEI_CAEE_MASK 0x40u
screamer 0:c5e2f793b59a 4031 #define DMA_CEEI_CAEE_SHIFT 6
screamer 0:c5e2f793b59a 4032 #define DMA_CEEI_NOP_MASK 0x80u
screamer 0:c5e2f793b59a 4033 #define DMA_CEEI_NOP_SHIFT 7
screamer 0:c5e2f793b59a 4034 /* SEEI Bit Fields */
screamer 0:c5e2f793b59a 4035 #define DMA_SEEI_SEEI_MASK 0xFu
screamer 0:c5e2f793b59a 4036 #define DMA_SEEI_SEEI_SHIFT 0
screamer 0:c5e2f793b59a 4037 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
screamer 0:c5e2f793b59a 4038 #define DMA_SEEI_SAEE_MASK 0x40u
screamer 0:c5e2f793b59a 4039 #define DMA_SEEI_SAEE_SHIFT 6
screamer 0:c5e2f793b59a 4040 #define DMA_SEEI_NOP_MASK 0x80u
screamer 0:c5e2f793b59a 4041 #define DMA_SEEI_NOP_SHIFT 7
screamer 0:c5e2f793b59a 4042 /* CERQ Bit Fields */
screamer 0:c5e2f793b59a 4043 #define DMA_CERQ_CERQ_MASK 0xFu
screamer 0:c5e2f793b59a 4044 #define DMA_CERQ_CERQ_SHIFT 0
screamer 0:c5e2f793b59a 4045 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
screamer 0:c5e2f793b59a 4046 #define DMA_CERQ_CAER_MASK 0x40u
screamer 0:c5e2f793b59a 4047 #define DMA_CERQ_CAER_SHIFT 6
screamer 0:c5e2f793b59a 4048 #define DMA_CERQ_NOP_MASK 0x80u
screamer 0:c5e2f793b59a 4049 #define DMA_CERQ_NOP_SHIFT 7
screamer 0:c5e2f793b59a 4050 /* SERQ Bit Fields */
screamer 0:c5e2f793b59a 4051 #define DMA_SERQ_SERQ_MASK 0xFu
screamer 0:c5e2f793b59a 4052 #define DMA_SERQ_SERQ_SHIFT 0
screamer 0:c5e2f793b59a 4053 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
screamer 0:c5e2f793b59a 4054 #define DMA_SERQ_SAER_MASK 0x40u
screamer 0:c5e2f793b59a 4055 #define DMA_SERQ_SAER_SHIFT 6
screamer 0:c5e2f793b59a 4056 #define DMA_SERQ_NOP_MASK 0x80u
screamer 0:c5e2f793b59a 4057 #define DMA_SERQ_NOP_SHIFT 7
screamer 0:c5e2f793b59a 4058 /* CDNE Bit Fields */
screamer 0:c5e2f793b59a 4059 #define DMA_CDNE_CDNE_MASK 0xFu
screamer 0:c5e2f793b59a 4060 #define DMA_CDNE_CDNE_SHIFT 0
screamer 0:c5e2f793b59a 4061 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
screamer 0:c5e2f793b59a 4062 #define DMA_CDNE_CADN_MASK 0x40u
screamer 0:c5e2f793b59a 4063 #define DMA_CDNE_CADN_SHIFT 6
screamer 0:c5e2f793b59a 4064 #define DMA_CDNE_NOP_MASK 0x80u
screamer 0:c5e2f793b59a 4065 #define DMA_CDNE_NOP_SHIFT 7
screamer 0:c5e2f793b59a 4066 /* SSRT Bit Fields */
screamer 0:c5e2f793b59a 4067 #define DMA_SSRT_SSRT_MASK 0xFu
screamer 0:c5e2f793b59a 4068 #define DMA_SSRT_SSRT_SHIFT 0
screamer 0:c5e2f793b59a 4069 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
screamer 0:c5e2f793b59a 4070 #define DMA_SSRT_SAST_MASK 0x40u
screamer 0:c5e2f793b59a 4071 #define DMA_SSRT_SAST_SHIFT 6
screamer 0:c5e2f793b59a 4072 #define DMA_SSRT_NOP_MASK 0x80u
screamer 0:c5e2f793b59a 4073 #define DMA_SSRT_NOP_SHIFT 7
screamer 0:c5e2f793b59a 4074 /* CERR Bit Fields */
screamer 0:c5e2f793b59a 4075 #define DMA_CERR_CERR_MASK 0xFu
screamer 0:c5e2f793b59a 4076 #define DMA_CERR_CERR_SHIFT 0
screamer 0:c5e2f793b59a 4077 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
screamer 0:c5e2f793b59a 4078 #define DMA_CERR_CAEI_MASK 0x40u
screamer 0:c5e2f793b59a 4079 #define DMA_CERR_CAEI_SHIFT 6
screamer 0:c5e2f793b59a 4080 #define DMA_CERR_NOP_MASK 0x80u
screamer 0:c5e2f793b59a 4081 #define DMA_CERR_NOP_SHIFT 7
screamer 0:c5e2f793b59a 4082 /* CINT Bit Fields */
screamer 0:c5e2f793b59a 4083 #define DMA_CINT_CINT_MASK 0xFu
screamer 0:c5e2f793b59a 4084 #define DMA_CINT_CINT_SHIFT 0
screamer 0:c5e2f793b59a 4085 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
screamer 0:c5e2f793b59a 4086 #define DMA_CINT_CAIR_MASK 0x40u
screamer 0:c5e2f793b59a 4087 #define DMA_CINT_CAIR_SHIFT 6
screamer 0:c5e2f793b59a 4088 #define DMA_CINT_NOP_MASK 0x80u
screamer 0:c5e2f793b59a 4089 #define DMA_CINT_NOP_SHIFT 7
screamer 0:c5e2f793b59a 4090 /* INT Bit Fields */
screamer 0:c5e2f793b59a 4091 #define DMA_INT_INT0_MASK 0x1u
screamer 0:c5e2f793b59a 4092 #define DMA_INT_INT0_SHIFT 0
screamer 0:c5e2f793b59a 4093 #define DMA_INT_INT1_MASK 0x2u
screamer 0:c5e2f793b59a 4094 #define DMA_INT_INT1_SHIFT 1
screamer 0:c5e2f793b59a 4095 #define DMA_INT_INT2_MASK 0x4u
screamer 0:c5e2f793b59a 4096 #define DMA_INT_INT2_SHIFT 2
screamer 0:c5e2f793b59a 4097 #define DMA_INT_INT3_MASK 0x8u
screamer 0:c5e2f793b59a 4098 #define DMA_INT_INT3_SHIFT 3
screamer 0:c5e2f793b59a 4099 #define DMA_INT_INT4_MASK 0x10u
screamer 0:c5e2f793b59a 4100 #define DMA_INT_INT4_SHIFT 4
screamer 0:c5e2f793b59a 4101 #define DMA_INT_INT5_MASK 0x20u
screamer 0:c5e2f793b59a 4102 #define DMA_INT_INT5_SHIFT 5
screamer 0:c5e2f793b59a 4103 #define DMA_INT_INT6_MASK 0x40u
screamer 0:c5e2f793b59a 4104 #define DMA_INT_INT6_SHIFT 6
screamer 0:c5e2f793b59a 4105 #define DMA_INT_INT7_MASK 0x80u
screamer 0:c5e2f793b59a 4106 #define DMA_INT_INT7_SHIFT 7
screamer 0:c5e2f793b59a 4107 #define DMA_INT_INT8_MASK 0x100u
screamer 0:c5e2f793b59a 4108 #define DMA_INT_INT8_SHIFT 8
screamer 0:c5e2f793b59a 4109 #define DMA_INT_INT9_MASK 0x200u
screamer 0:c5e2f793b59a 4110 #define DMA_INT_INT9_SHIFT 9
screamer 0:c5e2f793b59a 4111 #define DMA_INT_INT10_MASK 0x400u
screamer 0:c5e2f793b59a 4112 #define DMA_INT_INT10_SHIFT 10
screamer 0:c5e2f793b59a 4113 #define DMA_INT_INT11_MASK 0x800u
screamer 0:c5e2f793b59a 4114 #define DMA_INT_INT11_SHIFT 11
screamer 0:c5e2f793b59a 4115 #define DMA_INT_INT12_MASK 0x1000u
screamer 0:c5e2f793b59a 4116 #define DMA_INT_INT12_SHIFT 12
screamer 0:c5e2f793b59a 4117 #define DMA_INT_INT13_MASK 0x2000u
screamer 0:c5e2f793b59a 4118 #define DMA_INT_INT13_SHIFT 13
screamer 0:c5e2f793b59a 4119 #define DMA_INT_INT14_MASK 0x4000u
screamer 0:c5e2f793b59a 4120 #define DMA_INT_INT14_SHIFT 14
screamer 0:c5e2f793b59a 4121 #define DMA_INT_INT15_MASK 0x8000u
screamer 0:c5e2f793b59a 4122 #define DMA_INT_INT15_SHIFT 15
screamer 0:c5e2f793b59a 4123 /* ERR Bit Fields */
screamer 0:c5e2f793b59a 4124 #define DMA_ERR_ERR0_MASK 0x1u
screamer 0:c5e2f793b59a 4125 #define DMA_ERR_ERR0_SHIFT 0
screamer 0:c5e2f793b59a 4126 #define DMA_ERR_ERR1_MASK 0x2u
screamer 0:c5e2f793b59a 4127 #define DMA_ERR_ERR1_SHIFT 1
screamer 0:c5e2f793b59a 4128 #define DMA_ERR_ERR2_MASK 0x4u
screamer 0:c5e2f793b59a 4129 #define DMA_ERR_ERR2_SHIFT 2
screamer 0:c5e2f793b59a 4130 #define DMA_ERR_ERR3_MASK 0x8u
screamer 0:c5e2f793b59a 4131 #define DMA_ERR_ERR3_SHIFT 3
screamer 0:c5e2f793b59a 4132 #define DMA_ERR_ERR4_MASK 0x10u
screamer 0:c5e2f793b59a 4133 #define DMA_ERR_ERR4_SHIFT 4
screamer 0:c5e2f793b59a 4134 #define DMA_ERR_ERR5_MASK 0x20u
screamer 0:c5e2f793b59a 4135 #define DMA_ERR_ERR5_SHIFT 5
screamer 0:c5e2f793b59a 4136 #define DMA_ERR_ERR6_MASK 0x40u
screamer 0:c5e2f793b59a 4137 #define DMA_ERR_ERR6_SHIFT 6
screamer 0:c5e2f793b59a 4138 #define DMA_ERR_ERR7_MASK 0x80u
screamer 0:c5e2f793b59a 4139 #define DMA_ERR_ERR7_SHIFT 7
screamer 0:c5e2f793b59a 4140 #define DMA_ERR_ERR8_MASK 0x100u
screamer 0:c5e2f793b59a 4141 #define DMA_ERR_ERR8_SHIFT 8
screamer 0:c5e2f793b59a 4142 #define DMA_ERR_ERR9_MASK 0x200u
screamer 0:c5e2f793b59a 4143 #define DMA_ERR_ERR9_SHIFT 9
screamer 0:c5e2f793b59a 4144 #define DMA_ERR_ERR10_MASK 0x400u
screamer 0:c5e2f793b59a 4145 #define DMA_ERR_ERR10_SHIFT 10
screamer 0:c5e2f793b59a 4146 #define DMA_ERR_ERR11_MASK 0x800u
screamer 0:c5e2f793b59a 4147 #define DMA_ERR_ERR11_SHIFT 11
screamer 0:c5e2f793b59a 4148 #define DMA_ERR_ERR12_MASK 0x1000u
screamer 0:c5e2f793b59a 4149 #define DMA_ERR_ERR12_SHIFT 12
screamer 0:c5e2f793b59a 4150 #define DMA_ERR_ERR13_MASK 0x2000u
screamer 0:c5e2f793b59a 4151 #define DMA_ERR_ERR13_SHIFT 13
screamer 0:c5e2f793b59a 4152 #define DMA_ERR_ERR14_MASK 0x4000u
screamer 0:c5e2f793b59a 4153 #define DMA_ERR_ERR14_SHIFT 14
screamer 0:c5e2f793b59a 4154 #define DMA_ERR_ERR15_MASK 0x8000u
screamer 0:c5e2f793b59a 4155 #define DMA_ERR_ERR15_SHIFT 15
screamer 0:c5e2f793b59a 4156 /* HRS Bit Fields */
screamer 0:c5e2f793b59a 4157 #define DMA_HRS_HRS0_MASK 0x1u
screamer 0:c5e2f793b59a 4158 #define DMA_HRS_HRS0_SHIFT 0
screamer 0:c5e2f793b59a 4159 #define DMA_HRS_HRS1_MASK 0x2u
screamer 0:c5e2f793b59a 4160 #define DMA_HRS_HRS1_SHIFT 1
screamer 0:c5e2f793b59a 4161 #define DMA_HRS_HRS2_MASK 0x4u
screamer 0:c5e2f793b59a 4162 #define DMA_HRS_HRS2_SHIFT 2
screamer 0:c5e2f793b59a 4163 #define DMA_HRS_HRS3_MASK 0x8u
screamer 0:c5e2f793b59a 4164 #define DMA_HRS_HRS3_SHIFT 3
screamer 0:c5e2f793b59a 4165 #define DMA_HRS_HRS4_MASK 0x10u
screamer 0:c5e2f793b59a 4166 #define DMA_HRS_HRS4_SHIFT 4
screamer 0:c5e2f793b59a 4167 #define DMA_HRS_HRS5_MASK 0x20u
screamer 0:c5e2f793b59a 4168 #define DMA_HRS_HRS5_SHIFT 5
screamer 0:c5e2f793b59a 4169 #define DMA_HRS_HRS6_MASK 0x40u
screamer 0:c5e2f793b59a 4170 #define DMA_HRS_HRS6_SHIFT 6
screamer 0:c5e2f793b59a 4171 #define DMA_HRS_HRS7_MASK 0x80u
screamer 0:c5e2f793b59a 4172 #define DMA_HRS_HRS7_SHIFT 7
screamer 0:c5e2f793b59a 4173 #define DMA_HRS_HRS8_MASK 0x100u
screamer 0:c5e2f793b59a 4174 #define DMA_HRS_HRS8_SHIFT 8
screamer 0:c5e2f793b59a 4175 #define DMA_HRS_HRS9_MASK 0x200u
screamer 0:c5e2f793b59a 4176 #define DMA_HRS_HRS9_SHIFT 9
screamer 0:c5e2f793b59a 4177 #define DMA_HRS_HRS10_MASK 0x400u
screamer 0:c5e2f793b59a 4178 #define DMA_HRS_HRS10_SHIFT 10
screamer 0:c5e2f793b59a 4179 #define DMA_HRS_HRS11_MASK 0x800u
screamer 0:c5e2f793b59a 4180 #define DMA_HRS_HRS11_SHIFT 11
screamer 0:c5e2f793b59a 4181 #define DMA_HRS_HRS12_MASK 0x1000u
screamer 0:c5e2f793b59a 4182 #define DMA_HRS_HRS12_SHIFT 12
screamer 0:c5e2f793b59a 4183 #define DMA_HRS_HRS13_MASK 0x2000u
screamer 0:c5e2f793b59a 4184 #define DMA_HRS_HRS13_SHIFT 13
screamer 0:c5e2f793b59a 4185 #define DMA_HRS_HRS14_MASK 0x4000u
screamer 0:c5e2f793b59a 4186 #define DMA_HRS_HRS14_SHIFT 14
screamer 0:c5e2f793b59a 4187 #define DMA_HRS_HRS15_MASK 0x8000u
screamer 0:c5e2f793b59a 4188 #define DMA_HRS_HRS15_SHIFT 15
screamer 0:c5e2f793b59a 4189 /* DCHPRI3 Bit Fields */
screamer 0:c5e2f793b59a 4190 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4191 #define DMA_DCHPRI3_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4192 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
screamer 0:c5e2f793b59a 4193 #define DMA_DCHPRI3_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4194 #define DMA_DCHPRI3_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4195 #define DMA_DCHPRI3_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4196 #define DMA_DCHPRI3_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4197 /* DCHPRI2 Bit Fields */
screamer 0:c5e2f793b59a 4198 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4199 #define DMA_DCHPRI2_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4200 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
screamer 0:c5e2f793b59a 4201 #define DMA_DCHPRI2_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4202 #define DMA_DCHPRI2_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4203 #define DMA_DCHPRI2_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4204 #define DMA_DCHPRI2_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4205 /* DCHPRI1 Bit Fields */
screamer 0:c5e2f793b59a 4206 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4207 #define DMA_DCHPRI1_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4208 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
screamer 0:c5e2f793b59a 4209 #define DMA_DCHPRI1_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4210 #define DMA_DCHPRI1_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4211 #define DMA_DCHPRI1_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4212 #define DMA_DCHPRI1_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4213 /* DCHPRI0 Bit Fields */
screamer 0:c5e2f793b59a 4214 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4215 #define DMA_DCHPRI0_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4216 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
screamer 0:c5e2f793b59a 4217 #define DMA_DCHPRI0_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4218 #define DMA_DCHPRI0_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4219 #define DMA_DCHPRI0_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4220 #define DMA_DCHPRI0_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4221 /* DCHPRI7 Bit Fields */
screamer 0:c5e2f793b59a 4222 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4223 #define DMA_DCHPRI7_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4224 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
screamer 0:c5e2f793b59a 4225 #define DMA_DCHPRI7_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4226 #define DMA_DCHPRI7_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4227 #define DMA_DCHPRI7_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4228 #define DMA_DCHPRI7_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4229 /* DCHPRI6 Bit Fields */
screamer 0:c5e2f793b59a 4230 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4231 #define DMA_DCHPRI6_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4232 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
screamer 0:c5e2f793b59a 4233 #define DMA_DCHPRI6_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4234 #define DMA_DCHPRI6_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4235 #define DMA_DCHPRI6_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4236 #define DMA_DCHPRI6_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4237 /* DCHPRI5 Bit Fields */
screamer 0:c5e2f793b59a 4238 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4239 #define DMA_DCHPRI5_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4240 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
screamer 0:c5e2f793b59a 4241 #define DMA_DCHPRI5_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4242 #define DMA_DCHPRI5_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4243 #define DMA_DCHPRI5_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4244 #define DMA_DCHPRI5_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4245 /* DCHPRI4 Bit Fields */
screamer 0:c5e2f793b59a 4246 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4247 #define DMA_DCHPRI4_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4248 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
screamer 0:c5e2f793b59a 4249 #define DMA_DCHPRI4_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4250 #define DMA_DCHPRI4_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4251 #define DMA_DCHPRI4_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4252 #define DMA_DCHPRI4_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4253 /* DCHPRI11 Bit Fields */
screamer 0:c5e2f793b59a 4254 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4255 #define DMA_DCHPRI11_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4256 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
screamer 0:c5e2f793b59a 4257 #define DMA_DCHPRI11_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4258 #define DMA_DCHPRI11_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4259 #define DMA_DCHPRI11_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4260 #define DMA_DCHPRI11_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4261 /* DCHPRI10 Bit Fields */
screamer 0:c5e2f793b59a 4262 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4263 #define DMA_DCHPRI10_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4264 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
screamer 0:c5e2f793b59a 4265 #define DMA_DCHPRI10_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4266 #define DMA_DCHPRI10_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4267 #define DMA_DCHPRI10_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4268 #define DMA_DCHPRI10_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4269 /* DCHPRI9 Bit Fields */
screamer 0:c5e2f793b59a 4270 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4271 #define DMA_DCHPRI9_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4272 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
screamer 0:c5e2f793b59a 4273 #define DMA_DCHPRI9_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4274 #define DMA_DCHPRI9_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4275 #define DMA_DCHPRI9_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4276 #define DMA_DCHPRI9_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4277 /* DCHPRI8 Bit Fields */
screamer 0:c5e2f793b59a 4278 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4279 #define DMA_DCHPRI8_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4280 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
screamer 0:c5e2f793b59a 4281 #define DMA_DCHPRI8_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4282 #define DMA_DCHPRI8_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4283 #define DMA_DCHPRI8_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4284 #define DMA_DCHPRI8_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4285 /* DCHPRI15 Bit Fields */
screamer 0:c5e2f793b59a 4286 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4287 #define DMA_DCHPRI15_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4288 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
screamer 0:c5e2f793b59a 4289 #define DMA_DCHPRI15_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4290 #define DMA_DCHPRI15_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4291 #define DMA_DCHPRI15_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4292 #define DMA_DCHPRI15_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4293 /* DCHPRI14 Bit Fields */
screamer 0:c5e2f793b59a 4294 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4295 #define DMA_DCHPRI14_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4296 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
screamer 0:c5e2f793b59a 4297 #define DMA_DCHPRI14_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4298 #define DMA_DCHPRI14_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4299 #define DMA_DCHPRI14_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4300 #define DMA_DCHPRI14_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4301 /* DCHPRI13 Bit Fields */
screamer 0:c5e2f793b59a 4302 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4303 #define DMA_DCHPRI13_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4304 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
screamer 0:c5e2f793b59a 4305 #define DMA_DCHPRI13_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4306 #define DMA_DCHPRI13_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4307 #define DMA_DCHPRI13_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4308 #define DMA_DCHPRI13_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4309 /* DCHPRI12 Bit Fields */
screamer 0:c5e2f793b59a 4310 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
screamer 0:c5e2f793b59a 4311 #define DMA_DCHPRI12_CHPRI_SHIFT 0
screamer 0:c5e2f793b59a 4312 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
screamer 0:c5e2f793b59a 4313 #define DMA_DCHPRI12_DPA_MASK 0x40u
screamer 0:c5e2f793b59a 4314 #define DMA_DCHPRI12_DPA_SHIFT 6
screamer 0:c5e2f793b59a 4315 #define DMA_DCHPRI12_ECP_MASK 0x80u
screamer 0:c5e2f793b59a 4316 #define DMA_DCHPRI12_ECP_SHIFT 7
screamer 0:c5e2f793b59a 4317 /* SADDR Bit Fields */
screamer 0:c5e2f793b59a 4318 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 4319 #define DMA_SADDR_SADDR_SHIFT 0
screamer 0:c5e2f793b59a 4320 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
screamer 0:c5e2f793b59a 4321 /* SOFF Bit Fields */
screamer 0:c5e2f793b59a 4322 #define DMA_SOFF_SOFF_MASK 0xFFFFu
screamer 0:c5e2f793b59a 4323 #define DMA_SOFF_SOFF_SHIFT 0
screamer 0:c5e2f793b59a 4324 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
screamer 0:c5e2f793b59a 4325 /* ATTR Bit Fields */
screamer 0:c5e2f793b59a 4326 #define DMA_ATTR_DSIZE_MASK 0x7u
screamer 0:c5e2f793b59a 4327 #define DMA_ATTR_DSIZE_SHIFT 0
screamer 0:c5e2f793b59a 4328 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
screamer 0:c5e2f793b59a 4329 #define DMA_ATTR_DMOD_MASK 0xF8u
screamer 0:c5e2f793b59a 4330 #define DMA_ATTR_DMOD_SHIFT 3
screamer 0:c5e2f793b59a 4331 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
screamer 0:c5e2f793b59a 4332 #define DMA_ATTR_SSIZE_MASK 0x700u
screamer 0:c5e2f793b59a 4333 #define DMA_ATTR_SSIZE_SHIFT 8
screamer 0:c5e2f793b59a 4334 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
screamer 0:c5e2f793b59a 4335 #define DMA_ATTR_SMOD_MASK 0xF800u
screamer 0:c5e2f793b59a 4336 #define DMA_ATTR_SMOD_SHIFT 11
screamer 0:c5e2f793b59a 4337 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
screamer 0:c5e2f793b59a 4338 /* NBYTES_MLNO Bit Fields */
screamer 0:c5e2f793b59a 4339 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 4340 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
screamer 0:c5e2f793b59a 4341 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
screamer 0:c5e2f793b59a 4342 /* NBYTES_MLOFFNO Bit Fields */
screamer 0:c5e2f793b59a 4343 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
screamer 0:c5e2f793b59a 4344 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
screamer 0:c5e2f793b59a 4345 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
screamer 0:c5e2f793b59a 4346 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
screamer 0:c5e2f793b59a 4347 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
screamer 0:c5e2f793b59a 4348 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
screamer 0:c5e2f793b59a 4349 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
screamer 0:c5e2f793b59a 4350 /* NBYTES_MLOFFYES Bit Fields */
screamer 0:c5e2f793b59a 4351 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
screamer 0:c5e2f793b59a 4352 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
screamer 0:c5e2f793b59a 4353 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
screamer 0:c5e2f793b59a 4354 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
screamer 0:c5e2f793b59a 4355 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
screamer 0:c5e2f793b59a 4356 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
screamer 0:c5e2f793b59a 4357 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
screamer 0:c5e2f793b59a 4358 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
screamer 0:c5e2f793b59a 4359 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
screamer 0:c5e2f793b59a 4360 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
screamer 0:c5e2f793b59a 4361 /* SLAST Bit Fields */
screamer 0:c5e2f793b59a 4362 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 4363 #define DMA_SLAST_SLAST_SHIFT 0
screamer 0:c5e2f793b59a 4364 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
screamer 0:c5e2f793b59a 4365 /* DADDR Bit Fields */
screamer 0:c5e2f793b59a 4366 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 4367 #define DMA_DADDR_DADDR_SHIFT 0
screamer 0:c5e2f793b59a 4368 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
screamer 0:c5e2f793b59a 4369 /* DOFF Bit Fields */
screamer 0:c5e2f793b59a 4370 #define DMA_DOFF_DOFF_MASK 0xFFFFu
screamer 0:c5e2f793b59a 4371 #define DMA_DOFF_DOFF_SHIFT 0
screamer 0:c5e2f793b59a 4372 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
screamer 0:c5e2f793b59a 4373 /* CITER_ELINKNO Bit Fields */
screamer 0:c5e2f793b59a 4374 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
screamer 0:c5e2f793b59a 4375 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
screamer 0:c5e2f793b59a 4376 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
screamer 0:c5e2f793b59a 4377 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
screamer 0:c5e2f793b59a 4378 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
screamer 0:c5e2f793b59a 4379 /* CITER_ELINKYES Bit Fields */
screamer 0:c5e2f793b59a 4380 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
screamer 0:c5e2f793b59a 4381 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
screamer 0:c5e2f793b59a 4382 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
screamer 0:c5e2f793b59a 4383 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
screamer 0:c5e2f793b59a 4384 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
screamer 0:c5e2f793b59a 4385 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
screamer 0:c5e2f793b59a 4386 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
screamer 0:c5e2f793b59a 4387 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
screamer 0:c5e2f793b59a 4388 /* DLAST_SGA Bit Fields */
screamer 0:c5e2f793b59a 4389 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 4390 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
screamer 0:c5e2f793b59a 4391 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
screamer 0:c5e2f793b59a 4392 /* CSR Bit Fields */
screamer 0:c5e2f793b59a 4393 #define DMA_CSR_START_MASK 0x1u
screamer 0:c5e2f793b59a 4394 #define DMA_CSR_START_SHIFT 0
screamer 0:c5e2f793b59a 4395 #define DMA_CSR_INTMAJOR_MASK 0x2u
screamer 0:c5e2f793b59a 4396 #define DMA_CSR_INTMAJOR_SHIFT 1
screamer 0:c5e2f793b59a 4397 #define DMA_CSR_INTHALF_MASK 0x4u
screamer 0:c5e2f793b59a 4398 #define DMA_CSR_INTHALF_SHIFT 2
screamer 0:c5e2f793b59a 4399 #define DMA_CSR_DREQ_MASK 0x8u
screamer 0:c5e2f793b59a 4400 #define DMA_CSR_DREQ_SHIFT 3
screamer 0:c5e2f793b59a 4401 #define DMA_CSR_ESG_MASK 0x10u
screamer 0:c5e2f793b59a 4402 #define DMA_CSR_ESG_SHIFT 4
screamer 0:c5e2f793b59a 4403 #define DMA_CSR_MAJORELINK_MASK 0x20u
screamer 0:c5e2f793b59a 4404 #define DMA_CSR_MAJORELINK_SHIFT 5
screamer 0:c5e2f793b59a 4405 #define DMA_CSR_ACTIVE_MASK 0x40u
screamer 0:c5e2f793b59a 4406 #define DMA_CSR_ACTIVE_SHIFT 6
screamer 0:c5e2f793b59a 4407 #define DMA_CSR_DONE_MASK 0x80u
screamer 0:c5e2f793b59a 4408 #define DMA_CSR_DONE_SHIFT 7
screamer 0:c5e2f793b59a 4409 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
screamer 0:c5e2f793b59a 4410 #define DMA_CSR_MAJORLINKCH_SHIFT 8
screamer 0:c5e2f793b59a 4411 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
screamer 0:c5e2f793b59a 4412 #define DMA_CSR_BWC_MASK 0xC000u
screamer 0:c5e2f793b59a 4413 #define DMA_CSR_BWC_SHIFT 14
screamer 0:c5e2f793b59a 4414 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
screamer 0:c5e2f793b59a 4415 /* BITER_ELINKNO Bit Fields */
screamer 0:c5e2f793b59a 4416 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
screamer 0:c5e2f793b59a 4417 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
screamer 0:c5e2f793b59a 4418 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
screamer 0:c5e2f793b59a 4419 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
screamer 0:c5e2f793b59a 4420 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
screamer 0:c5e2f793b59a 4421 /* BITER_ELINKYES Bit Fields */
screamer 0:c5e2f793b59a 4422 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
screamer 0:c5e2f793b59a 4423 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
screamer 0:c5e2f793b59a 4424 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
screamer 0:c5e2f793b59a 4425 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
screamer 0:c5e2f793b59a 4426 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
screamer 0:c5e2f793b59a 4427 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
screamer 0:c5e2f793b59a 4428 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
screamer 0:c5e2f793b59a 4429 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
screamer 0:c5e2f793b59a 4430
screamer 0:c5e2f793b59a 4431 /*!
screamer 0:c5e2f793b59a 4432 * @}
screamer 0:c5e2f793b59a 4433 */ /* end of group DMA_Register_Masks */
screamer 0:c5e2f793b59a 4434
screamer 0:c5e2f793b59a 4435
screamer 0:c5e2f793b59a 4436 /* DMA - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 4437 /** Peripheral DMA base address */
screamer 0:c5e2f793b59a 4438 #define DMA_BASE (0x40008000u)
screamer 0:c5e2f793b59a 4439 /** Peripheral DMA base pointer */
screamer 0:c5e2f793b59a 4440 #define DMA0 ((DMA_Type *)DMA_BASE)
screamer 0:c5e2f793b59a 4441 #define DMA_BASE_PTR (DMA0)
screamer 0:c5e2f793b59a 4442 /** Array initializer of DMA peripheral base addresses */
screamer 0:c5e2f793b59a 4443 #define DMA_BASE_ADDRS { DMA_BASE }
screamer 0:c5e2f793b59a 4444 /** Array initializer of DMA peripheral base pointers */
screamer 0:c5e2f793b59a 4445 #define DMA_BASE_PTRS { DMA0 }
screamer 0:c5e2f793b59a 4446 /** Interrupt vectors for the DMA peripheral type */
screamer 0:c5e2f793b59a 4447 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
screamer 0:c5e2f793b59a 4448 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
screamer 0:c5e2f793b59a 4449
screamer 0:c5e2f793b59a 4450 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 4451 -- DMA - Register accessor macros
screamer 0:c5e2f793b59a 4452 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 4453
screamer 0:c5e2f793b59a 4454 /*!
screamer 0:c5e2f793b59a 4455 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
screamer 0:c5e2f793b59a 4456 * @{
screamer 0:c5e2f793b59a 4457 */
screamer 0:c5e2f793b59a 4458
screamer 0:c5e2f793b59a 4459
screamer 0:c5e2f793b59a 4460 /* DMA - Register instance definitions */
screamer 0:c5e2f793b59a 4461 /* DMA */
screamer 0:c5e2f793b59a 4462 #define DMA_CR DMA_CR_REG(DMA0)
screamer 0:c5e2f793b59a 4463 #define DMA_ES DMA_ES_REG(DMA0)
screamer 0:c5e2f793b59a 4464 #define DMA_ERQ DMA_ERQ_REG(DMA0)
screamer 0:c5e2f793b59a 4465 #define DMA_EEI DMA_EEI_REG(DMA0)
screamer 0:c5e2f793b59a 4466 #define DMA_CEEI DMA_CEEI_REG(DMA0)
screamer 0:c5e2f793b59a 4467 #define DMA_SEEI DMA_SEEI_REG(DMA0)
screamer 0:c5e2f793b59a 4468 #define DMA_CERQ DMA_CERQ_REG(DMA0)
screamer 0:c5e2f793b59a 4469 #define DMA_SERQ DMA_SERQ_REG(DMA0)
screamer 0:c5e2f793b59a 4470 #define DMA_CDNE DMA_CDNE_REG(DMA0)
screamer 0:c5e2f793b59a 4471 #define DMA_SSRT DMA_SSRT_REG(DMA0)
screamer 0:c5e2f793b59a 4472 #define DMA_CERR DMA_CERR_REG(DMA0)
screamer 0:c5e2f793b59a 4473 #define DMA_CINT DMA_CINT_REG(DMA0)
screamer 0:c5e2f793b59a 4474 #define DMA_INT DMA_INT_REG(DMA0)
screamer 0:c5e2f793b59a 4475 #define DMA_ERR DMA_ERR_REG(DMA0)
screamer 0:c5e2f793b59a 4476 #define DMA_HRS DMA_HRS_REG(DMA0)
screamer 0:c5e2f793b59a 4477 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
screamer 0:c5e2f793b59a 4478 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
screamer 0:c5e2f793b59a 4479 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
screamer 0:c5e2f793b59a 4480 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
screamer 0:c5e2f793b59a 4481 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
screamer 0:c5e2f793b59a 4482 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
screamer 0:c5e2f793b59a 4483 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
screamer 0:c5e2f793b59a 4484 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
screamer 0:c5e2f793b59a 4485 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
screamer 0:c5e2f793b59a 4486 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
screamer 0:c5e2f793b59a 4487 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
screamer 0:c5e2f793b59a 4488 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
screamer 0:c5e2f793b59a 4489 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
screamer 0:c5e2f793b59a 4490 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
screamer 0:c5e2f793b59a 4491 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
screamer 0:c5e2f793b59a 4492 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
screamer 0:c5e2f793b59a 4493 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
screamer 0:c5e2f793b59a 4494 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
screamer 0:c5e2f793b59a 4495 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
screamer 0:c5e2f793b59a 4496 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
screamer 0:c5e2f793b59a 4497 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
screamer 0:c5e2f793b59a 4498 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
screamer 0:c5e2f793b59a 4499 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
screamer 0:c5e2f793b59a 4500 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
screamer 0:c5e2f793b59a 4501 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
screamer 0:c5e2f793b59a 4502 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
screamer 0:c5e2f793b59a 4503 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
screamer 0:c5e2f793b59a 4504 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
screamer 0:c5e2f793b59a 4505 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
screamer 0:c5e2f793b59a 4506 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
screamer 0:c5e2f793b59a 4507 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
screamer 0:c5e2f793b59a 4508 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
screamer 0:c5e2f793b59a 4509 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
screamer 0:c5e2f793b59a 4510 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
screamer 0:c5e2f793b59a 4511 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
screamer 0:c5e2f793b59a 4512 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
screamer 0:c5e2f793b59a 4513 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
screamer 0:c5e2f793b59a 4514 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
screamer 0:c5e2f793b59a 4515 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
screamer 0:c5e2f793b59a 4516 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
screamer 0:c5e2f793b59a 4517 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
screamer 0:c5e2f793b59a 4518 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
screamer 0:c5e2f793b59a 4519 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
screamer 0:c5e2f793b59a 4520 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
screamer 0:c5e2f793b59a 4521 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
screamer 0:c5e2f793b59a 4522 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
screamer 0:c5e2f793b59a 4523 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
screamer 0:c5e2f793b59a 4524 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
screamer 0:c5e2f793b59a 4525 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
screamer 0:c5e2f793b59a 4526 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
screamer 0:c5e2f793b59a 4527 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
screamer 0:c5e2f793b59a 4528 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
screamer 0:c5e2f793b59a 4529 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
screamer 0:c5e2f793b59a 4530 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
screamer 0:c5e2f793b59a 4531 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
screamer 0:c5e2f793b59a 4532 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
screamer 0:c5e2f793b59a 4533 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
screamer 0:c5e2f793b59a 4534 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
screamer 0:c5e2f793b59a 4535 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
screamer 0:c5e2f793b59a 4536 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
screamer 0:c5e2f793b59a 4537 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
screamer 0:c5e2f793b59a 4538 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
screamer 0:c5e2f793b59a 4539 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
screamer 0:c5e2f793b59a 4540 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
screamer 0:c5e2f793b59a 4541 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
screamer 0:c5e2f793b59a 4542 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
screamer 0:c5e2f793b59a 4543 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
screamer 0:c5e2f793b59a 4544 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
screamer 0:c5e2f793b59a 4545 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
screamer 0:c5e2f793b59a 4546 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
screamer 0:c5e2f793b59a 4547 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
screamer 0:c5e2f793b59a 4548 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
screamer 0:c5e2f793b59a 4549 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
screamer 0:c5e2f793b59a 4550 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
screamer 0:c5e2f793b59a 4551 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
screamer 0:c5e2f793b59a 4552 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
screamer 0:c5e2f793b59a 4553 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
screamer 0:c5e2f793b59a 4554 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
screamer 0:c5e2f793b59a 4555 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
screamer 0:c5e2f793b59a 4556 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
screamer 0:c5e2f793b59a 4557 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
screamer 0:c5e2f793b59a 4558 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
screamer 0:c5e2f793b59a 4559 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
screamer 0:c5e2f793b59a 4560 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
screamer 0:c5e2f793b59a 4561 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
screamer 0:c5e2f793b59a 4562 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
screamer 0:c5e2f793b59a 4563 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
screamer 0:c5e2f793b59a 4564 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
screamer 0:c5e2f793b59a 4565 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
screamer 0:c5e2f793b59a 4566 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
screamer 0:c5e2f793b59a 4567 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
screamer 0:c5e2f793b59a 4568 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
screamer 0:c5e2f793b59a 4569 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
screamer 0:c5e2f793b59a 4570 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
screamer 0:c5e2f793b59a 4571 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
screamer 0:c5e2f793b59a 4572 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
screamer 0:c5e2f793b59a 4573 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
screamer 0:c5e2f793b59a 4574 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
screamer 0:c5e2f793b59a 4575 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
screamer 0:c5e2f793b59a 4576 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
screamer 0:c5e2f793b59a 4577 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
screamer 0:c5e2f793b59a 4578 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
screamer 0:c5e2f793b59a 4579 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
screamer 0:c5e2f793b59a 4580 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
screamer 0:c5e2f793b59a 4581 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
screamer 0:c5e2f793b59a 4582 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
screamer 0:c5e2f793b59a 4583 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
screamer 0:c5e2f793b59a 4584 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
screamer 0:c5e2f793b59a 4585 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
screamer 0:c5e2f793b59a 4586 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
screamer 0:c5e2f793b59a 4587 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
screamer 0:c5e2f793b59a 4588 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
screamer 0:c5e2f793b59a 4589 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
screamer 0:c5e2f793b59a 4590 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
screamer 0:c5e2f793b59a 4591 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
screamer 0:c5e2f793b59a 4592 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
screamer 0:c5e2f793b59a 4593 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
screamer 0:c5e2f793b59a 4594 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
screamer 0:c5e2f793b59a 4595 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
screamer 0:c5e2f793b59a 4596 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
screamer 0:c5e2f793b59a 4597 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
screamer 0:c5e2f793b59a 4598 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
screamer 0:c5e2f793b59a 4599 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
screamer 0:c5e2f793b59a 4600 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
screamer 0:c5e2f793b59a 4601 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
screamer 0:c5e2f793b59a 4602 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
screamer 0:c5e2f793b59a 4603 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
screamer 0:c5e2f793b59a 4604 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
screamer 0:c5e2f793b59a 4605 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
screamer 0:c5e2f793b59a 4606 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
screamer 0:c5e2f793b59a 4607 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
screamer 0:c5e2f793b59a 4608 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
screamer 0:c5e2f793b59a 4609 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
screamer 0:c5e2f793b59a 4610 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
screamer 0:c5e2f793b59a 4611 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
screamer 0:c5e2f793b59a 4612 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
screamer 0:c5e2f793b59a 4613 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
screamer 0:c5e2f793b59a 4614 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
screamer 0:c5e2f793b59a 4615 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
screamer 0:c5e2f793b59a 4616 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
screamer 0:c5e2f793b59a 4617 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
screamer 0:c5e2f793b59a 4618 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
screamer 0:c5e2f793b59a 4619 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
screamer 0:c5e2f793b59a 4620 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
screamer 0:c5e2f793b59a 4621 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
screamer 0:c5e2f793b59a 4622 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
screamer 0:c5e2f793b59a 4623 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
screamer 0:c5e2f793b59a 4624 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
screamer 0:c5e2f793b59a 4625 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
screamer 0:c5e2f793b59a 4626 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
screamer 0:c5e2f793b59a 4627 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
screamer 0:c5e2f793b59a 4628 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
screamer 0:c5e2f793b59a 4629 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
screamer 0:c5e2f793b59a 4630 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
screamer 0:c5e2f793b59a 4631 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
screamer 0:c5e2f793b59a 4632 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
screamer 0:c5e2f793b59a 4633 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
screamer 0:c5e2f793b59a 4634 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
screamer 0:c5e2f793b59a 4635 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
screamer 0:c5e2f793b59a 4636 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
screamer 0:c5e2f793b59a 4637 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
screamer 0:c5e2f793b59a 4638 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
screamer 0:c5e2f793b59a 4639 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
screamer 0:c5e2f793b59a 4640 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
screamer 0:c5e2f793b59a 4641 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
screamer 0:c5e2f793b59a 4642 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
screamer 0:c5e2f793b59a 4643 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
screamer 0:c5e2f793b59a 4644 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
screamer 0:c5e2f793b59a 4645 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
screamer 0:c5e2f793b59a 4646 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
screamer 0:c5e2f793b59a 4647 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
screamer 0:c5e2f793b59a 4648 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
screamer 0:c5e2f793b59a 4649 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
screamer 0:c5e2f793b59a 4650 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
screamer 0:c5e2f793b59a 4651 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
screamer 0:c5e2f793b59a 4652 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
screamer 0:c5e2f793b59a 4653 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
screamer 0:c5e2f793b59a 4654 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
screamer 0:c5e2f793b59a 4655 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
screamer 0:c5e2f793b59a 4656 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
screamer 0:c5e2f793b59a 4657 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
screamer 0:c5e2f793b59a 4658 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
screamer 0:c5e2f793b59a 4659 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
screamer 0:c5e2f793b59a 4660 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
screamer 0:c5e2f793b59a 4661 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
screamer 0:c5e2f793b59a 4662 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
screamer 0:c5e2f793b59a 4663 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
screamer 0:c5e2f793b59a 4664 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
screamer 0:c5e2f793b59a 4665 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
screamer 0:c5e2f793b59a 4666 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
screamer 0:c5e2f793b59a 4667 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
screamer 0:c5e2f793b59a 4668 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
screamer 0:c5e2f793b59a 4669 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
screamer 0:c5e2f793b59a 4670 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
screamer 0:c5e2f793b59a 4671 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
screamer 0:c5e2f793b59a 4672 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
screamer 0:c5e2f793b59a 4673 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
screamer 0:c5e2f793b59a 4674 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
screamer 0:c5e2f793b59a 4675 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
screamer 0:c5e2f793b59a 4676 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
screamer 0:c5e2f793b59a 4677 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
screamer 0:c5e2f793b59a 4678 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
screamer 0:c5e2f793b59a 4679 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
screamer 0:c5e2f793b59a 4680 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
screamer 0:c5e2f793b59a 4681 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
screamer 0:c5e2f793b59a 4682 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
screamer 0:c5e2f793b59a 4683 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
screamer 0:c5e2f793b59a 4684 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
screamer 0:c5e2f793b59a 4685 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
screamer 0:c5e2f793b59a 4686 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
screamer 0:c5e2f793b59a 4687 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
screamer 0:c5e2f793b59a 4688 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
screamer 0:c5e2f793b59a 4689 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
screamer 0:c5e2f793b59a 4690 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
screamer 0:c5e2f793b59a 4691 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
screamer 0:c5e2f793b59a 4692 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
screamer 0:c5e2f793b59a 4693 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
screamer 0:c5e2f793b59a 4694 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
screamer 0:c5e2f793b59a 4695 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
screamer 0:c5e2f793b59a 4696 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
screamer 0:c5e2f793b59a 4697 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
screamer 0:c5e2f793b59a 4698 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
screamer 0:c5e2f793b59a 4699 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
screamer 0:c5e2f793b59a 4700 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
screamer 0:c5e2f793b59a 4701 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
screamer 0:c5e2f793b59a 4702 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
screamer 0:c5e2f793b59a 4703 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
screamer 0:c5e2f793b59a 4704 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
screamer 0:c5e2f793b59a 4705 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
screamer 0:c5e2f793b59a 4706 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
screamer 0:c5e2f793b59a 4707 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
screamer 0:c5e2f793b59a 4708 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
screamer 0:c5e2f793b59a 4709 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
screamer 0:c5e2f793b59a 4710 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
screamer 0:c5e2f793b59a 4711 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
screamer 0:c5e2f793b59a 4712 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
screamer 0:c5e2f793b59a 4713 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
screamer 0:c5e2f793b59a 4714 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
screamer 0:c5e2f793b59a 4715 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
screamer 0:c5e2f793b59a 4716 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
screamer 0:c5e2f793b59a 4717 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
screamer 0:c5e2f793b59a 4718 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
screamer 0:c5e2f793b59a 4719 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
screamer 0:c5e2f793b59a 4720 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
screamer 0:c5e2f793b59a 4721 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
screamer 0:c5e2f793b59a 4722 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
screamer 0:c5e2f793b59a 4723 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
screamer 0:c5e2f793b59a 4724 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
screamer 0:c5e2f793b59a 4725 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
screamer 0:c5e2f793b59a 4726 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
screamer 0:c5e2f793b59a 4727 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
screamer 0:c5e2f793b59a 4728 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
screamer 0:c5e2f793b59a 4729 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
screamer 0:c5e2f793b59a 4730 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
screamer 0:c5e2f793b59a 4731 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
screamer 0:c5e2f793b59a 4732 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
screamer 0:c5e2f793b59a 4733
screamer 0:c5e2f793b59a 4734 /* DMA - Register array accessors */
screamer 0:c5e2f793b59a 4735 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
screamer 0:c5e2f793b59a 4736 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
screamer 0:c5e2f793b59a 4737 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
screamer 0:c5e2f793b59a 4738 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
screamer 0:c5e2f793b59a 4739 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
screamer 0:c5e2f793b59a 4740 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
screamer 0:c5e2f793b59a 4741 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
screamer 0:c5e2f793b59a 4742 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
screamer 0:c5e2f793b59a 4743 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
screamer 0:c5e2f793b59a 4744 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
screamer 0:c5e2f793b59a 4745 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
screamer 0:c5e2f793b59a 4746 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
screamer 0:c5e2f793b59a 4747 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
screamer 0:c5e2f793b59a 4748 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
screamer 0:c5e2f793b59a 4749 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
screamer 0:c5e2f793b59a 4750
screamer 0:c5e2f793b59a 4751 /*!
screamer 0:c5e2f793b59a 4752 * @}
screamer 0:c5e2f793b59a 4753 */ /* end of group DMA_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 4754
screamer 0:c5e2f793b59a 4755
screamer 0:c5e2f793b59a 4756 /*!
screamer 0:c5e2f793b59a 4757 * @}
screamer 0:c5e2f793b59a 4758 */ /* end of group DMA_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 4759
screamer 0:c5e2f793b59a 4760
screamer 0:c5e2f793b59a 4761 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 4762 -- DMAMUX Peripheral Access Layer
screamer 0:c5e2f793b59a 4763 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 4764
screamer 0:c5e2f793b59a 4765 /*!
screamer 0:c5e2f793b59a 4766 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
screamer 0:c5e2f793b59a 4767 * @{
screamer 0:c5e2f793b59a 4768 */
screamer 0:c5e2f793b59a 4769
screamer 0:c5e2f793b59a 4770 /** DMAMUX - Register Layout Typedef */
screamer 0:c5e2f793b59a 4771 typedef struct {
screamer 0:c5e2f793b59a 4772 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
screamer 0:c5e2f793b59a 4773 } DMAMUX_Type, *DMAMUX_MemMapPtr;
screamer 0:c5e2f793b59a 4774
screamer 0:c5e2f793b59a 4775 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 4776 -- DMAMUX - Register accessor macros
screamer 0:c5e2f793b59a 4777 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 4778
screamer 0:c5e2f793b59a 4779 /*!
screamer 0:c5e2f793b59a 4780 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
screamer 0:c5e2f793b59a 4781 * @{
screamer 0:c5e2f793b59a 4782 */
screamer 0:c5e2f793b59a 4783
screamer 0:c5e2f793b59a 4784
screamer 0:c5e2f793b59a 4785 /* DMAMUX - Register accessors */
screamer 0:c5e2f793b59a 4786 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
screamer 0:c5e2f793b59a 4787
screamer 0:c5e2f793b59a 4788 /*!
screamer 0:c5e2f793b59a 4789 * @}
screamer 0:c5e2f793b59a 4790 */ /* end of group DMAMUX_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 4791
screamer 0:c5e2f793b59a 4792
screamer 0:c5e2f793b59a 4793 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 4794 -- DMAMUX Register Masks
screamer 0:c5e2f793b59a 4795 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 4796
screamer 0:c5e2f793b59a 4797 /*!
screamer 0:c5e2f793b59a 4798 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
screamer 0:c5e2f793b59a 4799 * @{
screamer 0:c5e2f793b59a 4800 */
screamer 0:c5e2f793b59a 4801
screamer 0:c5e2f793b59a 4802 /* CHCFG Bit Fields */
screamer 0:c5e2f793b59a 4803 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
screamer 0:c5e2f793b59a 4804 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
screamer 0:c5e2f793b59a 4805 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
screamer 0:c5e2f793b59a 4806 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
screamer 0:c5e2f793b59a 4807 #define DMAMUX_CHCFG_TRIG_SHIFT 6
screamer 0:c5e2f793b59a 4808 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
screamer 0:c5e2f793b59a 4809 #define DMAMUX_CHCFG_ENBL_SHIFT 7
screamer 0:c5e2f793b59a 4810
screamer 0:c5e2f793b59a 4811 /*!
screamer 0:c5e2f793b59a 4812 * @}
screamer 0:c5e2f793b59a 4813 */ /* end of group DMAMUX_Register_Masks */
screamer 0:c5e2f793b59a 4814
screamer 0:c5e2f793b59a 4815
screamer 0:c5e2f793b59a 4816 /* DMAMUX - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 4817 /** Peripheral DMAMUX base address */
screamer 0:c5e2f793b59a 4818 #define DMAMUX_BASE (0x40021000u)
screamer 0:c5e2f793b59a 4819 /** Peripheral DMAMUX base pointer */
screamer 0:c5e2f793b59a 4820 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
screamer 0:c5e2f793b59a 4821 #define DMAMUX_BASE_PTR (DMAMUX)
screamer 0:c5e2f793b59a 4822 /** Array initializer of DMAMUX peripheral base addresses */
screamer 0:c5e2f793b59a 4823 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
screamer 0:c5e2f793b59a 4824 /** Array initializer of DMAMUX peripheral base pointers */
screamer 0:c5e2f793b59a 4825 #define DMAMUX_BASE_PTRS { DMAMUX }
screamer 0:c5e2f793b59a 4826
screamer 0:c5e2f793b59a 4827 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 4828 -- DMAMUX - Register accessor macros
screamer 0:c5e2f793b59a 4829 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 4830
screamer 0:c5e2f793b59a 4831 /*!
screamer 0:c5e2f793b59a 4832 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
screamer 0:c5e2f793b59a 4833 * @{
screamer 0:c5e2f793b59a 4834 */
screamer 0:c5e2f793b59a 4835
screamer 0:c5e2f793b59a 4836
screamer 0:c5e2f793b59a 4837 /* DMAMUX - Register instance definitions */
screamer 0:c5e2f793b59a 4838 /* DMAMUX */
screamer 0:c5e2f793b59a 4839 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
screamer 0:c5e2f793b59a 4840 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
screamer 0:c5e2f793b59a 4841 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
screamer 0:c5e2f793b59a 4842 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
screamer 0:c5e2f793b59a 4843 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
screamer 0:c5e2f793b59a 4844 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
screamer 0:c5e2f793b59a 4845 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
screamer 0:c5e2f793b59a 4846 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
screamer 0:c5e2f793b59a 4847 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
screamer 0:c5e2f793b59a 4848 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
screamer 0:c5e2f793b59a 4849 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
screamer 0:c5e2f793b59a 4850 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
screamer 0:c5e2f793b59a 4851 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
screamer 0:c5e2f793b59a 4852 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
screamer 0:c5e2f793b59a 4853 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
screamer 0:c5e2f793b59a 4854 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
screamer 0:c5e2f793b59a 4855
screamer 0:c5e2f793b59a 4856 /* DMAMUX - Register array accessors */
screamer 0:c5e2f793b59a 4857 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
screamer 0:c5e2f793b59a 4858
screamer 0:c5e2f793b59a 4859 /*!
screamer 0:c5e2f793b59a 4860 * @}
screamer 0:c5e2f793b59a 4861 */ /* end of group DMAMUX_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 4862
screamer 0:c5e2f793b59a 4863
screamer 0:c5e2f793b59a 4864 /*!
screamer 0:c5e2f793b59a 4865 * @}
screamer 0:c5e2f793b59a 4866 */ /* end of group DMAMUX_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 4867
screamer 0:c5e2f793b59a 4868
screamer 0:c5e2f793b59a 4869 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 4870 -- ENET Peripheral Access Layer
screamer 0:c5e2f793b59a 4871 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 4872
screamer 0:c5e2f793b59a 4873 /*!
screamer 0:c5e2f793b59a 4874 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
screamer 0:c5e2f793b59a 4875 * @{
screamer 0:c5e2f793b59a 4876 */
screamer 0:c5e2f793b59a 4877
screamer 0:c5e2f793b59a 4878 /** ENET - Register Layout Typedef */
screamer 0:c5e2f793b59a 4879 typedef struct {
screamer 0:c5e2f793b59a 4880 uint8_t RESERVED_0[4];
screamer 0:c5e2f793b59a 4881 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
screamer 0:c5e2f793b59a 4882 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
screamer 0:c5e2f793b59a 4883 uint8_t RESERVED_1[4];
screamer 0:c5e2f793b59a 4884 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
screamer 0:c5e2f793b59a 4885 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
screamer 0:c5e2f793b59a 4886 uint8_t RESERVED_2[12];
screamer 0:c5e2f793b59a 4887 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
screamer 0:c5e2f793b59a 4888 uint8_t RESERVED_3[24];
screamer 0:c5e2f793b59a 4889 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
screamer 0:c5e2f793b59a 4890 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
screamer 0:c5e2f793b59a 4891 uint8_t RESERVED_4[28];
screamer 0:c5e2f793b59a 4892 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
screamer 0:c5e2f793b59a 4893 uint8_t RESERVED_5[28];
screamer 0:c5e2f793b59a 4894 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
screamer 0:c5e2f793b59a 4895 uint8_t RESERVED_6[60];
screamer 0:c5e2f793b59a 4896 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
screamer 0:c5e2f793b59a 4897 uint8_t RESERVED_7[28];
screamer 0:c5e2f793b59a 4898 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
screamer 0:c5e2f793b59a 4899 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
screamer 0:c5e2f793b59a 4900 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
screamer 0:c5e2f793b59a 4901 uint8_t RESERVED_8[40];
screamer 0:c5e2f793b59a 4902 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
screamer 0:c5e2f793b59a 4903 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
screamer 0:c5e2f793b59a 4904 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
screamer 0:c5e2f793b59a 4905 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
screamer 0:c5e2f793b59a 4906 uint8_t RESERVED_9[28];
screamer 0:c5e2f793b59a 4907 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
screamer 0:c5e2f793b59a 4908 uint8_t RESERVED_10[56];
screamer 0:c5e2f793b59a 4909 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
screamer 0:c5e2f793b59a 4910 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
screamer 0:c5e2f793b59a 4911 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
screamer 0:c5e2f793b59a 4912 uint8_t RESERVED_11[4];
screamer 0:c5e2f793b59a 4913 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
screamer 0:c5e2f793b59a 4914 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
screamer 0:c5e2f793b59a 4915 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
screamer 0:c5e2f793b59a 4916 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
screamer 0:c5e2f793b59a 4917 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
screamer 0:c5e2f793b59a 4918 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
screamer 0:c5e2f793b59a 4919 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
screamer 0:c5e2f793b59a 4920 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
screamer 0:c5e2f793b59a 4921 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
screamer 0:c5e2f793b59a 4922 uint8_t RESERVED_12[12];
screamer 0:c5e2f793b59a 4923 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
screamer 0:c5e2f793b59a 4924 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
screamer 0:c5e2f793b59a 4925 uint8_t RESERVED_13[60];
screamer 0:c5e2f793b59a 4926 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
screamer 0:c5e2f793b59a 4927 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
screamer 0:c5e2f793b59a 4928 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
screamer 0:c5e2f793b59a 4929 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
screamer 0:c5e2f793b59a 4930 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
screamer 0:c5e2f793b59a 4931 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
screamer 0:c5e2f793b59a 4932 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
screamer 0:c5e2f793b59a 4933 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
screamer 0:c5e2f793b59a 4934 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
screamer 0:c5e2f793b59a 4935 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
screamer 0:c5e2f793b59a 4936 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
screamer 0:c5e2f793b59a 4937 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
screamer 0:c5e2f793b59a 4938 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
screamer 0:c5e2f793b59a 4939 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
screamer 0:c5e2f793b59a 4940 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
screamer 0:c5e2f793b59a 4941 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
screamer 0:c5e2f793b59a 4942 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
screamer 0:c5e2f793b59a 4943 uint8_t RESERVED_14[4];
screamer 0:c5e2f793b59a 4944 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
screamer 0:c5e2f793b59a 4945 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
screamer 0:c5e2f793b59a 4946 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
screamer 0:c5e2f793b59a 4947 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
screamer 0:c5e2f793b59a 4948 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
screamer 0:c5e2f793b59a 4949 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
screamer 0:c5e2f793b59a 4950 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
screamer 0:c5e2f793b59a 4951 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
screamer 0:c5e2f793b59a 4952 uint8_t RESERVED_15[4];
screamer 0:c5e2f793b59a 4953 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
screamer 0:c5e2f793b59a 4954 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
screamer 0:c5e2f793b59a 4955 uint8_t RESERVED_16[12];
screamer 0:c5e2f793b59a 4956 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
screamer 0:c5e2f793b59a 4957 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
screamer 0:c5e2f793b59a 4958 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
screamer 0:c5e2f793b59a 4959 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
screamer 0:c5e2f793b59a 4960 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
screamer 0:c5e2f793b59a 4961 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
screamer 0:c5e2f793b59a 4962 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
screamer 0:c5e2f793b59a 4963 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
screamer 0:c5e2f793b59a 4964 uint8_t RESERVED_17[4];
screamer 0:c5e2f793b59a 4965 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
screamer 0:c5e2f793b59a 4966 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
screamer 0:c5e2f793b59a 4967 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
screamer 0:c5e2f793b59a 4968 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
screamer 0:c5e2f793b59a 4969 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
screamer 0:c5e2f793b59a 4970 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
screamer 0:c5e2f793b59a 4971 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
screamer 0:c5e2f793b59a 4972 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
screamer 0:c5e2f793b59a 4973 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
screamer 0:c5e2f793b59a 4974 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
screamer 0:c5e2f793b59a 4975 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
screamer 0:c5e2f793b59a 4976 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
screamer 0:c5e2f793b59a 4977 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
screamer 0:c5e2f793b59a 4978 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
screamer 0:c5e2f793b59a 4979 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
screamer 0:c5e2f793b59a 4980 uint8_t RESERVED_18[284];
screamer 0:c5e2f793b59a 4981 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
screamer 0:c5e2f793b59a 4982 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
screamer 0:c5e2f793b59a 4983 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
screamer 0:c5e2f793b59a 4984 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
screamer 0:c5e2f793b59a 4985 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
screamer 0:c5e2f793b59a 4986 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
screamer 0:c5e2f793b59a 4987 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
screamer 0:c5e2f793b59a 4988 uint8_t RESERVED_19[488];
screamer 0:c5e2f793b59a 4989 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
screamer 0:c5e2f793b59a 4990 struct { /* offset: 0x608, array step: 0x8 */
screamer 0:c5e2f793b59a 4991 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
screamer 0:c5e2f793b59a 4992 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
screamer 0:c5e2f793b59a 4993 } CHANNEL[4];
screamer 0:c5e2f793b59a 4994 } ENET_Type, *ENET_MemMapPtr;
screamer 0:c5e2f793b59a 4995
screamer 0:c5e2f793b59a 4996 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 4997 -- ENET - Register accessor macros
screamer 0:c5e2f793b59a 4998 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 4999
screamer 0:c5e2f793b59a 5000 /*!
screamer 0:c5e2f793b59a 5001 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
screamer 0:c5e2f793b59a 5002 * @{
screamer 0:c5e2f793b59a 5003 */
screamer 0:c5e2f793b59a 5004
screamer 0:c5e2f793b59a 5005
screamer 0:c5e2f793b59a 5006 /* ENET - Register accessors */
screamer 0:c5e2f793b59a 5007 #define ENET_EIR_REG(base) ((base)->EIR)
screamer 0:c5e2f793b59a 5008 #define ENET_EIMR_REG(base) ((base)->EIMR)
screamer 0:c5e2f793b59a 5009 #define ENET_RDAR_REG(base) ((base)->RDAR)
screamer 0:c5e2f793b59a 5010 #define ENET_TDAR_REG(base) ((base)->TDAR)
screamer 0:c5e2f793b59a 5011 #define ENET_ECR_REG(base) ((base)->ECR)
screamer 0:c5e2f793b59a 5012 #define ENET_MMFR_REG(base) ((base)->MMFR)
screamer 0:c5e2f793b59a 5013 #define ENET_MSCR_REG(base) ((base)->MSCR)
screamer 0:c5e2f793b59a 5014 #define ENET_MIBC_REG(base) ((base)->MIBC)
screamer 0:c5e2f793b59a 5015 #define ENET_RCR_REG(base) ((base)->RCR)
screamer 0:c5e2f793b59a 5016 #define ENET_TCR_REG(base) ((base)->TCR)
screamer 0:c5e2f793b59a 5017 #define ENET_PALR_REG(base) ((base)->PALR)
screamer 0:c5e2f793b59a 5018 #define ENET_PAUR_REG(base) ((base)->PAUR)
screamer 0:c5e2f793b59a 5019 #define ENET_OPD_REG(base) ((base)->OPD)
screamer 0:c5e2f793b59a 5020 #define ENET_IAUR_REG(base) ((base)->IAUR)
screamer 0:c5e2f793b59a 5021 #define ENET_IALR_REG(base) ((base)->IALR)
screamer 0:c5e2f793b59a 5022 #define ENET_GAUR_REG(base) ((base)->GAUR)
screamer 0:c5e2f793b59a 5023 #define ENET_GALR_REG(base) ((base)->GALR)
screamer 0:c5e2f793b59a 5024 #define ENET_TFWR_REG(base) ((base)->TFWR)
screamer 0:c5e2f793b59a 5025 #define ENET_RDSR_REG(base) ((base)->RDSR)
screamer 0:c5e2f793b59a 5026 #define ENET_TDSR_REG(base) ((base)->TDSR)
screamer 0:c5e2f793b59a 5027 #define ENET_MRBR_REG(base) ((base)->MRBR)
screamer 0:c5e2f793b59a 5028 #define ENET_RSFL_REG(base) ((base)->RSFL)
screamer 0:c5e2f793b59a 5029 #define ENET_RSEM_REG(base) ((base)->RSEM)
screamer 0:c5e2f793b59a 5030 #define ENET_RAEM_REG(base) ((base)->RAEM)
screamer 0:c5e2f793b59a 5031 #define ENET_RAFL_REG(base) ((base)->RAFL)
screamer 0:c5e2f793b59a 5032 #define ENET_TSEM_REG(base) ((base)->TSEM)
screamer 0:c5e2f793b59a 5033 #define ENET_TAEM_REG(base) ((base)->TAEM)
screamer 0:c5e2f793b59a 5034 #define ENET_TAFL_REG(base) ((base)->TAFL)
screamer 0:c5e2f793b59a 5035 #define ENET_TIPG_REG(base) ((base)->TIPG)
screamer 0:c5e2f793b59a 5036 #define ENET_FTRL_REG(base) ((base)->FTRL)
screamer 0:c5e2f793b59a 5037 #define ENET_TACC_REG(base) ((base)->TACC)
screamer 0:c5e2f793b59a 5038 #define ENET_RACC_REG(base) ((base)->RACC)
screamer 0:c5e2f793b59a 5039 #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
screamer 0:c5e2f793b59a 5040 #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
screamer 0:c5e2f793b59a 5041 #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
screamer 0:c5e2f793b59a 5042 #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
screamer 0:c5e2f793b59a 5043 #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
screamer 0:c5e2f793b59a 5044 #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
screamer 0:c5e2f793b59a 5045 #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
screamer 0:c5e2f793b59a 5046 #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
screamer 0:c5e2f793b59a 5047 #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
screamer 0:c5e2f793b59a 5048 #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
screamer 0:c5e2f793b59a 5049 #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
screamer 0:c5e2f793b59a 5050 #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
screamer 0:c5e2f793b59a 5051 #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
screamer 0:c5e2f793b59a 5052 #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
screamer 0:c5e2f793b59a 5053 #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
screamer 0:c5e2f793b59a 5054 #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
screamer 0:c5e2f793b59a 5055 #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
screamer 0:c5e2f793b59a 5056 #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
screamer 0:c5e2f793b59a 5057 #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
screamer 0:c5e2f793b59a 5058 #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
screamer 0:c5e2f793b59a 5059 #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
screamer 0:c5e2f793b59a 5060 #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
screamer 0:c5e2f793b59a 5061 #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
screamer 0:c5e2f793b59a 5062 #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
screamer 0:c5e2f793b59a 5063 #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
screamer 0:c5e2f793b59a 5064 #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
screamer 0:c5e2f793b59a 5065 #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
screamer 0:c5e2f793b59a 5066 #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
screamer 0:c5e2f793b59a 5067 #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
screamer 0:c5e2f793b59a 5068 #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
screamer 0:c5e2f793b59a 5069 #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
screamer 0:c5e2f793b59a 5070 #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
screamer 0:c5e2f793b59a 5071 #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
screamer 0:c5e2f793b59a 5072 #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
screamer 0:c5e2f793b59a 5073 #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
screamer 0:c5e2f793b59a 5074 #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
screamer 0:c5e2f793b59a 5075 #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
screamer 0:c5e2f793b59a 5076 #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
screamer 0:c5e2f793b59a 5077 #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
screamer 0:c5e2f793b59a 5078 #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
screamer 0:c5e2f793b59a 5079 #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
screamer 0:c5e2f793b59a 5080 #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)
screamer 0:c5e2f793b59a 5081 #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
screamer 0:c5e2f793b59a 5082 #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
screamer 0:c5e2f793b59a 5083 #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
screamer 0:c5e2f793b59a 5084 #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
screamer 0:c5e2f793b59a 5085 #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
screamer 0:c5e2f793b59a 5086 #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
screamer 0:c5e2f793b59a 5087 #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
screamer 0:c5e2f793b59a 5088 #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
screamer 0:c5e2f793b59a 5089 #define ENET_ATCR_REG(base) ((base)->ATCR)
screamer 0:c5e2f793b59a 5090 #define ENET_ATVR_REG(base) ((base)->ATVR)
screamer 0:c5e2f793b59a 5091 #define ENET_ATOFF_REG(base) ((base)->ATOFF)
screamer 0:c5e2f793b59a 5092 #define ENET_ATPER_REG(base) ((base)->ATPER)
screamer 0:c5e2f793b59a 5093 #define ENET_ATCOR_REG(base) ((base)->ATCOR)
screamer 0:c5e2f793b59a 5094 #define ENET_ATINC_REG(base) ((base)->ATINC)
screamer 0:c5e2f793b59a 5095 #define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
screamer 0:c5e2f793b59a 5096 #define ENET_TGSR_REG(base) ((base)->TGSR)
screamer 0:c5e2f793b59a 5097 #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
screamer 0:c5e2f793b59a 5098 #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
screamer 0:c5e2f793b59a 5099
screamer 0:c5e2f793b59a 5100 /*!
screamer 0:c5e2f793b59a 5101 * @}
screamer 0:c5e2f793b59a 5102 */ /* end of group ENET_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 5103
screamer 0:c5e2f793b59a 5104
screamer 0:c5e2f793b59a 5105 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5106 -- ENET Register Masks
screamer 0:c5e2f793b59a 5107 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5108
screamer 0:c5e2f793b59a 5109 /*!
screamer 0:c5e2f793b59a 5110 * @addtogroup ENET_Register_Masks ENET Register Masks
screamer 0:c5e2f793b59a 5111 * @{
screamer 0:c5e2f793b59a 5112 */
screamer 0:c5e2f793b59a 5113
screamer 0:c5e2f793b59a 5114 /* EIR Bit Fields */
screamer 0:c5e2f793b59a 5115 #define ENET_EIR_TS_TIMER_MASK 0x8000u
screamer 0:c5e2f793b59a 5116 #define ENET_EIR_TS_TIMER_SHIFT 15
screamer 0:c5e2f793b59a 5117 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
screamer 0:c5e2f793b59a 5118 #define ENET_EIR_TS_AVAIL_SHIFT 16
screamer 0:c5e2f793b59a 5119 #define ENET_EIR_WAKEUP_MASK 0x20000u
screamer 0:c5e2f793b59a 5120 #define ENET_EIR_WAKEUP_SHIFT 17
screamer 0:c5e2f793b59a 5121 #define ENET_EIR_PLR_MASK 0x40000u
screamer 0:c5e2f793b59a 5122 #define ENET_EIR_PLR_SHIFT 18
screamer 0:c5e2f793b59a 5123 #define ENET_EIR_UN_MASK 0x80000u
screamer 0:c5e2f793b59a 5124 #define ENET_EIR_UN_SHIFT 19
screamer 0:c5e2f793b59a 5125 #define ENET_EIR_RL_MASK 0x100000u
screamer 0:c5e2f793b59a 5126 #define ENET_EIR_RL_SHIFT 20
screamer 0:c5e2f793b59a 5127 #define ENET_EIR_LC_MASK 0x200000u
screamer 0:c5e2f793b59a 5128 #define ENET_EIR_LC_SHIFT 21
screamer 0:c5e2f793b59a 5129 #define ENET_EIR_EBERR_MASK 0x400000u
screamer 0:c5e2f793b59a 5130 #define ENET_EIR_EBERR_SHIFT 22
screamer 0:c5e2f793b59a 5131 #define ENET_EIR_MII_MASK 0x800000u
screamer 0:c5e2f793b59a 5132 #define ENET_EIR_MII_SHIFT 23
screamer 0:c5e2f793b59a 5133 #define ENET_EIR_RXB_MASK 0x1000000u
screamer 0:c5e2f793b59a 5134 #define ENET_EIR_RXB_SHIFT 24
screamer 0:c5e2f793b59a 5135 #define ENET_EIR_RXF_MASK 0x2000000u
screamer 0:c5e2f793b59a 5136 #define ENET_EIR_RXF_SHIFT 25
screamer 0:c5e2f793b59a 5137 #define ENET_EIR_TXB_MASK 0x4000000u
screamer 0:c5e2f793b59a 5138 #define ENET_EIR_TXB_SHIFT 26
screamer 0:c5e2f793b59a 5139 #define ENET_EIR_TXF_MASK 0x8000000u
screamer 0:c5e2f793b59a 5140 #define ENET_EIR_TXF_SHIFT 27
screamer 0:c5e2f793b59a 5141 #define ENET_EIR_GRA_MASK 0x10000000u
screamer 0:c5e2f793b59a 5142 #define ENET_EIR_GRA_SHIFT 28
screamer 0:c5e2f793b59a 5143 #define ENET_EIR_BABT_MASK 0x20000000u
screamer 0:c5e2f793b59a 5144 #define ENET_EIR_BABT_SHIFT 29
screamer 0:c5e2f793b59a 5145 #define ENET_EIR_BABR_MASK 0x40000000u
screamer 0:c5e2f793b59a 5146 #define ENET_EIR_BABR_SHIFT 30
screamer 0:c5e2f793b59a 5147 /* EIMR Bit Fields */
screamer 0:c5e2f793b59a 5148 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
screamer 0:c5e2f793b59a 5149 #define ENET_EIMR_TS_TIMER_SHIFT 15
screamer 0:c5e2f793b59a 5150 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
screamer 0:c5e2f793b59a 5151 #define ENET_EIMR_TS_AVAIL_SHIFT 16
screamer 0:c5e2f793b59a 5152 #define ENET_EIMR_WAKEUP_MASK 0x20000u
screamer 0:c5e2f793b59a 5153 #define ENET_EIMR_WAKEUP_SHIFT 17
screamer 0:c5e2f793b59a 5154 #define ENET_EIMR_PLR_MASK 0x40000u
screamer 0:c5e2f793b59a 5155 #define ENET_EIMR_PLR_SHIFT 18
screamer 0:c5e2f793b59a 5156 #define ENET_EIMR_UN_MASK 0x80000u
screamer 0:c5e2f793b59a 5157 #define ENET_EIMR_UN_SHIFT 19
screamer 0:c5e2f793b59a 5158 #define ENET_EIMR_RL_MASK 0x100000u
screamer 0:c5e2f793b59a 5159 #define ENET_EIMR_RL_SHIFT 20
screamer 0:c5e2f793b59a 5160 #define ENET_EIMR_LC_MASK 0x200000u
screamer 0:c5e2f793b59a 5161 #define ENET_EIMR_LC_SHIFT 21
screamer 0:c5e2f793b59a 5162 #define ENET_EIMR_EBERR_MASK 0x400000u
screamer 0:c5e2f793b59a 5163 #define ENET_EIMR_EBERR_SHIFT 22
screamer 0:c5e2f793b59a 5164 #define ENET_EIMR_MII_MASK 0x800000u
screamer 0:c5e2f793b59a 5165 #define ENET_EIMR_MII_SHIFT 23
screamer 0:c5e2f793b59a 5166 #define ENET_EIMR_RXB_MASK 0x1000000u
screamer 0:c5e2f793b59a 5167 #define ENET_EIMR_RXB_SHIFT 24
screamer 0:c5e2f793b59a 5168 #define ENET_EIMR_RXF_MASK 0x2000000u
screamer 0:c5e2f793b59a 5169 #define ENET_EIMR_RXF_SHIFT 25
screamer 0:c5e2f793b59a 5170 #define ENET_EIMR_TXB_MASK 0x4000000u
screamer 0:c5e2f793b59a 5171 #define ENET_EIMR_TXB_SHIFT 26
screamer 0:c5e2f793b59a 5172 #define ENET_EIMR_TXF_MASK 0x8000000u
screamer 0:c5e2f793b59a 5173 #define ENET_EIMR_TXF_SHIFT 27
screamer 0:c5e2f793b59a 5174 #define ENET_EIMR_GRA_MASK 0x10000000u
screamer 0:c5e2f793b59a 5175 #define ENET_EIMR_GRA_SHIFT 28
screamer 0:c5e2f793b59a 5176 #define ENET_EIMR_BABT_MASK 0x20000000u
screamer 0:c5e2f793b59a 5177 #define ENET_EIMR_BABT_SHIFT 29
screamer 0:c5e2f793b59a 5178 #define ENET_EIMR_BABR_MASK 0x40000000u
screamer 0:c5e2f793b59a 5179 #define ENET_EIMR_BABR_SHIFT 30
screamer 0:c5e2f793b59a 5180 /* RDAR Bit Fields */
screamer 0:c5e2f793b59a 5181 #define ENET_RDAR_RDAR_MASK 0x1000000u
screamer 0:c5e2f793b59a 5182 #define ENET_RDAR_RDAR_SHIFT 24
screamer 0:c5e2f793b59a 5183 /* TDAR Bit Fields */
screamer 0:c5e2f793b59a 5184 #define ENET_TDAR_TDAR_MASK 0x1000000u
screamer 0:c5e2f793b59a 5185 #define ENET_TDAR_TDAR_SHIFT 24
screamer 0:c5e2f793b59a 5186 /* ECR Bit Fields */
screamer 0:c5e2f793b59a 5187 #define ENET_ECR_RESET_MASK 0x1u
screamer 0:c5e2f793b59a 5188 #define ENET_ECR_RESET_SHIFT 0
screamer 0:c5e2f793b59a 5189 #define ENET_ECR_ETHEREN_MASK 0x2u
screamer 0:c5e2f793b59a 5190 #define ENET_ECR_ETHEREN_SHIFT 1
screamer 0:c5e2f793b59a 5191 #define ENET_ECR_MAGICEN_MASK 0x4u
screamer 0:c5e2f793b59a 5192 #define ENET_ECR_MAGICEN_SHIFT 2
screamer 0:c5e2f793b59a 5193 #define ENET_ECR_SLEEP_MASK 0x8u
screamer 0:c5e2f793b59a 5194 #define ENET_ECR_SLEEP_SHIFT 3
screamer 0:c5e2f793b59a 5195 #define ENET_ECR_EN1588_MASK 0x10u
screamer 0:c5e2f793b59a 5196 #define ENET_ECR_EN1588_SHIFT 4
screamer 0:c5e2f793b59a 5197 #define ENET_ECR_DBGEN_MASK 0x40u
screamer 0:c5e2f793b59a 5198 #define ENET_ECR_DBGEN_SHIFT 6
screamer 0:c5e2f793b59a 5199 #define ENET_ECR_STOPEN_MASK 0x80u
screamer 0:c5e2f793b59a 5200 #define ENET_ECR_STOPEN_SHIFT 7
screamer 0:c5e2f793b59a 5201 #define ENET_ECR_DBSWP_MASK 0x100u
screamer 0:c5e2f793b59a 5202 #define ENET_ECR_DBSWP_SHIFT 8
screamer 0:c5e2f793b59a 5203 /* MMFR Bit Fields */
screamer 0:c5e2f793b59a 5204 #define ENET_MMFR_DATA_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5205 #define ENET_MMFR_DATA_SHIFT 0
screamer 0:c5e2f793b59a 5206 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
screamer 0:c5e2f793b59a 5207 #define ENET_MMFR_TA_MASK 0x30000u
screamer 0:c5e2f793b59a 5208 #define ENET_MMFR_TA_SHIFT 16
screamer 0:c5e2f793b59a 5209 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
screamer 0:c5e2f793b59a 5210 #define ENET_MMFR_RA_MASK 0x7C0000u
screamer 0:c5e2f793b59a 5211 #define ENET_MMFR_RA_SHIFT 18
screamer 0:c5e2f793b59a 5212 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
screamer 0:c5e2f793b59a 5213 #define ENET_MMFR_PA_MASK 0xF800000u
screamer 0:c5e2f793b59a 5214 #define ENET_MMFR_PA_SHIFT 23
screamer 0:c5e2f793b59a 5215 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
screamer 0:c5e2f793b59a 5216 #define ENET_MMFR_OP_MASK 0x30000000u
screamer 0:c5e2f793b59a 5217 #define ENET_MMFR_OP_SHIFT 28
screamer 0:c5e2f793b59a 5218 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
screamer 0:c5e2f793b59a 5219 #define ENET_MMFR_ST_MASK 0xC0000000u
screamer 0:c5e2f793b59a 5220 #define ENET_MMFR_ST_SHIFT 30
screamer 0:c5e2f793b59a 5221 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
screamer 0:c5e2f793b59a 5222 /* MSCR Bit Fields */
screamer 0:c5e2f793b59a 5223 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
screamer 0:c5e2f793b59a 5224 #define ENET_MSCR_MII_SPEED_SHIFT 1
screamer 0:c5e2f793b59a 5225 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
screamer 0:c5e2f793b59a 5226 #define ENET_MSCR_DIS_PRE_MASK 0x80u
screamer 0:c5e2f793b59a 5227 #define ENET_MSCR_DIS_PRE_SHIFT 7
screamer 0:c5e2f793b59a 5228 #define ENET_MSCR_HOLDTIME_MASK 0x700u
screamer 0:c5e2f793b59a 5229 #define ENET_MSCR_HOLDTIME_SHIFT 8
screamer 0:c5e2f793b59a 5230 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
screamer 0:c5e2f793b59a 5231 /* MIBC Bit Fields */
screamer 0:c5e2f793b59a 5232 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
screamer 0:c5e2f793b59a 5233 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
screamer 0:c5e2f793b59a 5234 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
screamer 0:c5e2f793b59a 5235 #define ENET_MIBC_MIB_IDLE_SHIFT 30
screamer 0:c5e2f793b59a 5236 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
screamer 0:c5e2f793b59a 5237 #define ENET_MIBC_MIB_DIS_SHIFT 31
screamer 0:c5e2f793b59a 5238 /* RCR Bit Fields */
screamer 0:c5e2f793b59a 5239 #define ENET_RCR_LOOP_MASK 0x1u
screamer 0:c5e2f793b59a 5240 #define ENET_RCR_LOOP_SHIFT 0
screamer 0:c5e2f793b59a 5241 #define ENET_RCR_DRT_MASK 0x2u
screamer 0:c5e2f793b59a 5242 #define ENET_RCR_DRT_SHIFT 1
screamer 0:c5e2f793b59a 5243 #define ENET_RCR_MII_MODE_MASK 0x4u
screamer 0:c5e2f793b59a 5244 #define ENET_RCR_MII_MODE_SHIFT 2
screamer 0:c5e2f793b59a 5245 #define ENET_RCR_PROM_MASK 0x8u
screamer 0:c5e2f793b59a 5246 #define ENET_RCR_PROM_SHIFT 3
screamer 0:c5e2f793b59a 5247 #define ENET_RCR_BC_REJ_MASK 0x10u
screamer 0:c5e2f793b59a 5248 #define ENET_RCR_BC_REJ_SHIFT 4
screamer 0:c5e2f793b59a 5249 #define ENET_RCR_FCE_MASK 0x20u
screamer 0:c5e2f793b59a 5250 #define ENET_RCR_FCE_SHIFT 5
screamer 0:c5e2f793b59a 5251 #define ENET_RCR_RMII_MODE_MASK 0x100u
screamer 0:c5e2f793b59a 5252 #define ENET_RCR_RMII_MODE_SHIFT 8
screamer 0:c5e2f793b59a 5253 #define ENET_RCR_RMII_10T_MASK 0x200u
screamer 0:c5e2f793b59a 5254 #define ENET_RCR_RMII_10T_SHIFT 9
screamer 0:c5e2f793b59a 5255 #define ENET_RCR_PADEN_MASK 0x1000u
screamer 0:c5e2f793b59a 5256 #define ENET_RCR_PADEN_SHIFT 12
screamer 0:c5e2f793b59a 5257 #define ENET_RCR_PAUFWD_MASK 0x2000u
screamer 0:c5e2f793b59a 5258 #define ENET_RCR_PAUFWD_SHIFT 13
screamer 0:c5e2f793b59a 5259 #define ENET_RCR_CRCFWD_MASK 0x4000u
screamer 0:c5e2f793b59a 5260 #define ENET_RCR_CRCFWD_SHIFT 14
screamer 0:c5e2f793b59a 5261 #define ENET_RCR_CFEN_MASK 0x8000u
screamer 0:c5e2f793b59a 5262 #define ENET_RCR_CFEN_SHIFT 15
screamer 0:c5e2f793b59a 5263 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
screamer 0:c5e2f793b59a 5264 #define ENET_RCR_MAX_FL_SHIFT 16
screamer 0:c5e2f793b59a 5265 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
screamer 0:c5e2f793b59a 5266 #define ENET_RCR_NLC_MASK 0x40000000u
screamer 0:c5e2f793b59a 5267 #define ENET_RCR_NLC_SHIFT 30
screamer 0:c5e2f793b59a 5268 #define ENET_RCR_GRS_MASK 0x80000000u
screamer 0:c5e2f793b59a 5269 #define ENET_RCR_GRS_SHIFT 31
screamer 0:c5e2f793b59a 5270 /* TCR Bit Fields */
screamer 0:c5e2f793b59a 5271 #define ENET_TCR_GTS_MASK 0x1u
screamer 0:c5e2f793b59a 5272 #define ENET_TCR_GTS_SHIFT 0
screamer 0:c5e2f793b59a 5273 #define ENET_TCR_FDEN_MASK 0x4u
screamer 0:c5e2f793b59a 5274 #define ENET_TCR_FDEN_SHIFT 2
screamer 0:c5e2f793b59a 5275 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
screamer 0:c5e2f793b59a 5276 #define ENET_TCR_TFC_PAUSE_SHIFT 3
screamer 0:c5e2f793b59a 5277 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
screamer 0:c5e2f793b59a 5278 #define ENET_TCR_RFC_PAUSE_SHIFT 4
screamer 0:c5e2f793b59a 5279 #define ENET_TCR_ADDSEL_MASK 0xE0u
screamer 0:c5e2f793b59a 5280 #define ENET_TCR_ADDSEL_SHIFT 5
screamer 0:c5e2f793b59a 5281 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
screamer 0:c5e2f793b59a 5282 #define ENET_TCR_ADDINS_MASK 0x100u
screamer 0:c5e2f793b59a 5283 #define ENET_TCR_ADDINS_SHIFT 8
screamer 0:c5e2f793b59a 5284 #define ENET_TCR_CRCFWD_MASK 0x200u
screamer 0:c5e2f793b59a 5285 #define ENET_TCR_CRCFWD_SHIFT 9
screamer 0:c5e2f793b59a 5286 /* PALR Bit Fields */
screamer 0:c5e2f793b59a 5287 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5288 #define ENET_PALR_PADDR1_SHIFT 0
screamer 0:c5e2f793b59a 5289 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
screamer 0:c5e2f793b59a 5290 /* PAUR Bit Fields */
screamer 0:c5e2f793b59a 5291 #define ENET_PAUR_TYPE_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5292 #define ENET_PAUR_TYPE_SHIFT 0
screamer 0:c5e2f793b59a 5293 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
screamer 0:c5e2f793b59a 5294 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 5295 #define ENET_PAUR_PADDR2_SHIFT 16
screamer 0:c5e2f793b59a 5296 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
screamer 0:c5e2f793b59a 5297 /* OPD Bit Fields */
screamer 0:c5e2f793b59a 5298 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5299 #define ENET_OPD_PAUSE_DUR_SHIFT 0
screamer 0:c5e2f793b59a 5300 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
screamer 0:c5e2f793b59a 5301 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 5302 #define ENET_OPD_OPCODE_SHIFT 16
screamer 0:c5e2f793b59a 5303 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
screamer 0:c5e2f793b59a 5304 /* IAUR Bit Fields */
screamer 0:c5e2f793b59a 5305 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5306 #define ENET_IAUR_IADDR1_SHIFT 0
screamer 0:c5e2f793b59a 5307 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
screamer 0:c5e2f793b59a 5308 /* IALR Bit Fields */
screamer 0:c5e2f793b59a 5309 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5310 #define ENET_IALR_IADDR2_SHIFT 0
screamer 0:c5e2f793b59a 5311 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
screamer 0:c5e2f793b59a 5312 /* GAUR Bit Fields */
screamer 0:c5e2f793b59a 5313 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5314 #define ENET_GAUR_GADDR1_SHIFT 0
screamer 0:c5e2f793b59a 5315 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
screamer 0:c5e2f793b59a 5316 /* GALR Bit Fields */
screamer 0:c5e2f793b59a 5317 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5318 #define ENET_GALR_GADDR2_SHIFT 0
screamer 0:c5e2f793b59a 5319 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
screamer 0:c5e2f793b59a 5320 /* TFWR Bit Fields */
screamer 0:c5e2f793b59a 5321 #define ENET_TFWR_TFWR_MASK 0x3Fu
screamer 0:c5e2f793b59a 5322 #define ENET_TFWR_TFWR_SHIFT 0
screamer 0:c5e2f793b59a 5323 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
screamer 0:c5e2f793b59a 5324 #define ENET_TFWR_STRFWD_MASK 0x100u
screamer 0:c5e2f793b59a 5325 #define ENET_TFWR_STRFWD_SHIFT 8
screamer 0:c5e2f793b59a 5326 /* RDSR Bit Fields */
screamer 0:c5e2f793b59a 5327 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
screamer 0:c5e2f793b59a 5328 #define ENET_RDSR_R_DES_START_SHIFT 3
screamer 0:c5e2f793b59a 5329 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
screamer 0:c5e2f793b59a 5330 /* TDSR Bit Fields */
screamer 0:c5e2f793b59a 5331 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
screamer 0:c5e2f793b59a 5332 #define ENET_TDSR_X_DES_START_SHIFT 3
screamer 0:c5e2f793b59a 5333 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
screamer 0:c5e2f793b59a 5334 /* MRBR Bit Fields */
screamer 0:c5e2f793b59a 5335 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
screamer 0:c5e2f793b59a 5336 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
screamer 0:c5e2f793b59a 5337 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
screamer 0:c5e2f793b59a 5338 /* RSFL Bit Fields */
screamer 0:c5e2f793b59a 5339 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
screamer 0:c5e2f793b59a 5340 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
screamer 0:c5e2f793b59a 5341 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
screamer 0:c5e2f793b59a 5342 /* RSEM Bit Fields */
screamer 0:c5e2f793b59a 5343 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
screamer 0:c5e2f793b59a 5344 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
screamer 0:c5e2f793b59a 5345 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
screamer 0:c5e2f793b59a 5346 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
screamer 0:c5e2f793b59a 5347 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
screamer 0:c5e2f793b59a 5348 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
screamer 0:c5e2f793b59a 5349 /* RAEM Bit Fields */
screamer 0:c5e2f793b59a 5350 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
screamer 0:c5e2f793b59a 5351 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
screamer 0:c5e2f793b59a 5352 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
screamer 0:c5e2f793b59a 5353 /* RAFL Bit Fields */
screamer 0:c5e2f793b59a 5354 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
screamer 0:c5e2f793b59a 5355 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
screamer 0:c5e2f793b59a 5356 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
screamer 0:c5e2f793b59a 5357 /* TSEM Bit Fields */
screamer 0:c5e2f793b59a 5358 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
screamer 0:c5e2f793b59a 5359 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
screamer 0:c5e2f793b59a 5360 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
screamer 0:c5e2f793b59a 5361 /* TAEM Bit Fields */
screamer 0:c5e2f793b59a 5362 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
screamer 0:c5e2f793b59a 5363 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
screamer 0:c5e2f793b59a 5364 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
screamer 0:c5e2f793b59a 5365 /* TAFL Bit Fields */
screamer 0:c5e2f793b59a 5366 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
screamer 0:c5e2f793b59a 5367 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
screamer 0:c5e2f793b59a 5368 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
screamer 0:c5e2f793b59a 5369 /* TIPG Bit Fields */
screamer 0:c5e2f793b59a 5370 #define ENET_TIPG_IPG_MASK 0x1Fu
screamer 0:c5e2f793b59a 5371 #define ENET_TIPG_IPG_SHIFT 0
screamer 0:c5e2f793b59a 5372 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
screamer 0:c5e2f793b59a 5373 /* FTRL Bit Fields */
screamer 0:c5e2f793b59a 5374 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
screamer 0:c5e2f793b59a 5375 #define ENET_FTRL_TRUNC_FL_SHIFT 0
screamer 0:c5e2f793b59a 5376 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
screamer 0:c5e2f793b59a 5377 /* TACC Bit Fields */
screamer 0:c5e2f793b59a 5378 #define ENET_TACC_SHIFT16_MASK 0x1u
screamer 0:c5e2f793b59a 5379 #define ENET_TACC_SHIFT16_SHIFT 0
screamer 0:c5e2f793b59a 5380 #define ENET_TACC_IPCHK_MASK 0x8u
screamer 0:c5e2f793b59a 5381 #define ENET_TACC_IPCHK_SHIFT 3
screamer 0:c5e2f793b59a 5382 #define ENET_TACC_PROCHK_MASK 0x10u
screamer 0:c5e2f793b59a 5383 #define ENET_TACC_PROCHK_SHIFT 4
screamer 0:c5e2f793b59a 5384 /* RACC Bit Fields */
screamer 0:c5e2f793b59a 5385 #define ENET_RACC_PADREM_MASK 0x1u
screamer 0:c5e2f793b59a 5386 #define ENET_RACC_PADREM_SHIFT 0
screamer 0:c5e2f793b59a 5387 #define ENET_RACC_IPDIS_MASK 0x2u
screamer 0:c5e2f793b59a 5388 #define ENET_RACC_IPDIS_SHIFT 1
screamer 0:c5e2f793b59a 5389 #define ENET_RACC_PRODIS_MASK 0x4u
screamer 0:c5e2f793b59a 5390 #define ENET_RACC_PRODIS_SHIFT 2
screamer 0:c5e2f793b59a 5391 #define ENET_RACC_LINEDIS_MASK 0x40u
screamer 0:c5e2f793b59a 5392 #define ENET_RACC_LINEDIS_SHIFT 6
screamer 0:c5e2f793b59a 5393 #define ENET_RACC_SHIFT16_MASK 0x80u
screamer 0:c5e2f793b59a 5394 #define ENET_RACC_SHIFT16_SHIFT 7
screamer 0:c5e2f793b59a 5395 /* RMON_T_PACKETS Bit Fields */
screamer 0:c5e2f793b59a 5396 #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5397 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5398 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5399 /* RMON_T_BC_PKT Bit Fields */
screamer 0:c5e2f793b59a 5400 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5401 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5402 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5403 /* RMON_T_MC_PKT Bit Fields */
screamer 0:c5e2f793b59a 5404 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5405 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5406 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5407 /* RMON_T_CRC_ALIGN Bit Fields */
screamer 0:c5e2f793b59a 5408 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5409 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5410 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5411 /* RMON_T_UNDERSIZE Bit Fields */
screamer 0:c5e2f793b59a 5412 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5413 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5414 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5415 /* RMON_T_OVERSIZE Bit Fields */
screamer 0:c5e2f793b59a 5416 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5417 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5418 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5419 /* RMON_T_FRAG Bit Fields */
screamer 0:c5e2f793b59a 5420 #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5421 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5422 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5423 /* RMON_T_JAB Bit Fields */
screamer 0:c5e2f793b59a 5424 #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5425 #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5426 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5427 /* RMON_T_COL Bit Fields */
screamer 0:c5e2f793b59a 5428 #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5429 #define ENET_RMON_T_COL_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5430 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5431 /* RMON_T_P64 Bit Fields */
screamer 0:c5e2f793b59a 5432 #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5433 #define ENET_RMON_T_P64_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5434 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5435 /* RMON_T_P65TO127 Bit Fields */
screamer 0:c5e2f793b59a 5436 #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5437 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5438 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5439 /* RMON_T_P128TO255 Bit Fields */
screamer 0:c5e2f793b59a 5440 #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5441 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5442 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5443 /* RMON_T_P256TO511 Bit Fields */
screamer 0:c5e2f793b59a 5444 #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5445 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5446 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5447 /* RMON_T_P512TO1023 Bit Fields */
screamer 0:c5e2f793b59a 5448 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5449 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5450 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5451 /* RMON_T_P1024TO2047 Bit Fields */
screamer 0:c5e2f793b59a 5452 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5453 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5454 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5455 /* RMON_T_P_GTE2048 Bit Fields */
screamer 0:c5e2f793b59a 5456 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5457 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
screamer 0:c5e2f793b59a 5458 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
screamer 0:c5e2f793b59a 5459 /* RMON_T_OCTETS Bit Fields */
screamer 0:c5e2f793b59a 5460 #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5461 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
screamer 0:c5e2f793b59a 5462 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
screamer 0:c5e2f793b59a 5463 /* IEEE_T_FRAME_OK Bit Fields */
screamer 0:c5e2f793b59a 5464 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5465 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5466 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
screamer 0:c5e2f793b59a 5467 /* IEEE_T_1COL Bit Fields */
screamer 0:c5e2f793b59a 5468 #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5469 #define ENET_IEEE_T_1COL_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5470 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
screamer 0:c5e2f793b59a 5471 /* IEEE_T_MCOL Bit Fields */
screamer 0:c5e2f793b59a 5472 #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5473 #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5474 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
screamer 0:c5e2f793b59a 5475 /* IEEE_T_DEF Bit Fields */
screamer 0:c5e2f793b59a 5476 #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5477 #define ENET_IEEE_T_DEF_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5478 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
screamer 0:c5e2f793b59a 5479 /* IEEE_T_LCOL Bit Fields */
screamer 0:c5e2f793b59a 5480 #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5481 #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5482 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
screamer 0:c5e2f793b59a 5483 /* IEEE_T_EXCOL Bit Fields */
screamer 0:c5e2f793b59a 5484 #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5485 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5486 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
screamer 0:c5e2f793b59a 5487 /* IEEE_T_MACERR Bit Fields */
screamer 0:c5e2f793b59a 5488 #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5489 #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5490 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
screamer 0:c5e2f793b59a 5491 /* IEEE_T_CSERR Bit Fields */
screamer 0:c5e2f793b59a 5492 #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5493 #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5494 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
screamer 0:c5e2f793b59a 5495 /* IEEE_T_FDXFC Bit Fields */
screamer 0:c5e2f793b59a 5496 #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5497 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5498 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
screamer 0:c5e2f793b59a 5499 /* IEEE_T_OCTETS_OK Bit Fields */
screamer 0:c5e2f793b59a 5500 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5501 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5502 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
screamer 0:c5e2f793b59a 5503 /* RMON_R_PACKETS Bit Fields */
screamer 0:c5e2f793b59a 5504 #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5505 #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5506 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
screamer 0:c5e2f793b59a 5507 /* RMON_R_BC_PKT Bit Fields */
screamer 0:c5e2f793b59a 5508 #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5509 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5510 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
screamer 0:c5e2f793b59a 5511 /* RMON_R_MC_PKT Bit Fields */
screamer 0:c5e2f793b59a 5512 #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5513 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5514 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
screamer 0:c5e2f793b59a 5515 /* RMON_R_CRC_ALIGN Bit Fields */
screamer 0:c5e2f793b59a 5516 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5517 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5518 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
screamer 0:c5e2f793b59a 5519 /* RMON_R_UNDERSIZE Bit Fields */
screamer 0:c5e2f793b59a 5520 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5521 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5522 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
screamer 0:c5e2f793b59a 5523 /* RMON_R_OVERSIZE Bit Fields */
screamer 0:c5e2f793b59a 5524 #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5525 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5526 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
screamer 0:c5e2f793b59a 5527 /* RMON_R_FRAG Bit Fields */
screamer 0:c5e2f793b59a 5528 #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5529 #define ENET_RMON_R_FRAG_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5530 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
screamer 0:c5e2f793b59a 5531 /* RMON_R_JAB Bit Fields */
screamer 0:c5e2f793b59a 5532 #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5533 #define ENET_RMON_R_JAB_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5534 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
screamer 0:c5e2f793b59a 5535 /* RMON_R_P64 Bit Fields */
screamer 0:c5e2f793b59a 5536 #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5537 #define ENET_RMON_R_P64_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5538 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
screamer 0:c5e2f793b59a 5539 /* RMON_R_P65TO127 Bit Fields */
screamer 0:c5e2f793b59a 5540 #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5541 #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5542 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
screamer 0:c5e2f793b59a 5543 /* RMON_R_P128TO255 Bit Fields */
screamer 0:c5e2f793b59a 5544 #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5545 #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5546 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
screamer 0:c5e2f793b59a 5547 /* RMON_R_P256TO511 Bit Fields */
screamer 0:c5e2f793b59a 5548 #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5549 #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5550 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
screamer 0:c5e2f793b59a 5551 /* RMON_R_P512TO1023 Bit Fields */
screamer 0:c5e2f793b59a 5552 #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5553 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5554 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
screamer 0:c5e2f793b59a 5555 /* RMON_R_P1024TO2047 Bit Fields */
screamer 0:c5e2f793b59a 5556 #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5557 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5558 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
screamer 0:c5e2f793b59a 5559 /* RMON_R_P_GTE2048 Bit Fields */
screamer 0:c5e2f793b59a 5560 #define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5561 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5562 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
screamer 0:c5e2f793b59a 5563 /* RMON_R_OCTETS Bit Fields */
screamer 0:c5e2f793b59a 5564 #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5565 #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5566 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
screamer 0:c5e2f793b59a 5567 /* IEEE_R_DROP Bit Fields */
screamer 0:c5e2f793b59a 5568 #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5569 #define ENET_IEEE_R_DROP_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5570 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
screamer 0:c5e2f793b59a 5571 /* IEEE_R_FRAME_OK Bit Fields */
screamer 0:c5e2f793b59a 5572 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5573 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5574 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
screamer 0:c5e2f793b59a 5575 /* IEEE_R_CRC Bit Fields */
screamer 0:c5e2f793b59a 5576 #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5577 #define ENET_IEEE_R_CRC_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5578 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
screamer 0:c5e2f793b59a 5579 /* IEEE_R_ALIGN Bit Fields */
screamer 0:c5e2f793b59a 5580 #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5581 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5582 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
screamer 0:c5e2f793b59a 5583 /* IEEE_R_MACERR Bit Fields */
screamer 0:c5e2f793b59a 5584 #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5585 #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5586 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
screamer 0:c5e2f793b59a 5587 /* IEEE_R_FDXFC Bit Fields */
screamer 0:c5e2f793b59a 5588 #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 5589 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5590 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
screamer 0:c5e2f793b59a 5591 /* IEEE_R_OCTETS_OK Bit Fields */
screamer 0:c5e2f793b59a 5592 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5593 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 5594 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
screamer 0:c5e2f793b59a 5595 /* ATCR Bit Fields */
screamer 0:c5e2f793b59a 5596 #define ENET_ATCR_EN_MASK 0x1u
screamer 0:c5e2f793b59a 5597 #define ENET_ATCR_EN_SHIFT 0
screamer 0:c5e2f793b59a 5598 #define ENET_ATCR_OFFEN_MASK 0x4u
screamer 0:c5e2f793b59a 5599 #define ENET_ATCR_OFFEN_SHIFT 2
screamer 0:c5e2f793b59a 5600 #define ENET_ATCR_OFFRST_MASK 0x8u
screamer 0:c5e2f793b59a 5601 #define ENET_ATCR_OFFRST_SHIFT 3
screamer 0:c5e2f793b59a 5602 #define ENET_ATCR_PEREN_MASK 0x10u
screamer 0:c5e2f793b59a 5603 #define ENET_ATCR_PEREN_SHIFT 4
screamer 0:c5e2f793b59a 5604 #define ENET_ATCR_PINPER_MASK 0x80u
screamer 0:c5e2f793b59a 5605 #define ENET_ATCR_PINPER_SHIFT 7
screamer 0:c5e2f793b59a 5606 #define ENET_ATCR_RESTART_MASK 0x200u
screamer 0:c5e2f793b59a 5607 #define ENET_ATCR_RESTART_SHIFT 9
screamer 0:c5e2f793b59a 5608 #define ENET_ATCR_CAPTURE_MASK 0x800u
screamer 0:c5e2f793b59a 5609 #define ENET_ATCR_CAPTURE_SHIFT 11
screamer 0:c5e2f793b59a 5610 #define ENET_ATCR_SLAVE_MASK 0x2000u
screamer 0:c5e2f793b59a 5611 #define ENET_ATCR_SLAVE_SHIFT 13
screamer 0:c5e2f793b59a 5612 /* ATVR Bit Fields */
screamer 0:c5e2f793b59a 5613 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5614 #define ENET_ATVR_ATIME_SHIFT 0
screamer 0:c5e2f793b59a 5615 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
screamer 0:c5e2f793b59a 5616 /* ATOFF Bit Fields */
screamer 0:c5e2f793b59a 5617 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5618 #define ENET_ATOFF_OFFSET_SHIFT 0
screamer 0:c5e2f793b59a 5619 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
screamer 0:c5e2f793b59a 5620 /* ATPER Bit Fields */
screamer 0:c5e2f793b59a 5621 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5622 #define ENET_ATPER_PERIOD_SHIFT 0
screamer 0:c5e2f793b59a 5623 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
screamer 0:c5e2f793b59a 5624 /* ATCOR Bit Fields */
screamer 0:c5e2f793b59a 5625 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
screamer 0:c5e2f793b59a 5626 #define ENET_ATCOR_COR_SHIFT 0
screamer 0:c5e2f793b59a 5627 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
screamer 0:c5e2f793b59a 5628 /* ATINC Bit Fields */
screamer 0:c5e2f793b59a 5629 #define ENET_ATINC_INC_MASK 0x7Fu
screamer 0:c5e2f793b59a 5630 #define ENET_ATINC_INC_SHIFT 0
screamer 0:c5e2f793b59a 5631 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
screamer 0:c5e2f793b59a 5632 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
screamer 0:c5e2f793b59a 5633 #define ENET_ATINC_INC_CORR_SHIFT 8
screamer 0:c5e2f793b59a 5634 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
screamer 0:c5e2f793b59a 5635 /* ATSTMP Bit Fields */
screamer 0:c5e2f793b59a 5636 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5637 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
screamer 0:c5e2f793b59a 5638 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
screamer 0:c5e2f793b59a 5639 /* TGSR Bit Fields */
screamer 0:c5e2f793b59a 5640 #define ENET_TGSR_TF0_MASK 0x1u
screamer 0:c5e2f793b59a 5641 #define ENET_TGSR_TF0_SHIFT 0
screamer 0:c5e2f793b59a 5642 #define ENET_TGSR_TF1_MASK 0x2u
screamer 0:c5e2f793b59a 5643 #define ENET_TGSR_TF1_SHIFT 1
screamer 0:c5e2f793b59a 5644 #define ENET_TGSR_TF2_MASK 0x4u
screamer 0:c5e2f793b59a 5645 #define ENET_TGSR_TF2_SHIFT 2
screamer 0:c5e2f793b59a 5646 #define ENET_TGSR_TF3_MASK 0x8u
screamer 0:c5e2f793b59a 5647 #define ENET_TGSR_TF3_SHIFT 3
screamer 0:c5e2f793b59a 5648 /* TCSR Bit Fields */
screamer 0:c5e2f793b59a 5649 #define ENET_TCSR_TDRE_MASK 0x1u
screamer 0:c5e2f793b59a 5650 #define ENET_TCSR_TDRE_SHIFT 0
screamer 0:c5e2f793b59a 5651 #define ENET_TCSR_TMODE_MASK 0x3Cu
screamer 0:c5e2f793b59a 5652 #define ENET_TCSR_TMODE_SHIFT 2
screamer 0:c5e2f793b59a 5653 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
screamer 0:c5e2f793b59a 5654 #define ENET_TCSR_TIE_MASK 0x40u
screamer 0:c5e2f793b59a 5655 #define ENET_TCSR_TIE_SHIFT 6
screamer 0:c5e2f793b59a 5656 #define ENET_TCSR_TF_MASK 0x80u
screamer 0:c5e2f793b59a 5657 #define ENET_TCSR_TF_SHIFT 7
screamer 0:c5e2f793b59a 5658 /* TCCR Bit Fields */
screamer 0:c5e2f793b59a 5659 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 5660 #define ENET_TCCR_TCC_SHIFT 0
screamer 0:c5e2f793b59a 5661 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
screamer 0:c5e2f793b59a 5662
screamer 0:c5e2f793b59a 5663 /*!
screamer 0:c5e2f793b59a 5664 * @}
screamer 0:c5e2f793b59a 5665 */ /* end of group ENET_Register_Masks */
screamer 0:c5e2f793b59a 5666
screamer 0:c5e2f793b59a 5667
screamer 0:c5e2f793b59a 5668 /* ENET - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 5669 /** Peripheral ENET base address */
screamer 0:c5e2f793b59a 5670 #define ENET_BASE (0x400C0000u)
screamer 0:c5e2f793b59a 5671 /** Peripheral ENET base pointer */
screamer 0:c5e2f793b59a 5672 #define ENET ((ENET_Type *)ENET_BASE)
screamer 0:c5e2f793b59a 5673 #define ENET_BASE_PTR (ENET)
screamer 0:c5e2f793b59a 5674 /** Array initializer of ENET peripheral base addresses */
screamer 0:c5e2f793b59a 5675 #define ENET_BASE_ADDRS { ENET_BASE }
screamer 0:c5e2f793b59a 5676 /** Array initializer of ENET peripheral base pointers */
screamer 0:c5e2f793b59a 5677 #define ENET_BASE_PTRS { ENET }
screamer 0:c5e2f793b59a 5678 /** Interrupt vectors for the ENET peripheral type */
screamer 0:c5e2f793b59a 5679 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
screamer 0:c5e2f793b59a 5680 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
screamer 0:c5e2f793b59a 5681 #define ENET_Error_IRQS { ENET_Error_IRQn }
screamer 0:c5e2f793b59a 5682 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
screamer 0:c5e2f793b59a 5683
screamer 0:c5e2f793b59a 5684 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5685 -- ENET - Register accessor macros
screamer 0:c5e2f793b59a 5686 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5687
screamer 0:c5e2f793b59a 5688 /*!
screamer 0:c5e2f793b59a 5689 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
screamer 0:c5e2f793b59a 5690 * @{
screamer 0:c5e2f793b59a 5691 */
screamer 0:c5e2f793b59a 5692
screamer 0:c5e2f793b59a 5693
screamer 0:c5e2f793b59a 5694 /* ENET - Register instance definitions */
screamer 0:c5e2f793b59a 5695 /* ENET */
screamer 0:c5e2f793b59a 5696 #define ENET_EIR ENET_EIR_REG(ENET)
screamer 0:c5e2f793b59a 5697 #define ENET_EIMR ENET_EIMR_REG(ENET)
screamer 0:c5e2f793b59a 5698 #define ENET_RDAR ENET_RDAR_REG(ENET)
screamer 0:c5e2f793b59a 5699 #define ENET_TDAR ENET_TDAR_REG(ENET)
screamer 0:c5e2f793b59a 5700 #define ENET_ECR ENET_ECR_REG(ENET)
screamer 0:c5e2f793b59a 5701 #define ENET_MMFR ENET_MMFR_REG(ENET)
screamer 0:c5e2f793b59a 5702 #define ENET_MSCR ENET_MSCR_REG(ENET)
screamer 0:c5e2f793b59a 5703 #define ENET_MIBC ENET_MIBC_REG(ENET)
screamer 0:c5e2f793b59a 5704 #define ENET_RCR ENET_RCR_REG(ENET)
screamer 0:c5e2f793b59a 5705 #define ENET_TCR ENET_TCR_REG(ENET)
screamer 0:c5e2f793b59a 5706 #define ENET_PALR ENET_PALR_REG(ENET)
screamer 0:c5e2f793b59a 5707 #define ENET_PAUR ENET_PAUR_REG(ENET)
screamer 0:c5e2f793b59a 5708 #define ENET_OPD ENET_OPD_REG(ENET)
screamer 0:c5e2f793b59a 5709 #define ENET_IAUR ENET_IAUR_REG(ENET)
screamer 0:c5e2f793b59a 5710 #define ENET_IALR ENET_IALR_REG(ENET)
screamer 0:c5e2f793b59a 5711 #define ENET_GAUR ENET_GAUR_REG(ENET)
screamer 0:c5e2f793b59a 5712 #define ENET_GALR ENET_GALR_REG(ENET)
screamer 0:c5e2f793b59a 5713 #define ENET_TFWR ENET_TFWR_REG(ENET)
screamer 0:c5e2f793b59a 5714 #define ENET_RDSR ENET_RDSR_REG(ENET)
screamer 0:c5e2f793b59a 5715 #define ENET_TDSR ENET_TDSR_REG(ENET)
screamer 0:c5e2f793b59a 5716 #define ENET_MRBR ENET_MRBR_REG(ENET)
screamer 0:c5e2f793b59a 5717 #define ENET_RSFL ENET_RSFL_REG(ENET)
screamer 0:c5e2f793b59a 5718 #define ENET_RSEM ENET_RSEM_REG(ENET)
screamer 0:c5e2f793b59a 5719 #define ENET_RAEM ENET_RAEM_REG(ENET)
screamer 0:c5e2f793b59a 5720 #define ENET_RAFL ENET_RAFL_REG(ENET)
screamer 0:c5e2f793b59a 5721 #define ENET_TSEM ENET_TSEM_REG(ENET)
screamer 0:c5e2f793b59a 5722 #define ENET_TAEM ENET_TAEM_REG(ENET)
screamer 0:c5e2f793b59a 5723 #define ENET_TAFL ENET_TAFL_REG(ENET)
screamer 0:c5e2f793b59a 5724 #define ENET_TIPG ENET_TIPG_REG(ENET)
screamer 0:c5e2f793b59a 5725 #define ENET_FTRL ENET_FTRL_REG(ENET)
screamer 0:c5e2f793b59a 5726 #define ENET_TACC ENET_TACC_REG(ENET)
screamer 0:c5e2f793b59a 5727 #define ENET_RACC ENET_RACC_REG(ENET)
screamer 0:c5e2f793b59a 5728 #define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
screamer 0:c5e2f793b59a 5729 #define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
screamer 0:c5e2f793b59a 5730 #define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
screamer 0:c5e2f793b59a 5731 #define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
screamer 0:c5e2f793b59a 5732 #define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
screamer 0:c5e2f793b59a 5733 #define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
screamer 0:c5e2f793b59a 5734 #define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
screamer 0:c5e2f793b59a 5735 #define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
screamer 0:c5e2f793b59a 5736 #define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
screamer 0:c5e2f793b59a 5737 #define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
screamer 0:c5e2f793b59a 5738 #define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
screamer 0:c5e2f793b59a 5739 #define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
screamer 0:c5e2f793b59a 5740 #define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
screamer 0:c5e2f793b59a 5741 #define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
screamer 0:c5e2f793b59a 5742 #define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
screamer 0:c5e2f793b59a 5743 #define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
screamer 0:c5e2f793b59a 5744 #define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
screamer 0:c5e2f793b59a 5745 #define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
screamer 0:c5e2f793b59a 5746 #define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
screamer 0:c5e2f793b59a 5747 #define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
screamer 0:c5e2f793b59a 5748 #define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
screamer 0:c5e2f793b59a 5749 #define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
screamer 0:c5e2f793b59a 5750 #define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
screamer 0:c5e2f793b59a 5751 #define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
screamer 0:c5e2f793b59a 5752 #define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
screamer 0:c5e2f793b59a 5753 #define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
screamer 0:c5e2f793b59a 5754 #define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
screamer 0:c5e2f793b59a 5755 #define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
screamer 0:c5e2f793b59a 5756 #define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
screamer 0:c5e2f793b59a 5757 #define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
screamer 0:c5e2f793b59a 5758 #define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
screamer 0:c5e2f793b59a 5759 #define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
screamer 0:c5e2f793b59a 5760 #define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
screamer 0:c5e2f793b59a 5761 #define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
screamer 0:c5e2f793b59a 5762 #define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
screamer 0:c5e2f793b59a 5763 #define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
screamer 0:c5e2f793b59a 5764 #define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
screamer 0:c5e2f793b59a 5765 #define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
screamer 0:c5e2f793b59a 5766 #define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
screamer 0:c5e2f793b59a 5767 #define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
screamer 0:c5e2f793b59a 5768 #define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
screamer 0:c5e2f793b59a 5769 #define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET)
screamer 0:c5e2f793b59a 5770 #define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
screamer 0:c5e2f793b59a 5771 #define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
screamer 0:c5e2f793b59a 5772 #define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
screamer 0:c5e2f793b59a 5773 #define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
screamer 0:c5e2f793b59a 5774 #define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
screamer 0:c5e2f793b59a 5775 #define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
screamer 0:c5e2f793b59a 5776 #define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
screamer 0:c5e2f793b59a 5777 #define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
screamer 0:c5e2f793b59a 5778 #define ENET_ATCR ENET_ATCR_REG(ENET)
screamer 0:c5e2f793b59a 5779 #define ENET_ATVR ENET_ATVR_REG(ENET)
screamer 0:c5e2f793b59a 5780 #define ENET_ATOFF ENET_ATOFF_REG(ENET)
screamer 0:c5e2f793b59a 5781 #define ENET_ATPER ENET_ATPER_REG(ENET)
screamer 0:c5e2f793b59a 5782 #define ENET_ATCOR ENET_ATCOR_REG(ENET)
screamer 0:c5e2f793b59a 5783 #define ENET_ATINC ENET_ATINC_REG(ENET)
screamer 0:c5e2f793b59a 5784 #define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
screamer 0:c5e2f793b59a 5785 #define ENET_TGSR ENET_TGSR_REG(ENET)
screamer 0:c5e2f793b59a 5786 #define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
screamer 0:c5e2f793b59a 5787 #define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
screamer 0:c5e2f793b59a 5788 #define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
screamer 0:c5e2f793b59a 5789 #define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
screamer 0:c5e2f793b59a 5790 #define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
screamer 0:c5e2f793b59a 5791 #define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
screamer 0:c5e2f793b59a 5792 #define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
screamer 0:c5e2f793b59a 5793 #define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
screamer 0:c5e2f793b59a 5794
screamer 0:c5e2f793b59a 5795 /* ENET - Register array accessors */
screamer 0:c5e2f793b59a 5796 #define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
screamer 0:c5e2f793b59a 5797 #define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
screamer 0:c5e2f793b59a 5798
screamer 0:c5e2f793b59a 5799 /*!
screamer 0:c5e2f793b59a 5800 * @}
screamer 0:c5e2f793b59a 5801 */ /* end of group ENET_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 5802
screamer 0:c5e2f793b59a 5803
screamer 0:c5e2f793b59a 5804 /*!
screamer 0:c5e2f793b59a 5805 * @}
screamer 0:c5e2f793b59a 5806 */ /* end of group ENET_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 5807
screamer 0:c5e2f793b59a 5808
screamer 0:c5e2f793b59a 5809 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5810 -- EWM Peripheral Access Layer
screamer 0:c5e2f793b59a 5811 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5812
screamer 0:c5e2f793b59a 5813 /*!
screamer 0:c5e2f793b59a 5814 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
screamer 0:c5e2f793b59a 5815 * @{
screamer 0:c5e2f793b59a 5816 */
screamer 0:c5e2f793b59a 5817
screamer 0:c5e2f793b59a 5818 /** EWM - Register Layout Typedef */
screamer 0:c5e2f793b59a 5819 typedef struct {
screamer 0:c5e2f793b59a 5820 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
screamer 0:c5e2f793b59a 5821 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
screamer 0:c5e2f793b59a 5822 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
screamer 0:c5e2f793b59a 5823 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
screamer 0:c5e2f793b59a 5824 } EWM_Type, *EWM_MemMapPtr;
screamer 0:c5e2f793b59a 5825
screamer 0:c5e2f793b59a 5826 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5827 -- EWM - Register accessor macros
screamer 0:c5e2f793b59a 5828 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5829
screamer 0:c5e2f793b59a 5830 /*!
screamer 0:c5e2f793b59a 5831 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
screamer 0:c5e2f793b59a 5832 * @{
screamer 0:c5e2f793b59a 5833 */
screamer 0:c5e2f793b59a 5834
screamer 0:c5e2f793b59a 5835
screamer 0:c5e2f793b59a 5836 /* EWM - Register accessors */
screamer 0:c5e2f793b59a 5837 #define EWM_CTRL_REG(base) ((base)->CTRL)
screamer 0:c5e2f793b59a 5838 #define EWM_SERV_REG(base) ((base)->SERV)
screamer 0:c5e2f793b59a 5839 #define EWM_CMPL_REG(base) ((base)->CMPL)
screamer 0:c5e2f793b59a 5840 #define EWM_CMPH_REG(base) ((base)->CMPH)
screamer 0:c5e2f793b59a 5841
screamer 0:c5e2f793b59a 5842 /*!
screamer 0:c5e2f793b59a 5843 * @}
screamer 0:c5e2f793b59a 5844 */ /* end of group EWM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 5845
screamer 0:c5e2f793b59a 5846
screamer 0:c5e2f793b59a 5847 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5848 -- EWM Register Masks
screamer 0:c5e2f793b59a 5849 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5850
screamer 0:c5e2f793b59a 5851 /*!
screamer 0:c5e2f793b59a 5852 * @addtogroup EWM_Register_Masks EWM Register Masks
screamer 0:c5e2f793b59a 5853 * @{
screamer 0:c5e2f793b59a 5854 */
screamer 0:c5e2f793b59a 5855
screamer 0:c5e2f793b59a 5856 /* CTRL Bit Fields */
screamer 0:c5e2f793b59a 5857 #define EWM_CTRL_EWMEN_MASK 0x1u
screamer 0:c5e2f793b59a 5858 #define EWM_CTRL_EWMEN_SHIFT 0
screamer 0:c5e2f793b59a 5859 #define EWM_CTRL_ASSIN_MASK 0x2u
screamer 0:c5e2f793b59a 5860 #define EWM_CTRL_ASSIN_SHIFT 1
screamer 0:c5e2f793b59a 5861 #define EWM_CTRL_INEN_MASK 0x4u
screamer 0:c5e2f793b59a 5862 #define EWM_CTRL_INEN_SHIFT 2
screamer 0:c5e2f793b59a 5863 #define EWM_CTRL_INTEN_MASK 0x8u
screamer 0:c5e2f793b59a 5864 #define EWM_CTRL_INTEN_SHIFT 3
screamer 0:c5e2f793b59a 5865 /* SERV Bit Fields */
screamer 0:c5e2f793b59a 5866 #define EWM_SERV_SERVICE_MASK 0xFFu
screamer 0:c5e2f793b59a 5867 #define EWM_SERV_SERVICE_SHIFT 0
screamer 0:c5e2f793b59a 5868 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
screamer 0:c5e2f793b59a 5869 /* CMPL Bit Fields */
screamer 0:c5e2f793b59a 5870 #define EWM_CMPL_COMPAREL_MASK 0xFFu
screamer 0:c5e2f793b59a 5871 #define EWM_CMPL_COMPAREL_SHIFT 0
screamer 0:c5e2f793b59a 5872 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
screamer 0:c5e2f793b59a 5873 /* CMPH Bit Fields */
screamer 0:c5e2f793b59a 5874 #define EWM_CMPH_COMPAREH_MASK 0xFFu
screamer 0:c5e2f793b59a 5875 #define EWM_CMPH_COMPAREH_SHIFT 0
screamer 0:c5e2f793b59a 5876 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
screamer 0:c5e2f793b59a 5877
screamer 0:c5e2f793b59a 5878 /*!
screamer 0:c5e2f793b59a 5879 * @}
screamer 0:c5e2f793b59a 5880 */ /* end of group EWM_Register_Masks */
screamer 0:c5e2f793b59a 5881
screamer 0:c5e2f793b59a 5882
screamer 0:c5e2f793b59a 5883 /* EWM - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 5884 /** Peripheral EWM base address */
screamer 0:c5e2f793b59a 5885 #define EWM_BASE (0x40061000u)
screamer 0:c5e2f793b59a 5886 /** Peripheral EWM base pointer */
screamer 0:c5e2f793b59a 5887 #define EWM ((EWM_Type *)EWM_BASE)
screamer 0:c5e2f793b59a 5888 #define EWM_BASE_PTR (EWM)
screamer 0:c5e2f793b59a 5889 /** Array initializer of EWM peripheral base addresses */
screamer 0:c5e2f793b59a 5890 #define EWM_BASE_ADDRS { EWM_BASE }
screamer 0:c5e2f793b59a 5891 /** Array initializer of EWM peripheral base pointers */
screamer 0:c5e2f793b59a 5892 #define EWM_BASE_PTRS { EWM }
screamer 0:c5e2f793b59a 5893 /** Interrupt vectors for the EWM peripheral type */
screamer 0:c5e2f793b59a 5894 #define EWM_IRQS { Watchdog_IRQn }
screamer 0:c5e2f793b59a 5895
screamer 0:c5e2f793b59a 5896 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5897 -- EWM - Register accessor macros
screamer 0:c5e2f793b59a 5898 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5899
screamer 0:c5e2f793b59a 5900 /*!
screamer 0:c5e2f793b59a 5901 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
screamer 0:c5e2f793b59a 5902 * @{
screamer 0:c5e2f793b59a 5903 */
screamer 0:c5e2f793b59a 5904
screamer 0:c5e2f793b59a 5905
screamer 0:c5e2f793b59a 5906 /* EWM - Register instance definitions */
screamer 0:c5e2f793b59a 5907 /* EWM */
screamer 0:c5e2f793b59a 5908 #define EWM_CTRL EWM_CTRL_REG(EWM)
screamer 0:c5e2f793b59a 5909 #define EWM_SERV EWM_SERV_REG(EWM)
screamer 0:c5e2f793b59a 5910 #define EWM_CMPL EWM_CMPL_REG(EWM)
screamer 0:c5e2f793b59a 5911 #define EWM_CMPH EWM_CMPH_REG(EWM)
screamer 0:c5e2f793b59a 5912
screamer 0:c5e2f793b59a 5913 /*!
screamer 0:c5e2f793b59a 5914 * @}
screamer 0:c5e2f793b59a 5915 */ /* end of group EWM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 5916
screamer 0:c5e2f793b59a 5917
screamer 0:c5e2f793b59a 5918 /*!
screamer 0:c5e2f793b59a 5919 * @}
screamer 0:c5e2f793b59a 5920 */ /* end of group EWM_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 5921
screamer 0:c5e2f793b59a 5922
screamer 0:c5e2f793b59a 5923 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5924 -- FB Peripheral Access Layer
screamer 0:c5e2f793b59a 5925 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5926
screamer 0:c5e2f793b59a 5927 /*!
screamer 0:c5e2f793b59a 5928 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
screamer 0:c5e2f793b59a 5929 * @{
screamer 0:c5e2f793b59a 5930 */
screamer 0:c5e2f793b59a 5931
screamer 0:c5e2f793b59a 5932 /** FB - Register Layout Typedef */
screamer 0:c5e2f793b59a 5933 typedef struct {
screamer 0:c5e2f793b59a 5934 struct { /* offset: 0x0, array step: 0xC */
screamer 0:c5e2f793b59a 5935 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
screamer 0:c5e2f793b59a 5936 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
screamer 0:c5e2f793b59a 5937 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
screamer 0:c5e2f793b59a 5938 } CS[6];
screamer 0:c5e2f793b59a 5939 uint8_t RESERVED_0[24];
screamer 0:c5e2f793b59a 5940 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
screamer 0:c5e2f793b59a 5941 } FB_Type, *FB_MemMapPtr;
screamer 0:c5e2f793b59a 5942
screamer 0:c5e2f793b59a 5943 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5944 -- FB - Register accessor macros
screamer 0:c5e2f793b59a 5945 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5946
screamer 0:c5e2f793b59a 5947 /*!
screamer 0:c5e2f793b59a 5948 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
screamer 0:c5e2f793b59a 5949 * @{
screamer 0:c5e2f793b59a 5950 */
screamer 0:c5e2f793b59a 5951
screamer 0:c5e2f793b59a 5952
screamer 0:c5e2f793b59a 5953 /* FB - Register accessors */
screamer 0:c5e2f793b59a 5954 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
screamer 0:c5e2f793b59a 5955 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
screamer 0:c5e2f793b59a 5956 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
screamer 0:c5e2f793b59a 5957 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
screamer 0:c5e2f793b59a 5958
screamer 0:c5e2f793b59a 5959 /*!
screamer 0:c5e2f793b59a 5960 * @}
screamer 0:c5e2f793b59a 5961 */ /* end of group FB_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 5962
screamer 0:c5e2f793b59a 5963
screamer 0:c5e2f793b59a 5964 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 5965 -- FB Register Masks
screamer 0:c5e2f793b59a 5966 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 5967
screamer 0:c5e2f793b59a 5968 /*!
screamer 0:c5e2f793b59a 5969 * @addtogroup FB_Register_Masks FB Register Masks
screamer 0:c5e2f793b59a 5970 * @{
screamer 0:c5e2f793b59a 5971 */
screamer 0:c5e2f793b59a 5972
screamer 0:c5e2f793b59a 5973 /* CSAR Bit Fields */
screamer 0:c5e2f793b59a 5974 #define FB_CSAR_BA_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 5975 #define FB_CSAR_BA_SHIFT 16
screamer 0:c5e2f793b59a 5976 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
screamer 0:c5e2f793b59a 5977 /* CSMR Bit Fields */
screamer 0:c5e2f793b59a 5978 #define FB_CSMR_V_MASK 0x1u
screamer 0:c5e2f793b59a 5979 #define FB_CSMR_V_SHIFT 0
screamer 0:c5e2f793b59a 5980 #define FB_CSMR_WP_MASK 0x100u
screamer 0:c5e2f793b59a 5981 #define FB_CSMR_WP_SHIFT 8
screamer 0:c5e2f793b59a 5982 #define FB_CSMR_BAM_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 5983 #define FB_CSMR_BAM_SHIFT 16
screamer 0:c5e2f793b59a 5984 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
screamer 0:c5e2f793b59a 5985 /* CSCR Bit Fields */
screamer 0:c5e2f793b59a 5986 #define FB_CSCR_BSTW_MASK 0x8u
screamer 0:c5e2f793b59a 5987 #define FB_CSCR_BSTW_SHIFT 3
screamer 0:c5e2f793b59a 5988 #define FB_CSCR_BSTR_MASK 0x10u
screamer 0:c5e2f793b59a 5989 #define FB_CSCR_BSTR_SHIFT 4
screamer 0:c5e2f793b59a 5990 #define FB_CSCR_BEM_MASK 0x20u
screamer 0:c5e2f793b59a 5991 #define FB_CSCR_BEM_SHIFT 5
screamer 0:c5e2f793b59a 5992 #define FB_CSCR_PS_MASK 0xC0u
screamer 0:c5e2f793b59a 5993 #define FB_CSCR_PS_SHIFT 6
screamer 0:c5e2f793b59a 5994 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
screamer 0:c5e2f793b59a 5995 #define FB_CSCR_AA_MASK 0x100u
screamer 0:c5e2f793b59a 5996 #define FB_CSCR_AA_SHIFT 8
screamer 0:c5e2f793b59a 5997 #define FB_CSCR_BLS_MASK 0x200u
screamer 0:c5e2f793b59a 5998 #define FB_CSCR_BLS_SHIFT 9
screamer 0:c5e2f793b59a 5999 #define FB_CSCR_WS_MASK 0xFC00u
screamer 0:c5e2f793b59a 6000 #define FB_CSCR_WS_SHIFT 10
screamer 0:c5e2f793b59a 6001 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
screamer 0:c5e2f793b59a 6002 #define FB_CSCR_WRAH_MASK 0x30000u
screamer 0:c5e2f793b59a 6003 #define FB_CSCR_WRAH_SHIFT 16
screamer 0:c5e2f793b59a 6004 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
screamer 0:c5e2f793b59a 6005 #define FB_CSCR_RDAH_MASK 0xC0000u
screamer 0:c5e2f793b59a 6006 #define FB_CSCR_RDAH_SHIFT 18
screamer 0:c5e2f793b59a 6007 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
screamer 0:c5e2f793b59a 6008 #define FB_CSCR_ASET_MASK 0x300000u
screamer 0:c5e2f793b59a 6009 #define FB_CSCR_ASET_SHIFT 20
screamer 0:c5e2f793b59a 6010 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
screamer 0:c5e2f793b59a 6011 #define FB_CSCR_EXTS_MASK 0x400000u
screamer 0:c5e2f793b59a 6012 #define FB_CSCR_EXTS_SHIFT 22
screamer 0:c5e2f793b59a 6013 #define FB_CSCR_SWSEN_MASK 0x800000u
screamer 0:c5e2f793b59a 6014 #define FB_CSCR_SWSEN_SHIFT 23
screamer 0:c5e2f793b59a 6015 #define FB_CSCR_SWS_MASK 0xFC000000u
screamer 0:c5e2f793b59a 6016 #define FB_CSCR_SWS_SHIFT 26
screamer 0:c5e2f793b59a 6017 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
screamer 0:c5e2f793b59a 6018 /* CSPMCR Bit Fields */
screamer 0:c5e2f793b59a 6019 #define FB_CSPMCR_GROUP5_MASK 0xF000u
screamer 0:c5e2f793b59a 6020 #define FB_CSPMCR_GROUP5_SHIFT 12
screamer 0:c5e2f793b59a 6021 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
screamer 0:c5e2f793b59a 6022 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
screamer 0:c5e2f793b59a 6023 #define FB_CSPMCR_GROUP4_SHIFT 16
screamer 0:c5e2f793b59a 6024 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
screamer 0:c5e2f793b59a 6025 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
screamer 0:c5e2f793b59a 6026 #define FB_CSPMCR_GROUP3_SHIFT 20
screamer 0:c5e2f793b59a 6027 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
screamer 0:c5e2f793b59a 6028 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
screamer 0:c5e2f793b59a 6029 #define FB_CSPMCR_GROUP2_SHIFT 24
screamer 0:c5e2f793b59a 6030 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
screamer 0:c5e2f793b59a 6031 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
screamer 0:c5e2f793b59a 6032 #define FB_CSPMCR_GROUP1_SHIFT 28
screamer 0:c5e2f793b59a 6033 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
screamer 0:c5e2f793b59a 6034
screamer 0:c5e2f793b59a 6035 /*!
screamer 0:c5e2f793b59a 6036 * @}
screamer 0:c5e2f793b59a 6037 */ /* end of group FB_Register_Masks */
screamer 0:c5e2f793b59a 6038
screamer 0:c5e2f793b59a 6039
screamer 0:c5e2f793b59a 6040 /* FB - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 6041 /** Peripheral FB base address */
screamer 0:c5e2f793b59a 6042 #define FB_BASE (0x4000C000u)
screamer 0:c5e2f793b59a 6043 /** Peripheral FB base pointer */
screamer 0:c5e2f793b59a 6044 #define FB ((FB_Type *)FB_BASE)
screamer 0:c5e2f793b59a 6045 #define FB_BASE_PTR (FB)
screamer 0:c5e2f793b59a 6046 /** Array initializer of FB peripheral base addresses */
screamer 0:c5e2f793b59a 6047 #define FB_BASE_ADDRS { FB_BASE }
screamer 0:c5e2f793b59a 6048 /** Array initializer of FB peripheral base pointers */
screamer 0:c5e2f793b59a 6049 #define FB_BASE_PTRS { FB }
screamer 0:c5e2f793b59a 6050
screamer 0:c5e2f793b59a 6051 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6052 -- FB - Register accessor macros
screamer 0:c5e2f793b59a 6053 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6054
screamer 0:c5e2f793b59a 6055 /*!
screamer 0:c5e2f793b59a 6056 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
screamer 0:c5e2f793b59a 6057 * @{
screamer 0:c5e2f793b59a 6058 */
screamer 0:c5e2f793b59a 6059
screamer 0:c5e2f793b59a 6060
screamer 0:c5e2f793b59a 6061 /* FB - Register instance definitions */
screamer 0:c5e2f793b59a 6062 /* FB */
screamer 0:c5e2f793b59a 6063 #define FB_CSAR0 FB_CSAR_REG(FB,0)
screamer 0:c5e2f793b59a 6064 #define FB_CSMR0 FB_CSMR_REG(FB,0)
screamer 0:c5e2f793b59a 6065 #define FB_CSCR0 FB_CSCR_REG(FB,0)
screamer 0:c5e2f793b59a 6066 #define FB_CSAR1 FB_CSAR_REG(FB,1)
screamer 0:c5e2f793b59a 6067 #define FB_CSMR1 FB_CSMR_REG(FB,1)
screamer 0:c5e2f793b59a 6068 #define FB_CSCR1 FB_CSCR_REG(FB,1)
screamer 0:c5e2f793b59a 6069 #define FB_CSAR2 FB_CSAR_REG(FB,2)
screamer 0:c5e2f793b59a 6070 #define FB_CSMR2 FB_CSMR_REG(FB,2)
screamer 0:c5e2f793b59a 6071 #define FB_CSCR2 FB_CSCR_REG(FB,2)
screamer 0:c5e2f793b59a 6072 #define FB_CSAR3 FB_CSAR_REG(FB,3)
screamer 0:c5e2f793b59a 6073 #define FB_CSMR3 FB_CSMR_REG(FB,3)
screamer 0:c5e2f793b59a 6074 #define FB_CSCR3 FB_CSCR_REG(FB,3)
screamer 0:c5e2f793b59a 6075 #define FB_CSAR4 FB_CSAR_REG(FB,4)
screamer 0:c5e2f793b59a 6076 #define FB_CSMR4 FB_CSMR_REG(FB,4)
screamer 0:c5e2f793b59a 6077 #define FB_CSCR4 FB_CSCR_REG(FB,4)
screamer 0:c5e2f793b59a 6078 #define FB_CSAR5 FB_CSAR_REG(FB,5)
screamer 0:c5e2f793b59a 6079 #define FB_CSMR5 FB_CSMR_REG(FB,5)
screamer 0:c5e2f793b59a 6080 #define FB_CSCR5 FB_CSCR_REG(FB,5)
screamer 0:c5e2f793b59a 6081 #define FB_CSPMCR FB_CSPMCR_REG(FB)
screamer 0:c5e2f793b59a 6082
screamer 0:c5e2f793b59a 6083 /* FB - Register array accessors */
screamer 0:c5e2f793b59a 6084 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
screamer 0:c5e2f793b59a 6085 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
screamer 0:c5e2f793b59a 6086 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
screamer 0:c5e2f793b59a 6087
screamer 0:c5e2f793b59a 6088 /*!
screamer 0:c5e2f793b59a 6089 * @}
screamer 0:c5e2f793b59a 6090 */ /* end of group FB_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 6091
screamer 0:c5e2f793b59a 6092
screamer 0:c5e2f793b59a 6093 /*!
screamer 0:c5e2f793b59a 6094 * @}
screamer 0:c5e2f793b59a 6095 */ /* end of group FB_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 6096
screamer 0:c5e2f793b59a 6097
screamer 0:c5e2f793b59a 6098 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6099 -- FMC Peripheral Access Layer
screamer 0:c5e2f793b59a 6100 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6101
screamer 0:c5e2f793b59a 6102 /*!
screamer 0:c5e2f793b59a 6103 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
screamer 0:c5e2f793b59a 6104 * @{
screamer 0:c5e2f793b59a 6105 */
screamer 0:c5e2f793b59a 6106
screamer 0:c5e2f793b59a 6107 /** FMC - Register Layout Typedef */
screamer 0:c5e2f793b59a 6108 typedef struct {
screamer 0:c5e2f793b59a 6109 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
screamer 0:c5e2f793b59a 6110 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
screamer 0:c5e2f793b59a 6111 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
screamer 0:c5e2f793b59a 6112 uint8_t RESERVED_0[244];
screamer 0:c5e2f793b59a 6113 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
screamer 0:c5e2f793b59a 6114 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
screamer 0:c5e2f793b59a 6115 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
screamer 0:c5e2f793b59a 6116 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
screamer 0:c5e2f793b59a 6117 uint8_t RESERVED_1[192];
screamer 0:c5e2f793b59a 6118 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
screamer 0:c5e2f793b59a 6119 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
screamer 0:c5e2f793b59a 6120 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
screamer 0:c5e2f793b59a 6121 } SET[4][4];
screamer 0:c5e2f793b59a 6122 } FMC_Type, *FMC_MemMapPtr;
screamer 0:c5e2f793b59a 6123
screamer 0:c5e2f793b59a 6124 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6125 -- FMC - Register accessor macros
screamer 0:c5e2f793b59a 6126 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6127
screamer 0:c5e2f793b59a 6128 /*!
screamer 0:c5e2f793b59a 6129 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
screamer 0:c5e2f793b59a 6130 * @{
screamer 0:c5e2f793b59a 6131 */
screamer 0:c5e2f793b59a 6132
screamer 0:c5e2f793b59a 6133
screamer 0:c5e2f793b59a 6134 /* FMC - Register accessors */
screamer 0:c5e2f793b59a 6135 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
screamer 0:c5e2f793b59a 6136 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
screamer 0:c5e2f793b59a 6137 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
screamer 0:c5e2f793b59a 6138 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
screamer 0:c5e2f793b59a 6139 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
screamer 0:c5e2f793b59a 6140 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
screamer 0:c5e2f793b59a 6141 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
screamer 0:c5e2f793b59a 6142 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
screamer 0:c5e2f793b59a 6143 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
screamer 0:c5e2f793b59a 6144
screamer 0:c5e2f793b59a 6145 /*!
screamer 0:c5e2f793b59a 6146 * @}
screamer 0:c5e2f793b59a 6147 */ /* end of group FMC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 6148
screamer 0:c5e2f793b59a 6149
screamer 0:c5e2f793b59a 6150 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6151 -- FMC Register Masks
screamer 0:c5e2f793b59a 6152 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6153
screamer 0:c5e2f793b59a 6154 /*!
screamer 0:c5e2f793b59a 6155 * @addtogroup FMC_Register_Masks FMC Register Masks
screamer 0:c5e2f793b59a 6156 * @{
screamer 0:c5e2f793b59a 6157 */
screamer 0:c5e2f793b59a 6158
screamer 0:c5e2f793b59a 6159 /* PFAPR Bit Fields */
screamer 0:c5e2f793b59a 6160 #define FMC_PFAPR_M0AP_MASK 0x3u
screamer 0:c5e2f793b59a 6161 #define FMC_PFAPR_M0AP_SHIFT 0
screamer 0:c5e2f793b59a 6162 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
screamer 0:c5e2f793b59a 6163 #define FMC_PFAPR_M1AP_MASK 0xCu
screamer 0:c5e2f793b59a 6164 #define FMC_PFAPR_M1AP_SHIFT 2
screamer 0:c5e2f793b59a 6165 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
screamer 0:c5e2f793b59a 6166 #define FMC_PFAPR_M2AP_MASK 0x30u
screamer 0:c5e2f793b59a 6167 #define FMC_PFAPR_M2AP_SHIFT 4
screamer 0:c5e2f793b59a 6168 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
screamer 0:c5e2f793b59a 6169 #define FMC_PFAPR_M3AP_MASK 0xC0u
screamer 0:c5e2f793b59a 6170 #define FMC_PFAPR_M3AP_SHIFT 6
screamer 0:c5e2f793b59a 6171 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
screamer 0:c5e2f793b59a 6172 #define FMC_PFAPR_M4AP_MASK 0x300u
screamer 0:c5e2f793b59a 6173 #define FMC_PFAPR_M4AP_SHIFT 8
screamer 0:c5e2f793b59a 6174 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
screamer 0:c5e2f793b59a 6175 #define FMC_PFAPR_M5AP_MASK 0xC00u
screamer 0:c5e2f793b59a 6176 #define FMC_PFAPR_M5AP_SHIFT 10
screamer 0:c5e2f793b59a 6177 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
screamer 0:c5e2f793b59a 6178 #define FMC_PFAPR_M6AP_MASK 0x3000u
screamer 0:c5e2f793b59a 6179 #define FMC_PFAPR_M6AP_SHIFT 12
screamer 0:c5e2f793b59a 6180 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
screamer 0:c5e2f793b59a 6181 #define FMC_PFAPR_M7AP_MASK 0xC000u
screamer 0:c5e2f793b59a 6182 #define FMC_PFAPR_M7AP_SHIFT 14
screamer 0:c5e2f793b59a 6183 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
screamer 0:c5e2f793b59a 6184 #define FMC_PFAPR_M0PFD_MASK 0x10000u
screamer 0:c5e2f793b59a 6185 #define FMC_PFAPR_M0PFD_SHIFT 16
screamer 0:c5e2f793b59a 6186 #define FMC_PFAPR_M1PFD_MASK 0x20000u
screamer 0:c5e2f793b59a 6187 #define FMC_PFAPR_M1PFD_SHIFT 17
screamer 0:c5e2f793b59a 6188 #define FMC_PFAPR_M2PFD_MASK 0x40000u
screamer 0:c5e2f793b59a 6189 #define FMC_PFAPR_M2PFD_SHIFT 18
screamer 0:c5e2f793b59a 6190 #define FMC_PFAPR_M3PFD_MASK 0x80000u
screamer 0:c5e2f793b59a 6191 #define FMC_PFAPR_M3PFD_SHIFT 19
screamer 0:c5e2f793b59a 6192 #define FMC_PFAPR_M4PFD_MASK 0x100000u
screamer 0:c5e2f793b59a 6193 #define FMC_PFAPR_M4PFD_SHIFT 20
screamer 0:c5e2f793b59a 6194 #define FMC_PFAPR_M5PFD_MASK 0x200000u
screamer 0:c5e2f793b59a 6195 #define FMC_PFAPR_M5PFD_SHIFT 21
screamer 0:c5e2f793b59a 6196 #define FMC_PFAPR_M6PFD_MASK 0x400000u
screamer 0:c5e2f793b59a 6197 #define FMC_PFAPR_M6PFD_SHIFT 22
screamer 0:c5e2f793b59a 6198 #define FMC_PFAPR_M7PFD_MASK 0x800000u
screamer 0:c5e2f793b59a 6199 #define FMC_PFAPR_M7PFD_SHIFT 23
screamer 0:c5e2f793b59a 6200 /* PFB0CR Bit Fields */
screamer 0:c5e2f793b59a 6201 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
screamer 0:c5e2f793b59a 6202 #define FMC_PFB0CR_B0SEBE_SHIFT 0
screamer 0:c5e2f793b59a 6203 #define FMC_PFB0CR_B0IPE_MASK 0x2u
screamer 0:c5e2f793b59a 6204 #define FMC_PFB0CR_B0IPE_SHIFT 1
screamer 0:c5e2f793b59a 6205 #define FMC_PFB0CR_B0DPE_MASK 0x4u
screamer 0:c5e2f793b59a 6206 #define FMC_PFB0CR_B0DPE_SHIFT 2
screamer 0:c5e2f793b59a 6207 #define FMC_PFB0CR_B0ICE_MASK 0x8u
screamer 0:c5e2f793b59a 6208 #define FMC_PFB0CR_B0ICE_SHIFT 3
screamer 0:c5e2f793b59a 6209 #define FMC_PFB0CR_B0DCE_MASK 0x10u
screamer 0:c5e2f793b59a 6210 #define FMC_PFB0CR_B0DCE_SHIFT 4
screamer 0:c5e2f793b59a 6211 #define FMC_PFB0CR_CRC_MASK 0xE0u
screamer 0:c5e2f793b59a 6212 #define FMC_PFB0CR_CRC_SHIFT 5
screamer 0:c5e2f793b59a 6213 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
screamer 0:c5e2f793b59a 6214 #define FMC_PFB0CR_B0MW_MASK 0x60000u
screamer 0:c5e2f793b59a 6215 #define FMC_PFB0CR_B0MW_SHIFT 17
screamer 0:c5e2f793b59a 6216 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
screamer 0:c5e2f793b59a 6217 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
screamer 0:c5e2f793b59a 6218 #define FMC_PFB0CR_S_B_INV_SHIFT 19
screamer 0:c5e2f793b59a 6219 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
screamer 0:c5e2f793b59a 6220 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
screamer 0:c5e2f793b59a 6221 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
screamer 0:c5e2f793b59a 6222 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
screamer 0:c5e2f793b59a 6223 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
screamer 0:c5e2f793b59a 6224 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
screamer 0:c5e2f793b59a 6225 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
screamer 0:c5e2f793b59a 6226 #define FMC_PFB0CR_B0RWSC_SHIFT 28
screamer 0:c5e2f793b59a 6227 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
screamer 0:c5e2f793b59a 6228 /* PFB1CR Bit Fields */
screamer 0:c5e2f793b59a 6229 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
screamer 0:c5e2f793b59a 6230 #define FMC_PFB1CR_B1SEBE_SHIFT 0
screamer 0:c5e2f793b59a 6231 #define FMC_PFB1CR_B1IPE_MASK 0x2u
screamer 0:c5e2f793b59a 6232 #define FMC_PFB1CR_B1IPE_SHIFT 1
screamer 0:c5e2f793b59a 6233 #define FMC_PFB1CR_B1DPE_MASK 0x4u
screamer 0:c5e2f793b59a 6234 #define FMC_PFB1CR_B1DPE_SHIFT 2
screamer 0:c5e2f793b59a 6235 #define FMC_PFB1CR_B1ICE_MASK 0x8u
screamer 0:c5e2f793b59a 6236 #define FMC_PFB1CR_B1ICE_SHIFT 3
screamer 0:c5e2f793b59a 6237 #define FMC_PFB1CR_B1DCE_MASK 0x10u
screamer 0:c5e2f793b59a 6238 #define FMC_PFB1CR_B1DCE_SHIFT 4
screamer 0:c5e2f793b59a 6239 #define FMC_PFB1CR_B1MW_MASK 0x60000u
screamer 0:c5e2f793b59a 6240 #define FMC_PFB1CR_B1MW_SHIFT 17
screamer 0:c5e2f793b59a 6241 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
screamer 0:c5e2f793b59a 6242 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
screamer 0:c5e2f793b59a 6243 #define FMC_PFB1CR_B1RWSC_SHIFT 28
screamer 0:c5e2f793b59a 6244 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
screamer 0:c5e2f793b59a 6245 /* TAGVDW0S Bit Fields */
screamer 0:c5e2f793b59a 6246 #define FMC_TAGVDW0S_valid_MASK 0x1u
screamer 0:c5e2f793b59a 6247 #define FMC_TAGVDW0S_valid_SHIFT 0
screamer 0:c5e2f793b59a 6248 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
screamer 0:c5e2f793b59a 6249 #define FMC_TAGVDW0S_tag_SHIFT 5
screamer 0:c5e2f793b59a 6250 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
screamer 0:c5e2f793b59a 6251 /* TAGVDW1S Bit Fields */
screamer 0:c5e2f793b59a 6252 #define FMC_TAGVDW1S_valid_MASK 0x1u
screamer 0:c5e2f793b59a 6253 #define FMC_TAGVDW1S_valid_SHIFT 0
screamer 0:c5e2f793b59a 6254 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
screamer 0:c5e2f793b59a 6255 #define FMC_TAGVDW1S_tag_SHIFT 5
screamer 0:c5e2f793b59a 6256 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
screamer 0:c5e2f793b59a 6257 /* TAGVDW2S Bit Fields */
screamer 0:c5e2f793b59a 6258 #define FMC_TAGVDW2S_valid_MASK 0x1u
screamer 0:c5e2f793b59a 6259 #define FMC_TAGVDW2S_valid_SHIFT 0
screamer 0:c5e2f793b59a 6260 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
screamer 0:c5e2f793b59a 6261 #define FMC_TAGVDW2S_tag_SHIFT 5
screamer 0:c5e2f793b59a 6262 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
screamer 0:c5e2f793b59a 6263 /* TAGVDW3S Bit Fields */
screamer 0:c5e2f793b59a 6264 #define FMC_TAGVDW3S_valid_MASK 0x1u
screamer 0:c5e2f793b59a 6265 #define FMC_TAGVDW3S_valid_SHIFT 0
screamer 0:c5e2f793b59a 6266 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
screamer 0:c5e2f793b59a 6267 #define FMC_TAGVDW3S_tag_SHIFT 5
screamer 0:c5e2f793b59a 6268 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
screamer 0:c5e2f793b59a 6269 /* DATA_U Bit Fields */
screamer 0:c5e2f793b59a 6270 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 6271 #define FMC_DATA_U_data_SHIFT 0
screamer 0:c5e2f793b59a 6272 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
screamer 0:c5e2f793b59a 6273 /* DATA_L Bit Fields */
screamer 0:c5e2f793b59a 6274 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 6275 #define FMC_DATA_L_data_SHIFT 0
screamer 0:c5e2f793b59a 6276 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
screamer 0:c5e2f793b59a 6277
screamer 0:c5e2f793b59a 6278 /*!
screamer 0:c5e2f793b59a 6279 * @}
screamer 0:c5e2f793b59a 6280 */ /* end of group FMC_Register_Masks */
screamer 0:c5e2f793b59a 6281
screamer 0:c5e2f793b59a 6282
screamer 0:c5e2f793b59a 6283 /* FMC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 6284 /** Peripheral FMC base address */
screamer 0:c5e2f793b59a 6285 #define FMC_BASE (0x4001F000u)
screamer 0:c5e2f793b59a 6286 /** Peripheral FMC base pointer */
screamer 0:c5e2f793b59a 6287 #define FMC ((FMC_Type *)FMC_BASE)
screamer 0:c5e2f793b59a 6288 #define FMC_BASE_PTR (FMC)
screamer 0:c5e2f793b59a 6289 /** Array initializer of FMC peripheral base addresses */
screamer 0:c5e2f793b59a 6290 #define FMC_BASE_ADDRS { FMC_BASE }
screamer 0:c5e2f793b59a 6291 /** Array initializer of FMC peripheral base pointers */
screamer 0:c5e2f793b59a 6292 #define FMC_BASE_PTRS { FMC }
screamer 0:c5e2f793b59a 6293
screamer 0:c5e2f793b59a 6294 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6295 -- FMC - Register accessor macros
screamer 0:c5e2f793b59a 6296 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6297
screamer 0:c5e2f793b59a 6298 /*!
screamer 0:c5e2f793b59a 6299 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
screamer 0:c5e2f793b59a 6300 * @{
screamer 0:c5e2f793b59a 6301 */
screamer 0:c5e2f793b59a 6302
screamer 0:c5e2f793b59a 6303
screamer 0:c5e2f793b59a 6304 /* FMC - Register instance definitions */
screamer 0:c5e2f793b59a 6305 /* FMC */
screamer 0:c5e2f793b59a 6306 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
screamer 0:c5e2f793b59a 6307 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
screamer 0:c5e2f793b59a 6308 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
screamer 0:c5e2f793b59a 6309 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
screamer 0:c5e2f793b59a 6310 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
screamer 0:c5e2f793b59a 6311 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
screamer 0:c5e2f793b59a 6312 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
screamer 0:c5e2f793b59a 6313 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
screamer 0:c5e2f793b59a 6314 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
screamer 0:c5e2f793b59a 6315 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
screamer 0:c5e2f793b59a 6316 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
screamer 0:c5e2f793b59a 6317 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
screamer 0:c5e2f793b59a 6318 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
screamer 0:c5e2f793b59a 6319 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
screamer 0:c5e2f793b59a 6320 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
screamer 0:c5e2f793b59a 6321 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
screamer 0:c5e2f793b59a 6322 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
screamer 0:c5e2f793b59a 6323 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
screamer 0:c5e2f793b59a 6324 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
screamer 0:c5e2f793b59a 6325 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
screamer 0:c5e2f793b59a 6326 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
screamer 0:c5e2f793b59a 6327 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
screamer 0:c5e2f793b59a 6328 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
screamer 0:c5e2f793b59a 6329 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
screamer 0:c5e2f793b59a 6330 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
screamer 0:c5e2f793b59a 6331 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
screamer 0:c5e2f793b59a 6332 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
screamer 0:c5e2f793b59a 6333 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
screamer 0:c5e2f793b59a 6334 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
screamer 0:c5e2f793b59a 6335 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
screamer 0:c5e2f793b59a 6336 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
screamer 0:c5e2f793b59a 6337 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
screamer 0:c5e2f793b59a 6338 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
screamer 0:c5e2f793b59a 6339 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
screamer 0:c5e2f793b59a 6340 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
screamer 0:c5e2f793b59a 6341 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
screamer 0:c5e2f793b59a 6342 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
screamer 0:c5e2f793b59a 6343 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
screamer 0:c5e2f793b59a 6344 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
screamer 0:c5e2f793b59a 6345 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
screamer 0:c5e2f793b59a 6346 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
screamer 0:c5e2f793b59a 6347 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
screamer 0:c5e2f793b59a 6348 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
screamer 0:c5e2f793b59a 6349 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
screamer 0:c5e2f793b59a 6350 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
screamer 0:c5e2f793b59a 6351 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
screamer 0:c5e2f793b59a 6352 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
screamer 0:c5e2f793b59a 6353 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
screamer 0:c5e2f793b59a 6354 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
screamer 0:c5e2f793b59a 6355 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
screamer 0:c5e2f793b59a 6356 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
screamer 0:c5e2f793b59a 6357
screamer 0:c5e2f793b59a 6358 /* FMC - Register array accessors */
screamer 0:c5e2f793b59a 6359 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
screamer 0:c5e2f793b59a 6360 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
screamer 0:c5e2f793b59a 6361 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
screamer 0:c5e2f793b59a 6362 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
screamer 0:c5e2f793b59a 6363 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
screamer 0:c5e2f793b59a 6364 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
screamer 0:c5e2f793b59a 6365
screamer 0:c5e2f793b59a 6366 /*!
screamer 0:c5e2f793b59a 6367 * @}
screamer 0:c5e2f793b59a 6368 */ /* end of group FMC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 6369
screamer 0:c5e2f793b59a 6370
screamer 0:c5e2f793b59a 6371 /*!
screamer 0:c5e2f793b59a 6372 * @}
screamer 0:c5e2f793b59a 6373 */ /* end of group FMC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 6374
screamer 0:c5e2f793b59a 6375
screamer 0:c5e2f793b59a 6376 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6377 -- FTFE Peripheral Access Layer
screamer 0:c5e2f793b59a 6378 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6379
screamer 0:c5e2f793b59a 6380 /*!
screamer 0:c5e2f793b59a 6381 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
screamer 0:c5e2f793b59a 6382 * @{
screamer 0:c5e2f793b59a 6383 */
screamer 0:c5e2f793b59a 6384
screamer 0:c5e2f793b59a 6385 /** FTFE - Register Layout Typedef */
screamer 0:c5e2f793b59a 6386 typedef struct {
screamer 0:c5e2f793b59a 6387 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
screamer 0:c5e2f793b59a 6388 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
screamer 0:c5e2f793b59a 6389 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
screamer 0:c5e2f793b59a 6390 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
screamer 0:c5e2f793b59a 6391 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
screamer 0:c5e2f793b59a 6392 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
screamer 0:c5e2f793b59a 6393 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
screamer 0:c5e2f793b59a 6394 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
screamer 0:c5e2f793b59a 6395 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
screamer 0:c5e2f793b59a 6396 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
screamer 0:c5e2f793b59a 6397 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
screamer 0:c5e2f793b59a 6398 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
screamer 0:c5e2f793b59a 6399 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
screamer 0:c5e2f793b59a 6400 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
screamer 0:c5e2f793b59a 6401 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
screamer 0:c5e2f793b59a 6402 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
screamer 0:c5e2f793b59a 6403 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
screamer 0:c5e2f793b59a 6404 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
screamer 0:c5e2f793b59a 6405 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
screamer 0:c5e2f793b59a 6406 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
screamer 0:c5e2f793b59a 6407 uint8_t RESERVED_0[2];
screamer 0:c5e2f793b59a 6408 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
screamer 0:c5e2f793b59a 6409 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
screamer 0:c5e2f793b59a 6410 } FTFE_Type, *FTFE_MemMapPtr;
screamer 0:c5e2f793b59a 6411
screamer 0:c5e2f793b59a 6412 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6413 -- FTFE - Register accessor macros
screamer 0:c5e2f793b59a 6414 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6415
screamer 0:c5e2f793b59a 6416 /*!
screamer 0:c5e2f793b59a 6417 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
screamer 0:c5e2f793b59a 6418 * @{
screamer 0:c5e2f793b59a 6419 */
screamer 0:c5e2f793b59a 6420
screamer 0:c5e2f793b59a 6421
screamer 0:c5e2f793b59a 6422 /* FTFE - Register accessors */
screamer 0:c5e2f793b59a 6423 #define FTFE_FSTAT_REG(base) ((base)->FSTAT)
screamer 0:c5e2f793b59a 6424 #define FTFE_FCNFG_REG(base) ((base)->FCNFG)
screamer 0:c5e2f793b59a 6425 #define FTFE_FSEC_REG(base) ((base)->FSEC)
screamer 0:c5e2f793b59a 6426 #define FTFE_FOPT_REG(base) ((base)->FOPT)
screamer 0:c5e2f793b59a 6427 #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
screamer 0:c5e2f793b59a 6428 #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
screamer 0:c5e2f793b59a 6429 #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
screamer 0:c5e2f793b59a 6430 #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
screamer 0:c5e2f793b59a 6431 #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
screamer 0:c5e2f793b59a 6432 #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
screamer 0:c5e2f793b59a 6433 #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
screamer 0:c5e2f793b59a 6434 #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
screamer 0:c5e2f793b59a 6435 #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
screamer 0:c5e2f793b59a 6436 #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
screamer 0:c5e2f793b59a 6437 #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
screamer 0:c5e2f793b59a 6438 #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
screamer 0:c5e2f793b59a 6439 #define FTFE_FPROT3_REG(base) ((base)->FPROT3)
screamer 0:c5e2f793b59a 6440 #define FTFE_FPROT2_REG(base) ((base)->FPROT2)
screamer 0:c5e2f793b59a 6441 #define FTFE_FPROT1_REG(base) ((base)->FPROT1)
screamer 0:c5e2f793b59a 6442 #define FTFE_FPROT0_REG(base) ((base)->FPROT0)
screamer 0:c5e2f793b59a 6443 #define FTFE_FEPROT_REG(base) ((base)->FEPROT)
screamer 0:c5e2f793b59a 6444 #define FTFE_FDPROT_REG(base) ((base)->FDPROT)
screamer 0:c5e2f793b59a 6445
screamer 0:c5e2f793b59a 6446 /*!
screamer 0:c5e2f793b59a 6447 * @}
screamer 0:c5e2f793b59a 6448 */ /* end of group FTFE_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 6449
screamer 0:c5e2f793b59a 6450
screamer 0:c5e2f793b59a 6451 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6452 -- FTFE Register Masks
screamer 0:c5e2f793b59a 6453 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6454
screamer 0:c5e2f793b59a 6455 /*!
screamer 0:c5e2f793b59a 6456 * @addtogroup FTFE_Register_Masks FTFE Register Masks
screamer 0:c5e2f793b59a 6457 * @{
screamer 0:c5e2f793b59a 6458 */
screamer 0:c5e2f793b59a 6459
screamer 0:c5e2f793b59a 6460 /* FSTAT Bit Fields */
screamer 0:c5e2f793b59a 6461 #define FTFE_FSTAT_MGSTAT0_MASK 0x1u
screamer 0:c5e2f793b59a 6462 #define FTFE_FSTAT_MGSTAT0_SHIFT 0
screamer 0:c5e2f793b59a 6463 #define FTFE_FSTAT_FPVIOL_MASK 0x10u
screamer 0:c5e2f793b59a 6464 #define FTFE_FSTAT_FPVIOL_SHIFT 4
screamer 0:c5e2f793b59a 6465 #define FTFE_FSTAT_ACCERR_MASK 0x20u
screamer 0:c5e2f793b59a 6466 #define FTFE_FSTAT_ACCERR_SHIFT 5
screamer 0:c5e2f793b59a 6467 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u
screamer 0:c5e2f793b59a 6468 #define FTFE_FSTAT_RDCOLERR_SHIFT 6
screamer 0:c5e2f793b59a 6469 #define FTFE_FSTAT_CCIF_MASK 0x80u
screamer 0:c5e2f793b59a 6470 #define FTFE_FSTAT_CCIF_SHIFT 7
screamer 0:c5e2f793b59a 6471 /* FCNFG Bit Fields */
screamer 0:c5e2f793b59a 6472 #define FTFE_FCNFG_EEERDY_MASK 0x1u
screamer 0:c5e2f793b59a 6473 #define FTFE_FCNFG_EEERDY_SHIFT 0
screamer 0:c5e2f793b59a 6474 #define FTFE_FCNFG_RAMRDY_MASK 0x2u
screamer 0:c5e2f793b59a 6475 #define FTFE_FCNFG_RAMRDY_SHIFT 1
screamer 0:c5e2f793b59a 6476 #define FTFE_FCNFG_PFLSH_MASK 0x4u
screamer 0:c5e2f793b59a 6477 #define FTFE_FCNFG_PFLSH_SHIFT 2
screamer 0:c5e2f793b59a 6478 #define FTFE_FCNFG_SWAP_MASK 0x8u
screamer 0:c5e2f793b59a 6479 #define FTFE_FCNFG_SWAP_SHIFT 3
screamer 0:c5e2f793b59a 6480 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u
screamer 0:c5e2f793b59a 6481 #define FTFE_FCNFG_ERSSUSP_SHIFT 4
screamer 0:c5e2f793b59a 6482 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u
screamer 0:c5e2f793b59a 6483 #define FTFE_FCNFG_ERSAREQ_SHIFT 5
screamer 0:c5e2f793b59a 6484 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
screamer 0:c5e2f793b59a 6485 #define FTFE_FCNFG_RDCOLLIE_SHIFT 6
screamer 0:c5e2f793b59a 6486 #define FTFE_FCNFG_CCIE_MASK 0x80u
screamer 0:c5e2f793b59a 6487 #define FTFE_FCNFG_CCIE_SHIFT 7
screamer 0:c5e2f793b59a 6488 /* FSEC Bit Fields */
screamer 0:c5e2f793b59a 6489 #define FTFE_FSEC_SEC_MASK 0x3u
screamer 0:c5e2f793b59a 6490 #define FTFE_FSEC_SEC_SHIFT 0
screamer 0:c5e2f793b59a 6491 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
screamer 0:c5e2f793b59a 6492 #define FTFE_FSEC_FSLACC_MASK 0xCu
screamer 0:c5e2f793b59a 6493 #define FTFE_FSEC_FSLACC_SHIFT 2
screamer 0:c5e2f793b59a 6494 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
screamer 0:c5e2f793b59a 6495 #define FTFE_FSEC_MEEN_MASK 0x30u
screamer 0:c5e2f793b59a 6496 #define FTFE_FSEC_MEEN_SHIFT 4
screamer 0:c5e2f793b59a 6497 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
screamer 0:c5e2f793b59a 6498 #define FTFE_FSEC_KEYEN_MASK 0xC0u
screamer 0:c5e2f793b59a 6499 #define FTFE_FSEC_KEYEN_SHIFT 6
screamer 0:c5e2f793b59a 6500 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
screamer 0:c5e2f793b59a 6501 /* FOPT Bit Fields */
screamer 0:c5e2f793b59a 6502 #define FTFE_FOPT_OPT_MASK 0xFFu
screamer 0:c5e2f793b59a 6503 #define FTFE_FOPT_OPT_SHIFT 0
screamer 0:c5e2f793b59a 6504 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
screamer 0:c5e2f793b59a 6505 /* FCCOB3 Bit Fields */
screamer 0:c5e2f793b59a 6506 #define FTFE_FCCOB3_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6507 #define FTFE_FCCOB3_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6508 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
screamer 0:c5e2f793b59a 6509 /* FCCOB2 Bit Fields */
screamer 0:c5e2f793b59a 6510 #define FTFE_FCCOB2_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6511 #define FTFE_FCCOB2_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6512 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
screamer 0:c5e2f793b59a 6513 /* FCCOB1 Bit Fields */
screamer 0:c5e2f793b59a 6514 #define FTFE_FCCOB1_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6515 #define FTFE_FCCOB1_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6516 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
screamer 0:c5e2f793b59a 6517 /* FCCOB0 Bit Fields */
screamer 0:c5e2f793b59a 6518 #define FTFE_FCCOB0_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6519 #define FTFE_FCCOB0_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6520 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
screamer 0:c5e2f793b59a 6521 /* FCCOB7 Bit Fields */
screamer 0:c5e2f793b59a 6522 #define FTFE_FCCOB7_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6523 #define FTFE_FCCOB7_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6524 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
screamer 0:c5e2f793b59a 6525 /* FCCOB6 Bit Fields */
screamer 0:c5e2f793b59a 6526 #define FTFE_FCCOB6_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6527 #define FTFE_FCCOB6_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6528 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
screamer 0:c5e2f793b59a 6529 /* FCCOB5 Bit Fields */
screamer 0:c5e2f793b59a 6530 #define FTFE_FCCOB5_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6531 #define FTFE_FCCOB5_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6532 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
screamer 0:c5e2f793b59a 6533 /* FCCOB4 Bit Fields */
screamer 0:c5e2f793b59a 6534 #define FTFE_FCCOB4_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6535 #define FTFE_FCCOB4_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6536 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
screamer 0:c5e2f793b59a 6537 /* FCCOBB Bit Fields */
screamer 0:c5e2f793b59a 6538 #define FTFE_FCCOBB_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6539 #define FTFE_FCCOBB_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6540 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
screamer 0:c5e2f793b59a 6541 /* FCCOBA Bit Fields */
screamer 0:c5e2f793b59a 6542 #define FTFE_FCCOBA_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6543 #define FTFE_FCCOBA_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6544 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
screamer 0:c5e2f793b59a 6545 /* FCCOB9 Bit Fields */
screamer 0:c5e2f793b59a 6546 #define FTFE_FCCOB9_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6547 #define FTFE_FCCOB9_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6548 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
screamer 0:c5e2f793b59a 6549 /* FCCOB8 Bit Fields */
screamer 0:c5e2f793b59a 6550 #define FTFE_FCCOB8_CCOBn_MASK 0xFFu
screamer 0:c5e2f793b59a 6551 #define FTFE_FCCOB8_CCOBn_SHIFT 0
screamer 0:c5e2f793b59a 6552 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
screamer 0:c5e2f793b59a 6553 /* FPROT3 Bit Fields */
screamer 0:c5e2f793b59a 6554 #define FTFE_FPROT3_PROT_MASK 0xFFu
screamer 0:c5e2f793b59a 6555 #define FTFE_FPROT3_PROT_SHIFT 0
screamer 0:c5e2f793b59a 6556 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
screamer 0:c5e2f793b59a 6557 /* FPROT2 Bit Fields */
screamer 0:c5e2f793b59a 6558 #define FTFE_FPROT2_PROT_MASK 0xFFu
screamer 0:c5e2f793b59a 6559 #define FTFE_FPROT2_PROT_SHIFT 0
screamer 0:c5e2f793b59a 6560 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
screamer 0:c5e2f793b59a 6561 /* FPROT1 Bit Fields */
screamer 0:c5e2f793b59a 6562 #define FTFE_FPROT1_PROT_MASK 0xFFu
screamer 0:c5e2f793b59a 6563 #define FTFE_FPROT1_PROT_SHIFT 0
screamer 0:c5e2f793b59a 6564 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
screamer 0:c5e2f793b59a 6565 /* FPROT0 Bit Fields */
screamer 0:c5e2f793b59a 6566 #define FTFE_FPROT0_PROT_MASK 0xFFu
screamer 0:c5e2f793b59a 6567 #define FTFE_FPROT0_PROT_SHIFT 0
screamer 0:c5e2f793b59a 6568 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
screamer 0:c5e2f793b59a 6569 /* FEPROT Bit Fields */
screamer 0:c5e2f793b59a 6570 #define FTFE_FEPROT_EPROT_MASK 0xFFu
screamer 0:c5e2f793b59a 6571 #define FTFE_FEPROT_EPROT_SHIFT 0
screamer 0:c5e2f793b59a 6572 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
screamer 0:c5e2f793b59a 6573 /* FDPROT Bit Fields */
screamer 0:c5e2f793b59a 6574 #define FTFE_FDPROT_DPROT_MASK 0xFFu
screamer 0:c5e2f793b59a 6575 #define FTFE_FDPROT_DPROT_SHIFT 0
screamer 0:c5e2f793b59a 6576 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
screamer 0:c5e2f793b59a 6577
screamer 0:c5e2f793b59a 6578 /*!
screamer 0:c5e2f793b59a 6579 * @}
screamer 0:c5e2f793b59a 6580 */ /* end of group FTFE_Register_Masks */
screamer 0:c5e2f793b59a 6581
screamer 0:c5e2f793b59a 6582
screamer 0:c5e2f793b59a 6583 /* FTFE - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 6584 /** Peripheral FTFE base address */
screamer 0:c5e2f793b59a 6585 #define FTFE_BASE (0x40020000u)
screamer 0:c5e2f793b59a 6586 /** Peripheral FTFE base pointer */
screamer 0:c5e2f793b59a 6587 #define FTFE ((FTFE_Type *)FTFE_BASE)
screamer 0:c5e2f793b59a 6588 #define FTFE_BASE_PTR (FTFE)
screamer 0:c5e2f793b59a 6589 /** Array initializer of FTFE peripheral base addresses */
screamer 0:c5e2f793b59a 6590 #define FTFE_BASE_ADDRS { FTFE_BASE }
screamer 0:c5e2f793b59a 6591 /** Array initializer of FTFE peripheral base pointers */
screamer 0:c5e2f793b59a 6592 #define FTFE_BASE_PTRS { FTFE }
screamer 0:c5e2f793b59a 6593 /** Interrupt vectors for the FTFE peripheral type */
screamer 0:c5e2f793b59a 6594 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
screamer 0:c5e2f793b59a 6595 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
screamer 0:c5e2f793b59a 6596
screamer 0:c5e2f793b59a 6597 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6598 -- FTFE - Register accessor macros
screamer 0:c5e2f793b59a 6599 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6600
screamer 0:c5e2f793b59a 6601 /*!
screamer 0:c5e2f793b59a 6602 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
screamer 0:c5e2f793b59a 6603 * @{
screamer 0:c5e2f793b59a 6604 */
screamer 0:c5e2f793b59a 6605
screamer 0:c5e2f793b59a 6606
screamer 0:c5e2f793b59a 6607 /* FTFE - Register instance definitions */
screamer 0:c5e2f793b59a 6608 /* FTFE */
screamer 0:c5e2f793b59a 6609 #define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
screamer 0:c5e2f793b59a 6610 #define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
screamer 0:c5e2f793b59a 6611 #define FTFE_FSEC FTFE_FSEC_REG(FTFE)
screamer 0:c5e2f793b59a 6612 #define FTFE_FOPT FTFE_FOPT_REG(FTFE)
screamer 0:c5e2f793b59a 6613 #define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
screamer 0:c5e2f793b59a 6614 #define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
screamer 0:c5e2f793b59a 6615 #define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
screamer 0:c5e2f793b59a 6616 #define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
screamer 0:c5e2f793b59a 6617 #define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
screamer 0:c5e2f793b59a 6618 #define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
screamer 0:c5e2f793b59a 6619 #define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
screamer 0:c5e2f793b59a 6620 #define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
screamer 0:c5e2f793b59a 6621 #define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
screamer 0:c5e2f793b59a 6622 #define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
screamer 0:c5e2f793b59a 6623 #define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
screamer 0:c5e2f793b59a 6624 #define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
screamer 0:c5e2f793b59a 6625 #define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
screamer 0:c5e2f793b59a 6626 #define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
screamer 0:c5e2f793b59a 6627 #define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
screamer 0:c5e2f793b59a 6628 #define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
screamer 0:c5e2f793b59a 6629 #define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
screamer 0:c5e2f793b59a 6630 #define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
screamer 0:c5e2f793b59a 6631
screamer 0:c5e2f793b59a 6632 /*!
screamer 0:c5e2f793b59a 6633 * @}
screamer 0:c5e2f793b59a 6634 */ /* end of group FTFE_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 6635
screamer 0:c5e2f793b59a 6636
screamer 0:c5e2f793b59a 6637 /*!
screamer 0:c5e2f793b59a 6638 * @}
screamer 0:c5e2f793b59a 6639 */ /* end of group FTFE_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 6640
screamer 0:c5e2f793b59a 6641
screamer 0:c5e2f793b59a 6642 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6643 -- FTM Peripheral Access Layer
screamer 0:c5e2f793b59a 6644 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6645
screamer 0:c5e2f793b59a 6646 /*!
screamer 0:c5e2f793b59a 6647 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
screamer 0:c5e2f793b59a 6648 * @{
screamer 0:c5e2f793b59a 6649 */
screamer 0:c5e2f793b59a 6650
screamer 0:c5e2f793b59a 6651 /** FTM - Register Layout Typedef */
screamer 0:c5e2f793b59a 6652 typedef struct {
screamer 0:c5e2f793b59a 6653 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
screamer 0:c5e2f793b59a 6654 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
screamer 0:c5e2f793b59a 6655 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
screamer 0:c5e2f793b59a 6656 struct { /* offset: 0xC, array step: 0x8 */
screamer 0:c5e2f793b59a 6657 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
screamer 0:c5e2f793b59a 6658 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
screamer 0:c5e2f793b59a 6659 } CONTROLS[8];
screamer 0:c5e2f793b59a 6660 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
screamer 0:c5e2f793b59a 6661 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
screamer 0:c5e2f793b59a 6662 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
screamer 0:c5e2f793b59a 6663 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
screamer 0:c5e2f793b59a 6664 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
screamer 0:c5e2f793b59a 6665 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
screamer 0:c5e2f793b59a 6666 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
screamer 0:c5e2f793b59a 6667 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
screamer 0:c5e2f793b59a 6668 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
screamer 0:c5e2f793b59a 6669 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
screamer 0:c5e2f793b59a 6670 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
screamer 0:c5e2f793b59a 6671 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
screamer 0:c5e2f793b59a 6672 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
screamer 0:c5e2f793b59a 6673 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
screamer 0:c5e2f793b59a 6674 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
screamer 0:c5e2f793b59a 6675 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
screamer 0:c5e2f793b59a 6676 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
screamer 0:c5e2f793b59a 6677 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
screamer 0:c5e2f793b59a 6678 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
screamer 0:c5e2f793b59a 6679 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
screamer 0:c5e2f793b59a 6680 } FTM_Type, *FTM_MemMapPtr;
screamer 0:c5e2f793b59a 6681
screamer 0:c5e2f793b59a 6682 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6683 -- FTM - Register accessor macros
screamer 0:c5e2f793b59a 6684 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6685
screamer 0:c5e2f793b59a 6686 /*!
screamer 0:c5e2f793b59a 6687 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
screamer 0:c5e2f793b59a 6688 * @{
screamer 0:c5e2f793b59a 6689 */
screamer 0:c5e2f793b59a 6690
screamer 0:c5e2f793b59a 6691
screamer 0:c5e2f793b59a 6692 /* FTM - Register accessors */
screamer 0:c5e2f793b59a 6693 #define FTM_SC_REG(base) ((base)->SC)
screamer 0:c5e2f793b59a 6694 #define FTM_CNT_REG(base) ((base)->CNT)
screamer 0:c5e2f793b59a 6695 #define FTM_MOD_REG(base) ((base)->MOD)
screamer 0:c5e2f793b59a 6696 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
screamer 0:c5e2f793b59a 6697 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
screamer 0:c5e2f793b59a 6698 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
screamer 0:c5e2f793b59a 6699 #define FTM_STATUS_REG(base) ((base)->STATUS)
screamer 0:c5e2f793b59a 6700 #define FTM_MODE_REG(base) ((base)->MODE)
screamer 0:c5e2f793b59a 6701 #define FTM_SYNC_REG(base) ((base)->SYNC)
screamer 0:c5e2f793b59a 6702 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
screamer 0:c5e2f793b59a 6703 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
screamer 0:c5e2f793b59a 6704 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
screamer 0:c5e2f793b59a 6705 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
screamer 0:c5e2f793b59a 6706 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
screamer 0:c5e2f793b59a 6707 #define FTM_POL_REG(base) ((base)->POL)
screamer 0:c5e2f793b59a 6708 #define FTM_FMS_REG(base) ((base)->FMS)
screamer 0:c5e2f793b59a 6709 #define FTM_FILTER_REG(base) ((base)->FILTER)
screamer 0:c5e2f793b59a 6710 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
screamer 0:c5e2f793b59a 6711 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
screamer 0:c5e2f793b59a 6712 #define FTM_CONF_REG(base) ((base)->CONF)
screamer 0:c5e2f793b59a 6713 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
screamer 0:c5e2f793b59a 6714 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
screamer 0:c5e2f793b59a 6715 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
screamer 0:c5e2f793b59a 6716 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
screamer 0:c5e2f793b59a 6717 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
screamer 0:c5e2f793b59a 6718
screamer 0:c5e2f793b59a 6719 /*!
screamer 0:c5e2f793b59a 6720 * @}
screamer 0:c5e2f793b59a 6721 */ /* end of group FTM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 6722
screamer 0:c5e2f793b59a 6723
screamer 0:c5e2f793b59a 6724 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 6725 -- FTM Register Masks
screamer 0:c5e2f793b59a 6726 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 6727
screamer 0:c5e2f793b59a 6728 /*!
screamer 0:c5e2f793b59a 6729 * @addtogroup FTM_Register_Masks FTM Register Masks
screamer 0:c5e2f793b59a 6730 * @{
screamer 0:c5e2f793b59a 6731 */
screamer 0:c5e2f793b59a 6732
screamer 0:c5e2f793b59a 6733 /* SC Bit Fields */
screamer 0:c5e2f793b59a 6734 #define FTM_SC_PS_MASK 0x7u
screamer 0:c5e2f793b59a 6735 #define FTM_SC_PS_SHIFT 0
screamer 0:c5e2f793b59a 6736 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
screamer 0:c5e2f793b59a 6737 #define FTM_SC_CLKS_MASK 0x18u
screamer 0:c5e2f793b59a 6738 #define FTM_SC_CLKS_SHIFT 3
screamer 0:c5e2f793b59a 6739 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
screamer 0:c5e2f793b59a 6740 #define FTM_SC_CPWMS_MASK 0x20u
screamer 0:c5e2f793b59a 6741 #define FTM_SC_CPWMS_SHIFT 5
screamer 0:c5e2f793b59a 6742 #define FTM_SC_TOIE_MASK 0x40u
screamer 0:c5e2f793b59a 6743 #define FTM_SC_TOIE_SHIFT 6
screamer 0:c5e2f793b59a 6744 #define FTM_SC_TOF_MASK 0x80u
screamer 0:c5e2f793b59a 6745 #define FTM_SC_TOF_SHIFT 7
screamer 0:c5e2f793b59a 6746 /* CNT Bit Fields */
screamer 0:c5e2f793b59a 6747 #define FTM_CNT_COUNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 6748 #define FTM_CNT_COUNT_SHIFT 0
screamer 0:c5e2f793b59a 6749 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
screamer 0:c5e2f793b59a 6750 /* MOD Bit Fields */
screamer 0:c5e2f793b59a 6751 #define FTM_MOD_MOD_MASK 0xFFFFu
screamer 0:c5e2f793b59a 6752 #define FTM_MOD_MOD_SHIFT 0
screamer 0:c5e2f793b59a 6753 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
screamer 0:c5e2f793b59a 6754 /* CnSC Bit Fields */
screamer 0:c5e2f793b59a 6755 #define FTM_CnSC_DMA_MASK 0x1u
screamer 0:c5e2f793b59a 6756 #define FTM_CnSC_DMA_SHIFT 0
screamer 0:c5e2f793b59a 6757 #define FTM_CnSC_ELSA_MASK 0x4u
screamer 0:c5e2f793b59a 6758 #define FTM_CnSC_ELSA_SHIFT 2
screamer 0:c5e2f793b59a 6759 #define FTM_CnSC_ELSB_MASK 0x8u
screamer 0:c5e2f793b59a 6760 #define FTM_CnSC_ELSB_SHIFT 3
screamer 0:c5e2f793b59a 6761 #define FTM_CnSC_MSA_MASK 0x10u
screamer 0:c5e2f793b59a 6762 #define FTM_CnSC_MSA_SHIFT 4
screamer 0:c5e2f793b59a 6763 #define FTM_CnSC_MSB_MASK 0x20u
screamer 0:c5e2f793b59a 6764 #define FTM_CnSC_MSB_SHIFT 5
screamer 0:c5e2f793b59a 6765 #define FTM_CnSC_CHIE_MASK 0x40u
screamer 0:c5e2f793b59a 6766 #define FTM_CnSC_CHIE_SHIFT 6
screamer 0:c5e2f793b59a 6767 #define FTM_CnSC_CHF_MASK 0x80u
screamer 0:c5e2f793b59a 6768 #define FTM_CnSC_CHF_SHIFT 7
screamer 0:c5e2f793b59a 6769 /* CnV Bit Fields */
screamer 0:c5e2f793b59a 6770 #define FTM_CnV_VAL_MASK 0xFFFFu
screamer 0:c5e2f793b59a 6771 #define FTM_CnV_VAL_SHIFT 0
screamer 0:c5e2f793b59a 6772 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
screamer 0:c5e2f793b59a 6773 /* CNTIN Bit Fields */
screamer 0:c5e2f793b59a 6774 #define FTM_CNTIN_INIT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 6775 #define FTM_CNTIN_INIT_SHIFT 0
screamer 0:c5e2f793b59a 6776 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
screamer 0:c5e2f793b59a 6777 /* STATUS Bit Fields */
screamer 0:c5e2f793b59a 6778 #define FTM_STATUS_CH0F_MASK 0x1u
screamer 0:c5e2f793b59a 6779 #define FTM_STATUS_CH0F_SHIFT 0
screamer 0:c5e2f793b59a 6780 #define FTM_STATUS_CH1F_MASK 0x2u
screamer 0:c5e2f793b59a 6781 #define FTM_STATUS_CH1F_SHIFT 1
screamer 0:c5e2f793b59a 6782 #define FTM_STATUS_CH2F_MASK 0x4u
screamer 0:c5e2f793b59a 6783 #define FTM_STATUS_CH2F_SHIFT 2
screamer 0:c5e2f793b59a 6784 #define FTM_STATUS_CH3F_MASK 0x8u
screamer 0:c5e2f793b59a 6785 #define FTM_STATUS_CH3F_SHIFT 3
screamer 0:c5e2f793b59a 6786 #define FTM_STATUS_CH4F_MASK 0x10u
screamer 0:c5e2f793b59a 6787 #define FTM_STATUS_CH4F_SHIFT 4
screamer 0:c5e2f793b59a 6788 #define FTM_STATUS_CH5F_MASK 0x20u
screamer 0:c5e2f793b59a 6789 #define FTM_STATUS_CH5F_SHIFT 5
screamer 0:c5e2f793b59a 6790 #define FTM_STATUS_CH6F_MASK 0x40u
screamer 0:c5e2f793b59a 6791 #define FTM_STATUS_CH6F_SHIFT 6
screamer 0:c5e2f793b59a 6792 #define FTM_STATUS_CH7F_MASK 0x80u
screamer 0:c5e2f793b59a 6793 #define FTM_STATUS_CH7F_SHIFT 7
screamer 0:c5e2f793b59a 6794 /* MODE Bit Fields */
screamer 0:c5e2f793b59a 6795 #define FTM_MODE_FTMEN_MASK 0x1u
screamer 0:c5e2f793b59a 6796 #define FTM_MODE_FTMEN_SHIFT 0
screamer 0:c5e2f793b59a 6797 #define FTM_MODE_INIT_MASK 0x2u
screamer 0:c5e2f793b59a 6798 #define FTM_MODE_INIT_SHIFT 1
screamer 0:c5e2f793b59a 6799 #define FTM_MODE_WPDIS_MASK 0x4u
screamer 0:c5e2f793b59a 6800 #define FTM_MODE_WPDIS_SHIFT 2
screamer 0:c5e2f793b59a 6801 #define FTM_MODE_PWMSYNC_MASK 0x8u
screamer 0:c5e2f793b59a 6802 #define FTM_MODE_PWMSYNC_SHIFT 3
screamer 0:c5e2f793b59a 6803 #define FTM_MODE_CAPTEST_MASK 0x10u
screamer 0:c5e2f793b59a 6804 #define FTM_MODE_CAPTEST_SHIFT 4
screamer 0:c5e2f793b59a 6805 #define FTM_MODE_FAULTM_MASK 0x60u
screamer 0:c5e2f793b59a 6806 #define FTM_MODE_FAULTM_SHIFT 5
screamer 0:c5e2f793b59a 6807 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
screamer 0:c5e2f793b59a 6808 #define FTM_MODE_FAULTIE_MASK 0x80u
screamer 0:c5e2f793b59a 6809 #define FTM_MODE_FAULTIE_SHIFT 7
screamer 0:c5e2f793b59a 6810 /* SYNC Bit Fields */
screamer 0:c5e2f793b59a 6811 #define FTM_SYNC_CNTMIN_MASK 0x1u
screamer 0:c5e2f793b59a 6812 #define FTM_SYNC_CNTMIN_SHIFT 0
screamer 0:c5e2f793b59a 6813 #define FTM_SYNC_CNTMAX_MASK 0x2u
screamer 0:c5e2f793b59a 6814 #define FTM_SYNC_CNTMAX_SHIFT 1
screamer 0:c5e2f793b59a 6815 #define FTM_SYNC_REINIT_MASK 0x4u
screamer 0:c5e2f793b59a 6816 #define FTM_SYNC_REINIT_SHIFT 2
screamer 0:c5e2f793b59a 6817 #define FTM_SYNC_SYNCHOM_MASK 0x8u
screamer 0:c5e2f793b59a 6818 #define FTM_SYNC_SYNCHOM_SHIFT 3
screamer 0:c5e2f793b59a 6819 #define FTM_SYNC_TRIG0_MASK 0x10u
screamer 0:c5e2f793b59a 6820 #define FTM_SYNC_TRIG0_SHIFT 4
screamer 0:c5e2f793b59a 6821 #define FTM_SYNC_TRIG1_MASK 0x20u
screamer 0:c5e2f793b59a 6822 #define FTM_SYNC_TRIG1_SHIFT 5
screamer 0:c5e2f793b59a 6823 #define FTM_SYNC_TRIG2_MASK 0x40u
screamer 0:c5e2f793b59a 6824 #define FTM_SYNC_TRIG2_SHIFT 6
screamer 0:c5e2f793b59a 6825 #define FTM_SYNC_SWSYNC_MASK 0x80u
screamer 0:c5e2f793b59a 6826 #define FTM_SYNC_SWSYNC_SHIFT 7
screamer 0:c5e2f793b59a 6827 /* OUTINIT Bit Fields */
screamer 0:c5e2f793b59a 6828 #define FTM_OUTINIT_CH0OI_MASK 0x1u
screamer 0:c5e2f793b59a 6829 #define FTM_OUTINIT_CH0OI_SHIFT 0
screamer 0:c5e2f793b59a 6830 #define FTM_OUTINIT_CH1OI_MASK 0x2u
screamer 0:c5e2f793b59a 6831 #define FTM_OUTINIT_CH1OI_SHIFT 1
screamer 0:c5e2f793b59a 6832 #define FTM_OUTINIT_CH2OI_MASK 0x4u
screamer 0:c5e2f793b59a 6833 #define FTM_OUTINIT_CH2OI_SHIFT 2
screamer 0:c5e2f793b59a 6834 #define FTM_OUTINIT_CH3OI_MASK 0x8u
screamer 0:c5e2f793b59a 6835 #define FTM_OUTINIT_CH3OI_SHIFT 3
screamer 0:c5e2f793b59a 6836 #define FTM_OUTINIT_CH4OI_MASK 0x10u
screamer 0:c5e2f793b59a 6837 #define FTM_OUTINIT_CH4OI_SHIFT 4
screamer 0:c5e2f793b59a 6838 #define FTM_OUTINIT_CH5OI_MASK 0x20u
screamer 0:c5e2f793b59a 6839 #define FTM_OUTINIT_CH5OI_SHIFT 5
screamer 0:c5e2f793b59a 6840 #define FTM_OUTINIT_CH6OI_MASK 0x40u
screamer 0:c5e2f793b59a 6841 #define FTM_OUTINIT_CH6OI_SHIFT 6
screamer 0:c5e2f793b59a 6842 #define FTM_OUTINIT_CH7OI_MASK 0x80u
screamer 0:c5e2f793b59a 6843 #define FTM_OUTINIT_CH7OI_SHIFT 7
screamer 0:c5e2f793b59a 6844 /* OUTMASK Bit Fields */
screamer 0:c5e2f793b59a 6845 #define FTM_OUTMASK_CH0OM_MASK 0x1u
screamer 0:c5e2f793b59a 6846 #define FTM_OUTMASK_CH0OM_SHIFT 0
screamer 0:c5e2f793b59a 6847 #define FTM_OUTMASK_CH1OM_MASK 0x2u
screamer 0:c5e2f793b59a 6848 #define FTM_OUTMASK_CH1OM_SHIFT 1
screamer 0:c5e2f793b59a 6849 #define FTM_OUTMASK_CH2OM_MASK 0x4u
screamer 0:c5e2f793b59a 6850 #define FTM_OUTMASK_CH2OM_SHIFT 2
screamer 0:c5e2f793b59a 6851 #define FTM_OUTMASK_CH3OM_MASK 0x8u
screamer 0:c5e2f793b59a 6852 #define FTM_OUTMASK_CH3OM_SHIFT 3
screamer 0:c5e2f793b59a 6853 #define FTM_OUTMASK_CH4OM_MASK 0x10u
screamer 0:c5e2f793b59a 6854 #define FTM_OUTMASK_CH4OM_SHIFT 4
screamer 0:c5e2f793b59a 6855 #define FTM_OUTMASK_CH5OM_MASK 0x20u
screamer 0:c5e2f793b59a 6856 #define FTM_OUTMASK_CH5OM_SHIFT 5
screamer 0:c5e2f793b59a 6857 #define FTM_OUTMASK_CH6OM_MASK 0x40u
screamer 0:c5e2f793b59a 6858 #define FTM_OUTMASK_CH6OM_SHIFT 6
screamer 0:c5e2f793b59a 6859 #define FTM_OUTMASK_CH7OM_MASK 0x80u
screamer 0:c5e2f793b59a 6860 #define FTM_OUTMASK_CH7OM_SHIFT 7
screamer 0:c5e2f793b59a 6861 /* COMBINE Bit Fields */
screamer 0:c5e2f793b59a 6862 #define FTM_COMBINE_COMBINE0_MASK 0x1u
screamer 0:c5e2f793b59a 6863 #define FTM_COMBINE_COMBINE0_SHIFT 0
screamer 0:c5e2f793b59a 6864 #define FTM_COMBINE_COMP0_MASK 0x2u
screamer 0:c5e2f793b59a 6865 #define FTM_COMBINE_COMP0_SHIFT 1
screamer 0:c5e2f793b59a 6866 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
screamer 0:c5e2f793b59a 6867 #define FTM_COMBINE_DECAPEN0_SHIFT 2
screamer 0:c5e2f793b59a 6868 #define FTM_COMBINE_DECAP0_MASK 0x8u
screamer 0:c5e2f793b59a 6869 #define FTM_COMBINE_DECAP0_SHIFT 3
screamer 0:c5e2f793b59a 6870 #define FTM_COMBINE_DTEN0_MASK 0x10u
screamer 0:c5e2f793b59a 6871 #define FTM_COMBINE_DTEN0_SHIFT 4
screamer 0:c5e2f793b59a 6872 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
screamer 0:c5e2f793b59a 6873 #define FTM_COMBINE_SYNCEN0_SHIFT 5
screamer 0:c5e2f793b59a 6874 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
screamer 0:c5e2f793b59a 6875 #define FTM_COMBINE_FAULTEN0_SHIFT 6
screamer 0:c5e2f793b59a 6876 #define FTM_COMBINE_COMBINE1_MASK 0x100u
screamer 0:c5e2f793b59a 6877 #define FTM_COMBINE_COMBINE1_SHIFT 8
screamer 0:c5e2f793b59a 6878 #define FTM_COMBINE_COMP1_MASK 0x200u
screamer 0:c5e2f793b59a 6879 #define FTM_COMBINE_COMP1_SHIFT 9
screamer 0:c5e2f793b59a 6880 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
screamer 0:c5e2f793b59a 6881 #define FTM_COMBINE_DECAPEN1_SHIFT 10
screamer 0:c5e2f793b59a 6882 #define FTM_COMBINE_DECAP1_MASK 0x800u
screamer 0:c5e2f793b59a 6883 #define FTM_COMBINE_DECAP1_SHIFT 11
screamer 0:c5e2f793b59a 6884 #define FTM_COMBINE_DTEN1_MASK 0x1000u
screamer 0:c5e2f793b59a 6885 #define FTM_COMBINE_DTEN1_SHIFT 12
screamer 0:c5e2f793b59a 6886 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
screamer 0:c5e2f793b59a 6887 #define FTM_COMBINE_SYNCEN1_SHIFT 13
screamer 0:c5e2f793b59a 6888 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
screamer 0:c5e2f793b59a 6889 #define FTM_COMBINE_FAULTEN1_SHIFT 14
screamer 0:c5e2f793b59a 6890 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
screamer 0:c5e2f793b59a 6891 #define FTM_COMBINE_COMBINE2_SHIFT 16
screamer 0:c5e2f793b59a 6892 #define FTM_COMBINE_COMP2_MASK 0x20000u
screamer 0:c5e2f793b59a 6893 #define FTM_COMBINE_COMP2_SHIFT 17
screamer 0:c5e2f793b59a 6894 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
screamer 0:c5e2f793b59a 6895 #define FTM_COMBINE_DECAPEN2_SHIFT 18
screamer 0:c5e2f793b59a 6896 #define FTM_COMBINE_DECAP2_MASK 0x80000u
screamer 0:c5e2f793b59a 6897 #define FTM_COMBINE_DECAP2_SHIFT 19
screamer 0:c5e2f793b59a 6898 #define FTM_COMBINE_DTEN2_MASK 0x100000u
screamer 0:c5e2f793b59a 6899 #define FTM_COMBINE_DTEN2_SHIFT 20
screamer 0:c5e2f793b59a 6900 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
screamer 0:c5e2f793b59a 6901 #define FTM_COMBINE_SYNCEN2_SHIFT 21
screamer 0:c5e2f793b59a 6902 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
screamer 0:c5e2f793b59a 6903 #define FTM_COMBINE_FAULTEN2_SHIFT 22
screamer 0:c5e2f793b59a 6904 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
screamer 0:c5e2f793b59a 6905 #define FTM_COMBINE_COMBINE3_SHIFT 24
screamer 0:c5e2f793b59a 6906 #define FTM_COMBINE_COMP3_MASK 0x2000000u
screamer 0:c5e2f793b59a 6907 #define FTM_COMBINE_COMP3_SHIFT 25
screamer 0:c5e2f793b59a 6908 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
screamer 0:c5e2f793b59a 6909 #define FTM_COMBINE_DECAPEN3_SHIFT 26
screamer 0:c5e2f793b59a 6910 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
screamer 0:c5e2f793b59a 6911 #define FTM_COMBINE_DECAP3_SHIFT 27
screamer 0:c5e2f793b59a 6912 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
screamer 0:c5e2f793b59a 6913 #define FTM_COMBINE_DTEN3_SHIFT 28
screamer 0:c5e2f793b59a 6914 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
screamer 0:c5e2f793b59a 6915 #define FTM_COMBINE_SYNCEN3_SHIFT 29
screamer 0:c5e2f793b59a 6916 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
screamer 0:c5e2f793b59a 6917 #define FTM_COMBINE_FAULTEN3_SHIFT 30
screamer 0:c5e2f793b59a 6918 /* DEADTIME Bit Fields */
screamer 0:c5e2f793b59a 6919 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
screamer 0:c5e2f793b59a 6920 #define FTM_DEADTIME_DTVAL_SHIFT 0
screamer 0:c5e2f793b59a 6921 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
screamer 0:c5e2f793b59a 6922 #define FTM_DEADTIME_DTPS_MASK 0xC0u
screamer 0:c5e2f793b59a 6923 #define FTM_DEADTIME_DTPS_SHIFT 6
screamer 0:c5e2f793b59a 6924 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
screamer 0:c5e2f793b59a 6925 /* EXTTRIG Bit Fields */
screamer 0:c5e2f793b59a 6926 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
screamer 0:c5e2f793b59a 6927 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
screamer 0:c5e2f793b59a 6928 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
screamer 0:c5e2f793b59a 6929 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
screamer 0:c5e2f793b59a 6930 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
screamer 0:c5e2f793b59a 6931 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
screamer 0:c5e2f793b59a 6932 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
screamer 0:c5e2f793b59a 6933 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
screamer 0:c5e2f793b59a 6934 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
screamer 0:c5e2f793b59a 6935 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
screamer 0:c5e2f793b59a 6936 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
screamer 0:c5e2f793b59a 6937 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
screamer 0:c5e2f793b59a 6938 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
screamer 0:c5e2f793b59a 6939 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
screamer 0:c5e2f793b59a 6940 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
screamer 0:c5e2f793b59a 6941 #define FTM_EXTTRIG_TRIGF_SHIFT 7
screamer 0:c5e2f793b59a 6942 /* POL Bit Fields */
screamer 0:c5e2f793b59a 6943 #define FTM_POL_POL0_MASK 0x1u
screamer 0:c5e2f793b59a 6944 #define FTM_POL_POL0_SHIFT 0
screamer 0:c5e2f793b59a 6945 #define FTM_POL_POL1_MASK 0x2u
screamer 0:c5e2f793b59a 6946 #define FTM_POL_POL1_SHIFT 1
screamer 0:c5e2f793b59a 6947 #define FTM_POL_POL2_MASK 0x4u
screamer 0:c5e2f793b59a 6948 #define FTM_POL_POL2_SHIFT 2
screamer 0:c5e2f793b59a 6949 #define FTM_POL_POL3_MASK 0x8u
screamer 0:c5e2f793b59a 6950 #define FTM_POL_POL3_SHIFT 3
screamer 0:c5e2f793b59a 6951 #define FTM_POL_POL4_MASK 0x10u
screamer 0:c5e2f793b59a 6952 #define FTM_POL_POL4_SHIFT 4
screamer 0:c5e2f793b59a 6953 #define FTM_POL_POL5_MASK 0x20u
screamer 0:c5e2f793b59a 6954 #define FTM_POL_POL5_SHIFT 5
screamer 0:c5e2f793b59a 6955 #define FTM_POL_POL6_MASK 0x40u
screamer 0:c5e2f793b59a 6956 #define FTM_POL_POL6_SHIFT 6
screamer 0:c5e2f793b59a 6957 #define FTM_POL_POL7_MASK 0x80u
screamer 0:c5e2f793b59a 6958 #define FTM_POL_POL7_SHIFT 7
screamer 0:c5e2f793b59a 6959 /* FMS Bit Fields */
screamer 0:c5e2f793b59a 6960 #define FTM_FMS_FAULTF0_MASK 0x1u
screamer 0:c5e2f793b59a 6961 #define FTM_FMS_FAULTF0_SHIFT 0
screamer 0:c5e2f793b59a 6962 #define FTM_FMS_FAULTF1_MASK 0x2u
screamer 0:c5e2f793b59a 6963 #define FTM_FMS_FAULTF1_SHIFT 1
screamer 0:c5e2f793b59a 6964 #define FTM_FMS_FAULTF2_MASK 0x4u
screamer 0:c5e2f793b59a 6965 #define FTM_FMS_FAULTF2_SHIFT 2
screamer 0:c5e2f793b59a 6966 #define FTM_FMS_FAULTF3_MASK 0x8u
screamer 0:c5e2f793b59a 6967 #define FTM_FMS_FAULTF3_SHIFT 3
screamer 0:c5e2f793b59a 6968 #define FTM_FMS_FAULTIN_MASK 0x20u
screamer 0:c5e2f793b59a 6969 #define FTM_FMS_FAULTIN_SHIFT 5
screamer 0:c5e2f793b59a 6970 #define FTM_FMS_WPEN_MASK 0x40u
screamer 0:c5e2f793b59a 6971 #define FTM_FMS_WPEN_SHIFT 6
screamer 0:c5e2f793b59a 6972 #define FTM_FMS_FAULTF_MASK 0x80u
screamer 0:c5e2f793b59a 6973 #define FTM_FMS_FAULTF_SHIFT 7
screamer 0:c5e2f793b59a 6974 /* FILTER Bit Fields */
screamer 0:c5e2f793b59a 6975 #define FTM_FILTER_CH0FVAL_MASK 0xFu
screamer 0:c5e2f793b59a 6976 #define FTM_FILTER_CH0FVAL_SHIFT 0
screamer 0:c5e2f793b59a 6977 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
screamer 0:c5e2f793b59a 6978 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
screamer 0:c5e2f793b59a 6979 #define FTM_FILTER_CH1FVAL_SHIFT 4
screamer 0:c5e2f793b59a 6980 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
screamer 0:c5e2f793b59a 6981 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
screamer 0:c5e2f793b59a 6982 #define FTM_FILTER_CH2FVAL_SHIFT 8
screamer 0:c5e2f793b59a 6983 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
screamer 0:c5e2f793b59a 6984 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
screamer 0:c5e2f793b59a 6985 #define FTM_FILTER_CH3FVAL_SHIFT 12
screamer 0:c5e2f793b59a 6986 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
screamer 0:c5e2f793b59a 6987 /* FLTCTRL Bit Fields */
screamer 0:c5e2f793b59a 6988 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
screamer 0:c5e2f793b59a 6989 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
screamer 0:c5e2f793b59a 6990 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
screamer 0:c5e2f793b59a 6991 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
screamer 0:c5e2f793b59a 6992 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
screamer 0:c5e2f793b59a 6993 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
screamer 0:c5e2f793b59a 6994 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
screamer 0:c5e2f793b59a 6995 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
screamer 0:c5e2f793b59a 6996 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
screamer 0:c5e2f793b59a 6997 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
screamer 0:c5e2f793b59a 6998 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
screamer 0:c5e2f793b59a 6999 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
screamer 0:c5e2f793b59a 7000 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
screamer 0:c5e2f793b59a 7001 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
screamer 0:c5e2f793b59a 7002 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
screamer 0:c5e2f793b59a 7003 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
screamer 0:c5e2f793b59a 7004 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
screamer 0:c5e2f793b59a 7005 #define FTM_FLTCTRL_FFVAL_SHIFT 8
screamer 0:c5e2f793b59a 7006 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
screamer 0:c5e2f793b59a 7007 /* QDCTRL Bit Fields */
screamer 0:c5e2f793b59a 7008 #define FTM_QDCTRL_QUADEN_MASK 0x1u
screamer 0:c5e2f793b59a 7009 #define FTM_QDCTRL_QUADEN_SHIFT 0
screamer 0:c5e2f793b59a 7010 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
screamer 0:c5e2f793b59a 7011 #define FTM_QDCTRL_TOFDIR_SHIFT 1
screamer 0:c5e2f793b59a 7012 #define FTM_QDCTRL_QUADIR_MASK 0x4u
screamer 0:c5e2f793b59a 7013 #define FTM_QDCTRL_QUADIR_SHIFT 2
screamer 0:c5e2f793b59a 7014 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
screamer 0:c5e2f793b59a 7015 #define FTM_QDCTRL_QUADMODE_SHIFT 3
screamer 0:c5e2f793b59a 7016 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
screamer 0:c5e2f793b59a 7017 #define FTM_QDCTRL_PHBPOL_SHIFT 4
screamer 0:c5e2f793b59a 7018 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
screamer 0:c5e2f793b59a 7019 #define FTM_QDCTRL_PHAPOL_SHIFT 5
screamer 0:c5e2f793b59a 7020 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
screamer 0:c5e2f793b59a 7021 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
screamer 0:c5e2f793b59a 7022 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
screamer 0:c5e2f793b59a 7023 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
screamer 0:c5e2f793b59a 7024 /* CONF Bit Fields */
screamer 0:c5e2f793b59a 7025 #define FTM_CONF_NUMTOF_MASK 0x1Fu
screamer 0:c5e2f793b59a 7026 #define FTM_CONF_NUMTOF_SHIFT 0
screamer 0:c5e2f793b59a 7027 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
screamer 0:c5e2f793b59a 7028 #define FTM_CONF_BDMMODE_MASK 0xC0u
screamer 0:c5e2f793b59a 7029 #define FTM_CONF_BDMMODE_SHIFT 6
screamer 0:c5e2f793b59a 7030 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
screamer 0:c5e2f793b59a 7031 #define FTM_CONF_GTBEEN_MASK 0x200u
screamer 0:c5e2f793b59a 7032 #define FTM_CONF_GTBEEN_SHIFT 9
screamer 0:c5e2f793b59a 7033 #define FTM_CONF_GTBEOUT_MASK 0x400u
screamer 0:c5e2f793b59a 7034 #define FTM_CONF_GTBEOUT_SHIFT 10
screamer 0:c5e2f793b59a 7035 /* FLTPOL Bit Fields */
screamer 0:c5e2f793b59a 7036 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
screamer 0:c5e2f793b59a 7037 #define FTM_FLTPOL_FLT0POL_SHIFT 0
screamer 0:c5e2f793b59a 7038 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
screamer 0:c5e2f793b59a 7039 #define FTM_FLTPOL_FLT1POL_SHIFT 1
screamer 0:c5e2f793b59a 7040 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
screamer 0:c5e2f793b59a 7041 #define FTM_FLTPOL_FLT2POL_SHIFT 2
screamer 0:c5e2f793b59a 7042 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
screamer 0:c5e2f793b59a 7043 #define FTM_FLTPOL_FLT3POL_SHIFT 3
screamer 0:c5e2f793b59a 7044 /* SYNCONF Bit Fields */
screamer 0:c5e2f793b59a 7045 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
screamer 0:c5e2f793b59a 7046 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
screamer 0:c5e2f793b59a 7047 #define FTM_SYNCONF_CNTINC_MASK 0x4u
screamer 0:c5e2f793b59a 7048 #define FTM_SYNCONF_CNTINC_SHIFT 2
screamer 0:c5e2f793b59a 7049 #define FTM_SYNCONF_INVC_MASK 0x10u
screamer 0:c5e2f793b59a 7050 #define FTM_SYNCONF_INVC_SHIFT 4
screamer 0:c5e2f793b59a 7051 #define FTM_SYNCONF_SWOC_MASK 0x20u
screamer 0:c5e2f793b59a 7052 #define FTM_SYNCONF_SWOC_SHIFT 5
screamer 0:c5e2f793b59a 7053 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
screamer 0:c5e2f793b59a 7054 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
screamer 0:c5e2f793b59a 7055 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
screamer 0:c5e2f793b59a 7056 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
screamer 0:c5e2f793b59a 7057 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
screamer 0:c5e2f793b59a 7058 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
screamer 0:c5e2f793b59a 7059 #define FTM_SYNCONF_SWOM_MASK 0x400u
screamer 0:c5e2f793b59a 7060 #define FTM_SYNCONF_SWOM_SHIFT 10
screamer 0:c5e2f793b59a 7061 #define FTM_SYNCONF_SWINVC_MASK 0x800u
screamer 0:c5e2f793b59a 7062 #define FTM_SYNCONF_SWINVC_SHIFT 11
screamer 0:c5e2f793b59a 7063 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
screamer 0:c5e2f793b59a 7064 #define FTM_SYNCONF_SWSOC_SHIFT 12
screamer 0:c5e2f793b59a 7065 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
screamer 0:c5e2f793b59a 7066 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
screamer 0:c5e2f793b59a 7067 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
screamer 0:c5e2f793b59a 7068 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
screamer 0:c5e2f793b59a 7069 #define FTM_SYNCONF_HWOM_MASK 0x40000u
screamer 0:c5e2f793b59a 7070 #define FTM_SYNCONF_HWOM_SHIFT 18
screamer 0:c5e2f793b59a 7071 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
screamer 0:c5e2f793b59a 7072 #define FTM_SYNCONF_HWINVC_SHIFT 19
screamer 0:c5e2f793b59a 7073 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
screamer 0:c5e2f793b59a 7074 #define FTM_SYNCONF_HWSOC_SHIFT 20
screamer 0:c5e2f793b59a 7075 /* INVCTRL Bit Fields */
screamer 0:c5e2f793b59a 7076 #define FTM_INVCTRL_INV0EN_MASK 0x1u
screamer 0:c5e2f793b59a 7077 #define FTM_INVCTRL_INV0EN_SHIFT 0
screamer 0:c5e2f793b59a 7078 #define FTM_INVCTRL_INV1EN_MASK 0x2u
screamer 0:c5e2f793b59a 7079 #define FTM_INVCTRL_INV1EN_SHIFT 1
screamer 0:c5e2f793b59a 7080 #define FTM_INVCTRL_INV2EN_MASK 0x4u
screamer 0:c5e2f793b59a 7081 #define FTM_INVCTRL_INV2EN_SHIFT 2
screamer 0:c5e2f793b59a 7082 #define FTM_INVCTRL_INV3EN_MASK 0x8u
screamer 0:c5e2f793b59a 7083 #define FTM_INVCTRL_INV3EN_SHIFT 3
screamer 0:c5e2f793b59a 7084 /* SWOCTRL Bit Fields */
screamer 0:c5e2f793b59a 7085 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
screamer 0:c5e2f793b59a 7086 #define FTM_SWOCTRL_CH0OC_SHIFT 0
screamer 0:c5e2f793b59a 7087 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
screamer 0:c5e2f793b59a 7088 #define FTM_SWOCTRL_CH1OC_SHIFT 1
screamer 0:c5e2f793b59a 7089 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
screamer 0:c5e2f793b59a 7090 #define FTM_SWOCTRL_CH2OC_SHIFT 2
screamer 0:c5e2f793b59a 7091 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
screamer 0:c5e2f793b59a 7092 #define FTM_SWOCTRL_CH3OC_SHIFT 3
screamer 0:c5e2f793b59a 7093 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
screamer 0:c5e2f793b59a 7094 #define FTM_SWOCTRL_CH4OC_SHIFT 4
screamer 0:c5e2f793b59a 7095 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
screamer 0:c5e2f793b59a 7096 #define FTM_SWOCTRL_CH5OC_SHIFT 5
screamer 0:c5e2f793b59a 7097 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
screamer 0:c5e2f793b59a 7098 #define FTM_SWOCTRL_CH6OC_SHIFT 6
screamer 0:c5e2f793b59a 7099 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
screamer 0:c5e2f793b59a 7100 #define FTM_SWOCTRL_CH7OC_SHIFT 7
screamer 0:c5e2f793b59a 7101 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
screamer 0:c5e2f793b59a 7102 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
screamer 0:c5e2f793b59a 7103 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
screamer 0:c5e2f793b59a 7104 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
screamer 0:c5e2f793b59a 7105 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
screamer 0:c5e2f793b59a 7106 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
screamer 0:c5e2f793b59a 7107 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
screamer 0:c5e2f793b59a 7108 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
screamer 0:c5e2f793b59a 7109 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
screamer 0:c5e2f793b59a 7110 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
screamer 0:c5e2f793b59a 7111 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
screamer 0:c5e2f793b59a 7112 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
screamer 0:c5e2f793b59a 7113 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
screamer 0:c5e2f793b59a 7114 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
screamer 0:c5e2f793b59a 7115 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
screamer 0:c5e2f793b59a 7116 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
screamer 0:c5e2f793b59a 7117 /* PWMLOAD Bit Fields */
screamer 0:c5e2f793b59a 7118 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
screamer 0:c5e2f793b59a 7119 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
screamer 0:c5e2f793b59a 7120 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
screamer 0:c5e2f793b59a 7121 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
screamer 0:c5e2f793b59a 7122 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
screamer 0:c5e2f793b59a 7123 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
screamer 0:c5e2f793b59a 7124 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
screamer 0:c5e2f793b59a 7125 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
screamer 0:c5e2f793b59a 7126 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
screamer 0:c5e2f793b59a 7127 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
screamer 0:c5e2f793b59a 7128 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
screamer 0:c5e2f793b59a 7129 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
screamer 0:c5e2f793b59a 7130 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
screamer 0:c5e2f793b59a 7131 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
screamer 0:c5e2f793b59a 7132 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
screamer 0:c5e2f793b59a 7133 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
screamer 0:c5e2f793b59a 7134 #define FTM_PWMLOAD_LDOK_MASK 0x200u
screamer 0:c5e2f793b59a 7135 #define FTM_PWMLOAD_LDOK_SHIFT 9
screamer 0:c5e2f793b59a 7136
screamer 0:c5e2f793b59a 7137 /*!
screamer 0:c5e2f793b59a 7138 * @}
screamer 0:c5e2f793b59a 7139 */ /* end of group FTM_Register_Masks */
screamer 0:c5e2f793b59a 7140
screamer 0:c5e2f793b59a 7141
screamer 0:c5e2f793b59a 7142 /* FTM - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 7143 /** Peripheral FTM0 base address */
screamer 0:c5e2f793b59a 7144 #define FTM0_BASE (0x40038000u)
screamer 0:c5e2f793b59a 7145 /** Peripheral FTM0 base pointer */
screamer 0:c5e2f793b59a 7146 #define FTM0 ((FTM_Type *)FTM0_BASE)
screamer 0:c5e2f793b59a 7147 #define FTM0_BASE_PTR (FTM0)
screamer 0:c5e2f793b59a 7148 /** Peripheral FTM1 base address */
screamer 0:c5e2f793b59a 7149 #define FTM1_BASE (0x40039000u)
screamer 0:c5e2f793b59a 7150 /** Peripheral FTM1 base pointer */
screamer 0:c5e2f793b59a 7151 #define FTM1 ((FTM_Type *)FTM1_BASE)
screamer 0:c5e2f793b59a 7152 #define FTM1_BASE_PTR (FTM1)
screamer 0:c5e2f793b59a 7153 /** Peripheral FTM2 base address */
screamer 0:c5e2f793b59a 7154 #define FTM2_BASE (0x4003A000u)
screamer 0:c5e2f793b59a 7155 /** Peripheral FTM2 base pointer */
screamer 0:c5e2f793b59a 7156 #define FTM2 ((FTM_Type *)FTM2_BASE)
screamer 0:c5e2f793b59a 7157 #define FTM2_BASE_PTR (FTM2)
screamer 0:c5e2f793b59a 7158 /** Peripheral FTM3 base address */
screamer 0:c5e2f793b59a 7159 #define FTM3_BASE (0x400B9000u)
screamer 0:c5e2f793b59a 7160 /** Peripheral FTM3 base pointer */
screamer 0:c5e2f793b59a 7161 #define FTM3 ((FTM_Type *)FTM3_BASE)
screamer 0:c5e2f793b59a 7162 #define FTM3_BASE_PTR (FTM3)
screamer 0:c5e2f793b59a 7163 /** Array initializer of FTM peripheral base addresses */
screamer 0:c5e2f793b59a 7164 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
screamer 0:c5e2f793b59a 7165 /** Array initializer of FTM peripheral base pointers */
screamer 0:c5e2f793b59a 7166 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
screamer 0:c5e2f793b59a 7167 /** Interrupt vectors for the FTM peripheral type */
screamer 0:c5e2f793b59a 7168 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
screamer 0:c5e2f793b59a 7169
screamer 0:c5e2f793b59a 7170 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7171 -- FTM - Register accessor macros
screamer 0:c5e2f793b59a 7172 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7173
screamer 0:c5e2f793b59a 7174 /*!
screamer 0:c5e2f793b59a 7175 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
screamer 0:c5e2f793b59a 7176 * @{
screamer 0:c5e2f793b59a 7177 */
screamer 0:c5e2f793b59a 7178
screamer 0:c5e2f793b59a 7179
screamer 0:c5e2f793b59a 7180 /* FTM - Register instance definitions */
screamer 0:c5e2f793b59a 7181 /* FTM0 */
screamer 0:c5e2f793b59a 7182 #define FTM0_SC FTM_SC_REG(FTM0)
screamer 0:c5e2f793b59a 7183 #define FTM0_CNT FTM_CNT_REG(FTM0)
screamer 0:c5e2f793b59a 7184 #define FTM0_MOD FTM_MOD_REG(FTM0)
screamer 0:c5e2f793b59a 7185 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
screamer 0:c5e2f793b59a 7186 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
screamer 0:c5e2f793b59a 7187 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
screamer 0:c5e2f793b59a 7188 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
screamer 0:c5e2f793b59a 7189 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
screamer 0:c5e2f793b59a 7190 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
screamer 0:c5e2f793b59a 7191 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
screamer 0:c5e2f793b59a 7192 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
screamer 0:c5e2f793b59a 7193 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
screamer 0:c5e2f793b59a 7194 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
screamer 0:c5e2f793b59a 7195 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
screamer 0:c5e2f793b59a 7196 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
screamer 0:c5e2f793b59a 7197 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
screamer 0:c5e2f793b59a 7198 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
screamer 0:c5e2f793b59a 7199 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
screamer 0:c5e2f793b59a 7200 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
screamer 0:c5e2f793b59a 7201 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
screamer 0:c5e2f793b59a 7202 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
screamer 0:c5e2f793b59a 7203 #define FTM0_MODE FTM_MODE_REG(FTM0)
screamer 0:c5e2f793b59a 7204 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
screamer 0:c5e2f793b59a 7205 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
screamer 0:c5e2f793b59a 7206 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
screamer 0:c5e2f793b59a 7207 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
screamer 0:c5e2f793b59a 7208 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
screamer 0:c5e2f793b59a 7209 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
screamer 0:c5e2f793b59a 7210 #define FTM0_POL FTM_POL_REG(FTM0)
screamer 0:c5e2f793b59a 7211 #define FTM0_FMS FTM_FMS_REG(FTM0)
screamer 0:c5e2f793b59a 7212 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
screamer 0:c5e2f793b59a 7213 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
screamer 0:c5e2f793b59a 7214 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
screamer 0:c5e2f793b59a 7215 #define FTM0_CONF FTM_CONF_REG(FTM0)
screamer 0:c5e2f793b59a 7216 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
screamer 0:c5e2f793b59a 7217 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
screamer 0:c5e2f793b59a 7218 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
screamer 0:c5e2f793b59a 7219 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
screamer 0:c5e2f793b59a 7220 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
screamer 0:c5e2f793b59a 7221 /* FTM1 */
screamer 0:c5e2f793b59a 7222 #define FTM1_SC FTM_SC_REG(FTM1)
screamer 0:c5e2f793b59a 7223 #define FTM1_CNT FTM_CNT_REG(FTM1)
screamer 0:c5e2f793b59a 7224 #define FTM1_MOD FTM_MOD_REG(FTM1)
screamer 0:c5e2f793b59a 7225 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
screamer 0:c5e2f793b59a 7226 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
screamer 0:c5e2f793b59a 7227 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
screamer 0:c5e2f793b59a 7228 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
screamer 0:c5e2f793b59a 7229 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
screamer 0:c5e2f793b59a 7230 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
screamer 0:c5e2f793b59a 7231 #define FTM1_MODE FTM_MODE_REG(FTM1)
screamer 0:c5e2f793b59a 7232 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
screamer 0:c5e2f793b59a 7233 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
screamer 0:c5e2f793b59a 7234 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
screamer 0:c5e2f793b59a 7235 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
screamer 0:c5e2f793b59a 7236 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
screamer 0:c5e2f793b59a 7237 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
screamer 0:c5e2f793b59a 7238 #define FTM1_POL FTM_POL_REG(FTM1)
screamer 0:c5e2f793b59a 7239 #define FTM1_FMS FTM_FMS_REG(FTM1)
screamer 0:c5e2f793b59a 7240 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
screamer 0:c5e2f793b59a 7241 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
screamer 0:c5e2f793b59a 7242 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
screamer 0:c5e2f793b59a 7243 #define FTM1_CONF FTM_CONF_REG(FTM1)
screamer 0:c5e2f793b59a 7244 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
screamer 0:c5e2f793b59a 7245 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
screamer 0:c5e2f793b59a 7246 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
screamer 0:c5e2f793b59a 7247 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
screamer 0:c5e2f793b59a 7248 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
screamer 0:c5e2f793b59a 7249 /* FTM2 */
screamer 0:c5e2f793b59a 7250 #define FTM2_SC FTM_SC_REG(FTM2)
screamer 0:c5e2f793b59a 7251 #define FTM2_CNT FTM_CNT_REG(FTM2)
screamer 0:c5e2f793b59a 7252 #define FTM2_MOD FTM_MOD_REG(FTM2)
screamer 0:c5e2f793b59a 7253 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
screamer 0:c5e2f793b59a 7254 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
screamer 0:c5e2f793b59a 7255 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
screamer 0:c5e2f793b59a 7256 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
screamer 0:c5e2f793b59a 7257 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
screamer 0:c5e2f793b59a 7258 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
screamer 0:c5e2f793b59a 7259 #define FTM2_MODE FTM_MODE_REG(FTM2)
screamer 0:c5e2f793b59a 7260 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
screamer 0:c5e2f793b59a 7261 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
screamer 0:c5e2f793b59a 7262 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
screamer 0:c5e2f793b59a 7263 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
screamer 0:c5e2f793b59a 7264 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
screamer 0:c5e2f793b59a 7265 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
screamer 0:c5e2f793b59a 7266 #define FTM2_POL FTM_POL_REG(FTM2)
screamer 0:c5e2f793b59a 7267 #define FTM2_FMS FTM_FMS_REG(FTM2)
screamer 0:c5e2f793b59a 7268 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
screamer 0:c5e2f793b59a 7269 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
screamer 0:c5e2f793b59a 7270 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
screamer 0:c5e2f793b59a 7271 #define FTM2_CONF FTM_CONF_REG(FTM2)
screamer 0:c5e2f793b59a 7272 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
screamer 0:c5e2f793b59a 7273 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
screamer 0:c5e2f793b59a 7274 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
screamer 0:c5e2f793b59a 7275 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
screamer 0:c5e2f793b59a 7276 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
screamer 0:c5e2f793b59a 7277 /* FTM3 */
screamer 0:c5e2f793b59a 7278 #define FTM3_SC FTM_SC_REG(FTM3)
screamer 0:c5e2f793b59a 7279 #define FTM3_CNT FTM_CNT_REG(FTM3)
screamer 0:c5e2f793b59a 7280 #define FTM3_MOD FTM_MOD_REG(FTM3)
screamer 0:c5e2f793b59a 7281 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
screamer 0:c5e2f793b59a 7282 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
screamer 0:c5e2f793b59a 7283 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
screamer 0:c5e2f793b59a 7284 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
screamer 0:c5e2f793b59a 7285 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
screamer 0:c5e2f793b59a 7286 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
screamer 0:c5e2f793b59a 7287 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
screamer 0:c5e2f793b59a 7288 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
screamer 0:c5e2f793b59a 7289 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
screamer 0:c5e2f793b59a 7290 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
screamer 0:c5e2f793b59a 7291 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
screamer 0:c5e2f793b59a 7292 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
screamer 0:c5e2f793b59a 7293 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
screamer 0:c5e2f793b59a 7294 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
screamer 0:c5e2f793b59a 7295 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
screamer 0:c5e2f793b59a 7296 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
screamer 0:c5e2f793b59a 7297 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
screamer 0:c5e2f793b59a 7298 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
screamer 0:c5e2f793b59a 7299 #define FTM3_MODE FTM_MODE_REG(FTM3)
screamer 0:c5e2f793b59a 7300 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
screamer 0:c5e2f793b59a 7301 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
screamer 0:c5e2f793b59a 7302 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
screamer 0:c5e2f793b59a 7303 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
screamer 0:c5e2f793b59a 7304 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
screamer 0:c5e2f793b59a 7305 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
screamer 0:c5e2f793b59a 7306 #define FTM3_POL FTM_POL_REG(FTM3)
screamer 0:c5e2f793b59a 7307 #define FTM3_FMS FTM_FMS_REG(FTM3)
screamer 0:c5e2f793b59a 7308 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
screamer 0:c5e2f793b59a 7309 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
screamer 0:c5e2f793b59a 7310 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
screamer 0:c5e2f793b59a 7311 #define FTM3_CONF FTM_CONF_REG(FTM3)
screamer 0:c5e2f793b59a 7312 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
screamer 0:c5e2f793b59a 7313 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
screamer 0:c5e2f793b59a 7314 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
screamer 0:c5e2f793b59a 7315 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
screamer 0:c5e2f793b59a 7316 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
screamer 0:c5e2f793b59a 7317
screamer 0:c5e2f793b59a 7318 /* FTM - Register array accessors */
screamer 0:c5e2f793b59a 7319 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
screamer 0:c5e2f793b59a 7320 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
screamer 0:c5e2f793b59a 7321 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
screamer 0:c5e2f793b59a 7322 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
screamer 0:c5e2f793b59a 7323 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
screamer 0:c5e2f793b59a 7324 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
screamer 0:c5e2f793b59a 7325 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
screamer 0:c5e2f793b59a 7326 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
screamer 0:c5e2f793b59a 7327
screamer 0:c5e2f793b59a 7328 /*!
screamer 0:c5e2f793b59a 7329 * @}
screamer 0:c5e2f793b59a 7330 */ /* end of group FTM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 7331
screamer 0:c5e2f793b59a 7332
screamer 0:c5e2f793b59a 7333 /*!
screamer 0:c5e2f793b59a 7334 * @}
screamer 0:c5e2f793b59a 7335 */ /* end of group FTM_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 7336
screamer 0:c5e2f793b59a 7337
screamer 0:c5e2f793b59a 7338 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7339 -- GPIO Peripheral Access Layer
screamer 0:c5e2f793b59a 7340 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7341
screamer 0:c5e2f793b59a 7342 /*!
screamer 0:c5e2f793b59a 7343 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
screamer 0:c5e2f793b59a 7344 * @{
screamer 0:c5e2f793b59a 7345 */
screamer 0:c5e2f793b59a 7346
screamer 0:c5e2f793b59a 7347 /** GPIO - Register Layout Typedef */
screamer 0:c5e2f793b59a 7348 typedef struct {
screamer 0:c5e2f793b59a 7349 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
screamer 0:c5e2f793b59a 7350 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
screamer 0:c5e2f793b59a 7351 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
screamer 0:c5e2f793b59a 7352 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
screamer 0:c5e2f793b59a 7353 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
screamer 0:c5e2f793b59a 7354 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
screamer 0:c5e2f793b59a 7355 } GPIO_Type, *GPIO_MemMapPtr;
screamer 0:c5e2f793b59a 7356
screamer 0:c5e2f793b59a 7357 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7358 -- GPIO - Register accessor macros
screamer 0:c5e2f793b59a 7359 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7360
screamer 0:c5e2f793b59a 7361 /*!
screamer 0:c5e2f793b59a 7362 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
screamer 0:c5e2f793b59a 7363 * @{
screamer 0:c5e2f793b59a 7364 */
screamer 0:c5e2f793b59a 7365
screamer 0:c5e2f793b59a 7366
screamer 0:c5e2f793b59a 7367 /* GPIO - Register accessors */
screamer 0:c5e2f793b59a 7368 #define GPIO_PDOR_REG(base) ((base)->PDOR)
screamer 0:c5e2f793b59a 7369 #define GPIO_PSOR_REG(base) ((base)->PSOR)
screamer 0:c5e2f793b59a 7370 #define GPIO_PCOR_REG(base) ((base)->PCOR)
screamer 0:c5e2f793b59a 7371 #define GPIO_PTOR_REG(base) ((base)->PTOR)
screamer 0:c5e2f793b59a 7372 #define GPIO_PDIR_REG(base) ((base)->PDIR)
screamer 0:c5e2f793b59a 7373 #define GPIO_PDDR_REG(base) ((base)->PDDR)
screamer 0:c5e2f793b59a 7374
screamer 0:c5e2f793b59a 7375 /*!
screamer 0:c5e2f793b59a 7376 * @}
screamer 0:c5e2f793b59a 7377 */ /* end of group GPIO_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 7378
screamer 0:c5e2f793b59a 7379
screamer 0:c5e2f793b59a 7380 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7381 -- GPIO Register Masks
screamer 0:c5e2f793b59a 7382 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7383
screamer 0:c5e2f793b59a 7384 /*!
screamer 0:c5e2f793b59a 7385 * @addtogroup GPIO_Register_Masks GPIO Register Masks
screamer 0:c5e2f793b59a 7386 * @{
screamer 0:c5e2f793b59a 7387 */
screamer 0:c5e2f793b59a 7388
screamer 0:c5e2f793b59a 7389 /* PDOR Bit Fields */
screamer 0:c5e2f793b59a 7390 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 7391 #define GPIO_PDOR_PDO_SHIFT 0
screamer 0:c5e2f793b59a 7392 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
screamer 0:c5e2f793b59a 7393 /* PSOR Bit Fields */
screamer 0:c5e2f793b59a 7394 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 7395 #define GPIO_PSOR_PTSO_SHIFT 0
screamer 0:c5e2f793b59a 7396 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
screamer 0:c5e2f793b59a 7397 /* PCOR Bit Fields */
screamer 0:c5e2f793b59a 7398 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 7399 #define GPIO_PCOR_PTCO_SHIFT 0
screamer 0:c5e2f793b59a 7400 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
screamer 0:c5e2f793b59a 7401 /* PTOR Bit Fields */
screamer 0:c5e2f793b59a 7402 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 7403 #define GPIO_PTOR_PTTO_SHIFT 0
screamer 0:c5e2f793b59a 7404 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
screamer 0:c5e2f793b59a 7405 /* PDIR Bit Fields */
screamer 0:c5e2f793b59a 7406 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 7407 #define GPIO_PDIR_PDI_SHIFT 0
screamer 0:c5e2f793b59a 7408 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
screamer 0:c5e2f793b59a 7409 /* PDDR Bit Fields */
screamer 0:c5e2f793b59a 7410 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 7411 #define GPIO_PDDR_PDD_SHIFT 0
screamer 0:c5e2f793b59a 7412 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
screamer 0:c5e2f793b59a 7413
screamer 0:c5e2f793b59a 7414 /*!
screamer 0:c5e2f793b59a 7415 * @}
screamer 0:c5e2f793b59a 7416 */ /* end of group GPIO_Register_Masks */
screamer 0:c5e2f793b59a 7417
screamer 0:c5e2f793b59a 7418
screamer 0:c5e2f793b59a 7419 /* GPIO - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 7420 /** Peripheral PTA base address */
screamer 0:c5e2f793b59a 7421 #define PTA_BASE (0x400FF000u)
screamer 0:c5e2f793b59a 7422 /** Peripheral PTA base pointer */
screamer 0:c5e2f793b59a 7423 #define PTA ((GPIO_Type *)PTA_BASE)
screamer 0:c5e2f793b59a 7424 #define PTA_BASE_PTR (PTA)
screamer 0:c5e2f793b59a 7425 /** Peripheral PTB base address */
screamer 0:c5e2f793b59a 7426 #define PTB_BASE (0x400FF040u)
screamer 0:c5e2f793b59a 7427 /** Peripheral PTB base pointer */
screamer 0:c5e2f793b59a 7428 #define PTB ((GPIO_Type *)PTB_BASE)
screamer 0:c5e2f793b59a 7429 #define PTB_BASE_PTR (PTB)
screamer 0:c5e2f793b59a 7430 /** Peripheral PTC base address */
screamer 0:c5e2f793b59a 7431 #define PTC_BASE (0x400FF080u)
screamer 0:c5e2f793b59a 7432 /** Peripheral PTC base pointer */
screamer 0:c5e2f793b59a 7433 #define PTC ((GPIO_Type *)PTC_BASE)
screamer 0:c5e2f793b59a 7434 #define PTC_BASE_PTR (PTC)
screamer 0:c5e2f793b59a 7435 /** Peripheral PTD base address */
screamer 0:c5e2f793b59a 7436 #define PTD_BASE (0x400FF0C0u)
screamer 0:c5e2f793b59a 7437 /** Peripheral PTD base pointer */
screamer 0:c5e2f793b59a 7438 #define PTD ((GPIO_Type *)PTD_BASE)
screamer 0:c5e2f793b59a 7439 #define PTD_BASE_PTR (PTD)
screamer 0:c5e2f793b59a 7440 /** Peripheral PTE base address */
screamer 0:c5e2f793b59a 7441 #define PTE_BASE (0x400FF100u)
screamer 0:c5e2f793b59a 7442 /** Peripheral PTE base pointer */
screamer 0:c5e2f793b59a 7443 #define PTE ((GPIO_Type *)PTE_BASE)
screamer 0:c5e2f793b59a 7444 #define PTE_BASE_PTR (PTE)
screamer 0:c5e2f793b59a 7445 /** Array initializer of GPIO peripheral base addresses */
screamer 0:c5e2f793b59a 7446 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
screamer 0:c5e2f793b59a 7447 /** Array initializer of GPIO peripheral base pointers */
screamer 0:c5e2f793b59a 7448 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
screamer 0:c5e2f793b59a 7449
screamer 0:c5e2f793b59a 7450 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7451 -- GPIO - Register accessor macros
screamer 0:c5e2f793b59a 7452 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7453
screamer 0:c5e2f793b59a 7454 /*!
screamer 0:c5e2f793b59a 7455 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
screamer 0:c5e2f793b59a 7456 * @{
screamer 0:c5e2f793b59a 7457 */
screamer 0:c5e2f793b59a 7458
screamer 0:c5e2f793b59a 7459
screamer 0:c5e2f793b59a 7460 /* GPIO - Register instance definitions */
screamer 0:c5e2f793b59a 7461 /* PTA */
screamer 0:c5e2f793b59a 7462 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
screamer 0:c5e2f793b59a 7463 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
screamer 0:c5e2f793b59a 7464 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
screamer 0:c5e2f793b59a 7465 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
screamer 0:c5e2f793b59a 7466 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
screamer 0:c5e2f793b59a 7467 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
screamer 0:c5e2f793b59a 7468 /* PTB */
screamer 0:c5e2f793b59a 7469 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
screamer 0:c5e2f793b59a 7470 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
screamer 0:c5e2f793b59a 7471 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
screamer 0:c5e2f793b59a 7472 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
screamer 0:c5e2f793b59a 7473 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
screamer 0:c5e2f793b59a 7474 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
screamer 0:c5e2f793b59a 7475 /* PTC */
screamer 0:c5e2f793b59a 7476 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
screamer 0:c5e2f793b59a 7477 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
screamer 0:c5e2f793b59a 7478 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
screamer 0:c5e2f793b59a 7479 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
screamer 0:c5e2f793b59a 7480 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
screamer 0:c5e2f793b59a 7481 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
screamer 0:c5e2f793b59a 7482 /* PTD */
screamer 0:c5e2f793b59a 7483 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
screamer 0:c5e2f793b59a 7484 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
screamer 0:c5e2f793b59a 7485 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
screamer 0:c5e2f793b59a 7486 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
screamer 0:c5e2f793b59a 7487 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
screamer 0:c5e2f793b59a 7488 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
screamer 0:c5e2f793b59a 7489 /* PTE */
screamer 0:c5e2f793b59a 7490 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
screamer 0:c5e2f793b59a 7491 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
screamer 0:c5e2f793b59a 7492 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
screamer 0:c5e2f793b59a 7493 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
screamer 0:c5e2f793b59a 7494 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
screamer 0:c5e2f793b59a 7495 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
screamer 0:c5e2f793b59a 7496
screamer 0:c5e2f793b59a 7497 /*!
screamer 0:c5e2f793b59a 7498 * @}
screamer 0:c5e2f793b59a 7499 */ /* end of group GPIO_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 7500
screamer 0:c5e2f793b59a 7501
screamer 0:c5e2f793b59a 7502 /*!
screamer 0:c5e2f793b59a 7503 * @}
screamer 0:c5e2f793b59a 7504 */ /* end of group GPIO_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 7505
screamer 0:c5e2f793b59a 7506
screamer 0:c5e2f793b59a 7507 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7508 -- I2C Peripheral Access Layer
screamer 0:c5e2f793b59a 7509 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7510
screamer 0:c5e2f793b59a 7511 /*!
screamer 0:c5e2f793b59a 7512 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
screamer 0:c5e2f793b59a 7513 * @{
screamer 0:c5e2f793b59a 7514 */
screamer 0:c5e2f793b59a 7515
screamer 0:c5e2f793b59a 7516 /** I2C - Register Layout Typedef */
screamer 0:c5e2f793b59a 7517 typedef struct {
screamer 0:c5e2f793b59a 7518 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
screamer 0:c5e2f793b59a 7519 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
screamer 0:c5e2f793b59a 7520 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
screamer 0:c5e2f793b59a 7521 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
screamer 0:c5e2f793b59a 7522 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
screamer 0:c5e2f793b59a 7523 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
screamer 0:c5e2f793b59a 7524 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
screamer 0:c5e2f793b59a 7525 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
screamer 0:c5e2f793b59a 7526 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
screamer 0:c5e2f793b59a 7527 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
screamer 0:c5e2f793b59a 7528 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
screamer 0:c5e2f793b59a 7529 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
screamer 0:c5e2f793b59a 7530 } I2C_Type, *I2C_MemMapPtr;
screamer 0:c5e2f793b59a 7531
screamer 0:c5e2f793b59a 7532 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7533 -- I2C - Register accessor macros
screamer 0:c5e2f793b59a 7534 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7535
screamer 0:c5e2f793b59a 7536 /*!
screamer 0:c5e2f793b59a 7537 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
screamer 0:c5e2f793b59a 7538 * @{
screamer 0:c5e2f793b59a 7539 */
screamer 0:c5e2f793b59a 7540
screamer 0:c5e2f793b59a 7541
screamer 0:c5e2f793b59a 7542 /* I2C - Register accessors */
screamer 0:c5e2f793b59a 7543 #define I2C_A1_REG(base) ((base)->A1)
screamer 0:c5e2f793b59a 7544 #define I2C_F_REG(base) ((base)->F)
screamer 0:c5e2f793b59a 7545 #define I2C_C1_REG(base) ((base)->C1)
screamer 0:c5e2f793b59a 7546 #define I2C_S_REG(base) ((base)->S)
screamer 0:c5e2f793b59a 7547 #define I2C_D_REG(base) ((base)->D)
screamer 0:c5e2f793b59a 7548 #define I2C_C2_REG(base) ((base)->C2)
screamer 0:c5e2f793b59a 7549 #define I2C_FLT_REG(base) ((base)->FLT)
screamer 0:c5e2f793b59a 7550 #define I2C_RA_REG(base) ((base)->RA)
screamer 0:c5e2f793b59a 7551 #define I2C_SMB_REG(base) ((base)->SMB)
screamer 0:c5e2f793b59a 7552 #define I2C_A2_REG(base) ((base)->A2)
screamer 0:c5e2f793b59a 7553 #define I2C_SLTH_REG(base) ((base)->SLTH)
screamer 0:c5e2f793b59a 7554 #define I2C_SLTL_REG(base) ((base)->SLTL)
screamer 0:c5e2f793b59a 7555
screamer 0:c5e2f793b59a 7556 /*!
screamer 0:c5e2f793b59a 7557 * @}
screamer 0:c5e2f793b59a 7558 */ /* end of group I2C_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 7559
screamer 0:c5e2f793b59a 7560
screamer 0:c5e2f793b59a 7561 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7562 -- I2C Register Masks
screamer 0:c5e2f793b59a 7563 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7564
screamer 0:c5e2f793b59a 7565 /*!
screamer 0:c5e2f793b59a 7566 * @addtogroup I2C_Register_Masks I2C Register Masks
screamer 0:c5e2f793b59a 7567 * @{
screamer 0:c5e2f793b59a 7568 */
screamer 0:c5e2f793b59a 7569
screamer 0:c5e2f793b59a 7570 /* A1 Bit Fields */
screamer 0:c5e2f793b59a 7571 #define I2C_A1_AD_MASK 0xFEu
screamer 0:c5e2f793b59a 7572 #define I2C_A1_AD_SHIFT 1
screamer 0:c5e2f793b59a 7573 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
screamer 0:c5e2f793b59a 7574 /* F Bit Fields */
screamer 0:c5e2f793b59a 7575 #define I2C_F_ICR_MASK 0x3Fu
screamer 0:c5e2f793b59a 7576 #define I2C_F_ICR_SHIFT 0
screamer 0:c5e2f793b59a 7577 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
screamer 0:c5e2f793b59a 7578 #define I2C_F_MULT_MASK 0xC0u
screamer 0:c5e2f793b59a 7579 #define I2C_F_MULT_SHIFT 6
screamer 0:c5e2f793b59a 7580 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
screamer 0:c5e2f793b59a 7581 /* C1 Bit Fields */
screamer 0:c5e2f793b59a 7582 #define I2C_C1_DMAEN_MASK 0x1u
screamer 0:c5e2f793b59a 7583 #define I2C_C1_DMAEN_SHIFT 0
screamer 0:c5e2f793b59a 7584 #define I2C_C1_WUEN_MASK 0x2u
screamer 0:c5e2f793b59a 7585 #define I2C_C1_WUEN_SHIFT 1
screamer 0:c5e2f793b59a 7586 #define I2C_C1_RSTA_MASK 0x4u
screamer 0:c5e2f793b59a 7587 #define I2C_C1_RSTA_SHIFT 2
screamer 0:c5e2f793b59a 7588 #define I2C_C1_TXAK_MASK 0x8u
screamer 0:c5e2f793b59a 7589 #define I2C_C1_TXAK_SHIFT 3
screamer 0:c5e2f793b59a 7590 #define I2C_C1_TX_MASK 0x10u
screamer 0:c5e2f793b59a 7591 #define I2C_C1_TX_SHIFT 4
screamer 0:c5e2f793b59a 7592 #define I2C_C1_MST_MASK 0x20u
screamer 0:c5e2f793b59a 7593 #define I2C_C1_MST_SHIFT 5
screamer 0:c5e2f793b59a 7594 #define I2C_C1_IICIE_MASK 0x40u
screamer 0:c5e2f793b59a 7595 #define I2C_C1_IICIE_SHIFT 6
screamer 0:c5e2f793b59a 7596 #define I2C_C1_IICEN_MASK 0x80u
screamer 0:c5e2f793b59a 7597 #define I2C_C1_IICEN_SHIFT 7
screamer 0:c5e2f793b59a 7598 /* S Bit Fields */
screamer 0:c5e2f793b59a 7599 #define I2C_S_RXAK_MASK 0x1u
screamer 0:c5e2f793b59a 7600 #define I2C_S_RXAK_SHIFT 0
screamer 0:c5e2f793b59a 7601 #define I2C_S_IICIF_MASK 0x2u
screamer 0:c5e2f793b59a 7602 #define I2C_S_IICIF_SHIFT 1
screamer 0:c5e2f793b59a 7603 #define I2C_S_SRW_MASK 0x4u
screamer 0:c5e2f793b59a 7604 #define I2C_S_SRW_SHIFT 2
screamer 0:c5e2f793b59a 7605 #define I2C_S_RAM_MASK 0x8u
screamer 0:c5e2f793b59a 7606 #define I2C_S_RAM_SHIFT 3
screamer 0:c5e2f793b59a 7607 #define I2C_S_ARBL_MASK 0x10u
screamer 0:c5e2f793b59a 7608 #define I2C_S_ARBL_SHIFT 4
screamer 0:c5e2f793b59a 7609 #define I2C_S_BUSY_MASK 0x20u
screamer 0:c5e2f793b59a 7610 #define I2C_S_BUSY_SHIFT 5
screamer 0:c5e2f793b59a 7611 #define I2C_S_IAAS_MASK 0x40u
screamer 0:c5e2f793b59a 7612 #define I2C_S_IAAS_SHIFT 6
screamer 0:c5e2f793b59a 7613 #define I2C_S_TCF_MASK 0x80u
screamer 0:c5e2f793b59a 7614 #define I2C_S_TCF_SHIFT 7
screamer 0:c5e2f793b59a 7615 /* D Bit Fields */
screamer 0:c5e2f793b59a 7616 #define I2C_D_DATA_MASK 0xFFu
screamer 0:c5e2f793b59a 7617 #define I2C_D_DATA_SHIFT 0
screamer 0:c5e2f793b59a 7618 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
screamer 0:c5e2f793b59a 7619 /* C2 Bit Fields */
screamer 0:c5e2f793b59a 7620 #define I2C_C2_AD_MASK 0x7u
screamer 0:c5e2f793b59a 7621 #define I2C_C2_AD_SHIFT 0
screamer 0:c5e2f793b59a 7622 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
screamer 0:c5e2f793b59a 7623 #define I2C_C2_RMEN_MASK 0x8u
screamer 0:c5e2f793b59a 7624 #define I2C_C2_RMEN_SHIFT 3
screamer 0:c5e2f793b59a 7625 #define I2C_C2_SBRC_MASK 0x10u
screamer 0:c5e2f793b59a 7626 #define I2C_C2_SBRC_SHIFT 4
screamer 0:c5e2f793b59a 7627 #define I2C_C2_HDRS_MASK 0x20u
screamer 0:c5e2f793b59a 7628 #define I2C_C2_HDRS_SHIFT 5
screamer 0:c5e2f793b59a 7629 #define I2C_C2_ADEXT_MASK 0x40u
screamer 0:c5e2f793b59a 7630 #define I2C_C2_ADEXT_SHIFT 6
screamer 0:c5e2f793b59a 7631 #define I2C_C2_GCAEN_MASK 0x80u
screamer 0:c5e2f793b59a 7632 #define I2C_C2_GCAEN_SHIFT 7
screamer 0:c5e2f793b59a 7633 /* FLT Bit Fields */
screamer 0:c5e2f793b59a 7634 #define I2C_FLT_FLT_MASK 0xFu
screamer 0:c5e2f793b59a 7635 #define I2C_FLT_FLT_SHIFT 0
screamer 0:c5e2f793b59a 7636 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
screamer 0:c5e2f793b59a 7637 #define I2C_FLT_STARTF_MASK 0x10u
screamer 0:c5e2f793b59a 7638 #define I2C_FLT_STARTF_SHIFT 4
screamer 0:c5e2f793b59a 7639 #define I2C_FLT_SSIE_MASK 0x20u
screamer 0:c5e2f793b59a 7640 #define I2C_FLT_SSIE_SHIFT 5
screamer 0:c5e2f793b59a 7641 #define I2C_FLT_STOPF_MASK 0x40u
screamer 0:c5e2f793b59a 7642 #define I2C_FLT_STOPF_SHIFT 6
screamer 0:c5e2f793b59a 7643 #define I2C_FLT_SHEN_MASK 0x80u
screamer 0:c5e2f793b59a 7644 #define I2C_FLT_SHEN_SHIFT 7
screamer 0:c5e2f793b59a 7645 /* RA Bit Fields */
screamer 0:c5e2f793b59a 7646 #define I2C_RA_RAD_MASK 0xFEu
screamer 0:c5e2f793b59a 7647 #define I2C_RA_RAD_SHIFT 1
screamer 0:c5e2f793b59a 7648 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
screamer 0:c5e2f793b59a 7649 /* SMB Bit Fields */
screamer 0:c5e2f793b59a 7650 #define I2C_SMB_SHTF2IE_MASK 0x1u
screamer 0:c5e2f793b59a 7651 #define I2C_SMB_SHTF2IE_SHIFT 0
screamer 0:c5e2f793b59a 7652 #define I2C_SMB_SHTF2_MASK 0x2u
screamer 0:c5e2f793b59a 7653 #define I2C_SMB_SHTF2_SHIFT 1
screamer 0:c5e2f793b59a 7654 #define I2C_SMB_SHTF1_MASK 0x4u
screamer 0:c5e2f793b59a 7655 #define I2C_SMB_SHTF1_SHIFT 2
screamer 0:c5e2f793b59a 7656 #define I2C_SMB_SLTF_MASK 0x8u
screamer 0:c5e2f793b59a 7657 #define I2C_SMB_SLTF_SHIFT 3
screamer 0:c5e2f793b59a 7658 #define I2C_SMB_TCKSEL_MASK 0x10u
screamer 0:c5e2f793b59a 7659 #define I2C_SMB_TCKSEL_SHIFT 4
screamer 0:c5e2f793b59a 7660 #define I2C_SMB_SIICAEN_MASK 0x20u
screamer 0:c5e2f793b59a 7661 #define I2C_SMB_SIICAEN_SHIFT 5
screamer 0:c5e2f793b59a 7662 #define I2C_SMB_ALERTEN_MASK 0x40u
screamer 0:c5e2f793b59a 7663 #define I2C_SMB_ALERTEN_SHIFT 6
screamer 0:c5e2f793b59a 7664 #define I2C_SMB_FACK_MASK 0x80u
screamer 0:c5e2f793b59a 7665 #define I2C_SMB_FACK_SHIFT 7
screamer 0:c5e2f793b59a 7666 /* A2 Bit Fields */
screamer 0:c5e2f793b59a 7667 #define I2C_A2_SAD_MASK 0xFEu
screamer 0:c5e2f793b59a 7668 #define I2C_A2_SAD_SHIFT 1
screamer 0:c5e2f793b59a 7669 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
screamer 0:c5e2f793b59a 7670 /* SLTH Bit Fields */
screamer 0:c5e2f793b59a 7671 #define I2C_SLTH_SSLT_MASK 0xFFu
screamer 0:c5e2f793b59a 7672 #define I2C_SLTH_SSLT_SHIFT 0
screamer 0:c5e2f793b59a 7673 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
screamer 0:c5e2f793b59a 7674 /* SLTL Bit Fields */
screamer 0:c5e2f793b59a 7675 #define I2C_SLTL_SSLT_MASK 0xFFu
screamer 0:c5e2f793b59a 7676 #define I2C_SLTL_SSLT_SHIFT 0
screamer 0:c5e2f793b59a 7677 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
screamer 0:c5e2f793b59a 7678
screamer 0:c5e2f793b59a 7679 /*!
screamer 0:c5e2f793b59a 7680 * @}
screamer 0:c5e2f793b59a 7681 */ /* end of group I2C_Register_Masks */
screamer 0:c5e2f793b59a 7682
screamer 0:c5e2f793b59a 7683
screamer 0:c5e2f793b59a 7684 /* I2C - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 7685 /** Peripheral I2C0 base address */
screamer 0:c5e2f793b59a 7686 #define I2C0_BASE (0x40066000u)
screamer 0:c5e2f793b59a 7687 /** Peripheral I2C0 base pointer */
screamer 0:c5e2f793b59a 7688 #define I2C0 ((I2C_Type *)I2C0_BASE)
screamer 0:c5e2f793b59a 7689 #define I2C0_BASE_PTR (I2C0)
screamer 0:c5e2f793b59a 7690 /** Peripheral I2C1 base address */
screamer 0:c5e2f793b59a 7691 #define I2C1_BASE (0x40067000u)
screamer 0:c5e2f793b59a 7692 /** Peripheral I2C1 base pointer */
screamer 0:c5e2f793b59a 7693 #define I2C1 ((I2C_Type *)I2C1_BASE)
screamer 0:c5e2f793b59a 7694 #define I2C1_BASE_PTR (I2C1)
screamer 0:c5e2f793b59a 7695 /** Peripheral I2C2 base address */
screamer 0:c5e2f793b59a 7696 #define I2C2_BASE (0x400E6000u)
screamer 0:c5e2f793b59a 7697 /** Peripheral I2C2 base pointer */
screamer 0:c5e2f793b59a 7698 #define I2C2 ((I2C_Type *)I2C2_BASE)
screamer 0:c5e2f793b59a 7699 #define I2C2_BASE_PTR (I2C2)
screamer 0:c5e2f793b59a 7700 /** Array initializer of I2C peripheral base addresses */
screamer 0:c5e2f793b59a 7701 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
screamer 0:c5e2f793b59a 7702 /** Array initializer of I2C peripheral base pointers */
screamer 0:c5e2f793b59a 7703 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
screamer 0:c5e2f793b59a 7704 /** Interrupt vectors for the I2C peripheral type */
screamer 0:c5e2f793b59a 7705 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
screamer 0:c5e2f793b59a 7706
screamer 0:c5e2f793b59a 7707 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7708 -- I2C - Register accessor macros
screamer 0:c5e2f793b59a 7709 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7710
screamer 0:c5e2f793b59a 7711 /*!
screamer 0:c5e2f793b59a 7712 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
screamer 0:c5e2f793b59a 7713 * @{
screamer 0:c5e2f793b59a 7714 */
screamer 0:c5e2f793b59a 7715
screamer 0:c5e2f793b59a 7716
screamer 0:c5e2f793b59a 7717 /* I2C - Register instance definitions */
screamer 0:c5e2f793b59a 7718 /* I2C0 */
screamer 0:c5e2f793b59a 7719 #define I2C0_A1 I2C_A1_REG(I2C0)
screamer 0:c5e2f793b59a 7720 #define I2C0_F I2C_F_REG(I2C0)
screamer 0:c5e2f793b59a 7721 #define I2C0_C1 I2C_C1_REG(I2C0)
screamer 0:c5e2f793b59a 7722 #define I2C0_S I2C_S_REG(I2C0)
screamer 0:c5e2f793b59a 7723 #define I2C0_D I2C_D_REG(I2C0)
screamer 0:c5e2f793b59a 7724 #define I2C0_C2 I2C_C2_REG(I2C0)
screamer 0:c5e2f793b59a 7725 #define I2C0_FLT I2C_FLT_REG(I2C0)
screamer 0:c5e2f793b59a 7726 #define I2C0_RA I2C_RA_REG(I2C0)
screamer 0:c5e2f793b59a 7727 #define I2C0_SMB I2C_SMB_REG(I2C0)
screamer 0:c5e2f793b59a 7728 #define I2C0_A2 I2C_A2_REG(I2C0)
screamer 0:c5e2f793b59a 7729 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
screamer 0:c5e2f793b59a 7730 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
screamer 0:c5e2f793b59a 7731 /* I2C1 */
screamer 0:c5e2f793b59a 7732 #define I2C1_A1 I2C_A1_REG(I2C1)
screamer 0:c5e2f793b59a 7733 #define I2C1_F I2C_F_REG(I2C1)
screamer 0:c5e2f793b59a 7734 #define I2C1_C1 I2C_C1_REG(I2C1)
screamer 0:c5e2f793b59a 7735 #define I2C1_S I2C_S_REG(I2C1)
screamer 0:c5e2f793b59a 7736 #define I2C1_D I2C_D_REG(I2C1)
screamer 0:c5e2f793b59a 7737 #define I2C1_C2 I2C_C2_REG(I2C1)
screamer 0:c5e2f793b59a 7738 #define I2C1_FLT I2C_FLT_REG(I2C1)
screamer 0:c5e2f793b59a 7739 #define I2C1_RA I2C_RA_REG(I2C1)
screamer 0:c5e2f793b59a 7740 #define I2C1_SMB I2C_SMB_REG(I2C1)
screamer 0:c5e2f793b59a 7741 #define I2C1_A2 I2C_A2_REG(I2C1)
screamer 0:c5e2f793b59a 7742 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
screamer 0:c5e2f793b59a 7743 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
screamer 0:c5e2f793b59a 7744 /* I2C2 */
screamer 0:c5e2f793b59a 7745 #define I2C2_A1 I2C_A1_REG(I2C2)
screamer 0:c5e2f793b59a 7746 #define I2C2_F I2C_F_REG(I2C2)
screamer 0:c5e2f793b59a 7747 #define I2C2_C1 I2C_C1_REG(I2C2)
screamer 0:c5e2f793b59a 7748 #define I2C2_S I2C_S_REG(I2C2)
screamer 0:c5e2f793b59a 7749 #define I2C2_D I2C_D_REG(I2C2)
screamer 0:c5e2f793b59a 7750 #define I2C2_C2 I2C_C2_REG(I2C2)
screamer 0:c5e2f793b59a 7751 #define I2C2_FLT I2C_FLT_REG(I2C2)
screamer 0:c5e2f793b59a 7752 #define I2C2_RA I2C_RA_REG(I2C2)
screamer 0:c5e2f793b59a 7753 #define I2C2_SMB I2C_SMB_REG(I2C2)
screamer 0:c5e2f793b59a 7754 #define I2C2_A2 I2C_A2_REG(I2C2)
screamer 0:c5e2f793b59a 7755 #define I2C2_SLTH I2C_SLTH_REG(I2C2)
screamer 0:c5e2f793b59a 7756 #define I2C2_SLTL I2C_SLTL_REG(I2C2)
screamer 0:c5e2f793b59a 7757
screamer 0:c5e2f793b59a 7758 /*!
screamer 0:c5e2f793b59a 7759 * @}
screamer 0:c5e2f793b59a 7760 */ /* end of group I2C_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 7761
screamer 0:c5e2f793b59a 7762
screamer 0:c5e2f793b59a 7763 /*!
screamer 0:c5e2f793b59a 7764 * @}
screamer 0:c5e2f793b59a 7765 */ /* end of group I2C_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 7766
screamer 0:c5e2f793b59a 7767
screamer 0:c5e2f793b59a 7768 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7769 -- I2S Peripheral Access Layer
screamer 0:c5e2f793b59a 7770 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7771
screamer 0:c5e2f793b59a 7772 /*!
screamer 0:c5e2f793b59a 7773 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
screamer 0:c5e2f793b59a 7774 * @{
screamer 0:c5e2f793b59a 7775 */
screamer 0:c5e2f793b59a 7776
screamer 0:c5e2f793b59a 7777 /** I2S - Register Layout Typedef */
screamer 0:c5e2f793b59a 7778 typedef struct {
screamer 0:c5e2f793b59a 7779 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
screamer 0:c5e2f793b59a 7780 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
screamer 0:c5e2f793b59a 7781 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
screamer 0:c5e2f793b59a 7782 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
screamer 0:c5e2f793b59a 7783 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
screamer 0:c5e2f793b59a 7784 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
screamer 0:c5e2f793b59a 7785 uint8_t RESERVED_0[8];
screamer 0:c5e2f793b59a 7786 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
screamer 0:c5e2f793b59a 7787 uint8_t RESERVED_1[24];
screamer 0:c5e2f793b59a 7788 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
screamer 0:c5e2f793b59a 7789 uint8_t RESERVED_2[24];
screamer 0:c5e2f793b59a 7790 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
screamer 0:c5e2f793b59a 7791 uint8_t RESERVED_3[28];
screamer 0:c5e2f793b59a 7792 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
screamer 0:c5e2f793b59a 7793 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
screamer 0:c5e2f793b59a 7794 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
screamer 0:c5e2f793b59a 7795 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
screamer 0:c5e2f793b59a 7796 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
screamer 0:c5e2f793b59a 7797 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
screamer 0:c5e2f793b59a 7798 uint8_t RESERVED_4[8];
screamer 0:c5e2f793b59a 7799 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
screamer 0:c5e2f793b59a 7800 uint8_t RESERVED_5[24];
screamer 0:c5e2f793b59a 7801 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
screamer 0:c5e2f793b59a 7802 uint8_t RESERVED_6[24];
screamer 0:c5e2f793b59a 7803 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
screamer 0:c5e2f793b59a 7804 uint8_t RESERVED_7[28];
screamer 0:c5e2f793b59a 7805 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
screamer 0:c5e2f793b59a 7806 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
screamer 0:c5e2f793b59a 7807 } I2S_Type, *I2S_MemMapPtr;
screamer 0:c5e2f793b59a 7808
screamer 0:c5e2f793b59a 7809 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7810 -- I2S - Register accessor macros
screamer 0:c5e2f793b59a 7811 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7812
screamer 0:c5e2f793b59a 7813 /*!
screamer 0:c5e2f793b59a 7814 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
screamer 0:c5e2f793b59a 7815 * @{
screamer 0:c5e2f793b59a 7816 */
screamer 0:c5e2f793b59a 7817
screamer 0:c5e2f793b59a 7818
screamer 0:c5e2f793b59a 7819 /* I2S - Register accessors */
screamer 0:c5e2f793b59a 7820 #define I2S_TCSR_REG(base) ((base)->TCSR)
screamer 0:c5e2f793b59a 7821 #define I2S_TCR1_REG(base) ((base)->TCR1)
screamer 0:c5e2f793b59a 7822 #define I2S_TCR2_REG(base) ((base)->TCR2)
screamer 0:c5e2f793b59a 7823 #define I2S_TCR3_REG(base) ((base)->TCR3)
screamer 0:c5e2f793b59a 7824 #define I2S_TCR4_REG(base) ((base)->TCR4)
screamer 0:c5e2f793b59a 7825 #define I2S_TCR5_REG(base) ((base)->TCR5)
screamer 0:c5e2f793b59a 7826 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
screamer 0:c5e2f793b59a 7827 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
screamer 0:c5e2f793b59a 7828 #define I2S_TMR_REG(base) ((base)->TMR)
screamer 0:c5e2f793b59a 7829 #define I2S_RCSR_REG(base) ((base)->RCSR)
screamer 0:c5e2f793b59a 7830 #define I2S_RCR1_REG(base) ((base)->RCR1)
screamer 0:c5e2f793b59a 7831 #define I2S_RCR2_REG(base) ((base)->RCR2)
screamer 0:c5e2f793b59a 7832 #define I2S_RCR3_REG(base) ((base)->RCR3)
screamer 0:c5e2f793b59a 7833 #define I2S_RCR4_REG(base) ((base)->RCR4)
screamer 0:c5e2f793b59a 7834 #define I2S_RCR5_REG(base) ((base)->RCR5)
screamer 0:c5e2f793b59a 7835 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
screamer 0:c5e2f793b59a 7836 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
screamer 0:c5e2f793b59a 7837 #define I2S_RMR_REG(base) ((base)->RMR)
screamer 0:c5e2f793b59a 7838 #define I2S_MCR_REG(base) ((base)->MCR)
screamer 0:c5e2f793b59a 7839 #define I2S_MDR_REG(base) ((base)->MDR)
screamer 0:c5e2f793b59a 7840
screamer 0:c5e2f793b59a 7841 /*!
screamer 0:c5e2f793b59a 7842 * @}
screamer 0:c5e2f793b59a 7843 */ /* end of group I2S_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 7844
screamer 0:c5e2f793b59a 7845
screamer 0:c5e2f793b59a 7846 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 7847 -- I2S Register Masks
screamer 0:c5e2f793b59a 7848 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 7849
screamer 0:c5e2f793b59a 7850 /*!
screamer 0:c5e2f793b59a 7851 * @addtogroup I2S_Register_Masks I2S Register Masks
screamer 0:c5e2f793b59a 7852 * @{
screamer 0:c5e2f793b59a 7853 */
screamer 0:c5e2f793b59a 7854
screamer 0:c5e2f793b59a 7855 /* TCSR Bit Fields */
screamer 0:c5e2f793b59a 7856 #define I2S_TCSR_FRDE_MASK 0x1u
screamer 0:c5e2f793b59a 7857 #define I2S_TCSR_FRDE_SHIFT 0
screamer 0:c5e2f793b59a 7858 #define I2S_TCSR_FWDE_MASK 0x2u
screamer 0:c5e2f793b59a 7859 #define I2S_TCSR_FWDE_SHIFT 1
screamer 0:c5e2f793b59a 7860 #define I2S_TCSR_FRIE_MASK 0x100u
screamer 0:c5e2f793b59a 7861 #define I2S_TCSR_FRIE_SHIFT 8
screamer 0:c5e2f793b59a 7862 #define I2S_TCSR_FWIE_MASK 0x200u
screamer 0:c5e2f793b59a 7863 #define I2S_TCSR_FWIE_SHIFT 9
screamer 0:c5e2f793b59a 7864 #define I2S_TCSR_FEIE_MASK 0x400u
screamer 0:c5e2f793b59a 7865 #define I2S_TCSR_FEIE_SHIFT 10
screamer 0:c5e2f793b59a 7866 #define I2S_TCSR_SEIE_MASK 0x800u
screamer 0:c5e2f793b59a 7867 #define I2S_TCSR_SEIE_SHIFT 11
screamer 0:c5e2f793b59a 7868 #define I2S_TCSR_WSIE_MASK 0x1000u
screamer 0:c5e2f793b59a 7869 #define I2S_TCSR_WSIE_SHIFT 12
screamer 0:c5e2f793b59a 7870 #define I2S_TCSR_FRF_MASK 0x10000u
screamer 0:c5e2f793b59a 7871 #define I2S_TCSR_FRF_SHIFT 16
screamer 0:c5e2f793b59a 7872 #define I2S_TCSR_FWF_MASK 0x20000u
screamer 0:c5e2f793b59a 7873 #define I2S_TCSR_FWF_SHIFT 17
screamer 0:c5e2f793b59a 7874 #define I2S_TCSR_FEF_MASK 0x40000u
screamer 0:c5e2f793b59a 7875 #define I2S_TCSR_FEF_SHIFT 18
screamer 0:c5e2f793b59a 7876 #define I2S_TCSR_SEF_MASK 0x80000u
screamer 0:c5e2f793b59a 7877 #define I2S_TCSR_SEF_SHIFT 19
screamer 0:c5e2f793b59a 7878 #define I2S_TCSR_WSF_MASK 0x100000u
screamer 0:c5e2f793b59a 7879 #define I2S_TCSR_WSF_SHIFT 20
screamer 0:c5e2f793b59a 7880 #define I2S_TCSR_SR_MASK 0x1000000u
screamer 0:c5e2f793b59a 7881 #define I2S_TCSR_SR_SHIFT 24
screamer 0:c5e2f793b59a 7882 #define I2S_TCSR_FR_MASK 0x2000000u
screamer 0:c5e2f793b59a 7883 #define I2S_TCSR_FR_SHIFT 25
screamer 0:c5e2f793b59a 7884 #define I2S_TCSR_BCE_MASK 0x10000000u
screamer 0:c5e2f793b59a 7885 #define I2S_TCSR_BCE_SHIFT 28
screamer 0:c5e2f793b59a 7886 #define I2S_TCSR_DBGE_MASK 0x20000000u
screamer 0:c5e2f793b59a 7887 #define I2S_TCSR_DBGE_SHIFT 29
screamer 0:c5e2f793b59a 7888 #define I2S_TCSR_STOPE_MASK 0x40000000u
screamer 0:c5e2f793b59a 7889 #define I2S_TCSR_STOPE_SHIFT 30
screamer 0:c5e2f793b59a 7890 #define I2S_TCSR_TE_MASK 0x80000000u
screamer 0:c5e2f793b59a 7891 #define I2S_TCSR_TE_SHIFT 31
screamer 0:c5e2f793b59a 7892 /* TCR1 Bit Fields */
screamer 0:c5e2f793b59a 7893 #define I2S_TCR1_TFW_MASK 0x7u
screamer 0:c5e2f793b59a 7894 #define I2S_TCR1_TFW_SHIFT 0
screamer 0:c5e2f793b59a 7895 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
screamer 0:c5e2f793b59a 7896 /* TCR2 Bit Fields */
screamer 0:c5e2f793b59a 7897 #define I2S_TCR2_DIV_MASK 0xFFu
screamer 0:c5e2f793b59a 7898 #define I2S_TCR2_DIV_SHIFT 0
screamer 0:c5e2f793b59a 7899 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
screamer 0:c5e2f793b59a 7900 #define I2S_TCR2_BCD_MASK 0x1000000u
screamer 0:c5e2f793b59a 7901 #define I2S_TCR2_BCD_SHIFT 24
screamer 0:c5e2f793b59a 7902 #define I2S_TCR2_BCP_MASK 0x2000000u
screamer 0:c5e2f793b59a 7903 #define I2S_TCR2_BCP_SHIFT 25
screamer 0:c5e2f793b59a 7904 #define I2S_TCR2_MSEL_MASK 0xC000000u
screamer 0:c5e2f793b59a 7905 #define I2S_TCR2_MSEL_SHIFT 26
screamer 0:c5e2f793b59a 7906 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
screamer 0:c5e2f793b59a 7907 #define I2S_TCR2_BCI_MASK 0x10000000u
screamer 0:c5e2f793b59a 7908 #define I2S_TCR2_BCI_SHIFT 28
screamer 0:c5e2f793b59a 7909 #define I2S_TCR2_BCS_MASK 0x20000000u
screamer 0:c5e2f793b59a 7910 #define I2S_TCR2_BCS_SHIFT 29
screamer 0:c5e2f793b59a 7911 #define I2S_TCR2_SYNC_MASK 0xC0000000u
screamer 0:c5e2f793b59a 7912 #define I2S_TCR2_SYNC_SHIFT 30
screamer 0:c5e2f793b59a 7913 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
screamer 0:c5e2f793b59a 7914 /* TCR3 Bit Fields */
screamer 0:c5e2f793b59a 7915 #define I2S_TCR3_WDFL_MASK 0x1Fu
screamer 0:c5e2f793b59a 7916 #define I2S_TCR3_WDFL_SHIFT 0
screamer 0:c5e2f793b59a 7917 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
screamer 0:c5e2f793b59a 7918 #define I2S_TCR3_TCE_MASK 0x30000u
screamer 0:c5e2f793b59a 7919 #define I2S_TCR3_TCE_SHIFT 16
screamer 0:c5e2f793b59a 7920 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
screamer 0:c5e2f793b59a 7921 /* TCR4 Bit Fields */
screamer 0:c5e2f793b59a 7922 #define I2S_TCR4_FSD_MASK 0x1u
screamer 0:c5e2f793b59a 7923 #define I2S_TCR4_FSD_SHIFT 0
screamer 0:c5e2f793b59a 7924 #define I2S_TCR4_FSP_MASK 0x2u
screamer 0:c5e2f793b59a 7925 #define I2S_TCR4_FSP_SHIFT 1
screamer 0:c5e2f793b59a 7926 #define I2S_TCR4_FSE_MASK 0x8u
screamer 0:c5e2f793b59a 7927 #define I2S_TCR4_FSE_SHIFT 3
screamer 0:c5e2f793b59a 7928 #define I2S_TCR4_MF_MASK 0x10u
screamer 0:c5e2f793b59a 7929 #define I2S_TCR4_MF_SHIFT 4
screamer 0:c5e2f793b59a 7930 #define I2S_TCR4_SYWD_MASK 0x1F00u
screamer 0:c5e2f793b59a 7931 #define I2S_TCR4_SYWD_SHIFT 8
screamer 0:c5e2f793b59a 7932 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
screamer 0:c5e2f793b59a 7933 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
screamer 0:c5e2f793b59a 7934 #define I2S_TCR4_FRSZ_SHIFT 16
screamer 0:c5e2f793b59a 7935 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
screamer 0:c5e2f793b59a 7936 /* TCR5 Bit Fields */
screamer 0:c5e2f793b59a 7937 #define I2S_TCR5_FBT_MASK 0x1F00u
screamer 0:c5e2f793b59a 7938 #define I2S_TCR5_FBT_SHIFT 8
screamer 0:c5e2f793b59a 7939 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
screamer 0:c5e2f793b59a 7940 #define I2S_TCR5_W0W_MASK 0x1F0000u
screamer 0:c5e2f793b59a 7941 #define I2S_TCR5_W0W_SHIFT 16
screamer 0:c5e2f793b59a 7942 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
screamer 0:c5e2f793b59a 7943 #define I2S_TCR5_WNW_MASK 0x1F000000u
screamer 0:c5e2f793b59a 7944 #define I2S_TCR5_WNW_SHIFT 24
screamer 0:c5e2f793b59a 7945 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
screamer 0:c5e2f793b59a 7946 /* TDR Bit Fields */
screamer 0:c5e2f793b59a 7947 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 7948 #define I2S_TDR_TDR_SHIFT 0
screamer 0:c5e2f793b59a 7949 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
screamer 0:c5e2f793b59a 7950 /* TFR Bit Fields */
screamer 0:c5e2f793b59a 7951 #define I2S_TFR_RFP_MASK 0xFu
screamer 0:c5e2f793b59a 7952 #define I2S_TFR_RFP_SHIFT 0
screamer 0:c5e2f793b59a 7953 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
screamer 0:c5e2f793b59a 7954 #define I2S_TFR_WFP_MASK 0xF0000u
screamer 0:c5e2f793b59a 7955 #define I2S_TFR_WFP_SHIFT 16
screamer 0:c5e2f793b59a 7956 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
screamer 0:c5e2f793b59a 7957 /* TMR Bit Fields */
screamer 0:c5e2f793b59a 7958 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 7959 #define I2S_TMR_TWM_SHIFT 0
screamer 0:c5e2f793b59a 7960 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
screamer 0:c5e2f793b59a 7961 /* RCSR Bit Fields */
screamer 0:c5e2f793b59a 7962 #define I2S_RCSR_FRDE_MASK 0x1u
screamer 0:c5e2f793b59a 7963 #define I2S_RCSR_FRDE_SHIFT 0
screamer 0:c5e2f793b59a 7964 #define I2S_RCSR_FWDE_MASK 0x2u
screamer 0:c5e2f793b59a 7965 #define I2S_RCSR_FWDE_SHIFT 1
screamer 0:c5e2f793b59a 7966 #define I2S_RCSR_FRIE_MASK 0x100u
screamer 0:c5e2f793b59a 7967 #define I2S_RCSR_FRIE_SHIFT 8
screamer 0:c5e2f793b59a 7968 #define I2S_RCSR_FWIE_MASK 0x200u
screamer 0:c5e2f793b59a 7969 #define I2S_RCSR_FWIE_SHIFT 9
screamer 0:c5e2f793b59a 7970 #define I2S_RCSR_FEIE_MASK 0x400u
screamer 0:c5e2f793b59a 7971 #define I2S_RCSR_FEIE_SHIFT 10
screamer 0:c5e2f793b59a 7972 #define I2S_RCSR_SEIE_MASK 0x800u
screamer 0:c5e2f793b59a 7973 #define I2S_RCSR_SEIE_SHIFT 11
screamer 0:c5e2f793b59a 7974 #define I2S_RCSR_WSIE_MASK 0x1000u
screamer 0:c5e2f793b59a 7975 #define I2S_RCSR_WSIE_SHIFT 12
screamer 0:c5e2f793b59a 7976 #define I2S_RCSR_FRF_MASK 0x10000u
screamer 0:c5e2f793b59a 7977 #define I2S_RCSR_FRF_SHIFT 16
screamer 0:c5e2f793b59a 7978 #define I2S_RCSR_FWF_MASK 0x20000u
screamer 0:c5e2f793b59a 7979 #define I2S_RCSR_FWF_SHIFT 17
screamer 0:c5e2f793b59a 7980 #define I2S_RCSR_FEF_MASK 0x40000u
screamer 0:c5e2f793b59a 7981 #define I2S_RCSR_FEF_SHIFT 18
screamer 0:c5e2f793b59a 7982 #define I2S_RCSR_SEF_MASK 0x80000u
screamer 0:c5e2f793b59a 7983 #define I2S_RCSR_SEF_SHIFT 19
screamer 0:c5e2f793b59a 7984 #define I2S_RCSR_WSF_MASK 0x100000u
screamer 0:c5e2f793b59a 7985 #define I2S_RCSR_WSF_SHIFT 20
screamer 0:c5e2f793b59a 7986 #define I2S_RCSR_SR_MASK 0x1000000u
screamer 0:c5e2f793b59a 7987 #define I2S_RCSR_SR_SHIFT 24
screamer 0:c5e2f793b59a 7988 #define I2S_RCSR_FR_MASK 0x2000000u
screamer 0:c5e2f793b59a 7989 #define I2S_RCSR_FR_SHIFT 25
screamer 0:c5e2f793b59a 7990 #define I2S_RCSR_BCE_MASK 0x10000000u
screamer 0:c5e2f793b59a 7991 #define I2S_RCSR_BCE_SHIFT 28
screamer 0:c5e2f793b59a 7992 #define I2S_RCSR_DBGE_MASK 0x20000000u
screamer 0:c5e2f793b59a 7993 #define I2S_RCSR_DBGE_SHIFT 29
screamer 0:c5e2f793b59a 7994 #define I2S_RCSR_STOPE_MASK 0x40000000u
screamer 0:c5e2f793b59a 7995 #define I2S_RCSR_STOPE_SHIFT 30
screamer 0:c5e2f793b59a 7996 #define I2S_RCSR_RE_MASK 0x80000000u
screamer 0:c5e2f793b59a 7997 #define I2S_RCSR_RE_SHIFT 31
screamer 0:c5e2f793b59a 7998 /* RCR1 Bit Fields */
screamer 0:c5e2f793b59a 7999 #define I2S_RCR1_RFW_MASK 0x7u
screamer 0:c5e2f793b59a 8000 #define I2S_RCR1_RFW_SHIFT 0
screamer 0:c5e2f793b59a 8001 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
screamer 0:c5e2f793b59a 8002 /* RCR2 Bit Fields */
screamer 0:c5e2f793b59a 8003 #define I2S_RCR2_DIV_MASK 0xFFu
screamer 0:c5e2f793b59a 8004 #define I2S_RCR2_DIV_SHIFT 0
screamer 0:c5e2f793b59a 8005 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
screamer 0:c5e2f793b59a 8006 #define I2S_RCR2_BCD_MASK 0x1000000u
screamer 0:c5e2f793b59a 8007 #define I2S_RCR2_BCD_SHIFT 24
screamer 0:c5e2f793b59a 8008 #define I2S_RCR2_BCP_MASK 0x2000000u
screamer 0:c5e2f793b59a 8009 #define I2S_RCR2_BCP_SHIFT 25
screamer 0:c5e2f793b59a 8010 #define I2S_RCR2_MSEL_MASK 0xC000000u
screamer 0:c5e2f793b59a 8011 #define I2S_RCR2_MSEL_SHIFT 26
screamer 0:c5e2f793b59a 8012 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
screamer 0:c5e2f793b59a 8013 #define I2S_RCR2_BCI_MASK 0x10000000u
screamer 0:c5e2f793b59a 8014 #define I2S_RCR2_BCI_SHIFT 28
screamer 0:c5e2f793b59a 8015 #define I2S_RCR2_BCS_MASK 0x20000000u
screamer 0:c5e2f793b59a 8016 #define I2S_RCR2_BCS_SHIFT 29
screamer 0:c5e2f793b59a 8017 #define I2S_RCR2_SYNC_MASK 0xC0000000u
screamer 0:c5e2f793b59a 8018 #define I2S_RCR2_SYNC_SHIFT 30
screamer 0:c5e2f793b59a 8019 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
screamer 0:c5e2f793b59a 8020 /* RCR3 Bit Fields */
screamer 0:c5e2f793b59a 8021 #define I2S_RCR3_WDFL_MASK 0x1Fu
screamer 0:c5e2f793b59a 8022 #define I2S_RCR3_WDFL_SHIFT 0
screamer 0:c5e2f793b59a 8023 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
screamer 0:c5e2f793b59a 8024 #define I2S_RCR3_RCE_MASK 0x30000u
screamer 0:c5e2f793b59a 8025 #define I2S_RCR3_RCE_SHIFT 16
screamer 0:c5e2f793b59a 8026 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
screamer 0:c5e2f793b59a 8027 /* RCR4 Bit Fields */
screamer 0:c5e2f793b59a 8028 #define I2S_RCR4_FSD_MASK 0x1u
screamer 0:c5e2f793b59a 8029 #define I2S_RCR4_FSD_SHIFT 0
screamer 0:c5e2f793b59a 8030 #define I2S_RCR4_FSP_MASK 0x2u
screamer 0:c5e2f793b59a 8031 #define I2S_RCR4_FSP_SHIFT 1
screamer 0:c5e2f793b59a 8032 #define I2S_RCR4_FSE_MASK 0x8u
screamer 0:c5e2f793b59a 8033 #define I2S_RCR4_FSE_SHIFT 3
screamer 0:c5e2f793b59a 8034 #define I2S_RCR4_MF_MASK 0x10u
screamer 0:c5e2f793b59a 8035 #define I2S_RCR4_MF_SHIFT 4
screamer 0:c5e2f793b59a 8036 #define I2S_RCR4_SYWD_MASK 0x1F00u
screamer 0:c5e2f793b59a 8037 #define I2S_RCR4_SYWD_SHIFT 8
screamer 0:c5e2f793b59a 8038 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
screamer 0:c5e2f793b59a 8039 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
screamer 0:c5e2f793b59a 8040 #define I2S_RCR4_FRSZ_SHIFT 16
screamer 0:c5e2f793b59a 8041 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
screamer 0:c5e2f793b59a 8042 /* RCR5 Bit Fields */
screamer 0:c5e2f793b59a 8043 #define I2S_RCR5_FBT_MASK 0x1F00u
screamer 0:c5e2f793b59a 8044 #define I2S_RCR5_FBT_SHIFT 8
screamer 0:c5e2f793b59a 8045 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
screamer 0:c5e2f793b59a 8046 #define I2S_RCR5_W0W_MASK 0x1F0000u
screamer 0:c5e2f793b59a 8047 #define I2S_RCR5_W0W_SHIFT 16
screamer 0:c5e2f793b59a 8048 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
screamer 0:c5e2f793b59a 8049 #define I2S_RCR5_WNW_MASK 0x1F000000u
screamer 0:c5e2f793b59a 8050 #define I2S_RCR5_WNW_SHIFT 24
screamer 0:c5e2f793b59a 8051 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
screamer 0:c5e2f793b59a 8052 /* RDR Bit Fields */
screamer 0:c5e2f793b59a 8053 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 8054 #define I2S_RDR_RDR_SHIFT 0
screamer 0:c5e2f793b59a 8055 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
screamer 0:c5e2f793b59a 8056 /* RFR Bit Fields */
screamer 0:c5e2f793b59a 8057 #define I2S_RFR_RFP_MASK 0xFu
screamer 0:c5e2f793b59a 8058 #define I2S_RFR_RFP_SHIFT 0
screamer 0:c5e2f793b59a 8059 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
screamer 0:c5e2f793b59a 8060 #define I2S_RFR_WFP_MASK 0xF0000u
screamer 0:c5e2f793b59a 8061 #define I2S_RFR_WFP_SHIFT 16
screamer 0:c5e2f793b59a 8062 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
screamer 0:c5e2f793b59a 8063 /* RMR Bit Fields */
screamer 0:c5e2f793b59a 8064 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 8065 #define I2S_RMR_RWM_SHIFT 0
screamer 0:c5e2f793b59a 8066 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
screamer 0:c5e2f793b59a 8067 /* MCR Bit Fields */
screamer 0:c5e2f793b59a 8068 #define I2S_MCR_MICS_MASK 0x3000000u
screamer 0:c5e2f793b59a 8069 #define I2S_MCR_MICS_SHIFT 24
screamer 0:c5e2f793b59a 8070 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
screamer 0:c5e2f793b59a 8071 #define I2S_MCR_MOE_MASK 0x40000000u
screamer 0:c5e2f793b59a 8072 #define I2S_MCR_MOE_SHIFT 30
screamer 0:c5e2f793b59a 8073 #define I2S_MCR_DUF_MASK 0x80000000u
screamer 0:c5e2f793b59a 8074 #define I2S_MCR_DUF_SHIFT 31
screamer 0:c5e2f793b59a 8075 /* MDR Bit Fields */
screamer 0:c5e2f793b59a 8076 #define I2S_MDR_DIVIDE_MASK 0xFFFu
screamer 0:c5e2f793b59a 8077 #define I2S_MDR_DIVIDE_SHIFT 0
screamer 0:c5e2f793b59a 8078 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
screamer 0:c5e2f793b59a 8079 #define I2S_MDR_FRACT_MASK 0xFF000u
screamer 0:c5e2f793b59a 8080 #define I2S_MDR_FRACT_SHIFT 12
screamer 0:c5e2f793b59a 8081 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
screamer 0:c5e2f793b59a 8082
screamer 0:c5e2f793b59a 8083 /*!
screamer 0:c5e2f793b59a 8084 * @}
screamer 0:c5e2f793b59a 8085 */ /* end of group I2S_Register_Masks */
screamer 0:c5e2f793b59a 8086
screamer 0:c5e2f793b59a 8087
screamer 0:c5e2f793b59a 8088 /* I2S - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 8089 /** Peripheral I2S0 base address */
screamer 0:c5e2f793b59a 8090 #define I2S0_BASE (0x4002F000u)
screamer 0:c5e2f793b59a 8091 /** Peripheral I2S0 base pointer */
screamer 0:c5e2f793b59a 8092 #define I2S0 ((I2S_Type *)I2S0_BASE)
screamer 0:c5e2f793b59a 8093 #define I2S0_BASE_PTR (I2S0)
screamer 0:c5e2f793b59a 8094 /** Array initializer of I2S peripheral base addresses */
screamer 0:c5e2f793b59a 8095 #define I2S_BASE_ADDRS { I2S0_BASE }
screamer 0:c5e2f793b59a 8096 /** Array initializer of I2S peripheral base pointers */
screamer 0:c5e2f793b59a 8097 #define I2S_BASE_PTRS { I2S0 }
screamer 0:c5e2f793b59a 8098 /** Interrupt vectors for the I2S peripheral type */
screamer 0:c5e2f793b59a 8099 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
screamer 0:c5e2f793b59a 8100 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
screamer 0:c5e2f793b59a 8101
screamer 0:c5e2f793b59a 8102 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8103 -- I2S - Register accessor macros
screamer 0:c5e2f793b59a 8104 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8105
screamer 0:c5e2f793b59a 8106 /*!
screamer 0:c5e2f793b59a 8107 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
screamer 0:c5e2f793b59a 8108 * @{
screamer 0:c5e2f793b59a 8109 */
screamer 0:c5e2f793b59a 8110
screamer 0:c5e2f793b59a 8111
screamer 0:c5e2f793b59a 8112 /* I2S - Register instance definitions */
screamer 0:c5e2f793b59a 8113 /* I2S0 */
screamer 0:c5e2f793b59a 8114 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
screamer 0:c5e2f793b59a 8115 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
screamer 0:c5e2f793b59a 8116 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
screamer 0:c5e2f793b59a 8117 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
screamer 0:c5e2f793b59a 8118 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
screamer 0:c5e2f793b59a 8119 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
screamer 0:c5e2f793b59a 8120 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
screamer 0:c5e2f793b59a 8121 #define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
screamer 0:c5e2f793b59a 8122 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
screamer 0:c5e2f793b59a 8123 #define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
screamer 0:c5e2f793b59a 8124 #define I2S0_TMR I2S_TMR_REG(I2S0)
screamer 0:c5e2f793b59a 8125 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
screamer 0:c5e2f793b59a 8126 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
screamer 0:c5e2f793b59a 8127 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
screamer 0:c5e2f793b59a 8128 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
screamer 0:c5e2f793b59a 8129 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
screamer 0:c5e2f793b59a 8130 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
screamer 0:c5e2f793b59a 8131 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
screamer 0:c5e2f793b59a 8132 #define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
screamer 0:c5e2f793b59a 8133 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
screamer 0:c5e2f793b59a 8134 #define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
screamer 0:c5e2f793b59a 8135 #define I2S0_RMR I2S_RMR_REG(I2S0)
screamer 0:c5e2f793b59a 8136 #define I2S0_MCR I2S_MCR_REG(I2S0)
screamer 0:c5e2f793b59a 8137 #define I2S0_MDR I2S_MDR_REG(I2S0)
screamer 0:c5e2f793b59a 8138
screamer 0:c5e2f793b59a 8139 /* I2S - Register array accessors */
screamer 0:c5e2f793b59a 8140 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
screamer 0:c5e2f793b59a 8141 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
screamer 0:c5e2f793b59a 8142 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
screamer 0:c5e2f793b59a 8143 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
screamer 0:c5e2f793b59a 8144
screamer 0:c5e2f793b59a 8145 /*!
screamer 0:c5e2f793b59a 8146 * @}
screamer 0:c5e2f793b59a 8147 */ /* end of group I2S_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8148
screamer 0:c5e2f793b59a 8149
screamer 0:c5e2f793b59a 8150 /*!
screamer 0:c5e2f793b59a 8151 * @}
screamer 0:c5e2f793b59a 8152 */ /* end of group I2S_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 8153
screamer 0:c5e2f793b59a 8154
screamer 0:c5e2f793b59a 8155 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8156 -- LLWU Peripheral Access Layer
screamer 0:c5e2f793b59a 8157 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8158
screamer 0:c5e2f793b59a 8159 /*!
screamer 0:c5e2f793b59a 8160 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
screamer 0:c5e2f793b59a 8161 * @{
screamer 0:c5e2f793b59a 8162 */
screamer 0:c5e2f793b59a 8163
screamer 0:c5e2f793b59a 8164 /** LLWU - Register Layout Typedef */
screamer 0:c5e2f793b59a 8165 typedef struct {
screamer 0:c5e2f793b59a 8166 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
screamer 0:c5e2f793b59a 8167 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
screamer 0:c5e2f793b59a 8168 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
screamer 0:c5e2f793b59a 8169 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
screamer 0:c5e2f793b59a 8170 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
screamer 0:c5e2f793b59a 8171 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
screamer 0:c5e2f793b59a 8172 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
screamer 0:c5e2f793b59a 8173 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
screamer 0:c5e2f793b59a 8174 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
screamer 0:c5e2f793b59a 8175 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
screamer 0:c5e2f793b59a 8176 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
screamer 0:c5e2f793b59a 8177 } LLWU_Type, *LLWU_MemMapPtr;
screamer 0:c5e2f793b59a 8178
screamer 0:c5e2f793b59a 8179 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8180 -- LLWU - Register accessor macros
screamer 0:c5e2f793b59a 8181 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8182
screamer 0:c5e2f793b59a 8183 /*!
screamer 0:c5e2f793b59a 8184 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
screamer 0:c5e2f793b59a 8185 * @{
screamer 0:c5e2f793b59a 8186 */
screamer 0:c5e2f793b59a 8187
screamer 0:c5e2f793b59a 8188
screamer 0:c5e2f793b59a 8189 /* LLWU - Register accessors */
screamer 0:c5e2f793b59a 8190 #define LLWU_PE1_REG(base) ((base)->PE1)
screamer 0:c5e2f793b59a 8191 #define LLWU_PE2_REG(base) ((base)->PE2)
screamer 0:c5e2f793b59a 8192 #define LLWU_PE3_REG(base) ((base)->PE3)
screamer 0:c5e2f793b59a 8193 #define LLWU_PE4_REG(base) ((base)->PE4)
screamer 0:c5e2f793b59a 8194 #define LLWU_ME_REG(base) ((base)->ME)
screamer 0:c5e2f793b59a 8195 #define LLWU_F1_REG(base) ((base)->F1)
screamer 0:c5e2f793b59a 8196 #define LLWU_F2_REG(base) ((base)->F2)
screamer 0:c5e2f793b59a 8197 #define LLWU_F3_REG(base) ((base)->F3)
screamer 0:c5e2f793b59a 8198 #define LLWU_FILT1_REG(base) ((base)->FILT1)
screamer 0:c5e2f793b59a 8199 #define LLWU_FILT2_REG(base) ((base)->FILT2)
screamer 0:c5e2f793b59a 8200 #define LLWU_RST_REG(base) ((base)->RST)
screamer 0:c5e2f793b59a 8201
screamer 0:c5e2f793b59a 8202 /*!
screamer 0:c5e2f793b59a 8203 * @}
screamer 0:c5e2f793b59a 8204 */ /* end of group LLWU_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8205
screamer 0:c5e2f793b59a 8206
screamer 0:c5e2f793b59a 8207 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8208 -- LLWU Register Masks
screamer 0:c5e2f793b59a 8209 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8210
screamer 0:c5e2f793b59a 8211 /*!
screamer 0:c5e2f793b59a 8212 * @addtogroup LLWU_Register_Masks LLWU Register Masks
screamer 0:c5e2f793b59a 8213 * @{
screamer 0:c5e2f793b59a 8214 */
screamer 0:c5e2f793b59a 8215
screamer 0:c5e2f793b59a 8216 /* PE1 Bit Fields */
screamer 0:c5e2f793b59a 8217 #define LLWU_PE1_WUPE0_MASK 0x3u
screamer 0:c5e2f793b59a 8218 #define LLWU_PE1_WUPE0_SHIFT 0
screamer 0:c5e2f793b59a 8219 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
screamer 0:c5e2f793b59a 8220 #define LLWU_PE1_WUPE1_MASK 0xCu
screamer 0:c5e2f793b59a 8221 #define LLWU_PE1_WUPE1_SHIFT 2
screamer 0:c5e2f793b59a 8222 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
screamer 0:c5e2f793b59a 8223 #define LLWU_PE1_WUPE2_MASK 0x30u
screamer 0:c5e2f793b59a 8224 #define LLWU_PE1_WUPE2_SHIFT 4
screamer 0:c5e2f793b59a 8225 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
screamer 0:c5e2f793b59a 8226 #define LLWU_PE1_WUPE3_MASK 0xC0u
screamer 0:c5e2f793b59a 8227 #define LLWU_PE1_WUPE3_SHIFT 6
screamer 0:c5e2f793b59a 8228 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
screamer 0:c5e2f793b59a 8229 /* PE2 Bit Fields */
screamer 0:c5e2f793b59a 8230 #define LLWU_PE2_WUPE4_MASK 0x3u
screamer 0:c5e2f793b59a 8231 #define LLWU_PE2_WUPE4_SHIFT 0
screamer 0:c5e2f793b59a 8232 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
screamer 0:c5e2f793b59a 8233 #define LLWU_PE2_WUPE5_MASK 0xCu
screamer 0:c5e2f793b59a 8234 #define LLWU_PE2_WUPE5_SHIFT 2
screamer 0:c5e2f793b59a 8235 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
screamer 0:c5e2f793b59a 8236 #define LLWU_PE2_WUPE6_MASK 0x30u
screamer 0:c5e2f793b59a 8237 #define LLWU_PE2_WUPE6_SHIFT 4
screamer 0:c5e2f793b59a 8238 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
screamer 0:c5e2f793b59a 8239 #define LLWU_PE2_WUPE7_MASK 0xC0u
screamer 0:c5e2f793b59a 8240 #define LLWU_PE2_WUPE7_SHIFT 6
screamer 0:c5e2f793b59a 8241 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
screamer 0:c5e2f793b59a 8242 /* PE3 Bit Fields */
screamer 0:c5e2f793b59a 8243 #define LLWU_PE3_WUPE8_MASK 0x3u
screamer 0:c5e2f793b59a 8244 #define LLWU_PE3_WUPE8_SHIFT 0
screamer 0:c5e2f793b59a 8245 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
screamer 0:c5e2f793b59a 8246 #define LLWU_PE3_WUPE9_MASK 0xCu
screamer 0:c5e2f793b59a 8247 #define LLWU_PE3_WUPE9_SHIFT 2
screamer 0:c5e2f793b59a 8248 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
screamer 0:c5e2f793b59a 8249 #define LLWU_PE3_WUPE10_MASK 0x30u
screamer 0:c5e2f793b59a 8250 #define LLWU_PE3_WUPE10_SHIFT 4
screamer 0:c5e2f793b59a 8251 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
screamer 0:c5e2f793b59a 8252 #define LLWU_PE3_WUPE11_MASK 0xC0u
screamer 0:c5e2f793b59a 8253 #define LLWU_PE3_WUPE11_SHIFT 6
screamer 0:c5e2f793b59a 8254 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
screamer 0:c5e2f793b59a 8255 /* PE4 Bit Fields */
screamer 0:c5e2f793b59a 8256 #define LLWU_PE4_WUPE12_MASK 0x3u
screamer 0:c5e2f793b59a 8257 #define LLWU_PE4_WUPE12_SHIFT 0
screamer 0:c5e2f793b59a 8258 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
screamer 0:c5e2f793b59a 8259 #define LLWU_PE4_WUPE13_MASK 0xCu
screamer 0:c5e2f793b59a 8260 #define LLWU_PE4_WUPE13_SHIFT 2
screamer 0:c5e2f793b59a 8261 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
screamer 0:c5e2f793b59a 8262 #define LLWU_PE4_WUPE14_MASK 0x30u
screamer 0:c5e2f793b59a 8263 #define LLWU_PE4_WUPE14_SHIFT 4
screamer 0:c5e2f793b59a 8264 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
screamer 0:c5e2f793b59a 8265 #define LLWU_PE4_WUPE15_MASK 0xC0u
screamer 0:c5e2f793b59a 8266 #define LLWU_PE4_WUPE15_SHIFT 6
screamer 0:c5e2f793b59a 8267 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
screamer 0:c5e2f793b59a 8268 /* ME Bit Fields */
screamer 0:c5e2f793b59a 8269 #define LLWU_ME_WUME0_MASK 0x1u
screamer 0:c5e2f793b59a 8270 #define LLWU_ME_WUME0_SHIFT 0
screamer 0:c5e2f793b59a 8271 #define LLWU_ME_WUME1_MASK 0x2u
screamer 0:c5e2f793b59a 8272 #define LLWU_ME_WUME1_SHIFT 1
screamer 0:c5e2f793b59a 8273 #define LLWU_ME_WUME2_MASK 0x4u
screamer 0:c5e2f793b59a 8274 #define LLWU_ME_WUME2_SHIFT 2
screamer 0:c5e2f793b59a 8275 #define LLWU_ME_WUME3_MASK 0x8u
screamer 0:c5e2f793b59a 8276 #define LLWU_ME_WUME3_SHIFT 3
screamer 0:c5e2f793b59a 8277 #define LLWU_ME_WUME4_MASK 0x10u
screamer 0:c5e2f793b59a 8278 #define LLWU_ME_WUME4_SHIFT 4
screamer 0:c5e2f793b59a 8279 #define LLWU_ME_WUME5_MASK 0x20u
screamer 0:c5e2f793b59a 8280 #define LLWU_ME_WUME5_SHIFT 5
screamer 0:c5e2f793b59a 8281 #define LLWU_ME_WUME6_MASK 0x40u
screamer 0:c5e2f793b59a 8282 #define LLWU_ME_WUME6_SHIFT 6
screamer 0:c5e2f793b59a 8283 #define LLWU_ME_WUME7_MASK 0x80u
screamer 0:c5e2f793b59a 8284 #define LLWU_ME_WUME7_SHIFT 7
screamer 0:c5e2f793b59a 8285 /* F1 Bit Fields */
screamer 0:c5e2f793b59a 8286 #define LLWU_F1_WUF0_MASK 0x1u
screamer 0:c5e2f793b59a 8287 #define LLWU_F1_WUF0_SHIFT 0
screamer 0:c5e2f793b59a 8288 #define LLWU_F1_WUF1_MASK 0x2u
screamer 0:c5e2f793b59a 8289 #define LLWU_F1_WUF1_SHIFT 1
screamer 0:c5e2f793b59a 8290 #define LLWU_F1_WUF2_MASK 0x4u
screamer 0:c5e2f793b59a 8291 #define LLWU_F1_WUF2_SHIFT 2
screamer 0:c5e2f793b59a 8292 #define LLWU_F1_WUF3_MASK 0x8u
screamer 0:c5e2f793b59a 8293 #define LLWU_F1_WUF3_SHIFT 3
screamer 0:c5e2f793b59a 8294 #define LLWU_F1_WUF4_MASK 0x10u
screamer 0:c5e2f793b59a 8295 #define LLWU_F1_WUF4_SHIFT 4
screamer 0:c5e2f793b59a 8296 #define LLWU_F1_WUF5_MASK 0x20u
screamer 0:c5e2f793b59a 8297 #define LLWU_F1_WUF5_SHIFT 5
screamer 0:c5e2f793b59a 8298 #define LLWU_F1_WUF6_MASK 0x40u
screamer 0:c5e2f793b59a 8299 #define LLWU_F1_WUF6_SHIFT 6
screamer 0:c5e2f793b59a 8300 #define LLWU_F1_WUF7_MASK 0x80u
screamer 0:c5e2f793b59a 8301 #define LLWU_F1_WUF7_SHIFT 7
screamer 0:c5e2f793b59a 8302 /* F2 Bit Fields */
screamer 0:c5e2f793b59a 8303 #define LLWU_F2_WUF8_MASK 0x1u
screamer 0:c5e2f793b59a 8304 #define LLWU_F2_WUF8_SHIFT 0
screamer 0:c5e2f793b59a 8305 #define LLWU_F2_WUF9_MASK 0x2u
screamer 0:c5e2f793b59a 8306 #define LLWU_F2_WUF9_SHIFT 1
screamer 0:c5e2f793b59a 8307 #define LLWU_F2_WUF10_MASK 0x4u
screamer 0:c5e2f793b59a 8308 #define LLWU_F2_WUF10_SHIFT 2
screamer 0:c5e2f793b59a 8309 #define LLWU_F2_WUF11_MASK 0x8u
screamer 0:c5e2f793b59a 8310 #define LLWU_F2_WUF11_SHIFT 3
screamer 0:c5e2f793b59a 8311 #define LLWU_F2_WUF12_MASK 0x10u
screamer 0:c5e2f793b59a 8312 #define LLWU_F2_WUF12_SHIFT 4
screamer 0:c5e2f793b59a 8313 #define LLWU_F2_WUF13_MASK 0x20u
screamer 0:c5e2f793b59a 8314 #define LLWU_F2_WUF13_SHIFT 5
screamer 0:c5e2f793b59a 8315 #define LLWU_F2_WUF14_MASK 0x40u
screamer 0:c5e2f793b59a 8316 #define LLWU_F2_WUF14_SHIFT 6
screamer 0:c5e2f793b59a 8317 #define LLWU_F2_WUF15_MASK 0x80u
screamer 0:c5e2f793b59a 8318 #define LLWU_F2_WUF15_SHIFT 7
screamer 0:c5e2f793b59a 8319 /* F3 Bit Fields */
screamer 0:c5e2f793b59a 8320 #define LLWU_F3_MWUF0_MASK 0x1u
screamer 0:c5e2f793b59a 8321 #define LLWU_F3_MWUF0_SHIFT 0
screamer 0:c5e2f793b59a 8322 #define LLWU_F3_MWUF1_MASK 0x2u
screamer 0:c5e2f793b59a 8323 #define LLWU_F3_MWUF1_SHIFT 1
screamer 0:c5e2f793b59a 8324 #define LLWU_F3_MWUF2_MASK 0x4u
screamer 0:c5e2f793b59a 8325 #define LLWU_F3_MWUF2_SHIFT 2
screamer 0:c5e2f793b59a 8326 #define LLWU_F3_MWUF3_MASK 0x8u
screamer 0:c5e2f793b59a 8327 #define LLWU_F3_MWUF3_SHIFT 3
screamer 0:c5e2f793b59a 8328 #define LLWU_F3_MWUF4_MASK 0x10u
screamer 0:c5e2f793b59a 8329 #define LLWU_F3_MWUF4_SHIFT 4
screamer 0:c5e2f793b59a 8330 #define LLWU_F3_MWUF5_MASK 0x20u
screamer 0:c5e2f793b59a 8331 #define LLWU_F3_MWUF5_SHIFT 5
screamer 0:c5e2f793b59a 8332 #define LLWU_F3_MWUF6_MASK 0x40u
screamer 0:c5e2f793b59a 8333 #define LLWU_F3_MWUF6_SHIFT 6
screamer 0:c5e2f793b59a 8334 #define LLWU_F3_MWUF7_MASK 0x80u
screamer 0:c5e2f793b59a 8335 #define LLWU_F3_MWUF7_SHIFT 7
screamer 0:c5e2f793b59a 8336 /* FILT1 Bit Fields */
screamer 0:c5e2f793b59a 8337 #define LLWU_FILT1_FILTSEL_MASK 0xFu
screamer 0:c5e2f793b59a 8338 #define LLWU_FILT1_FILTSEL_SHIFT 0
screamer 0:c5e2f793b59a 8339 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
screamer 0:c5e2f793b59a 8340 #define LLWU_FILT1_FILTE_MASK 0x60u
screamer 0:c5e2f793b59a 8341 #define LLWU_FILT1_FILTE_SHIFT 5
screamer 0:c5e2f793b59a 8342 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
screamer 0:c5e2f793b59a 8343 #define LLWU_FILT1_FILTF_MASK 0x80u
screamer 0:c5e2f793b59a 8344 #define LLWU_FILT1_FILTF_SHIFT 7
screamer 0:c5e2f793b59a 8345 /* FILT2 Bit Fields */
screamer 0:c5e2f793b59a 8346 #define LLWU_FILT2_FILTSEL_MASK 0xFu
screamer 0:c5e2f793b59a 8347 #define LLWU_FILT2_FILTSEL_SHIFT 0
screamer 0:c5e2f793b59a 8348 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
screamer 0:c5e2f793b59a 8349 #define LLWU_FILT2_FILTE_MASK 0x60u
screamer 0:c5e2f793b59a 8350 #define LLWU_FILT2_FILTE_SHIFT 5
screamer 0:c5e2f793b59a 8351 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
screamer 0:c5e2f793b59a 8352 #define LLWU_FILT2_FILTF_MASK 0x80u
screamer 0:c5e2f793b59a 8353 #define LLWU_FILT2_FILTF_SHIFT 7
screamer 0:c5e2f793b59a 8354 /* RST Bit Fields */
screamer 0:c5e2f793b59a 8355 #define LLWU_RST_RSTFILT_MASK 0x1u
screamer 0:c5e2f793b59a 8356 #define LLWU_RST_RSTFILT_SHIFT 0
screamer 0:c5e2f793b59a 8357 #define LLWU_RST_LLRSTE_MASK 0x2u
screamer 0:c5e2f793b59a 8358 #define LLWU_RST_LLRSTE_SHIFT 1
screamer 0:c5e2f793b59a 8359
screamer 0:c5e2f793b59a 8360 /*!
screamer 0:c5e2f793b59a 8361 * @}
screamer 0:c5e2f793b59a 8362 */ /* end of group LLWU_Register_Masks */
screamer 0:c5e2f793b59a 8363
screamer 0:c5e2f793b59a 8364
screamer 0:c5e2f793b59a 8365 /* LLWU - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 8366 /** Peripheral LLWU base address */
screamer 0:c5e2f793b59a 8367 #define LLWU_BASE (0x4007C000u)
screamer 0:c5e2f793b59a 8368 /** Peripheral LLWU base pointer */
screamer 0:c5e2f793b59a 8369 #define LLWU ((LLWU_Type *)LLWU_BASE)
screamer 0:c5e2f793b59a 8370 #define LLWU_BASE_PTR (LLWU)
screamer 0:c5e2f793b59a 8371 /** Array initializer of LLWU peripheral base addresses */
screamer 0:c5e2f793b59a 8372 #define LLWU_BASE_ADDRS { LLWU_BASE }
screamer 0:c5e2f793b59a 8373 /** Array initializer of LLWU peripheral base pointers */
screamer 0:c5e2f793b59a 8374 #define LLWU_BASE_PTRS { LLWU }
screamer 0:c5e2f793b59a 8375 /** Interrupt vectors for the LLWU peripheral type */
screamer 0:c5e2f793b59a 8376 #define LLWU_IRQS { LLW_IRQn }
screamer 0:c5e2f793b59a 8377
screamer 0:c5e2f793b59a 8378 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8379 -- LLWU - Register accessor macros
screamer 0:c5e2f793b59a 8380 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8381
screamer 0:c5e2f793b59a 8382 /*!
screamer 0:c5e2f793b59a 8383 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
screamer 0:c5e2f793b59a 8384 * @{
screamer 0:c5e2f793b59a 8385 */
screamer 0:c5e2f793b59a 8386
screamer 0:c5e2f793b59a 8387
screamer 0:c5e2f793b59a 8388 /* LLWU - Register instance definitions */
screamer 0:c5e2f793b59a 8389 /* LLWU */
screamer 0:c5e2f793b59a 8390 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
screamer 0:c5e2f793b59a 8391 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
screamer 0:c5e2f793b59a 8392 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
screamer 0:c5e2f793b59a 8393 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
screamer 0:c5e2f793b59a 8394 #define LLWU_ME LLWU_ME_REG(LLWU)
screamer 0:c5e2f793b59a 8395 #define LLWU_F1 LLWU_F1_REG(LLWU)
screamer 0:c5e2f793b59a 8396 #define LLWU_F2 LLWU_F2_REG(LLWU)
screamer 0:c5e2f793b59a 8397 #define LLWU_F3 LLWU_F3_REG(LLWU)
screamer 0:c5e2f793b59a 8398 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
screamer 0:c5e2f793b59a 8399 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
screamer 0:c5e2f793b59a 8400 #define LLWU_RST LLWU_RST_REG(LLWU)
screamer 0:c5e2f793b59a 8401
screamer 0:c5e2f793b59a 8402 /*!
screamer 0:c5e2f793b59a 8403 * @}
screamer 0:c5e2f793b59a 8404 */ /* end of group LLWU_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8405
screamer 0:c5e2f793b59a 8406
screamer 0:c5e2f793b59a 8407 /*!
screamer 0:c5e2f793b59a 8408 * @}
screamer 0:c5e2f793b59a 8409 */ /* end of group LLWU_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 8410
screamer 0:c5e2f793b59a 8411
screamer 0:c5e2f793b59a 8412 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8413 -- LPTMR Peripheral Access Layer
screamer 0:c5e2f793b59a 8414 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8415
screamer 0:c5e2f793b59a 8416 /*!
screamer 0:c5e2f793b59a 8417 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
screamer 0:c5e2f793b59a 8418 * @{
screamer 0:c5e2f793b59a 8419 */
screamer 0:c5e2f793b59a 8420
screamer 0:c5e2f793b59a 8421 /** LPTMR - Register Layout Typedef */
screamer 0:c5e2f793b59a 8422 typedef struct {
screamer 0:c5e2f793b59a 8423 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
screamer 0:c5e2f793b59a 8424 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
screamer 0:c5e2f793b59a 8425 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
screamer 0:c5e2f793b59a 8426 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
screamer 0:c5e2f793b59a 8427 } LPTMR_Type, *LPTMR_MemMapPtr;
screamer 0:c5e2f793b59a 8428
screamer 0:c5e2f793b59a 8429 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8430 -- LPTMR - Register accessor macros
screamer 0:c5e2f793b59a 8431 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8432
screamer 0:c5e2f793b59a 8433 /*!
screamer 0:c5e2f793b59a 8434 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
screamer 0:c5e2f793b59a 8435 * @{
screamer 0:c5e2f793b59a 8436 */
screamer 0:c5e2f793b59a 8437
screamer 0:c5e2f793b59a 8438
screamer 0:c5e2f793b59a 8439 /* LPTMR - Register accessors */
screamer 0:c5e2f793b59a 8440 #define LPTMR_CSR_REG(base) ((base)->CSR)
screamer 0:c5e2f793b59a 8441 #define LPTMR_PSR_REG(base) ((base)->PSR)
screamer 0:c5e2f793b59a 8442 #define LPTMR_CMR_REG(base) ((base)->CMR)
screamer 0:c5e2f793b59a 8443 #define LPTMR_CNR_REG(base) ((base)->CNR)
screamer 0:c5e2f793b59a 8444
screamer 0:c5e2f793b59a 8445 /*!
screamer 0:c5e2f793b59a 8446 * @}
screamer 0:c5e2f793b59a 8447 */ /* end of group LPTMR_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8448
screamer 0:c5e2f793b59a 8449
screamer 0:c5e2f793b59a 8450 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8451 -- LPTMR Register Masks
screamer 0:c5e2f793b59a 8452 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8453
screamer 0:c5e2f793b59a 8454 /*!
screamer 0:c5e2f793b59a 8455 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
screamer 0:c5e2f793b59a 8456 * @{
screamer 0:c5e2f793b59a 8457 */
screamer 0:c5e2f793b59a 8458
screamer 0:c5e2f793b59a 8459 /* CSR Bit Fields */
screamer 0:c5e2f793b59a 8460 #define LPTMR_CSR_TEN_MASK 0x1u
screamer 0:c5e2f793b59a 8461 #define LPTMR_CSR_TEN_SHIFT 0
screamer 0:c5e2f793b59a 8462 #define LPTMR_CSR_TMS_MASK 0x2u
screamer 0:c5e2f793b59a 8463 #define LPTMR_CSR_TMS_SHIFT 1
screamer 0:c5e2f793b59a 8464 #define LPTMR_CSR_TFC_MASK 0x4u
screamer 0:c5e2f793b59a 8465 #define LPTMR_CSR_TFC_SHIFT 2
screamer 0:c5e2f793b59a 8466 #define LPTMR_CSR_TPP_MASK 0x8u
screamer 0:c5e2f793b59a 8467 #define LPTMR_CSR_TPP_SHIFT 3
screamer 0:c5e2f793b59a 8468 #define LPTMR_CSR_TPS_MASK 0x30u
screamer 0:c5e2f793b59a 8469 #define LPTMR_CSR_TPS_SHIFT 4
screamer 0:c5e2f793b59a 8470 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
screamer 0:c5e2f793b59a 8471 #define LPTMR_CSR_TIE_MASK 0x40u
screamer 0:c5e2f793b59a 8472 #define LPTMR_CSR_TIE_SHIFT 6
screamer 0:c5e2f793b59a 8473 #define LPTMR_CSR_TCF_MASK 0x80u
screamer 0:c5e2f793b59a 8474 #define LPTMR_CSR_TCF_SHIFT 7
screamer 0:c5e2f793b59a 8475 /* PSR Bit Fields */
screamer 0:c5e2f793b59a 8476 #define LPTMR_PSR_PCS_MASK 0x3u
screamer 0:c5e2f793b59a 8477 #define LPTMR_PSR_PCS_SHIFT 0
screamer 0:c5e2f793b59a 8478 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
screamer 0:c5e2f793b59a 8479 #define LPTMR_PSR_PBYP_MASK 0x4u
screamer 0:c5e2f793b59a 8480 #define LPTMR_PSR_PBYP_SHIFT 2
screamer 0:c5e2f793b59a 8481 #define LPTMR_PSR_PRESCALE_MASK 0x78u
screamer 0:c5e2f793b59a 8482 #define LPTMR_PSR_PRESCALE_SHIFT 3
screamer 0:c5e2f793b59a 8483 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
screamer 0:c5e2f793b59a 8484 /* CMR Bit Fields */
screamer 0:c5e2f793b59a 8485 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
screamer 0:c5e2f793b59a 8486 #define LPTMR_CMR_COMPARE_SHIFT 0
screamer 0:c5e2f793b59a 8487 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
screamer 0:c5e2f793b59a 8488 /* CNR Bit Fields */
screamer 0:c5e2f793b59a 8489 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
screamer 0:c5e2f793b59a 8490 #define LPTMR_CNR_COUNTER_SHIFT 0
screamer 0:c5e2f793b59a 8491 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
screamer 0:c5e2f793b59a 8492
screamer 0:c5e2f793b59a 8493 /*!
screamer 0:c5e2f793b59a 8494 * @}
screamer 0:c5e2f793b59a 8495 */ /* end of group LPTMR_Register_Masks */
screamer 0:c5e2f793b59a 8496
screamer 0:c5e2f793b59a 8497
screamer 0:c5e2f793b59a 8498 /* LPTMR - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 8499 /** Peripheral LPTMR0 base address */
screamer 0:c5e2f793b59a 8500 #define LPTMR0_BASE (0x40040000u)
screamer 0:c5e2f793b59a 8501 /** Peripheral LPTMR0 base pointer */
screamer 0:c5e2f793b59a 8502 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
screamer 0:c5e2f793b59a 8503 #define LPTMR0_BASE_PTR (LPTMR0)
screamer 0:c5e2f793b59a 8504 /** Array initializer of LPTMR peripheral base addresses */
screamer 0:c5e2f793b59a 8505 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
screamer 0:c5e2f793b59a 8506 /** Array initializer of LPTMR peripheral base pointers */
screamer 0:c5e2f793b59a 8507 #define LPTMR_BASE_PTRS { LPTMR0 }
screamer 0:c5e2f793b59a 8508 /** Interrupt vectors for the LPTMR peripheral type */
screamer 0:c5e2f793b59a 8509 #define LPTMR_IRQS { LPTimer_IRQn }
screamer 0:c5e2f793b59a 8510
screamer 0:c5e2f793b59a 8511 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8512 -- LPTMR - Register accessor macros
screamer 0:c5e2f793b59a 8513 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8514
screamer 0:c5e2f793b59a 8515 /*!
screamer 0:c5e2f793b59a 8516 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
screamer 0:c5e2f793b59a 8517 * @{
screamer 0:c5e2f793b59a 8518 */
screamer 0:c5e2f793b59a 8519
screamer 0:c5e2f793b59a 8520
screamer 0:c5e2f793b59a 8521 /* LPTMR - Register instance definitions */
screamer 0:c5e2f793b59a 8522 /* LPTMR0 */
screamer 0:c5e2f793b59a 8523 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
screamer 0:c5e2f793b59a 8524 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
screamer 0:c5e2f793b59a 8525 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
screamer 0:c5e2f793b59a 8526 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
screamer 0:c5e2f793b59a 8527
screamer 0:c5e2f793b59a 8528 /*!
screamer 0:c5e2f793b59a 8529 * @}
screamer 0:c5e2f793b59a 8530 */ /* end of group LPTMR_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8531
screamer 0:c5e2f793b59a 8532
screamer 0:c5e2f793b59a 8533 /*!
screamer 0:c5e2f793b59a 8534 * @}
screamer 0:c5e2f793b59a 8535 */ /* end of group LPTMR_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 8536
screamer 0:c5e2f793b59a 8537
screamer 0:c5e2f793b59a 8538 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8539 -- MCG Peripheral Access Layer
screamer 0:c5e2f793b59a 8540 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8541
screamer 0:c5e2f793b59a 8542 /*!
screamer 0:c5e2f793b59a 8543 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
screamer 0:c5e2f793b59a 8544 * @{
screamer 0:c5e2f793b59a 8545 */
screamer 0:c5e2f793b59a 8546
screamer 0:c5e2f793b59a 8547 /** MCG - Register Layout Typedef */
screamer 0:c5e2f793b59a 8548 typedef struct {
screamer 0:c5e2f793b59a 8549 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
screamer 0:c5e2f793b59a 8550 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
screamer 0:c5e2f793b59a 8551 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
screamer 0:c5e2f793b59a 8552 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
screamer 0:c5e2f793b59a 8553 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
screamer 0:c5e2f793b59a 8554 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
screamer 0:c5e2f793b59a 8555 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
screamer 0:c5e2f793b59a 8556 uint8_t RESERVED_0[1];
screamer 0:c5e2f793b59a 8557 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
screamer 0:c5e2f793b59a 8558 uint8_t RESERVED_1[1];
screamer 0:c5e2f793b59a 8559 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
screamer 0:c5e2f793b59a 8560 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
screamer 0:c5e2f793b59a 8561 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
screamer 0:c5e2f793b59a 8562 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
screamer 0:c5e2f793b59a 8563 } MCG_Type, *MCG_MemMapPtr;
screamer 0:c5e2f793b59a 8564
screamer 0:c5e2f793b59a 8565 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8566 -- MCG - Register accessor macros
screamer 0:c5e2f793b59a 8567 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8568
screamer 0:c5e2f793b59a 8569 /*!
screamer 0:c5e2f793b59a 8570 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
screamer 0:c5e2f793b59a 8571 * @{
screamer 0:c5e2f793b59a 8572 */
screamer 0:c5e2f793b59a 8573
screamer 0:c5e2f793b59a 8574
screamer 0:c5e2f793b59a 8575 /* MCG - Register accessors */
screamer 0:c5e2f793b59a 8576 #define MCG_C1_REG(base) ((base)->C1)
screamer 0:c5e2f793b59a 8577 #define MCG_C2_REG(base) ((base)->C2)
screamer 0:c5e2f793b59a 8578 #define MCG_C3_REG(base) ((base)->C3)
screamer 0:c5e2f793b59a 8579 #define MCG_C4_REG(base) ((base)->C4)
screamer 0:c5e2f793b59a 8580 #define MCG_C5_REG(base) ((base)->C5)
screamer 0:c5e2f793b59a 8581 #define MCG_C6_REG(base) ((base)->C6)
screamer 0:c5e2f793b59a 8582 #define MCG_S_REG(base) ((base)->S)
screamer 0:c5e2f793b59a 8583 #define MCG_SC_REG(base) ((base)->SC)
screamer 0:c5e2f793b59a 8584 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
screamer 0:c5e2f793b59a 8585 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
screamer 0:c5e2f793b59a 8586 #define MCG_C7_REG(base) ((base)->C7)
screamer 0:c5e2f793b59a 8587 #define MCG_C8_REG(base) ((base)->C8)
screamer 0:c5e2f793b59a 8588
screamer 0:c5e2f793b59a 8589 /*!
screamer 0:c5e2f793b59a 8590 * @}
screamer 0:c5e2f793b59a 8591 */ /* end of group MCG_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8592
screamer 0:c5e2f793b59a 8593
screamer 0:c5e2f793b59a 8594 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8595 -- MCG Register Masks
screamer 0:c5e2f793b59a 8596 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8597
screamer 0:c5e2f793b59a 8598 /*!
screamer 0:c5e2f793b59a 8599 * @addtogroup MCG_Register_Masks MCG Register Masks
screamer 0:c5e2f793b59a 8600 * @{
screamer 0:c5e2f793b59a 8601 */
screamer 0:c5e2f793b59a 8602
screamer 0:c5e2f793b59a 8603 /* C1 Bit Fields */
screamer 0:c5e2f793b59a 8604 #define MCG_C1_IREFSTEN_MASK 0x1u
screamer 0:c5e2f793b59a 8605 #define MCG_C1_IREFSTEN_SHIFT 0
screamer 0:c5e2f793b59a 8606 #define MCG_C1_IRCLKEN_MASK 0x2u
screamer 0:c5e2f793b59a 8607 #define MCG_C1_IRCLKEN_SHIFT 1
screamer 0:c5e2f793b59a 8608 #define MCG_C1_IREFS_MASK 0x4u
screamer 0:c5e2f793b59a 8609 #define MCG_C1_IREFS_SHIFT 2
screamer 0:c5e2f793b59a 8610 #define MCG_C1_FRDIV_MASK 0x38u
screamer 0:c5e2f793b59a 8611 #define MCG_C1_FRDIV_SHIFT 3
screamer 0:c5e2f793b59a 8612 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
screamer 0:c5e2f793b59a 8613 #define MCG_C1_CLKS_MASK 0xC0u
screamer 0:c5e2f793b59a 8614 #define MCG_C1_CLKS_SHIFT 6
screamer 0:c5e2f793b59a 8615 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
screamer 0:c5e2f793b59a 8616 /* C2 Bit Fields */
screamer 0:c5e2f793b59a 8617 #define MCG_C2_IRCS_MASK 0x1u
screamer 0:c5e2f793b59a 8618 #define MCG_C2_IRCS_SHIFT 0
screamer 0:c5e2f793b59a 8619 #define MCG_C2_LP_MASK 0x2u
screamer 0:c5e2f793b59a 8620 #define MCG_C2_LP_SHIFT 1
screamer 0:c5e2f793b59a 8621 #define MCG_C2_EREFS_MASK 0x4u
screamer 0:c5e2f793b59a 8622 #define MCG_C2_EREFS_SHIFT 2
screamer 0:c5e2f793b59a 8623 #define MCG_C2_HGO_MASK 0x8u
screamer 0:c5e2f793b59a 8624 #define MCG_C2_HGO_SHIFT 3
screamer 0:c5e2f793b59a 8625 #define MCG_C2_RANGE_MASK 0x30u
screamer 0:c5e2f793b59a 8626 #define MCG_C2_RANGE_SHIFT 4
screamer 0:c5e2f793b59a 8627 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
screamer 0:c5e2f793b59a 8628 #define MCG_C2_FCFTRIM_MASK 0x40u
screamer 0:c5e2f793b59a 8629 #define MCG_C2_FCFTRIM_SHIFT 6
screamer 0:c5e2f793b59a 8630 #define MCG_C2_LOCRE0_MASK 0x80u
screamer 0:c5e2f793b59a 8631 #define MCG_C2_LOCRE0_SHIFT 7
screamer 0:c5e2f793b59a 8632 /* C3 Bit Fields */
screamer 0:c5e2f793b59a 8633 #define MCG_C3_SCTRIM_MASK 0xFFu
screamer 0:c5e2f793b59a 8634 #define MCG_C3_SCTRIM_SHIFT 0
screamer 0:c5e2f793b59a 8635 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
screamer 0:c5e2f793b59a 8636 /* C4 Bit Fields */
screamer 0:c5e2f793b59a 8637 #define MCG_C4_SCFTRIM_MASK 0x1u
screamer 0:c5e2f793b59a 8638 #define MCG_C4_SCFTRIM_SHIFT 0
screamer 0:c5e2f793b59a 8639 #define MCG_C4_FCTRIM_MASK 0x1Eu
screamer 0:c5e2f793b59a 8640 #define MCG_C4_FCTRIM_SHIFT 1
screamer 0:c5e2f793b59a 8641 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
screamer 0:c5e2f793b59a 8642 #define MCG_C4_DRST_DRS_MASK 0x60u
screamer 0:c5e2f793b59a 8643 #define MCG_C4_DRST_DRS_SHIFT 5
screamer 0:c5e2f793b59a 8644 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
screamer 0:c5e2f793b59a 8645 #define MCG_C4_DMX32_MASK 0x80u
screamer 0:c5e2f793b59a 8646 #define MCG_C4_DMX32_SHIFT 7
screamer 0:c5e2f793b59a 8647 /* C5 Bit Fields */
screamer 0:c5e2f793b59a 8648 #define MCG_C5_PRDIV0_MASK 0x1Fu
screamer 0:c5e2f793b59a 8649 #define MCG_C5_PRDIV0_SHIFT 0
screamer 0:c5e2f793b59a 8650 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
screamer 0:c5e2f793b59a 8651 #define MCG_C5_PLLSTEN0_MASK 0x20u
screamer 0:c5e2f793b59a 8652 #define MCG_C5_PLLSTEN0_SHIFT 5
screamer 0:c5e2f793b59a 8653 #define MCG_C5_PLLCLKEN0_MASK 0x40u
screamer 0:c5e2f793b59a 8654 #define MCG_C5_PLLCLKEN0_SHIFT 6
screamer 0:c5e2f793b59a 8655 /* C6 Bit Fields */
screamer 0:c5e2f793b59a 8656 #define MCG_C6_VDIV0_MASK 0x1Fu
screamer 0:c5e2f793b59a 8657 #define MCG_C6_VDIV0_SHIFT 0
screamer 0:c5e2f793b59a 8658 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
screamer 0:c5e2f793b59a 8659 #define MCG_C6_CME0_MASK 0x20u
screamer 0:c5e2f793b59a 8660 #define MCG_C6_CME0_SHIFT 5
screamer 0:c5e2f793b59a 8661 #define MCG_C6_PLLS_MASK 0x40u
screamer 0:c5e2f793b59a 8662 #define MCG_C6_PLLS_SHIFT 6
screamer 0:c5e2f793b59a 8663 #define MCG_C6_LOLIE0_MASK 0x80u
screamer 0:c5e2f793b59a 8664 #define MCG_C6_LOLIE0_SHIFT 7
screamer 0:c5e2f793b59a 8665 /* S Bit Fields */
screamer 0:c5e2f793b59a 8666 #define MCG_S_IRCST_MASK 0x1u
screamer 0:c5e2f793b59a 8667 #define MCG_S_IRCST_SHIFT 0
screamer 0:c5e2f793b59a 8668 #define MCG_S_OSCINIT0_MASK 0x2u
screamer 0:c5e2f793b59a 8669 #define MCG_S_OSCINIT0_SHIFT 1
screamer 0:c5e2f793b59a 8670 #define MCG_S_CLKST_MASK 0xCu
screamer 0:c5e2f793b59a 8671 #define MCG_S_CLKST_SHIFT 2
screamer 0:c5e2f793b59a 8672 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
screamer 0:c5e2f793b59a 8673 #define MCG_S_IREFST_MASK 0x10u
screamer 0:c5e2f793b59a 8674 #define MCG_S_IREFST_SHIFT 4
screamer 0:c5e2f793b59a 8675 #define MCG_S_PLLST_MASK 0x20u
screamer 0:c5e2f793b59a 8676 #define MCG_S_PLLST_SHIFT 5
screamer 0:c5e2f793b59a 8677 #define MCG_S_LOCK0_MASK 0x40u
screamer 0:c5e2f793b59a 8678 #define MCG_S_LOCK0_SHIFT 6
screamer 0:c5e2f793b59a 8679 #define MCG_S_LOLS0_MASK 0x80u
screamer 0:c5e2f793b59a 8680 #define MCG_S_LOLS0_SHIFT 7
screamer 0:c5e2f793b59a 8681 /* SC Bit Fields */
screamer 0:c5e2f793b59a 8682 #define MCG_SC_LOCS0_MASK 0x1u
screamer 0:c5e2f793b59a 8683 #define MCG_SC_LOCS0_SHIFT 0
screamer 0:c5e2f793b59a 8684 #define MCG_SC_FCRDIV_MASK 0xEu
screamer 0:c5e2f793b59a 8685 #define MCG_SC_FCRDIV_SHIFT 1
screamer 0:c5e2f793b59a 8686 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
screamer 0:c5e2f793b59a 8687 #define MCG_SC_FLTPRSRV_MASK 0x10u
screamer 0:c5e2f793b59a 8688 #define MCG_SC_FLTPRSRV_SHIFT 4
screamer 0:c5e2f793b59a 8689 #define MCG_SC_ATMF_MASK 0x20u
screamer 0:c5e2f793b59a 8690 #define MCG_SC_ATMF_SHIFT 5
screamer 0:c5e2f793b59a 8691 #define MCG_SC_ATMS_MASK 0x40u
screamer 0:c5e2f793b59a 8692 #define MCG_SC_ATMS_SHIFT 6
screamer 0:c5e2f793b59a 8693 #define MCG_SC_ATME_MASK 0x80u
screamer 0:c5e2f793b59a 8694 #define MCG_SC_ATME_SHIFT 7
screamer 0:c5e2f793b59a 8695 /* ATCVH Bit Fields */
screamer 0:c5e2f793b59a 8696 #define MCG_ATCVH_ATCVH_MASK 0xFFu
screamer 0:c5e2f793b59a 8697 #define MCG_ATCVH_ATCVH_SHIFT 0
screamer 0:c5e2f793b59a 8698 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
screamer 0:c5e2f793b59a 8699 /* ATCVL Bit Fields */
screamer 0:c5e2f793b59a 8700 #define MCG_ATCVL_ATCVL_MASK 0xFFu
screamer 0:c5e2f793b59a 8701 #define MCG_ATCVL_ATCVL_SHIFT 0
screamer 0:c5e2f793b59a 8702 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
screamer 0:c5e2f793b59a 8703 /* C7 Bit Fields */
screamer 0:c5e2f793b59a 8704 #define MCG_C7_OSCSEL_MASK 0x3u
screamer 0:c5e2f793b59a 8705 #define MCG_C7_OSCSEL_SHIFT 0
screamer 0:c5e2f793b59a 8706 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
screamer 0:c5e2f793b59a 8707 /* C8 Bit Fields */
screamer 0:c5e2f793b59a 8708 #define MCG_C8_LOCS1_MASK 0x1u
screamer 0:c5e2f793b59a 8709 #define MCG_C8_LOCS1_SHIFT 0
screamer 0:c5e2f793b59a 8710 #define MCG_C8_CME1_MASK 0x20u
screamer 0:c5e2f793b59a 8711 #define MCG_C8_CME1_SHIFT 5
screamer 0:c5e2f793b59a 8712 #define MCG_C8_LOLRE_MASK 0x40u
screamer 0:c5e2f793b59a 8713 #define MCG_C8_LOLRE_SHIFT 6
screamer 0:c5e2f793b59a 8714 #define MCG_C8_LOCRE1_MASK 0x80u
screamer 0:c5e2f793b59a 8715 #define MCG_C8_LOCRE1_SHIFT 7
screamer 0:c5e2f793b59a 8716
screamer 0:c5e2f793b59a 8717 /*!
screamer 0:c5e2f793b59a 8718 * @}
screamer 0:c5e2f793b59a 8719 */ /* end of group MCG_Register_Masks */
screamer 0:c5e2f793b59a 8720
screamer 0:c5e2f793b59a 8721
screamer 0:c5e2f793b59a 8722 /* MCG - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 8723 /** Peripheral MCG base address */
screamer 0:c5e2f793b59a 8724 #define MCG_BASE (0x40064000u)
screamer 0:c5e2f793b59a 8725 /** Peripheral MCG base pointer */
screamer 0:c5e2f793b59a 8726 #define MCG ((MCG_Type *)MCG_BASE)
screamer 0:c5e2f793b59a 8727 #define MCG_BASE_PTR (MCG)
screamer 0:c5e2f793b59a 8728 /** Array initializer of MCG peripheral base addresses */
screamer 0:c5e2f793b59a 8729 #define MCG_BASE_ADDRS { MCG_BASE }
screamer 0:c5e2f793b59a 8730 /** Array initializer of MCG peripheral base pointers */
screamer 0:c5e2f793b59a 8731 #define MCG_BASE_PTRS { MCG }
screamer 0:c5e2f793b59a 8732
screamer 0:c5e2f793b59a 8733 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8734 -- MCG - Register accessor macros
screamer 0:c5e2f793b59a 8735 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8736
screamer 0:c5e2f793b59a 8737 /*!
screamer 0:c5e2f793b59a 8738 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
screamer 0:c5e2f793b59a 8739 * @{
screamer 0:c5e2f793b59a 8740 */
screamer 0:c5e2f793b59a 8741
screamer 0:c5e2f793b59a 8742
screamer 0:c5e2f793b59a 8743 /* MCG - Register instance definitions */
screamer 0:c5e2f793b59a 8744 /* MCG */
screamer 0:c5e2f793b59a 8745 #define MCG_C1 MCG_C1_REG(MCG)
screamer 0:c5e2f793b59a 8746 #define MCG_C2 MCG_C2_REG(MCG)
screamer 0:c5e2f793b59a 8747 #define MCG_C3 MCG_C3_REG(MCG)
screamer 0:c5e2f793b59a 8748 #define MCG_C4 MCG_C4_REG(MCG)
screamer 0:c5e2f793b59a 8749 #define MCG_C5 MCG_C5_REG(MCG)
screamer 0:c5e2f793b59a 8750 #define MCG_C6 MCG_C6_REG(MCG)
screamer 0:c5e2f793b59a 8751 #define MCG_S MCG_S_REG(MCG)
screamer 0:c5e2f793b59a 8752 #define MCG_SC MCG_SC_REG(MCG)
screamer 0:c5e2f793b59a 8753 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
screamer 0:c5e2f793b59a 8754 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
screamer 0:c5e2f793b59a 8755 #define MCG_C7 MCG_C7_REG(MCG)
screamer 0:c5e2f793b59a 8756 #define MCG_C8 MCG_C8_REG(MCG)
screamer 0:c5e2f793b59a 8757
screamer 0:c5e2f793b59a 8758 /*!
screamer 0:c5e2f793b59a 8759 * @}
screamer 0:c5e2f793b59a 8760 */ /* end of group MCG_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8761
screamer 0:c5e2f793b59a 8762
screamer 0:c5e2f793b59a 8763 /*!
screamer 0:c5e2f793b59a 8764 * @}
screamer 0:c5e2f793b59a 8765 */ /* end of group MCG_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 8766
screamer 0:c5e2f793b59a 8767
screamer 0:c5e2f793b59a 8768 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8769 -- MCM Peripheral Access Layer
screamer 0:c5e2f793b59a 8770 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8771
screamer 0:c5e2f793b59a 8772 /*!
screamer 0:c5e2f793b59a 8773 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
screamer 0:c5e2f793b59a 8774 * @{
screamer 0:c5e2f793b59a 8775 */
screamer 0:c5e2f793b59a 8776
screamer 0:c5e2f793b59a 8777 /** MCM - Register Layout Typedef */
screamer 0:c5e2f793b59a 8778 typedef struct {
screamer 0:c5e2f793b59a 8779 uint8_t RESERVED_0[8];
screamer 0:c5e2f793b59a 8780 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
screamer 0:c5e2f793b59a 8781 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
screamer 0:c5e2f793b59a 8782 __IO uint32_t CR; /**< Control Register, offset: 0xC */
screamer 0:c5e2f793b59a 8783 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
screamer 0:c5e2f793b59a 8784 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
screamer 0:c5e2f793b59a 8785 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
screamer 0:c5e2f793b59a 8786 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
screamer 0:c5e2f793b59a 8787 uint8_t RESERVED_1[16];
screamer 0:c5e2f793b59a 8788 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
screamer 0:c5e2f793b59a 8789 } MCM_Type, *MCM_MemMapPtr;
screamer 0:c5e2f793b59a 8790
screamer 0:c5e2f793b59a 8791 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8792 -- MCM - Register accessor macros
screamer 0:c5e2f793b59a 8793 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8794
screamer 0:c5e2f793b59a 8795 /*!
screamer 0:c5e2f793b59a 8796 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
screamer 0:c5e2f793b59a 8797 * @{
screamer 0:c5e2f793b59a 8798 */
screamer 0:c5e2f793b59a 8799
screamer 0:c5e2f793b59a 8800
screamer 0:c5e2f793b59a 8801 /* MCM - Register accessors */
screamer 0:c5e2f793b59a 8802 #define MCM_PLASC_REG(base) ((base)->PLASC)
screamer 0:c5e2f793b59a 8803 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
screamer 0:c5e2f793b59a 8804 #define MCM_CR_REG(base) ((base)->CR)
screamer 0:c5e2f793b59a 8805 #define MCM_ISCR_REG(base) ((base)->ISCR)
screamer 0:c5e2f793b59a 8806 #define MCM_ETBCC_REG(base) ((base)->ETBCC)
screamer 0:c5e2f793b59a 8807 #define MCM_ETBRL_REG(base) ((base)->ETBRL)
screamer 0:c5e2f793b59a 8808 #define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
screamer 0:c5e2f793b59a 8809 #define MCM_PID_REG(base) ((base)->PID)
screamer 0:c5e2f793b59a 8810
screamer 0:c5e2f793b59a 8811 /*!
screamer 0:c5e2f793b59a 8812 * @}
screamer 0:c5e2f793b59a 8813 */ /* end of group MCM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8814
screamer 0:c5e2f793b59a 8815
screamer 0:c5e2f793b59a 8816 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8817 -- MCM Register Masks
screamer 0:c5e2f793b59a 8818 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8819
screamer 0:c5e2f793b59a 8820 /*!
screamer 0:c5e2f793b59a 8821 * @addtogroup MCM_Register_Masks MCM Register Masks
screamer 0:c5e2f793b59a 8822 * @{
screamer 0:c5e2f793b59a 8823 */
screamer 0:c5e2f793b59a 8824
screamer 0:c5e2f793b59a 8825 /* PLASC Bit Fields */
screamer 0:c5e2f793b59a 8826 #define MCM_PLASC_ASC_MASK 0xFFu
screamer 0:c5e2f793b59a 8827 #define MCM_PLASC_ASC_SHIFT 0
screamer 0:c5e2f793b59a 8828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
screamer 0:c5e2f793b59a 8829 /* PLAMC Bit Fields */
screamer 0:c5e2f793b59a 8830 #define MCM_PLAMC_AMC_MASK 0xFFu
screamer 0:c5e2f793b59a 8831 #define MCM_PLAMC_AMC_SHIFT 0
screamer 0:c5e2f793b59a 8832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
screamer 0:c5e2f793b59a 8833 /* CR Bit Fields */
screamer 0:c5e2f793b59a 8834 #define MCM_CR_SRAMUAP_MASK 0x3000000u
screamer 0:c5e2f793b59a 8835 #define MCM_CR_SRAMUAP_SHIFT 24
screamer 0:c5e2f793b59a 8836 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
screamer 0:c5e2f793b59a 8837 #define MCM_CR_SRAMUWP_MASK 0x4000000u
screamer 0:c5e2f793b59a 8838 #define MCM_CR_SRAMUWP_SHIFT 26
screamer 0:c5e2f793b59a 8839 #define MCM_CR_SRAMLAP_MASK 0x30000000u
screamer 0:c5e2f793b59a 8840 #define MCM_CR_SRAMLAP_SHIFT 28
screamer 0:c5e2f793b59a 8841 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
screamer 0:c5e2f793b59a 8842 #define MCM_CR_SRAMLWP_MASK 0x40000000u
screamer 0:c5e2f793b59a 8843 #define MCM_CR_SRAMLWP_SHIFT 30
screamer 0:c5e2f793b59a 8844 /* ISCR Bit Fields */
screamer 0:c5e2f793b59a 8845 #define MCM_ISCR_IRQ_MASK 0x2u
screamer 0:c5e2f793b59a 8846 #define MCM_ISCR_IRQ_SHIFT 1
screamer 0:c5e2f793b59a 8847 #define MCM_ISCR_NMI_MASK 0x4u
screamer 0:c5e2f793b59a 8848 #define MCM_ISCR_NMI_SHIFT 2
screamer 0:c5e2f793b59a 8849 #define MCM_ISCR_DHREQ_MASK 0x8u
screamer 0:c5e2f793b59a 8850 #define MCM_ISCR_DHREQ_SHIFT 3
screamer 0:c5e2f793b59a 8851 #define MCM_ISCR_FIOC_MASK 0x100u
screamer 0:c5e2f793b59a 8852 #define MCM_ISCR_FIOC_SHIFT 8
screamer 0:c5e2f793b59a 8853 #define MCM_ISCR_FDZC_MASK 0x200u
screamer 0:c5e2f793b59a 8854 #define MCM_ISCR_FDZC_SHIFT 9
screamer 0:c5e2f793b59a 8855 #define MCM_ISCR_FOFC_MASK 0x400u
screamer 0:c5e2f793b59a 8856 #define MCM_ISCR_FOFC_SHIFT 10
screamer 0:c5e2f793b59a 8857 #define MCM_ISCR_FUFC_MASK 0x800u
screamer 0:c5e2f793b59a 8858 #define MCM_ISCR_FUFC_SHIFT 11
screamer 0:c5e2f793b59a 8859 #define MCM_ISCR_FIXC_MASK 0x1000u
screamer 0:c5e2f793b59a 8860 #define MCM_ISCR_FIXC_SHIFT 12
screamer 0:c5e2f793b59a 8861 #define MCM_ISCR_FIDC_MASK 0x8000u
screamer 0:c5e2f793b59a 8862 #define MCM_ISCR_FIDC_SHIFT 15
screamer 0:c5e2f793b59a 8863 #define MCM_ISCR_FIOCE_MASK 0x1000000u
screamer 0:c5e2f793b59a 8864 #define MCM_ISCR_FIOCE_SHIFT 24
screamer 0:c5e2f793b59a 8865 #define MCM_ISCR_FDZCE_MASK 0x2000000u
screamer 0:c5e2f793b59a 8866 #define MCM_ISCR_FDZCE_SHIFT 25
screamer 0:c5e2f793b59a 8867 #define MCM_ISCR_FOFCE_MASK 0x4000000u
screamer 0:c5e2f793b59a 8868 #define MCM_ISCR_FOFCE_SHIFT 26
screamer 0:c5e2f793b59a 8869 #define MCM_ISCR_FUFCE_MASK 0x8000000u
screamer 0:c5e2f793b59a 8870 #define MCM_ISCR_FUFCE_SHIFT 27
screamer 0:c5e2f793b59a 8871 #define MCM_ISCR_FIXCE_MASK 0x10000000u
screamer 0:c5e2f793b59a 8872 #define MCM_ISCR_FIXCE_SHIFT 28
screamer 0:c5e2f793b59a 8873 #define MCM_ISCR_FIDCE_MASK 0x80000000u
screamer 0:c5e2f793b59a 8874 #define MCM_ISCR_FIDCE_SHIFT 31
screamer 0:c5e2f793b59a 8875 /* ETBCC Bit Fields */
screamer 0:c5e2f793b59a 8876 #define MCM_ETBCC_CNTEN_MASK 0x1u
screamer 0:c5e2f793b59a 8877 #define MCM_ETBCC_CNTEN_SHIFT 0
screamer 0:c5e2f793b59a 8878 #define MCM_ETBCC_RSPT_MASK 0x6u
screamer 0:c5e2f793b59a 8879 #define MCM_ETBCC_RSPT_SHIFT 1
screamer 0:c5e2f793b59a 8880 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
screamer 0:c5e2f793b59a 8881 #define MCM_ETBCC_RLRQ_MASK 0x8u
screamer 0:c5e2f793b59a 8882 #define MCM_ETBCC_RLRQ_SHIFT 3
screamer 0:c5e2f793b59a 8883 #define MCM_ETBCC_ETDIS_MASK 0x10u
screamer 0:c5e2f793b59a 8884 #define MCM_ETBCC_ETDIS_SHIFT 4
screamer 0:c5e2f793b59a 8885 #define MCM_ETBCC_ITDIS_MASK 0x20u
screamer 0:c5e2f793b59a 8886 #define MCM_ETBCC_ITDIS_SHIFT 5
screamer 0:c5e2f793b59a 8887 /* ETBRL Bit Fields */
screamer 0:c5e2f793b59a 8888 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
screamer 0:c5e2f793b59a 8889 #define MCM_ETBRL_RELOAD_SHIFT 0
screamer 0:c5e2f793b59a 8890 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
screamer 0:c5e2f793b59a 8891 /* ETBCNT Bit Fields */
screamer 0:c5e2f793b59a 8892 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
screamer 0:c5e2f793b59a 8893 #define MCM_ETBCNT_COUNTER_SHIFT 0
screamer 0:c5e2f793b59a 8894 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
screamer 0:c5e2f793b59a 8895 /* PID Bit Fields */
screamer 0:c5e2f793b59a 8896 #define MCM_PID_PID_MASK 0xFFu
screamer 0:c5e2f793b59a 8897 #define MCM_PID_PID_SHIFT 0
screamer 0:c5e2f793b59a 8898 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
screamer 0:c5e2f793b59a 8899
screamer 0:c5e2f793b59a 8900 /*!
screamer 0:c5e2f793b59a 8901 * @}
screamer 0:c5e2f793b59a 8902 */ /* end of group MCM_Register_Masks */
screamer 0:c5e2f793b59a 8903
screamer 0:c5e2f793b59a 8904
screamer 0:c5e2f793b59a 8905 /* MCM - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 8906 /** Peripheral MCM base address */
screamer 0:c5e2f793b59a 8907 #define MCM_BASE (0xE0080000u)
screamer 0:c5e2f793b59a 8908 /** Peripheral MCM base pointer */
screamer 0:c5e2f793b59a 8909 #define MCM ((MCM_Type *)MCM_BASE)
screamer 0:c5e2f793b59a 8910 #define MCM_BASE_PTR (MCM)
screamer 0:c5e2f793b59a 8911 /** Array initializer of MCM peripheral base addresses */
screamer 0:c5e2f793b59a 8912 #define MCM_BASE_ADDRS { MCM_BASE }
screamer 0:c5e2f793b59a 8913 /** Array initializer of MCM peripheral base pointers */
screamer 0:c5e2f793b59a 8914 #define MCM_BASE_PTRS { MCM }
screamer 0:c5e2f793b59a 8915
screamer 0:c5e2f793b59a 8916 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8917 -- MCM - Register accessor macros
screamer 0:c5e2f793b59a 8918 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8919
screamer 0:c5e2f793b59a 8920 /*!
screamer 0:c5e2f793b59a 8921 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
screamer 0:c5e2f793b59a 8922 * @{
screamer 0:c5e2f793b59a 8923 */
screamer 0:c5e2f793b59a 8924
screamer 0:c5e2f793b59a 8925
screamer 0:c5e2f793b59a 8926 /* MCM - Register instance definitions */
screamer 0:c5e2f793b59a 8927 /* MCM */
screamer 0:c5e2f793b59a 8928 #define MCM_PLASC MCM_PLASC_REG(MCM)
screamer 0:c5e2f793b59a 8929 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
screamer 0:c5e2f793b59a 8930 #define MCM_CR MCM_CR_REG(MCM)
screamer 0:c5e2f793b59a 8931 #define MCM_ISCR MCM_ISCR_REG(MCM)
screamer 0:c5e2f793b59a 8932 #define MCM_ETBCC MCM_ETBCC_REG(MCM)
screamer 0:c5e2f793b59a 8933 #define MCM_ETBRL MCM_ETBRL_REG(MCM)
screamer 0:c5e2f793b59a 8934 #define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
screamer 0:c5e2f793b59a 8935 #define MCM_PID MCM_PID_REG(MCM)
screamer 0:c5e2f793b59a 8936
screamer 0:c5e2f793b59a 8937 /*!
screamer 0:c5e2f793b59a 8938 * @}
screamer 0:c5e2f793b59a 8939 */ /* end of group MCM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8940
screamer 0:c5e2f793b59a 8941
screamer 0:c5e2f793b59a 8942 /*!
screamer 0:c5e2f793b59a 8943 * @}
screamer 0:c5e2f793b59a 8944 */ /* end of group MCM_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 8945
screamer 0:c5e2f793b59a 8946
screamer 0:c5e2f793b59a 8947 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8948 -- MPU Peripheral Access Layer
screamer 0:c5e2f793b59a 8949 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8950
screamer 0:c5e2f793b59a 8951 /*!
screamer 0:c5e2f793b59a 8952 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
screamer 0:c5e2f793b59a 8953 * @{
screamer 0:c5e2f793b59a 8954 */
screamer 0:c5e2f793b59a 8955
screamer 0:c5e2f793b59a 8956 /** MPU - Register Layout Typedef */
screamer 0:c5e2f793b59a 8957 typedef struct {
screamer 0:c5e2f793b59a 8958 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
screamer 0:c5e2f793b59a 8959 uint8_t RESERVED_0[12];
screamer 0:c5e2f793b59a 8960 struct { /* offset: 0x10, array step: 0x8 */
screamer 0:c5e2f793b59a 8961 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
screamer 0:c5e2f793b59a 8962 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
screamer 0:c5e2f793b59a 8963 } SP[5];
screamer 0:c5e2f793b59a 8964 uint8_t RESERVED_1[968];
screamer 0:c5e2f793b59a 8965 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
screamer 0:c5e2f793b59a 8966 uint8_t RESERVED_2[832];
screamer 0:c5e2f793b59a 8967 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
screamer 0:c5e2f793b59a 8968 } MPU_Type, *MPU_MemMapPtr;
screamer 0:c5e2f793b59a 8969
screamer 0:c5e2f793b59a 8970 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8971 -- MPU - Register accessor macros
screamer 0:c5e2f793b59a 8972 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8973
screamer 0:c5e2f793b59a 8974 /*!
screamer 0:c5e2f793b59a 8975 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
screamer 0:c5e2f793b59a 8976 * @{
screamer 0:c5e2f793b59a 8977 */
screamer 0:c5e2f793b59a 8978
screamer 0:c5e2f793b59a 8979
screamer 0:c5e2f793b59a 8980 /* MPU - Register accessors */
screamer 0:c5e2f793b59a 8981 #define MPU_CESR_REG(base) ((base)->CESR)
screamer 0:c5e2f793b59a 8982 #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
screamer 0:c5e2f793b59a 8983 #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
screamer 0:c5e2f793b59a 8984 #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
screamer 0:c5e2f793b59a 8985 #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
screamer 0:c5e2f793b59a 8986
screamer 0:c5e2f793b59a 8987 /*!
screamer 0:c5e2f793b59a 8988 * @}
screamer 0:c5e2f793b59a 8989 */ /* end of group MPU_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 8990
screamer 0:c5e2f793b59a 8991
screamer 0:c5e2f793b59a 8992 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 8993 -- MPU Register Masks
screamer 0:c5e2f793b59a 8994 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 8995
screamer 0:c5e2f793b59a 8996 /*!
screamer 0:c5e2f793b59a 8997 * @addtogroup MPU_Register_Masks MPU Register Masks
screamer 0:c5e2f793b59a 8998 * @{
screamer 0:c5e2f793b59a 8999 */
screamer 0:c5e2f793b59a 9000
screamer 0:c5e2f793b59a 9001 /* CESR Bit Fields */
screamer 0:c5e2f793b59a 9002 #define MPU_CESR_VLD_MASK 0x1u
screamer 0:c5e2f793b59a 9003 #define MPU_CESR_VLD_SHIFT 0
screamer 0:c5e2f793b59a 9004 #define MPU_CESR_NRGD_MASK 0xF00u
screamer 0:c5e2f793b59a 9005 #define MPU_CESR_NRGD_SHIFT 8
screamer 0:c5e2f793b59a 9006 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
screamer 0:c5e2f793b59a 9007 #define MPU_CESR_NSP_MASK 0xF000u
screamer 0:c5e2f793b59a 9008 #define MPU_CESR_NSP_SHIFT 12
screamer 0:c5e2f793b59a 9009 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
screamer 0:c5e2f793b59a 9010 #define MPU_CESR_HRL_MASK 0xF0000u
screamer 0:c5e2f793b59a 9011 #define MPU_CESR_HRL_SHIFT 16
screamer 0:c5e2f793b59a 9012 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
screamer 0:c5e2f793b59a 9013 #define MPU_CESR_SPERR_MASK 0xF8000000u
screamer 0:c5e2f793b59a 9014 #define MPU_CESR_SPERR_SHIFT 27
screamer 0:c5e2f793b59a 9015 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
screamer 0:c5e2f793b59a 9016 /* EAR Bit Fields */
screamer 0:c5e2f793b59a 9017 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 9018 #define MPU_EAR_EADDR_SHIFT 0
screamer 0:c5e2f793b59a 9019 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
screamer 0:c5e2f793b59a 9020 /* EDR Bit Fields */
screamer 0:c5e2f793b59a 9021 #define MPU_EDR_ERW_MASK 0x1u
screamer 0:c5e2f793b59a 9022 #define MPU_EDR_ERW_SHIFT 0
screamer 0:c5e2f793b59a 9023 #define MPU_EDR_EATTR_MASK 0xEu
screamer 0:c5e2f793b59a 9024 #define MPU_EDR_EATTR_SHIFT 1
screamer 0:c5e2f793b59a 9025 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
screamer 0:c5e2f793b59a 9026 #define MPU_EDR_EMN_MASK 0xF0u
screamer 0:c5e2f793b59a 9027 #define MPU_EDR_EMN_SHIFT 4
screamer 0:c5e2f793b59a 9028 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
screamer 0:c5e2f793b59a 9029 #define MPU_EDR_EPID_MASK 0xFF00u
screamer 0:c5e2f793b59a 9030 #define MPU_EDR_EPID_SHIFT 8
screamer 0:c5e2f793b59a 9031 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
screamer 0:c5e2f793b59a 9032 #define MPU_EDR_EACD_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 9033 #define MPU_EDR_EACD_SHIFT 16
screamer 0:c5e2f793b59a 9034 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
screamer 0:c5e2f793b59a 9035 /* WORD Bit Fields */
screamer 0:c5e2f793b59a 9036 #define MPU_WORD_VLD_MASK 0x1u
screamer 0:c5e2f793b59a 9037 #define MPU_WORD_VLD_SHIFT 0
screamer 0:c5e2f793b59a 9038 #define MPU_WORD_M0UM_MASK 0x7u
screamer 0:c5e2f793b59a 9039 #define MPU_WORD_M0UM_SHIFT 0
screamer 0:c5e2f793b59a 9040 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
screamer 0:c5e2f793b59a 9041 #define MPU_WORD_M0SM_MASK 0x18u
screamer 0:c5e2f793b59a 9042 #define MPU_WORD_M0SM_SHIFT 3
screamer 0:c5e2f793b59a 9043 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
screamer 0:c5e2f793b59a 9044 #define MPU_WORD_M0PE_MASK 0x20u
screamer 0:c5e2f793b59a 9045 #define MPU_WORD_M0PE_SHIFT 5
screamer 0:c5e2f793b59a 9046 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
screamer 0:c5e2f793b59a 9047 #define MPU_WORD_ENDADDR_SHIFT 5
screamer 0:c5e2f793b59a 9048 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
screamer 0:c5e2f793b59a 9049 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
screamer 0:c5e2f793b59a 9050 #define MPU_WORD_SRTADDR_SHIFT 5
screamer 0:c5e2f793b59a 9051 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
screamer 0:c5e2f793b59a 9052 #define MPU_WORD_M1UM_MASK 0x1C0u
screamer 0:c5e2f793b59a 9053 #define MPU_WORD_M1UM_SHIFT 6
screamer 0:c5e2f793b59a 9054 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
screamer 0:c5e2f793b59a 9055 #define MPU_WORD_M1SM_MASK 0x600u
screamer 0:c5e2f793b59a 9056 #define MPU_WORD_M1SM_SHIFT 9
screamer 0:c5e2f793b59a 9057 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
screamer 0:c5e2f793b59a 9058 #define MPU_WORD_M1PE_MASK 0x800u
screamer 0:c5e2f793b59a 9059 #define MPU_WORD_M1PE_SHIFT 11
screamer 0:c5e2f793b59a 9060 #define MPU_WORD_M2UM_MASK 0x7000u
screamer 0:c5e2f793b59a 9061 #define MPU_WORD_M2UM_SHIFT 12
screamer 0:c5e2f793b59a 9062 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
screamer 0:c5e2f793b59a 9063 #define MPU_WORD_M2SM_MASK 0x18000u
screamer 0:c5e2f793b59a 9064 #define MPU_WORD_M2SM_SHIFT 15
screamer 0:c5e2f793b59a 9065 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
screamer 0:c5e2f793b59a 9066 #define MPU_WORD_PIDMASK_MASK 0xFF0000u
screamer 0:c5e2f793b59a 9067 #define MPU_WORD_PIDMASK_SHIFT 16
screamer 0:c5e2f793b59a 9068 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
screamer 0:c5e2f793b59a 9069 #define MPU_WORD_M2PE_MASK 0x20000u
screamer 0:c5e2f793b59a 9070 #define MPU_WORD_M2PE_SHIFT 17
screamer 0:c5e2f793b59a 9071 #define MPU_WORD_M3UM_MASK 0x1C0000u
screamer 0:c5e2f793b59a 9072 #define MPU_WORD_M3UM_SHIFT 18
screamer 0:c5e2f793b59a 9073 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
screamer 0:c5e2f793b59a 9074 #define MPU_WORD_M3SM_MASK 0x600000u
screamer 0:c5e2f793b59a 9075 #define MPU_WORD_M3SM_SHIFT 21
screamer 0:c5e2f793b59a 9076 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
screamer 0:c5e2f793b59a 9077 #define MPU_WORD_M3PE_MASK 0x800000u
screamer 0:c5e2f793b59a 9078 #define MPU_WORD_M3PE_SHIFT 23
screamer 0:c5e2f793b59a 9079 #define MPU_WORD_PID_MASK 0xFF000000u
screamer 0:c5e2f793b59a 9080 #define MPU_WORD_PID_SHIFT 24
screamer 0:c5e2f793b59a 9081 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
screamer 0:c5e2f793b59a 9082 #define MPU_WORD_M4WE_MASK 0x1000000u
screamer 0:c5e2f793b59a 9083 #define MPU_WORD_M4WE_SHIFT 24
screamer 0:c5e2f793b59a 9084 #define MPU_WORD_M4RE_MASK 0x2000000u
screamer 0:c5e2f793b59a 9085 #define MPU_WORD_M4RE_SHIFT 25
screamer 0:c5e2f793b59a 9086 #define MPU_WORD_M5WE_MASK 0x4000000u
screamer 0:c5e2f793b59a 9087 #define MPU_WORD_M5WE_SHIFT 26
screamer 0:c5e2f793b59a 9088 #define MPU_WORD_M5RE_MASK 0x8000000u
screamer 0:c5e2f793b59a 9089 #define MPU_WORD_M5RE_SHIFT 27
screamer 0:c5e2f793b59a 9090 #define MPU_WORD_M6WE_MASK 0x10000000u
screamer 0:c5e2f793b59a 9091 #define MPU_WORD_M6WE_SHIFT 28
screamer 0:c5e2f793b59a 9092 #define MPU_WORD_M6RE_MASK 0x20000000u
screamer 0:c5e2f793b59a 9093 #define MPU_WORD_M6RE_SHIFT 29
screamer 0:c5e2f793b59a 9094 #define MPU_WORD_M7WE_MASK 0x40000000u
screamer 0:c5e2f793b59a 9095 #define MPU_WORD_M7WE_SHIFT 30
screamer 0:c5e2f793b59a 9096 #define MPU_WORD_M7RE_MASK 0x80000000u
screamer 0:c5e2f793b59a 9097 #define MPU_WORD_M7RE_SHIFT 31
screamer 0:c5e2f793b59a 9098 /* RGDAAC Bit Fields */
screamer 0:c5e2f793b59a 9099 #define MPU_RGDAAC_M0UM_MASK 0x7u
screamer 0:c5e2f793b59a 9100 #define MPU_RGDAAC_M0UM_SHIFT 0
screamer 0:c5e2f793b59a 9101 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
screamer 0:c5e2f793b59a 9102 #define MPU_RGDAAC_M0SM_MASK 0x18u
screamer 0:c5e2f793b59a 9103 #define MPU_RGDAAC_M0SM_SHIFT 3
screamer 0:c5e2f793b59a 9104 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
screamer 0:c5e2f793b59a 9105 #define MPU_RGDAAC_M0PE_MASK 0x20u
screamer 0:c5e2f793b59a 9106 #define MPU_RGDAAC_M0PE_SHIFT 5
screamer 0:c5e2f793b59a 9107 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
screamer 0:c5e2f793b59a 9108 #define MPU_RGDAAC_M1UM_SHIFT 6
screamer 0:c5e2f793b59a 9109 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
screamer 0:c5e2f793b59a 9110 #define MPU_RGDAAC_M1SM_MASK 0x600u
screamer 0:c5e2f793b59a 9111 #define MPU_RGDAAC_M1SM_SHIFT 9
screamer 0:c5e2f793b59a 9112 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
screamer 0:c5e2f793b59a 9113 #define MPU_RGDAAC_M1PE_MASK 0x800u
screamer 0:c5e2f793b59a 9114 #define MPU_RGDAAC_M1PE_SHIFT 11
screamer 0:c5e2f793b59a 9115 #define MPU_RGDAAC_M2UM_MASK 0x7000u
screamer 0:c5e2f793b59a 9116 #define MPU_RGDAAC_M2UM_SHIFT 12
screamer 0:c5e2f793b59a 9117 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
screamer 0:c5e2f793b59a 9118 #define MPU_RGDAAC_M2SM_MASK 0x18000u
screamer 0:c5e2f793b59a 9119 #define MPU_RGDAAC_M2SM_SHIFT 15
screamer 0:c5e2f793b59a 9120 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
screamer 0:c5e2f793b59a 9121 #define MPU_RGDAAC_M2PE_MASK 0x20000u
screamer 0:c5e2f793b59a 9122 #define MPU_RGDAAC_M2PE_SHIFT 17
screamer 0:c5e2f793b59a 9123 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
screamer 0:c5e2f793b59a 9124 #define MPU_RGDAAC_M3UM_SHIFT 18
screamer 0:c5e2f793b59a 9125 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
screamer 0:c5e2f793b59a 9126 #define MPU_RGDAAC_M3SM_MASK 0x600000u
screamer 0:c5e2f793b59a 9127 #define MPU_RGDAAC_M3SM_SHIFT 21
screamer 0:c5e2f793b59a 9128 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
screamer 0:c5e2f793b59a 9129 #define MPU_RGDAAC_M3PE_MASK 0x800000u
screamer 0:c5e2f793b59a 9130 #define MPU_RGDAAC_M3PE_SHIFT 23
screamer 0:c5e2f793b59a 9131 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
screamer 0:c5e2f793b59a 9132 #define MPU_RGDAAC_M4WE_SHIFT 24
screamer 0:c5e2f793b59a 9133 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
screamer 0:c5e2f793b59a 9134 #define MPU_RGDAAC_M4RE_SHIFT 25
screamer 0:c5e2f793b59a 9135 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
screamer 0:c5e2f793b59a 9136 #define MPU_RGDAAC_M5WE_SHIFT 26
screamer 0:c5e2f793b59a 9137 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
screamer 0:c5e2f793b59a 9138 #define MPU_RGDAAC_M5RE_SHIFT 27
screamer 0:c5e2f793b59a 9139 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
screamer 0:c5e2f793b59a 9140 #define MPU_RGDAAC_M6WE_SHIFT 28
screamer 0:c5e2f793b59a 9141 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
screamer 0:c5e2f793b59a 9142 #define MPU_RGDAAC_M6RE_SHIFT 29
screamer 0:c5e2f793b59a 9143 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
screamer 0:c5e2f793b59a 9144 #define MPU_RGDAAC_M7WE_SHIFT 30
screamer 0:c5e2f793b59a 9145 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
screamer 0:c5e2f793b59a 9146 #define MPU_RGDAAC_M7RE_SHIFT 31
screamer 0:c5e2f793b59a 9147
screamer 0:c5e2f793b59a 9148 /*!
screamer 0:c5e2f793b59a 9149 * @}
screamer 0:c5e2f793b59a 9150 */ /* end of group MPU_Register_Masks */
screamer 0:c5e2f793b59a 9151
screamer 0:c5e2f793b59a 9152
screamer 0:c5e2f793b59a 9153 /* MPU - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 9154 /** Peripheral MPU base address */
screamer 0:c5e2f793b59a 9155 #define MPU_BASE (0x4000D000u)
screamer 0:c5e2f793b59a 9156 /** Peripheral MPU base pointer */
screamer 0:c5e2f793b59a 9157 #define MPU ((MPU_Type *)MPU_BASE)
screamer 0:c5e2f793b59a 9158 #define MPU_BASE_PTR (MPU)
screamer 0:c5e2f793b59a 9159 /** Array initializer of MPU peripheral base addresses */
screamer 0:c5e2f793b59a 9160 #define MPU_BASE_ADDRS { MPU_BASE }
screamer 0:c5e2f793b59a 9161 /** Array initializer of MPU peripheral base pointers */
screamer 0:c5e2f793b59a 9162 #define MPU_BASE_PTRS { MPU }
screamer 0:c5e2f793b59a 9163
screamer 0:c5e2f793b59a 9164 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9165 -- MPU - Register accessor macros
screamer 0:c5e2f793b59a 9166 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9167
screamer 0:c5e2f793b59a 9168 /*!
screamer 0:c5e2f793b59a 9169 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
screamer 0:c5e2f793b59a 9170 * @{
screamer 0:c5e2f793b59a 9171 */
screamer 0:c5e2f793b59a 9172
screamer 0:c5e2f793b59a 9173
screamer 0:c5e2f793b59a 9174 /* MPU - Register instance definitions */
screamer 0:c5e2f793b59a 9175 /* MPU */
screamer 0:c5e2f793b59a 9176 #define MPU_CESR MPU_CESR_REG(MPU)
screamer 0:c5e2f793b59a 9177 #define MPU_EAR0 MPU_EAR_REG(MPU,0)
screamer 0:c5e2f793b59a 9178 #define MPU_EDR0 MPU_EDR_REG(MPU,0)
screamer 0:c5e2f793b59a 9179 #define MPU_EAR1 MPU_EAR_REG(MPU,1)
screamer 0:c5e2f793b59a 9180 #define MPU_EDR1 MPU_EDR_REG(MPU,1)
screamer 0:c5e2f793b59a 9181 #define MPU_EAR2 MPU_EAR_REG(MPU,2)
screamer 0:c5e2f793b59a 9182 #define MPU_EDR2 MPU_EDR_REG(MPU,2)
screamer 0:c5e2f793b59a 9183 #define MPU_EAR3 MPU_EAR_REG(MPU,3)
screamer 0:c5e2f793b59a 9184 #define MPU_EDR3 MPU_EDR_REG(MPU,3)
screamer 0:c5e2f793b59a 9185 #define MPU_EAR4 MPU_EAR_REG(MPU,4)
screamer 0:c5e2f793b59a 9186 #define MPU_EDR4 MPU_EDR_REG(MPU,4)
screamer 0:c5e2f793b59a 9187 #define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
screamer 0:c5e2f793b59a 9188 #define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
screamer 0:c5e2f793b59a 9189 #define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
screamer 0:c5e2f793b59a 9190 #define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
screamer 0:c5e2f793b59a 9191 #define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
screamer 0:c5e2f793b59a 9192 #define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
screamer 0:c5e2f793b59a 9193 #define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
screamer 0:c5e2f793b59a 9194 #define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
screamer 0:c5e2f793b59a 9195 #define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
screamer 0:c5e2f793b59a 9196 #define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
screamer 0:c5e2f793b59a 9197 #define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
screamer 0:c5e2f793b59a 9198 #define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
screamer 0:c5e2f793b59a 9199 #define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
screamer 0:c5e2f793b59a 9200 #define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
screamer 0:c5e2f793b59a 9201 #define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
screamer 0:c5e2f793b59a 9202 #define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
screamer 0:c5e2f793b59a 9203 #define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
screamer 0:c5e2f793b59a 9204 #define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
screamer 0:c5e2f793b59a 9205 #define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
screamer 0:c5e2f793b59a 9206 #define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
screamer 0:c5e2f793b59a 9207 #define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
screamer 0:c5e2f793b59a 9208 #define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
screamer 0:c5e2f793b59a 9209 #define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
screamer 0:c5e2f793b59a 9210 #define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
screamer 0:c5e2f793b59a 9211 #define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
screamer 0:c5e2f793b59a 9212 #define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
screamer 0:c5e2f793b59a 9213 #define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
screamer 0:c5e2f793b59a 9214 #define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
screamer 0:c5e2f793b59a 9215 #define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
screamer 0:c5e2f793b59a 9216 #define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
screamer 0:c5e2f793b59a 9217 #define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
screamer 0:c5e2f793b59a 9218 #define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
screamer 0:c5e2f793b59a 9219 #define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
screamer 0:c5e2f793b59a 9220 #define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
screamer 0:c5e2f793b59a 9221 #define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
screamer 0:c5e2f793b59a 9222 #define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
screamer 0:c5e2f793b59a 9223 #define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
screamer 0:c5e2f793b59a 9224 #define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
screamer 0:c5e2f793b59a 9225 #define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
screamer 0:c5e2f793b59a 9226 #define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
screamer 0:c5e2f793b59a 9227 #define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
screamer 0:c5e2f793b59a 9228 #define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
screamer 0:c5e2f793b59a 9229 #define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
screamer 0:c5e2f793b59a 9230 #define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
screamer 0:c5e2f793b59a 9231 #define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
screamer 0:c5e2f793b59a 9232 #define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
screamer 0:c5e2f793b59a 9233 #define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
screamer 0:c5e2f793b59a 9234 #define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
screamer 0:c5e2f793b59a 9235 #define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
screamer 0:c5e2f793b59a 9236 #define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
screamer 0:c5e2f793b59a 9237 #define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
screamer 0:c5e2f793b59a 9238 #define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
screamer 0:c5e2f793b59a 9239 #define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
screamer 0:c5e2f793b59a 9240 #define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
screamer 0:c5e2f793b59a 9241 #define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
screamer 0:c5e2f793b59a 9242 #define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
screamer 0:c5e2f793b59a 9243 #define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
screamer 0:c5e2f793b59a 9244 #define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
screamer 0:c5e2f793b59a 9245 #define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
screamer 0:c5e2f793b59a 9246 #define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
screamer 0:c5e2f793b59a 9247
screamer 0:c5e2f793b59a 9248 /* MPU - Register array accessors */
screamer 0:c5e2f793b59a 9249 #define MPU_EAR(index) MPU_EAR_REG(MPU,index)
screamer 0:c5e2f793b59a 9250 #define MPU_EDR(index) MPU_EDR_REG(MPU,index)
screamer 0:c5e2f793b59a 9251 #define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
screamer 0:c5e2f793b59a 9252 #define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
screamer 0:c5e2f793b59a 9253
screamer 0:c5e2f793b59a 9254 /*!
screamer 0:c5e2f793b59a 9255 * @}
screamer 0:c5e2f793b59a 9256 */ /* end of group MPU_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9257
screamer 0:c5e2f793b59a 9258
screamer 0:c5e2f793b59a 9259 /*!
screamer 0:c5e2f793b59a 9260 * @}
screamer 0:c5e2f793b59a 9261 */ /* end of group MPU_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 9262
screamer 0:c5e2f793b59a 9263
screamer 0:c5e2f793b59a 9264 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9265 -- NV Peripheral Access Layer
screamer 0:c5e2f793b59a 9266 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9267
screamer 0:c5e2f793b59a 9268 /*!
screamer 0:c5e2f793b59a 9269 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
screamer 0:c5e2f793b59a 9270 * @{
screamer 0:c5e2f793b59a 9271 */
screamer 0:c5e2f793b59a 9272
screamer 0:c5e2f793b59a 9273 /** NV - Register Layout Typedef */
screamer 0:c5e2f793b59a 9274 typedef struct {
screamer 0:c5e2f793b59a 9275 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
screamer 0:c5e2f793b59a 9276 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
screamer 0:c5e2f793b59a 9277 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
screamer 0:c5e2f793b59a 9278 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
screamer 0:c5e2f793b59a 9279 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
screamer 0:c5e2f793b59a 9280 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
screamer 0:c5e2f793b59a 9281 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
screamer 0:c5e2f793b59a 9282 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
screamer 0:c5e2f793b59a 9283 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
screamer 0:c5e2f793b59a 9284 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
screamer 0:c5e2f793b59a 9285 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
screamer 0:c5e2f793b59a 9286 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
screamer 0:c5e2f793b59a 9287 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
screamer 0:c5e2f793b59a 9288 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
screamer 0:c5e2f793b59a 9289 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
screamer 0:c5e2f793b59a 9290 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
screamer 0:c5e2f793b59a 9291 } NV_Type, *NV_MemMapPtr;
screamer 0:c5e2f793b59a 9292
screamer 0:c5e2f793b59a 9293 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9294 -- NV - Register accessor macros
screamer 0:c5e2f793b59a 9295 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9296
screamer 0:c5e2f793b59a 9297 /*!
screamer 0:c5e2f793b59a 9298 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
screamer 0:c5e2f793b59a 9299 * @{
screamer 0:c5e2f793b59a 9300 */
screamer 0:c5e2f793b59a 9301
screamer 0:c5e2f793b59a 9302
screamer 0:c5e2f793b59a 9303 /* NV - Register accessors */
screamer 0:c5e2f793b59a 9304 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
screamer 0:c5e2f793b59a 9305 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
screamer 0:c5e2f793b59a 9306 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
screamer 0:c5e2f793b59a 9307 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
screamer 0:c5e2f793b59a 9308 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
screamer 0:c5e2f793b59a 9309 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
screamer 0:c5e2f793b59a 9310 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
screamer 0:c5e2f793b59a 9311 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
screamer 0:c5e2f793b59a 9312 #define NV_FPROT3_REG(base) ((base)->FPROT3)
screamer 0:c5e2f793b59a 9313 #define NV_FPROT2_REG(base) ((base)->FPROT2)
screamer 0:c5e2f793b59a 9314 #define NV_FPROT1_REG(base) ((base)->FPROT1)
screamer 0:c5e2f793b59a 9315 #define NV_FPROT0_REG(base) ((base)->FPROT0)
screamer 0:c5e2f793b59a 9316 #define NV_FSEC_REG(base) ((base)->FSEC)
screamer 0:c5e2f793b59a 9317 #define NV_FOPT_REG(base) ((base)->FOPT)
screamer 0:c5e2f793b59a 9318 #define NV_FEPROT_REG(base) ((base)->FEPROT)
screamer 0:c5e2f793b59a 9319 #define NV_FDPROT_REG(base) ((base)->FDPROT)
screamer 0:c5e2f793b59a 9320
screamer 0:c5e2f793b59a 9321 /*!
screamer 0:c5e2f793b59a 9322 * @}
screamer 0:c5e2f793b59a 9323 */ /* end of group NV_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9324
screamer 0:c5e2f793b59a 9325
screamer 0:c5e2f793b59a 9326 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9327 -- NV Register Masks
screamer 0:c5e2f793b59a 9328 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9329
screamer 0:c5e2f793b59a 9330 /*!
screamer 0:c5e2f793b59a 9331 * @addtogroup NV_Register_Masks NV Register Masks
screamer 0:c5e2f793b59a 9332 * @{
screamer 0:c5e2f793b59a 9333 */
screamer 0:c5e2f793b59a 9334
screamer 0:c5e2f793b59a 9335 /* BACKKEY3 Bit Fields */
screamer 0:c5e2f793b59a 9336 #define NV_BACKKEY3_KEY_MASK 0xFFu
screamer 0:c5e2f793b59a 9337 #define NV_BACKKEY3_KEY_SHIFT 0
screamer 0:c5e2f793b59a 9338 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
screamer 0:c5e2f793b59a 9339 /* BACKKEY2 Bit Fields */
screamer 0:c5e2f793b59a 9340 #define NV_BACKKEY2_KEY_MASK 0xFFu
screamer 0:c5e2f793b59a 9341 #define NV_BACKKEY2_KEY_SHIFT 0
screamer 0:c5e2f793b59a 9342 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
screamer 0:c5e2f793b59a 9343 /* BACKKEY1 Bit Fields */
screamer 0:c5e2f793b59a 9344 #define NV_BACKKEY1_KEY_MASK 0xFFu
screamer 0:c5e2f793b59a 9345 #define NV_BACKKEY1_KEY_SHIFT 0
screamer 0:c5e2f793b59a 9346 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
screamer 0:c5e2f793b59a 9347 /* BACKKEY0 Bit Fields */
screamer 0:c5e2f793b59a 9348 #define NV_BACKKEY0_KEY_MASK 0xFFu
screamer 0:c5e2f793b59a 9349 #define NV_BACKKEY0_KEY_SHIFT 0
screamer 0:c5e2f793b59a 9350 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
screamer 0:c5e2f793b59a 9351 /* BACKKEY7 Bit Fields */
screamer 0:c5e2f793b59a 9352 #define NV_BACKKEY7_KEY_MASK 0xFFu
screamer 0:c5e2f793b59a 9353 #define NV_BACKKEY7_KEY_SHIFT 0
screamer 0:c5e2f793b59a 9354 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
screamer 0:c5e2f793b59a 9355 /* BACKKEY6 Bit Fields */
screamer 0:c5e2f793b59a 9356 #define NV_BACKKEY6_KEY_MASK 0xFFu
screamer 0:c5e2f793b59a 9357 #define NV_BACKKEY6_KEY_SHIFT 0
screamer 0:c5e2f793b59a 9358 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
screamer 0:c5e2f793b59a 9359 /* BACKKEY5 Bit Fields */
screamer 0:c5e2f793b59a 9360 #define NV_BACKKEY5_KEY_MASK 0xFFu
screamer 0:c5e2f793b59a 9361 #define NV_BACKKEY5_KEY_SHIFT 0
screamer 0:c5e2f793b59a 9362 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
screamer 0:c5e2f793b59a 9363 /* BACKKEY4 Bit Fields */
screamer 0:c5e2f793b59a 9364 #define NV_BACKKEY4_KEY_MASK 0xFFu
screamer 0:c5e2f793b59a 9365 #define NV_BACKKEY4_KEY_SHIFT 0
screamer 0:c5e2f793b59a 9366 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
screamer 0:c5e2f793b59a 9367 /* FPROT3 Bit Fields */
screamer 0:c5e2f793b59a 9368 #define NV_FPROT3_PROT_MASK 0xFFu
screamer 0:c5e2f793b59a 9369 #define NV_FPROT3_PROT_SHIFT 0
screamer 0:c5e2f793b59a 9370 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
screamer 0:c5e2f793b59a 9371 /* FPROT2 Bit Fields */
screamer 0:c5e2f793b59a 9372 #define NV_FPROT2_PROT_MASK 0xFFu
screamer 0:c5e2f793b59a 9373 #define NV_FPROT2_PROT_SHIFT 0
screamer 0:c5e2f793b59a 9374 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
screamer 0:c5e2f793b59a 9375 /* FPROT1 Bit Fields */
screamer 0:c5e2f793b59a 9376 #define NV_FPROT1_PROT_MASK 0xFFu
screamer 0:c5e2f793b59a 9377 #define NV_FPROT1_PROT_SHIFT 0
screamer 0:c5e2f793b59a 9378 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
screamer 0:c5e2f793b59a 9379 /* FPROT0 Bit Fields */
screamer 0:c5e2f793b59a 9380 #define NV_FPROT0_PROT_MASK 0xFFu
screamer 0:c5e2f793b59a 9381 #define NV_FPROT0_PROT_SHIFT 0
screamer 0:c5e2f793b59a 9382 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
screamer 0:c5e2f793b59a 9383 /* FSEC Bit Fields */
screamer 0:c5e2f793b59a 9384 #define NV_FSEC_SEC_MASK 0x3u
screamer 0:c5e2f793b59a 9385 #define NV_FSEC_SEC_SHIFT 0
screamer 0:c5e2f793b59a 9386 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
screamer 0:c5e2f793b59a 9387 #define NV_FSEC_FSLACC_MASK 0xCu
screamer 0:c5e2f793b59a 9388 #define NV_FSEC_FSLACC_SHIFT 2
screamer 0:c5e2f793b59a 9389 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
screamer 0:c5e2f793b59a 9390 #define NV_FSEC_MEEN_MASK 0x30u
screamer 0:c5e2f793b59a 9391 #define NV_FSEC_MEEN_SHIFT 4
screamer 0:c5e2f793b59a 9392 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
screamer 0:c5e2f793b59a 9393 #define NV_FSEC_KEYEN_MASK 0xC0u
screamer 0:c5e2f793b59a 9394 #define NV_FSEC_KEYEN_SHIFT 6
screamer 0:c5e2f793b59a 9395 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
screamer 0:c5e2f793b59a 9396 /* FOPT Bit Fields */
screamer 0:c5e2f793b59a 9397 #define NV_FOPT_LPBOOT_MASK 0x1u
screamer 0:c5e2f793b59a 9398 #define NV_FOPT_LPBOOT_SHIFT 0
screamer 0:c5e2f793b59a 9399 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
screamer 0:c5e2f793b59a 9400 #define NV_FOPT_EZPORT_DIS_SHIFT 1
screamer 0:c5e2f793b59a 9401 /* FEPROT Bit Fields */
screamer 0:c5e2f793b59a 9402 #define NV_FEPROT_EPROT_MASK 0xFFu
screamer 0:c5e2f793b59a 9403 #define NV_FEPROT_EPROT_SHIFT 0
screamer 0:c5e2f793b59a 9404 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
screamer 0:c5e2f793b59a 9405 /* FDPROT Bit Fields */
screamer 0:c5e2f793b59a 9406 #define NV_FDPROT_DPROT_MASK 0xFFu
screamer 0:c5e2f793b59a 9407 #define NV_FDPROT_DPROT_SHIFT 0
screamer 0:c5e2f793b59a 9408 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
screamer 0:c5e2f793b59a 9409
screamer 0:c5e2f793b59a 9410 /*!
screamer 0:c5e2f793b59a 9411 * @}
screamer 0:c5e2f793b59a 9412 */ /* end of group NV_Register_Masks */
screamer 0:c5e2f793b59a 9413
screamer 0:c5e2f793b59a 9414
screamer 0:c5e2f793b59a 9415 /* NV - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 9416 /** Peripheral FTFE_FlashConfig base address */
screamer 0:c5e2f793b59a 9417 #define FTFE_FlashConfig_BASE (0x400u)
screamer 0:c5e2f793b59a 9418 /** Peripheral FTFE_FlashConfig base pointer */
screamer 0:c5e2f793b59a 9419 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
screamer 0:c5e2f793b59a 9420 #define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9421 /** Array initializer of NV peripheral base addresses */
screamer 0:c5e2f793b59a 9422 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
screamer 0:c5e2f793b59a 9423 /** Array initializer of NV peripheral base pointers */
screamer 0:c5e2f793b59a 9424 #define NV_BASE_PTRS { FTFE_FlashConfig }
screamer 0:c5e2f793b59a 9425
screamer 0:c5e2f793b59a 9426 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9427 -- NV - Register accessor macros
screamer 0:c5e2f793b59a 9428 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9429
screamer 0:c5e2f793b59a 9430 /*!
screamer 0:c5e2f793b59a 9431 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
screamer 0:c5e2f793b59a 9432 * @{
screamer 0:c5e2f793b59a 9433 */
screamer 0:c5e2f793b59a 9434
screamer 0:c5e2f793b59a 9435
screamer 0:c5e2f793b59a 9436 /* NV - Register instance definitions */
screamer 0:c5e2f793b59a 9437 /* FTFE_FlashConfig */
screamer 0:c5e2f793b59a 9438 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9439 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9440 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9441 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9442 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9443 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9444 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9445 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9446 #define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9447 #define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9448 #define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9449 #define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9450 #define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9451 #define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9452 #define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9453 #define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
screamer 0:c5e2f793b59a 9454
screamer 0:c5e2f793b59a 9455 /*!
screamer 0:c5e2f793b59a 9456 * @}
screamer 0:c5e2f793b59a 9457 */ /* end of group NV_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9458
screamer 0:c5e2f793b59a 9459
screamer 0:c5e2f793b59a 9460 /*!
screamer 0:c5e2f793b59a 9461 * @}
screamer 0:c5e2f793b59a 9462 */ /* end of group NV_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 9463
screamer 0:c5e2f793b59a 9464
screamer 0:c5e2f793b59a 9465 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9466 -- OSC Peripheral Access Layer
screamer 0:c5e2f793b59a 9467 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9468
screamer 0:c5e2f793b59a 9469 /*!
screamer 0:c5e2f793b59a 9470 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
screamer 0:c5e2f793b59a 9471 * @{
screamer 0:c5e2f793b59a 9472 */
screamer 0:c5e2f793b59a 9473
screamer 0:c5e2f793b59a 9474 /** OSC - Register Layout Typedef */
screamer 0:c5e2f793b59a 9475 typedef struct {
screamer 0:c5e2f793b59a 9476 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
screamer 0:c5e2f793b59a 9477 } OSC_Type, *OSC_MemMapPtr;
screamer 0:c5e2f793b59a 9478
screamer 0:c5e2f793b59a 9479 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9480 -- OSC - Register accessor macros
screamer 0:c5e2f793b59a 9481 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9482
screamer 0:c5e2f793b59a 9483 /*!
screamer 0:c5e2f793b59a 9484 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
screamer 0:c5e2f793b59a 9485 * @{
screamer 0:c5e2f793b59a 9486 */
screamer 0:c5e2f793b59a 9487
screamer 0:c5e2f793b59a 9488
screamer 0:c5e2f793b59a 9489 /* OSC - Register accessors */
screamer 0:c5e2f793b59a 9490 #define OSC_CR_REG(base) ((base)->CR)
screamer 0:c5e2f793b59a 9491
screamer 0:c5e2f793b59a 9492 /*!
screamer 0:c5e2f793b59a 9493 * @}
screamer 0:c5e2f793b59a 9494 */ /* end of group OSC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9495
screamer 0:c5e2f793b59a 9496
screamer 0:c5e2f793b59a 9497 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9498 -- OSC Register Masks
screamer 0:c5e2f793b59a 9499 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9500
screamer 0:c5e2f793b59a 9501 /*!
screamer 0:c5e2f793b59a 9502 * @addtogroup OSC_Register_Masks OSC Register Masks
screamer 0:c5e2f793b59a 9503 * @{
screamer 0:c5e2f793b59a 9504 */
screamer 0:c5e2f793b59a 9505
screamer 0:c5e2f793b59a 9506 /* CR Bit Fields */
screamer 0:c5e2f793b59a 9507 #define OSC_CR_SC16P_MASK 0x1u
screamer 0:c5e2f793b59a 9508 #define OSC_CR_SC16P_SHIFT 0
screamer 0:c5e2f793b59a 9509 #define OSC_CR_SC8P_MASK 0x2u
screamer 0:c5e2f793b59a 9510 #define OSC_CR_SC8P_SHIFT 1
screamer 0:c5e2f793b59a 9511 #define OSC_CR_SC4P_MASK 0x4u
screamer 0:c5e2f793b59a 9512 #define OSC_CR_SC4P_SHIFT 2
screamer 0:c5e2f793b59a 9513 #define OSC_CR_SC2P_MASK 0x8u
screamer 0:c5e2f793b59a 9514 #define OSC_CR_SC2P_SHIFT 3
screamer 0:c5e2f793b59a 9515 #define OSC_CR_EREFSTEN_MASK 0x20u
screamer 0:c5e2f793b59a 9516 #define OSC_CR_EREFSTEN_SHIFT 5
screamer 0:c5e2f793b59a 9517 #define OSC_CR_ERCLKEN_MASK 0x80u
screamer 0:c5e2f793b59a 9518 #define OSC_CR_ERCLKEN_SHIFT 7
screamer 0:c5e2f793b59a 9519
screamer 0:c5e2f793b59a 9520 /*!
screamer 0:c5e2f793b59a 9521 * @}
screamer 0:c5e2f793b59a 9522 */ /* end of group OSC_Register_Masks */
screamer 0:c5e2f793b59a 9523
screamer 0:c5e2f793b59a 9524
screamer 0:c5e2f793b59a 9525 /* OSC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 9526 /** Peripheral OSC base address */
screamer 0:c5e2f793b59a 9527 #define OSC_BASE (0x40065000u)
screamer 0:c5e2f793b59a 9528 /** Peripheral OSC base pointer */
screamer 0:c5e2f793b59a 9529 #define OSC ((OSC_Type *)OSC_BASE)
screamer 0:c5e2f793b59a 9530 #define OSC_BASE_PTR (OSC)
screamer 0:c5e2f793b59a 9531 /** Array initializer of OSC peripheral base addresses */
screamer 0:c5e2f793b59a 9532 #define OSC_BASE_ADDRS { OSC_BASE }
screamer 0:c5e2f793b59a 9533 /** Array initializer of OSC peripheral base pointers */
screamer 0:c5e2f793b59a 9534 #define OSC_BASE_PTRS { OSC }
screamer 0:c5e2f793b59a 9535
screamer 0:c5e2f793b59a 9536 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9537 -- OSC - Register accessor macros
screamer 0:c5e2f793b59a 9538 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9539
screamer 0:c5e2f793b59a 9540 /*!
screamer 0:c5e2f793b59a 9541 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
screamer 0:c5e2f793b59a 9542 * @{
screamer 0:c5e2f793b59a 9543 */
screamer 0:c5e2f793b59a 9544
screamer 0:c5e2f793b59a 9545
screamer 0:c5e2f793b59a 9546 /* OSC - Register instance definitions */
screamer 0:c5e2f793b59a 9547 /* OSC */
screamer 0:c5e2f793b59a 9548 #define OSC_CR OSC_CR_REG(OSC)
screamer 0:c5e2f793b59a 9549
screamer 0:c5e2f793b59a 9550 /*!
screamer 0:c5e2f793b59a 9551 * @}
screamer 0:c5e2f793b59a 9552 */ /* end of group OSC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9553
screamer 0:c5e2f793b59a 9554
screamer 0:c5e2f793b59a 9555 /*!
screamer 0:c5e2f793b59a 9556 * @}
screamer 0:c5e2f793b59a 9557 */ /* end of group OSC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 9558
screamer 0:c5e2f793b59a 9559
screamer 0:c5e2f793b59a 9560 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9561 -- PDB Peripheral Access Layer
screamer 0:c5e2f793b59a 9562 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9563
screamer 0:c5e2f793b59a 9564 /*!
screamer 0:c5e2f793b59a 9565 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
screamer 0:c5e2f793b59a 9566 * @{
screamer 0:c5e2f793b59a 9567 */
screamer 0:c5e2f793b59a 9568
screamer 0:c5e2f793b59a 9569 /** PDB - Register Layout Typedef */
screamer 0:c5e2f793b59a 9570 typedef struct {
screamer 0:c5e2f793b59a 9571 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
screamer 0:c5e2f793b59a 9572 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
screamer 0:c5e2f793b59a 9573 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
screamer 0:c5e2f793b59a 9574 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
screamer 0:c5e2f793b59a 9575 struct { /* offset: 0x10, array step: 0x28 */
screamer 0:c5e2f793b59a 9576 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
screamer 0:c5e2f793b59a 9577 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
screamer 0:c5e2f793b59a 9578 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
screamer 0:c5e2f793b59a 9579 uint8_t RESERVED_0[24];
screamer 0:c5e2f793b59a 9580 } CH[2];
screamer 0:c5e2f793b59a 9581 uint8_t RESERVED_0[240];
screamer 0:c5e2f793b59a 9582 struct { /* offset: 0x150, array step: 0x8 */
screamer 0:c5e2f793b59a 9583 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
screamer 0:c5e2f793b59a 9584 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
screamer 0:c5e2f793b59a 9585 } DAC[2];
screamer 0:c5e2f793b59a 9586 uint8_t RESERVED_1[48];
screamer 0:c5e2f793b59a 9587 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
screamer 0:c5e2f793b59a 9588 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
screamer 0:c5e2f793b59a 9589 } PDB_Type, *PDB_MemMapPtr;
screamer 0:c5e2f793b59a 9590
screamer 0:c5e2f793b59a 9591 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9592 -- PDB - Register accessor macros
screamer 0:c5e2f793b59a 9593 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9594
screamer 0:c5e2f793b59a 9595 /*!
screamer 0:c5e2f793b59a 9596 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
screamer 0:c5e2f793b59a 9597 * @{
screamer 0:c5e2f793b59a 9598 */
screamer 0:c5e2f793b59a 9599
screamer 0:c5e2f793b59a 9600
screamer 0:c5e2f793b59a 9601 /* PDB - Register accessors */
screamer 0:c5e2f793b59a 9602 #define PDB_SC_REG(base) ((base)->SC)
screamer 0:c5e2f793b59a 9603 #define PDB_MOD_REG(base) ((base)->MOD)
screamer 0:c5e2f793b59a 9604 #define PDB_CNT_REG(base) ((base)->CNT)
screamer 0:c5e2f793b59a 9605 #define PDB_IDLY_REG(base) ((base)->IDLY)
screamer 0:c5e2f793b59a 9606 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
screamer 0:c5e2f793b59a 9607 #define PDB_S_REG(base,index) ((base)->CH[index].S)
screamer 0:c5e2f793b59a 9608 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
screamer 0:c5e2f793b59a 9609 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
screamer 0:c5e2f793b59a 9610 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
screamer 0:c5e2f793b59a 9611 #define PDB_POEN_REG(base) ((base)->POEN)
screamer 0:c5e2f793b59a 9612 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
screamer 0:c5e2f793b59a 9613
screamer 0:c5e2f793b59a 9614 /*!
screamer 0:c5e2f793b59a 9615 * @}
screamer 0:c5e2f793b59a 9616 */ /* end of group PDB_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9617
screamer 0:c5e2f793b59a 9618
screamer 0:c5e2f793b59a 9619 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9620 -- PDB Register Masks
screamer 0:c5e2f793b59a 9621 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9622
screamer 0:c5e2f793b59a 9623 /*!
screamer 0:c5e2f793b59a 9624 * @addtogroup PDB_Register_Masks PDB Register Masks
screamer 0:c5e2f793b59a 9625 * @{
screamer 0:c5e2f793b59a 9626 */
screamer 0:c5e2f793b59a 9627
screamer 0:c5e2f793b59a 9628 /* SC Bit Fields */
screamer 0:c5e2f793b59a 9629 #define PDB_SC_LDOK_MASK 0x1u
screamer 0:c5e2f793b59a 9630 #define PDB_SC_LDOK_SHIFT 0
screamer 0:c5e2f793b59a 9631 #define PDB_SC_CONT_MASK 0x2u
screamer 0:c5e2f793b59a 9632 #define PDB_SC_CONT_SHIFT 1
screamer 0:c5e2f793b59a 9633 #define PDB_SC_MULT_MASK 0xCu
screamer 0:c5e2f793b59a 9634 #define PDB_SC_MULT_SHIFT 2
screamer 0:c5e2f793b59a 9635 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
screamer 0:c5e2f793b59a 9636 #define PDB_SC_PDBIE_MASK 0x20u
screamer 0:c5e2f793b59a 9637 #define PDB_SC_PDBIE_SHIFT 5
screamer 0:c5e2f793b59a 9638 #define PDB_SC_PDBIF_MASK 0x40u
screamer 0:c5e2f793b59a 9639 #define PDB_SC_PDBIF_SHIFT 6
screamer 0:c5e2f793b59a 9640 #define PDB_SC_PDBEN_MASK 0x80u
screamer 0:c5e2f793b59a 9641 #define PDB_SC_PDBEN_SHIFT 7
screamer 0:c5e2f793b59a 9642 #define PDB_SC_TRGSEL_MASK 0xF00u
screamer 0:c5e2f793b59a 9643 #define PDB_SC_TRGSEL_SHIFT 8
screamer 0:c5e2f793b59a 9644 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
screamer 0:c5e2f793b59a 9645 #define PDB_SC_PRESCALER_MASK 0x7000u
screamer 0:c5e2f793b59a 9646 #define PDB_SC_PRESCALER_SHIFT 12
screamer 0:c5e2f793b59a 9647 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
screamer 0:c5e2f793b59a 9648 #define PDB_SC_DMAEN_MASK 0x8000u
screamer 0:c5e2f793b59a 9649 #define PDB_SC_DMAEN_SHIFT 15
screamer 0:c5e2f793b59a 9650 #define PDB_SC_SWTRIG_MASK 0x10000u
screamer 0:c5e2f793b59a 9651 #define PDB_SC_SWTRIG_SHIFT 16
screamer 0:c5e2f793b59a 9652 #define PDB_SC_PDBEIE_MASK 0x20000u
screamer 0:c5e2f793b59a 9653 #define PDB_SC_PDBEIE_SHIFT 17
screamer 0:c5e2f793b59a 9654 #define PDB_SC_LDMOD_MASK 0xC0000u
screamer 0:c5e2f793b59a 9655 #define PDB_SC_LDMOD_SHIFT 18
screamer 0:c5e2f793b59a 9656 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
screamer 0:c5e2f793b59a 9657 /* MOD Bit Fields */
screamer 0:c5e2f793b59a 9658 #define PDB_MOD_MOD_MASK 0xFFFFu
screamer 0:c5e2f793b59a 9659 #define PDB_MOD_MOD_SHIFT 0
screamer 0:c5e2f793b59a 9660 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
screamer 0:c5e2f793b59a 9661 /* CNT Bit Fields */
screamer 0:c5e2f793b59a 9662 #define PDB_CNT_CNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 9663 #define PDB_CNT_CNT_SHIFT 0
screamer 0:c5e2f793b59a 9664 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
screamer 0:c5e2f793b59a 9665 /* IDLY Bit Fields */
screamer 0:c5e2f793b59a 9666 #define PDB_IDLY_IDLY_MASK 0xFFFFu
screamer 0:c5e2f793b59a 9667 #define PDB_IDLY_IDLY_SHIFT 0
screamer 0:c5e2f793b59a 9668 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
screamer 0:c5e2f793b59a 9669 /* C1 Bit Fields */
screamer 0:c5e2f793b59a 9670 #define PDB_C1_EN_MASK 0xFFu
screamer 0:c5e2f793b59a 9671 #define PDB_C1_EN_SHIFT 0
screamer 0:c5e2f793b59a 9672 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
screamer 0:c5e2f793b59a 9673 #define PDB_C1_TOS_MASK 0xFF00u
screamer 0:c5e2f793b59a 9674 #define PDB_C1_TOS_SHIFT 8
screamer 0:c5e2f793b59a 9675 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
screamer 0:c5e2f793b59a 9676 #define PDB_C1_BB_MASK 0xFF0000u
screamer 0:c5e2f793b59a 9677 #define PDB_C1_BB_SHIFT 16
screamer 0:c5e2f793b59a 9678 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
screamer 0:c5e2f793b59a 9679 /* S Bit Fields */
screamer 0:c5e2f793b59a 9680 #define PDB_S_ERR_MASK 0xFFu
screamer 0:c5e2f793b59a 9681 #define PDB_S_ERR_SHIFT 0
screamer 0:c5e2f793b59a 9682 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
screamer 0:c5e2f793b59a 9683 #define PDB_S_CF_MASK 0xFF0000u
screamer 0:c5e2f793b59a 9684 #define PDB_S_CF_SHIFT 16
screamer 0:c5e2f793b59a 9685 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
screamer 0:c5e2f793b59a 9686 /* DLY Bit Fields */
screamer 0:c5e2f793b59a 9687 #define PDB_DLY_DLY_MASK 0xFFFFu
screamer 0:c5e2f793b59a 9688 #define PDB_DLY_DLY_SHIFT 0
screamer 0:c5e2f793b59a 9689 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
screamer 0:c5e2f793b59a 9690 /* INTC Bit Fields */
screamer 0:c5e2f793b59a 9691 #define PDB_INTC_TOE_MASK 0x1u
screamer 0:c5e2f793b59a 9692 #define PDB_INTC_TOE_SHIFT 0
screamer 0:c5e2f793b59a 9693 #define PDB_INTC_EXT_MASK 0x2u
screamer 0:c5e2f793b59a 9694 #define PDB_INTC_EXT_SHIFT 1
screamer 0:c5e2f793b59a 9695 /* INT Bit Fields */
screamer 0:c5e2f793b59a 9696 #define PDB_INT_INT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 9697 #define PDB_INT_INT_SHIFT 0
screamer 0:c5e2f793b59a 9698 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
screamer 0:c5e2f793b59a 9699 /* POEN Bit Fields */
screamer 0:c5e2f793b59a 9700 #define PDB_POEN_POEN_MASK 0xFFu
screamer 0:c5e2f793b59a 9701 #define PDB_POEN_POEN_SHIFT 0
screamer 0:c5e2f793b59a 9702 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
screamer 0:c5e2f793b59a 9703 /* PODLY Bit Fields */
screamer 0:c5e2f793b59a 9704 #define PDB_PODLY_DLY2_MASK 0xFFFFu
screamer 0:c5e2f793b59a 9705 #define PDB_PODLY_DLY2_SHIFT 0
screamer 0:c5e2f793b59a 9706 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
screamer 0:c5e2f793b59a 9707 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 9708 #define PDB_PODLY_DLY1_SHIFT 16
screamer 0:c5e2f793b59a 9709 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
screamer 0:c5e2f793b59a 9710
screamer 0:c5e2f793b59a 9711 /*!
screamer 0:c5e2f793b59a 9712 * @}
screamer 0:c5e2f793b59a 9713 */ /* end of group PDB_Register_Masks */
screamer 0:c5e2f793b59a 9714
screamer 0:c5e2f793b59a 9715
screamer 0:c5e2f793b59a 9716 /* PDB - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 9717 /** Peripheral PDB0 base address */
screamer 0:c5e2f793b59a 9718 #define PDB0_BASE (0x40036000u)
screamer 0:c5e2f793b59a 9719 /** Peripheral PDB0 base pointer */
screamer 0:c5e2f793b59a 9720 #define PDB0 ((PDB_Type *)PDB0_BASE)
screamer 0:c5e2f793b59a 9721 #define PDB0_BASE_PTR (PDB0)
screamer 0:c5e2f793b59a 9722 /** Array initializer of PDB peripheral base addresses */
screamer 0:c5e2f793b59a 9723 #define PDB_BASE_ADDRS { PDB0_BASE }
screamer 0:c5e2f793b59a 9724 /** Array initializer of PDB peripheral base pointers */
screamer 0:c5e2f793b59a 9725 #define PDB_BASE_PTRS { PDB0 }
screamer 0:c5e2f793b59a 9726 /** Interrupt vectors for the PDB peripheral type */
screamer 0:c5e2f793b59a 9727 #define PDB_IRQS { PDB0_IRQn }
screamer 0:c5e2f793b59a 9728
screamer 0:c5e2f793b59a 9729 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9730 -- PDB - Register accessor macros
screamer 0:c5e2f793b59a 9731 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9732
screamer 0:c5e2f793b59a 9733 /*!
screamer 0:c5e2f793b59a 9734 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
screamer 0:c5e2f793b59a 9735 * @{
screamer 0:c5e2f793b59a 9736 */
screamer 0:c5e2f793b59a 9737
screamer 0:c5e2f793b59a 9738
screamer 0:c5e2f793b59a 9739 /* PDB - Register instance definitions */
screamer 0:c5e2f793b59a 9740 /* PDB0 */
screamer 0:c5e2f793b59a 9741 #define PDB0_SC PDB_SC_REG(PDB0)
screamer 0:c5e2f793b59a 9742 #define PDB0_MOD PDB_MOD_REG(PDB0)
screamer 0:c5e2f793b59a 9743 #define PDB0_CNT PDB_CNT_REG(PDB0)
screamer 0:c5e2f793b59a 9744 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
screamer 0:c5e2f793b59a 9745 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
screamer 0:c5e2f793b59a 9746 #define PDB0_CH0S PDB_S_REG(PDB0,0)
screamer 0:c5e2f793b59a 9747 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
screamer 0:c5e2f793b59a 9748 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
screamer 0:c5e2f793b59a 9749 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
screamer 0:c5e2f793b59a 9750 #define PDB0_CH1S PDB_S_REG(PDB0,1)
screamer 0:c5e2f793b59a 9751 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
screamer 0:c5e2f793b59a 9752 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
screamer 0:c5e2f793b59a 9753 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
screamer 0:c5e2f793b59a 9754 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
screamer 0:c5e2f793b59a 9755 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
screamer 0:c5e2f793b59a 9756 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
screamer 0:c5e2f793b59a 9757 #define PDB0_POEN PDB_POEN_REG(PDB0)
screamer 0:c5e2f793b59a 9758 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
screamer 0:c5e2f793b59a 9759 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
screamer 0:c5e2f793b59a 9760 #define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
screamer 0:c5e2f793b59a 9761
screamer 0:c5e2f793b59a 9762 /* PDB - Register array accessors */
screamer 0:c5e2f793b59a 9763 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
screamer 0:c5e2f793b59a 9764 #define PDB0_S(index) PDB_S_REG(PDB0,index)
screamer 0:c5e2f793b59a 9765 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
screamer 0:c5e2f793b59a 9766 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
screamer 0:c5e2f793b59a 9767 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
screamer 0:c5e2f793b59a 9768 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
screamer 0:c5e2f793b59a 9769
screamer 0:c5e2f793b59a 9770 /*!
screamer 0:c5e2f793b59a 9771 * @}
screamer 0:c5e2f793b59a 9772 */ /* end of group PDB_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9773
screamer 0:c5e2f793b59a 9774
screamer 0:c5e2f793b59a 9775 /*!
screamer 0:c5e2f793b59a 9776 * @}
screamer 0:c5e2f793b59a 9777 */ /* end of group PDB_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 9778
screamer 0:c5e2f793b59a 9779
screamer 0:c5e2f793b59a 9780 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9781 -- PIT Peripheral Access Layer
screamer 0:c5e2f793b59a 9782 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9783
screamer 0:c5e2f793b59a 9784 /*!
screamer 0:c5e2f793b59a 9785 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
screamer 0:c5e2f793b59a 9786 * @{
screamer 0:c5e2f793b59a 9787 */
screamer 0:c5e2f793b59a 9788
screamer 0:c5e2f793b59a 9789 /** PIT - Register Layout Typedef */
screamer 0:c5e2f793b59a 9790 typedef struct {
screamer 0:c5e2f793b59a 9791 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
screamer 0:c5e2f793b59a 9792 uint8_t RESERVED_0[252];
screamer 0:c5e2f793b59a 9793 struct { /* offset: 0x100, array step: 0x10 */
screamer 0:c5e2f793b59a 9794 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
screamer 0:c5e2f793b59a 9795 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
screamer 0:c5e2f793b59a 9796 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
screamer 0:c5e2f793b59a 9797 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
screamer 0:c5e2f793b59a 9798 } CHANNEL[4];
screamer 0:c5e2f793b59a 9799 } PIT_Type, *PIT_MemMapPtr;
screamer 0:c5e2f793b59a 9800
screamer 0:c5e2f793b59a 9801 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9802 -- PIT - Register accessor macros
screamer 0:c5e2f793b59a 9803 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9804
screamer 0:c5e2f793b59a 9805 /*!
screamer 0:c5e2f793b59a 9806 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
screamer 0:c5e2f793b59a 9807 * @{
screamer 0:c5e2f793b59a 9808 */
screamer 0:c5e2f793b59a 9809
screamer 0:c5e2f793b59a 9810
screamer 0:c5e2f793b59a 9811 /* PIT - Register accessors */
screamer 0:c5e2f793b59a 9812 #define PIT_MCR_REG(base) ((base)->MCR)
screamer 0:c5e2f793b59a 9813 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
screamer 0:c5e2f793b59a 9814 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
screamer 0:c5e2f793b59a 9815 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
screamer 0:c5e2f793b59a 9816 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
screamer 0:c5e2f793b59a 9817
screamer 0:c5e2f793b59a 9818 /*!
screamer 0:c5e2f793b59a 9819 * @}
screamer 0:c5e2f793b59a 9820 */ /* end of group PIT_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9821
screamer 0:c5e2f793b59a 9822
screamer 0:c5e2f793b59a 9823 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9824 -- PIT Register Masks
screamer 0:c5e2f793b59a 9825 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9826
screamer 0:c5e2f793b59a 9827 /*!
screamer 0:c5e2f793b59a 9828 * @addtogroup PIT_Register_Masks PIT Register Masks
screamer 0:c5e2f793b59a 9829 * @{
screamer 0:c5e2f793b59a 9830 */
screamer 0:c5e2f793b59a 9831
screamer 0:c5e2f793b59a 9832 /* MCR Bit Fields */
screamer 0:c5e2f793b59a 9833 #define PIT_MCR_FRZ_MASK 0x1u
screamer 0:c5e2f793b59a 9834 #define PIT_MCR_FRZ_SHIFT 0
screamer 0:c5e2f793b59a 9835 #define PIT_MCR_MDIS_MASK 0x2u
screamer 0:c5e2f793b59a 9836 #define PIT_MCR_MDIS_SHIFT 1
screamer 0:c5e2f793b59a 9837 /* LDVAL Bit Fields */
screamer 0:c5e2f793b59a 9838 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 9839 #define PIT_LDVAL_TSV_SHIFT 0
screamer 0:c5e2f793b59a 9840 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
screamer 0:c5e2f793b59a 9841 /* CVAL Bit Fields */
screamer 0:c5e2f793b59a 9842 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 9843 #define PIT_CVAL_TVL_SHIFT 0
screamer 0:c5e2f793b59a 9844 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
screamer 0:c5e2f793b59a 9845 /* TCTRL Bit Fields */
screamer 0:c5e2f793b59a 9846 #define PIT_TCTRL_TEN_MASK 0x1u
screamer 0:c5e2f793b59a 9847 #define PIT_TCTRL_TEN_SHIFT 0
screamer 0:c5e2f793b59a 9848 #define PIT_TCTRL_TIE_MASK 0x2u
screamer 0:c5e2f793b59a 9849 #define PIT_TCTRL_TIE_SHIFT 1
screamer 0:c5e2f793b59a 9850 #define PIT_TCTRL_CHN_MASK 0x4u
screamer 0:c5e2f793b59a 9851 #define PIT_TCTRL_CHN_SHIFT 2
screamer 0:c5e2f793b59a 9852 /* TFLG Bit Fields */
screamer 0:c5e2f793b59a 9853 #define PIT_TFLG_TIF_MASK 0x1u
screamer 0:c5e2f793b59a 9854 #define PIT_TFLG_TIF_SHIFT 0
screamer 0:c5e2f793b59a 9855
screamer 0:c5e2f793b59a 9856 /*!
screamer 0:c5e2f793b59a 9857 * @}
screamer 0:c5e2f793b59a 9858 */ /* end of group PIT_Register_Masks */
screamer 0:c5e2f793b59a 9859
screamer 0:c5e2f793b59a 9860
screamer 0:c5e2f793b59a 9861 /* PIT - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 9862 /** Peripheral PIT base address */
screamer 0:c5e2f793b59a 9863 #define PIT_BASE (0x40037000u)
screamer 0:c5e2f793b59a 9864 /** Peripheral PIT base pointer */
screamer 0:c5e2f793b59a 9865 #define PIT ((PIT_Type *)PIT_BASE)
screamer 0:c5e2f793b59a 9866 #define PIT_BASE_PTR (PIT)
screamer 0:c5e2f793b59a 9867 /** Array initializer of PIT peripheral base addresses */
screamer 0:c5e2f793b59a 9868 #define PIT_BASE_ADDRS { PIT_BASE }
screamer 0:c5e2f793b59a 9869 /** Array initializer of PIT peripheral base pointers */
screamer 0:c5e2f793b59a 9870 #define PIT_BASE_PTRS { PIT }
screamer 0:c5e2f793b59a 9871 /** Interrupt vectors for the PIT peripheral type */
screamer 0:c5e2f793b59a 9872 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
screamer 0:c5e2f793b59a 9873
screamer 0:c5e2f793b59a 9874 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9875 -- PIT - Register accessor macros
screamer 0:c5e2f793b59a 9876 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9877
screamer 0:c5e2f793b59a 9878 /*!
screamer 0:c5e2f793b59a 9879 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
screamer 0:c5e2f793b59a 9880 * @{
screamer 0:c5e2f793b59a 9881 */
screamer 0:c5e2f793b59a 9882
screamer 0:c5e2f793b59a 9883
screamer 0:c5e2f793b59a 9884 /* PIT - Register instance definitions */
screamer 0:c5e2f793b59a 9885 /* PIT */
screamer 0:c5e2f793b59a 9886 #define PIT_MCR PIT_MCR_REG(PIT)
screamer 0:c5e2f793b59a 9887 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
screamer 0:c5e2f793b59a 9888 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
screamer 0:c5e2f793b59a 9889 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
screamer 0:c5e2f793b59a 9890 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
screamer 0:c5e2f793b59a 9891 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
screamer 0:c5e2f793b59a 9892 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
screamer 0:c5e2f793b59a 9893 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
screamer 0:c5e2f793b59a 9894 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
screamer 0:c5e2f793b59a 9895 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
screamer 0:c5e2f793b59a 9896 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
screamer 0:c5e2f793b59a 9897 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
screamer 0:c5e2f793b59a 9898 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
screamer 0:c5e2f793b59a 9899 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
screamer 0:c5e2f793b59a 9900 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
screamer 0:c5e2f793b59a 9901 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
screamer 0:c5e2f793b59a 9902 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
screamer 0:c5e2f793b59a 9903
screamer 0:c5e2f793b59a 9904 /* PIT - Register array accessors */
screamer 0:c5e2f793b59a 9905 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
screamer 0:c5e2f793b59a 9906 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
screamer 0:c5e2f793b59a 9907 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
screamer 0:c5e2f793b59a 9908 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
screamer 0:c5e2f793b59a 9909
screamer 0:c5e2f793b59a 9910 /*!
screamer 0:c5e2f793b59a 9911 * @}
screamer 0:c5e2f793b59a 9912 */ /* end of group PIT_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9913
screamer 0:c5e2f793b59a 9914
screamer 0:c5e2f793b59a 9915 /*!
screamer 0:c5e2f793b59a 9916 * @}
screamer 0:c5e2f793b59a 9917 */ /* end of group PIT_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 9918
screamer 0:c5e2f793b59a 9919
screamer 0:c5e2f793b59a 9920 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9921 -- PMC Peripheral Access Layer
screamer 0:c5e2f793b59a 9922 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9923
screamer 0:c5e2f793b59a 9924 /*!
screamer 0:c5e2f793b59a 9925 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
screamer 0:c5e2f793b59a 9926 * @{
screamer 0:c5e2f793b59a 9927 */
screamer 0:c5e2f793b59a 9928
screamer 0:c5e2f793b59a 9929 /** PMC - Register Layout Typedef */
screamer 0:c5e2f793b59a 9930 typedef struct {
screamer 0:c5e2f793b59a 9931 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
screamer 0:c5e2f793b59a 9932 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
screamer 0:c5e2f793b59a 9933 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
screamer 0:c5e2f793b59a 9934 } PMC_Type, *PMC_MemMapPtr;
screamer 0:c5e2f793b59a 9935
screamer 0:c5e2f793b59a 9936 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9937 -- PMC - Register accessor macros
screamer 0:c5e2f793b59a 9938 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9939
screamer 0:c5e2f793b59a 9940 /*!
screamer 0:c5e2f793b59a 9941 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
screamer 0:c5e2f793b59a 9942 * @{
screamer 0:c5e2f793b59a 9943 */
screamer 0:c5e2f793b59a 9944
screamer 0:c5e2f793b59a 9945
screamer 0:c5e2f793b59a 9946 /* PMC - Register accessors */
screamer 0:c5e2f793b59a 9947 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
screamer 0:c5e2f793b59a 9948 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
screamer 0:c5e2f793b59a 9949 #define PMC_REGSC_REG(base) ((base)->REGSC)
screamer 0:c5e2f793b59a 9950
screamer 0:c5e2f793b59a 9951 /*!
screamer 0:c5e2f793b59a 9952 * @}
screamer 0:c5e2f793b59a 9953 */ /* end of group PMC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 9954
screamer 0:c5e2f793b59a 9955
screamer 0:c5e2f793b59a 9956 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 9957 -- PMC Register Masks
screamer 0:c5e2f793b59a 9958 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 9959
screamer 0:c5e2f793b59a 9960 /*!
screamer 0:c5e2f793b59a 9961 * @addtogroup PMC_Register_Masks PMC Register Masks
screamer 0:c5e2f793b59a 9962 * @{
screamer 0:c5e2f793b59a 9963 */
screamer 0:c5e2f793b59a 9964
screamer 0:c5e2f793b59a 9965 /* LVDSC1 Bit Fields */
screamer 0:c5e2f793b59a 9966 #define PMC_LVDSC1_LVDV_MASK 0x3u
screamer 0:c5e2f793b59a 9967 #define PMC_LVDSC1_LVDV_SHIFT 0
screamer 0:c5e2f793b59a 9968 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
screamer 0:c5e2f793b59a 9969 #define PMC_LVDSC1_LVDRE_MASK 0x10u
screamer 0:c5e2f793b59a 9970 #define PMC_LVDSC1_LVDRE_SHIFT 4
screamer 0:c5e2f793b59a 9971 #define PMC_LVDSC1_LVDIE_MASK 0x20u
screamer 0:c5e2f793b59a 9972 #define PMC_LVDSC1_LVDIE_SHIFT 5
screamer 0:c5e2f793b59a 9973 #define PMC_LVDSC1_LVDACK_MASK 0x40u
screamer 0:c5e2f793b59a 9974 #define PMC_LVDSC1_LVDACK_SHIFT 6
screamer 0:c5e2f793b59a 9975 #define PMC_LVDSC1_LVDF_MASK 0x80u
screamer 0:c5e2f793b59a 9976 #define PMC_LVDSC1_LVDF_SHIFT 7
screamer 0:c5e2f793b59a 9977 /* LVDSC2 Bit Fields */
screamer 0:c5e2f793b59a 9978 #define PMC_LVDSC2_LVWV_MASK 0x3u
screamer 0:c5e2f793b59a 9979 #define PMC_LVDSC2_LVWV_SHIFT 0
screamer 0:c5e2f793b59a 9980 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
screamer 0:c5e2f793b59a 9981 #define PMC_LVDSC2_LVWIE_MASK 0x20u
screamer 0:c5e2f793b59a 9982 #define PMC_LVDSC2_LVWIE_SHIFT 5
screamer 0:c5e2f793b59a 9983 #define PMC_LVDSC2_LVWACK_MASK 0x40u
screamer 0:c5e2f793b59a 9984 #define PMC_LVDSC2_LVWACK_SHIFT 6
screamer 0:c5e2f793b59a 9985 #define PMC_LVDSC2_LVWF_MASK 0x80u
screamer 0:c5e2f793b59a 9986 #define PMC_LVDSC2_LVWF_SHIFT 7
screamer 0:c5e2f793b59a 9987 /* REGSC Bit Fields */
screamer 0:c5e2f793b59a 9988 #define PMC_REGSC_BGBE_MASK 0x1u
screamer 0:c5e2f793b59a 9989 #define PMC_REGSC_BGBE_SHIFT 0
screamer 0:c5e2f793b59a 9990 #define PMC_REGSC_REGONS_MASK 0x4u
screamer 0:c5e2f793b59a 9991 #define PMC_REGSC_REGONS_SHIFT 2
screamer 0:c5e2f793b59a 9992 #define PMC_REGSC_ACKISO_MASK 0x8u
screamer 0:c5e2f793b59a 9993 #define PMC_REGSC_ACKISO_SHIFT 3
screamer 0:c5e2f793b59a 9994 #define PMC_REGSC_BGEN_MASK 0x10u
screamer 0:c5e2f793b59a 9995 #define PMC_REGSC_BGEN_SHIFT 4
screamer 0:c5e2f793b59a 9996
screamer 0:c5e2f793b59a 9997 /*!
screamer 0:c5e2f793b59a 9998 * @}
screamer 0:c5e2f793b59a 9999 */ /* end of group PMC_Register_Masks */
screamer 0:c5e2f793b59a 10000
screamer 0:c5e2f793b59a 10001
screamer 0:c5e2f793b59a 10002 /* PMC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 10003 /** Peripheral PMC base address */
screamer 0:c5e2f793b59a 10004 #define PMC_BASE (0x4007D000u)
screamer 0:c5e2f793b59a 10005 /** Peripheral PMC base pointer */
screamer 0:c5e2f793b59a 10006 #define PMC ((PMC_Type *)PMC_BASE)
screamer 0:c5e2f793b59a 10007 #define PMC_BASE_PTR (PMC)
screamer 0:c5e2f793b59a 10008 /** Array initializer of PMC peripheral base addresses */
screamer 0:c5e2f793b59a 10009 #define PMC_BASE_ADDRS { PMC_BASE }
screamer 0:c5e2f793b59a 10010 /** Array initializer of PMC peripheral base pointers */
screamer 0:c5e2f793b59a 10011 #define PMC_BASE_PTRS { PMC }
screamer 0:c5e2f793b59a 10012 /** Interrupt vectors for the PMC peripheral type */
screamer 0:c5e2f793b59a 10013 #define PMC_IRQS { LVD_LVW_IRQn }
screamer 0:c5e2f793b59a 10014
screamer 0:c5e2f793b59a 10015 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10016 -- PMC - Register accessor macros
screamer 0:c5e2f793b59a 10017 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10018
screamer 0:c5e2f793b59a 10019 /*!
screamer 0:c5e2f793b59a 10020 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
screamer 0:c5e2f793b59a 10021 * @{
screamer 0:c5e2f793b59a 10022 */
screamer 0:c5e2f793b59a 10023
screamer 0:c5e2f793b59a 10024
screamer 0:c5e2f793b59a 10025 /* PMC - Register instance definitions */
screamer 0:c5e2f793b59a 10026 /* PMC */
screamer 0:c5e2f793b59a 10027 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
screamer 0:c5e2f793b59a 10028 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
screamer 0:c5e2f793b59a 10029 #define PMC_REGSC PMC_REGSC_REG(PMC)
screamer 0:c5e2f793b59a 10030
screamer 0:c5e2f793b59a 10031 /*!
screamer 0:c5e2f793b59a 10032 * @}
screamer 0:c5e2f793b59a 10033 */ /* end of group PMC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10034
screamer 0:c5e2f793b59a 10035
screamer 0:c5e2f793b59a 10036 /*!
screamer 0:c5e2f793b59a 10037 * @}
screamer 0:c5e2f793b59a 10038 */ /* end of group PMC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 10039
screamer 0:c5e2f793b59a 10040
screamer 0:c5e2f793b59a 10041 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10042 -- PORT Peripheral Access Layer
screamer 0:c5e2f793b59a 10043 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10044
screamer 0:c5e2f793b59a 10045 /*!
screamer 0:c5e2f793b59a 10046 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
screamer 0:c5e2f793b59a 10047 * @{
screamer 0:c5e2f793b59a 10048 */
screamer 0:c5e2f793b59a 10049
screamer 0:c5e2f793b59a 10050 /** PORT - Register Layout Typedef */
screamer 0:c5e2f793b59a 10051 typedef struct {
screamer 0:c5e2f793b59a 10052 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
screamer 0:c5e2f793b59a 10053 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
screamer 0:c5e2f793b59a 10054 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
screamer 0:c5e2f793b59a 10055 uint8_t RESERVED_0[24];
screamer 0:c5e2f793b59a 10056 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
screamer 0:c5e2f793b59a 10057 uint8_t RESERVED_1[28];
screamer 0:c5e2f793b59a 10058 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
screamer 0:c5e2f793b59a 10059 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
screamer 0:c5e2f793b59a 10060 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
screamer 0:c5e2f793b59a 10061 } PORT_Type, *PORT_MemMapPtr;
screamer 0:c5e2f793b59a 10062
screamer 0:c5e2f793b59a 10063 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10064 -- PORT - Register accessor macros
screamer 0:c5e2f793b59a 10065 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10066
screamer 0:c5e2f793b59a 10067 /*!
screamer 0:c5e2f793b59a 10068 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
screamer 0:c5e2f793b59a 10069 * @{
screamer 0:c5e2f793b59a 10070 */
screamer 0:c5e2f793b59a 10071
screamer 0:c5e2f793b59a 10072
screamer 0:c5e2f793b59a 10073 /* PORT - Register accessors */
screamer 0:c5e2f793b59a 10074 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
screamer 0:c5e2f793b59a 10075 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
screamer 0:c5e2f793b59a 10076 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
screamer 0:c5e2f793b59a 10077 #define PORT_ISFR_REG(base) ((base)->ISFR)
screamer 0:c5e2f793b59a 10078 #define PORT_DFER_REG(base) ((base)->DFER)
screamer 0:c5e2f793b59a 10079 #define PORT_DFCR_REG(base) ((base)->DFCR)
screamer 0:c5e2f793b59a 10080 #define PORT_DFWR_REG(base) ((base)->DFWR)
screamer 0:c5e2f793b59a 10081
screamer 0:c5e2f793b59a 10082 /*!
screamer 0:c5e2f793b59a 10083 * @}
screamer 0:c5e2f793b59a 10084 */ /* end of group PORT_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10085
screamer 0:c5e2f793b59a 10086
screamer 0:c5e2f793b59a 10087 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10088 -- PORT Register Masks
screamer 0:c5e2f793b59a 10089 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10090
screamer 0:c5e2f793b59a 10091 /*!
screamer 0:c5e2f793b59a 10092 * @addtogroup PORT_Register_Masks PORT Register Masks
screamer 0:c5e2f793b59a 10093 * @{
screamer 0:c5e2f793b59a 10094 */
screamer 0:c5e2f793b59a 10095
screamer 0:c5e2f793b59a 10096 /* PCR Bit Fields */
screamer 0:c5e2f793b59a 10097 #define PORT_PCR_PS_MASK 0x1u
screamer 0:c5e2f793b59a 10098 #define PORT_PCR_PS_SHIFT 0
screamer 0:c5e2f793b59a 10099 #define PORT_PCR_PE_MASK 0x2u
screamer 0:c5e2f793b59a 10100 #define PORT_PCR_PE_SHIFT 1
screamer 0:c5e2f793b59a 10101 #define PORT_PCR_SRE_MASK 0x4u
screamer 0:c5e2f793b59a 10102 #define PORT_PCR_SRE_SHIFT 2
screamer 0:c5e2f793b59a 10103 #define PORT_PCR_PFE_MASK 0x10u
screamer 0:c5e2f793b59a 10104 #define PORT_PCR_PFE_SHIFT 4
screamer 0:c5e2f793b59a 10105 #define PORT_PCR_ODE_MASK 0x20u
screamer 0:c5e2f793b59a 10106 #define PORT_PCR_ODE_SHIFT 5
screamer 0:c5e2f793b59a 10107 #define PORT_PCR_DSE_MASK 0x40u
screamer 0:c5e2f793b59a 10108 #define PORT_PCR_DSE_SHIFT 6
screamer 0:c5e2f793b59a 10109 #define PORT_PCR_MUX_MASK 0x700u
screamer 0:c5e2f793b59a 10110 #define PORT_PCR_MUX_SHIFT 8
screamer 0:c5e2f793b59a 10111 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
screamer 0:c5e2f793b59a 10112 #define PORT_PCR_LK_MASK 0x8000u
screamer 0:c5e2f793b59a 10113 #define PORT_PCR_LK_SHIFT 15
screamer 0:c5e2f793b59a 10114 #define PORT_PCR_IRQC_MASK 0xF0000u
screamer 0:c5e2f793b59a 10115 #define PORT_PCR_IRQC_SHIFT 16
screamer 0:c5e2f793b59a 10116 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
screamer 0:c5e2f793b59a 10117 #define PORT_PCR_ISF_MASK 0x1000000u
screamer 0:c5e2f793b59a 10118 #define PORT_PCR_ISF_SHIFT 24
screamer 0:c5e2f793b59a 10119 /* GPCLR Bit Fields */
screamer 0:c5e2f793b59a 10120 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
screamer 0:c5e2f793b59a 10121 #define PORT_GPCLR_GPWD_SHIFT 0
screamer 0:c5e2f793b59a 10122 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
screamer 0:c5e2f793b59a 10123 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 10124 #define PORT_GPCLR_GPWE_SHIFT 16
screamer 0:c5e2f793b59a 10125 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
screamer 0:c5e2f793b59a 10126 /* GPCHR Bit Fields */
screamer 0:c5e2f793b59a 10127 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
screamer 0:c5e2f793b59a 10128 #define PORT_GPCHR_GPWD_SHIFT 0
screamer 0:c5e2f793b59a 10129 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
screamer 0:c5e2f793b59a 10130 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 10131 #define PORT_GPCHR_GPWE_SHIFT 16
screamer 0:c5e2f793b59a 10132 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
screamer 0:c5e2f793b59a 10133 /* ISFR Bit Fields */
screamer 0:c5e2f793b59a 10134 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 10135 #define PORT_ISFR_ISF_SHIFT 0
screamer 0:c5e2f793b59a 10136 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
screamer 0:c5e2f793b59a 10137 /* DFER Bit Fields */
screamer 0:c5e2f793b59a 10138 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 10139 #define PORT_DFER_DFE_SHIFT 0
screamer 0:c5e2f793b59a 10140 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
screamer 0:c5e2f793b59a 10141 /* DFCR Bit Fields */
screamer 0:c5e2f793b59a 10142 #define PORT_DFCR_CS_MASK 0x1u
screamer 0:c5e2f793b59a 10143 #define PORT_DFCR_CS_SHIFT 0
screamer 0:c5e2f793b59a 10144 /* DFWR Bit Fields */
screamer 0:c5e2f793b59a 10145 #define PORT_DFWR_FILT_MASK 0x1Fu
screamer 0:c5e2f793b59a 10146 #define PORT_DFWR_FILT_SHIFT 0
screamer 0:c5e2f793b59a 10147 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
screamer 0:c5e2f793b59a 10148
screamer 0:c5e2f793b59a 10149 /*!
screamer 0:c5e2f793b59a 10150 * @}
screamer 0:c5e2f793b59a 10151 */ /* end of group PORT_Register_Masks */
screamer 0:c5e2f793b59a 10152
screamer 0:c5e2f793b59a 10153
screamer 0:c5e2f793b59a 10154 /* PORT - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 10155 /** Peripheral PORTA base address */
screamer 0:c5e2f793b59a 10156 #define PORTA_BASE (0x40049000u)
screamer 0:c5e2f793b59a 10157 /** Peripheral PORTA base pointer */
screamer 0:c5e2f793b59a 10158 #define PORTA ((PORT_Type *)PORTA_BASE)
screamer 0:c5e2f793b59a 10159 #define PORTA_BASE_PTR (PORTA)
screamer 0:c5e2f793b59a 10160 /** Peripheral PORTB base address */
screamer 0:c5e2f793b59a 10161 #define PORTB_BASE (0x4004A000u)
screamer 0:c5e2f793b59a 10162 /** Peripheral PORTB base pointer */
screamer 0:c5e2f793b59a 10163 #define PORTB ((PORT_Type *)PORTB_BASE)
screamer 0:c5e2f793b59a 10164 #define PORTB_BASE_PTR (PORTB)
screamer 0:c5e2f793b59a 10165 /** Peripheral PORTC base address */
screamer 0:c5e2f793b59a 10166 #define PORTC_BASE (0x4004B000u)
screamer 0:c5e2f793b59a 10167 /** Peripheral PORTC base pointer */
screamer 0:c5e2f793b59a 10168 #define PORTC ((PORT_Type *)PORTC_BASE)
screamer 0:c5e2f793b59a 10169 #define PORTC_BASE_PTR (PORTC)
screamer 0:c5e2f793b59a 10170 /** Peripheral PORTD base address */
screamer 0:c5e2f793b59a 10171 #define PORTD_BASE (0x4004C000u)
screamer 0:c5e2f793b59a 10172 /** Peripheral PORTD base pointer */
screamer 0:c5e2f793b59a 10173 #define PORTD ((PORT_Type *)PORTD_BASE)
screamer 0:c5e2f793b59a 10174 #define PORTD_BASE_PTR (PORTD)
screamer 0:c5e2f793b59a 10175 /** Peripheral PORTE base address */
screamer 0:c5e2f793b59a 10176 #define PORTE_BASE (0x4004D000u)
screamer 0:c5e2f793b59a 10177 /** Peripheral PORTE base pointer */
screamer 0:c5e2f793b59a 10178 #define PORTE ((PORT_Type *)PORTE_BASE)
screamer 0:c5e2f793b59a 10179 #define PORTE_BASE_PTR (PORTE)
screamer 0:c5e2f793b59a 10180 /** Array initializer of PORT peripheral base addresses */
screamer 0:c5e2f793b59a 10181 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
screamer 0:c5e2f793b59a 10182 /** Array initializer of PORT peripheral base pointers */
screamer 0:c5e2f793b59a 10183 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
screamer 0:c5e2f793b59a 10184 /** Interrupt vectors for the PORT peripheral type */
screamer 0:c5e2f793b59a 10185 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
screamer 0:c5e2f793b59a 10186
screamer 0:c5e2f793b59a 10187 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10188 -- PORT - Register accessor macros
screamer 0:c5e2f793b59a 10189 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10190
screamer 0:c5e2f793b59a 10191 /*!
screamer 0:c5e2f793b59a 10192 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
screamer 0:c5e2f793b59a 10193 * @{
screamer 0:c5e2f793b59a 10194 */
screamer 0:c5e2f793b59a 10195
screamer 0:c5e2f793b59a 10196
screamer 0:c5e2f793b59a 10197 /* PORT - Register instance definitions */
screamer 0:c5e2f793b59a 10198 /* PORTA */
screamer 0:c5e2f793b59a 10199 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
screamer 0:c5e2f793b59a 10200 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
screamer 0:c5e2f793b59a 10201 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
screamer 0:c5e2f793b59a 10202 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
screamer 0:c5e2f793b59a 10203 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
screamer 0:c5e2f793b59a 10204 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
screamer 0:c5e2f793b59a 10205 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
screamer 0:c5e2f793b59a 10206 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
screamer 0:c5e2f793b59a 10207 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
screamer 0:c5e2f793b59a 10208 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
screamer 0:c5e2f793b59a 10209 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
screamer 0:c5e2f793b59a 10210 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
screamer 0:c5e2f793b59a 10211 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
screamer 0:c5e2f793b59a 10212 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
screamer 0:c5e2f793b59a 10213 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
screamer 0:c5e2f793b59a 10214 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
screamer 0:c5e2f793b59a 10215 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
screamer 0:c5e2f793b59a 10216 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
screamer 0:c5e2f793b59a 10217 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
screamer 0:c5e2f793b59a 10218 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
screamer 0:c5e2f793b59a 10219 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
screamer 0:c5e2f793b59a 10220 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
screamer 0:c5e2f793b59a 10221 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
screamer 0:c5e2f793b59a 10222 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
screamer 0:c5e2f793b59a 10223 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
screamer 0:c5e2f793b59a 10224 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
screamer 0:c5e2f793b59a 10225 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
screamer 0:c5e2f793b59a 10226 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
screamer 0:c5e2f793b59a 10227 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
screamer 0:c5e2f793b59a 10228 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
screamer 0:c5e2f793b59a 10229 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
screamer 0:c5e2f793b59a 10230 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
screamer 0:c5e2f793b59a 10231 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
screamer 0:c5e2f793b59a 10232 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
screamer 0:c5e2f793b59a 10233 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
screamer 0:c5e2f793b59a 10234 /* PORTB */
screamer 0:c5e2f793b59a 10235 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
screamer 0:c5e2f793b59a 10236 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
screamer 0:c5e2f793b59a 10237 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
screamer 0:c5e2f793b59a 10238 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
screamer 0:c5e2f793b59a 10239 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
screamer 0:c5e2f793b59a 10240 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
screamer 0:c5e2f793b59a 10241 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
screamer 0:c5e2f793b59a 10242 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
screamer 0:c5e2f793b59a 10243 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
screamer 0:c5e2f793b59a 10244 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
screamer 0:c5e2f793b59a 10245 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
screamer 0:c5e2f793b59a 10246 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
screamer 0:c5e2f793b59a 10247 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
screamer 0:c5e2f793b59a 10248 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
screamer 0:c5e2f793b59a 10249 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
screamer 0:c5e2f793b59a 10250 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
screamer 0:c5e2f793b59a 10251 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
screamer 0:c5e2f793b59a 10252 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
screamer 0:c5e2f793b59a 10253 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
screamer 0:c5e2f793b59a 10254 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
screamer 0:c5e2f793b59a 10255 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
screamer 0:c5e2f793b59a 10256 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
screamer 0:c5e2f793b59a 10257 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
screamer 0:c5e2f793b59a 10258 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
screamer 0:c5e2f793b59a 10259 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
screamer 0:c5e2f793b59a 10260 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
screamer 0:c5e2f793b59a 10261 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
screamer 0:c5e2f793b59a 10262 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
screamer 0:c5e2f793b59a 10263 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
screamer 0:c5e2f793b59a 10264 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
screamer 0:c5e2f793b59a 10265 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
screamer 0:c5e2f793b59a 10266 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
screamer 0:c5e2f793b59a 10267 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
screamer 0:c5e2f793b59a 10268 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
screamer 0:c5e2f793b59a 10269 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
screamer 0:c5e2f793b59a 10270 /* PORTC */
screamer 0:c5e2f793b59a 10271 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
screamer 0:c5e2f793b59a 10272 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
screamer 0:c5e2f793b59a 10273 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
screamer 0:c5e2f793b59a 10274 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
screamer 0:c5e2f793b59a 10275 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
screamer 0:c5e2f793b59a 10276 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
screamer 0:c5e2f793b59a 10277 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
screamer 0:c5e2f793b59a 10278 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
screamer 0:c5e2f793b59a 10279 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
screamer 0:c5e2f793b59a 10280 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
screamer 0:c5e2f793b59a 10281 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
screamer 0:c5e2f793b59a 10282 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
screamer 0:c5e2f793b59a 10283 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
screamer 0:c5e2f793b59a 10284 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
screamer 0:c5e2f793b59a 10285 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
screamer 0:c5e2f793b59a 10286 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
screamer 0:c5e2f793b59a 10287 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
screamer 0:c5e2f793b59a 10288 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
screamer 0:c5e2f793b59a 10289 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
screamer 0:c5e2f793b59a 10290 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
screamer 0:c5e2f793b59a 10291 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
screamer 0:c5e2f793b59a 10292 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
screamer 0:c5e2f793b59a 10293 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
screamer 0:c5e2f793b59a 10294 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
screamer 0:c5e2f793b59a 10295 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
screamer 0:c5e2f793b59a 10296 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
screamer 0:c5e2f793b59a 10297 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
screamer 0:c5e2f793b59a 10298 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
screamer 0:c5e2f793b59a 10299 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
screamer 0:c5e2f793b59a 10300 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
screamer 0:c5e2f793b59a 10301 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
screamer 0:c5e2f793b59a 10302 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
screamer 0:c5e2f793b59a 10303 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
screamer 0:c5e2f793b59a 10304 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
screamer 0:c5e2f793b59a 10305 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
screamer 0:c5e2f793b59a 10306 /* PORTD */
screamer 0:c5e2f793b59a 10307 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
screamer 0:c5e2f793b59a 10308 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
screamer 0:c5e2f793b59a 10309 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
screamer 0:c5e2f793b59a 10310 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
screamer 0:c5e2f793b59a 10311 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
screamer 0:c5e2f793b59a 10312 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
screamer 0:c5e2f793b59a 10313 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
screamer 0:c5e2f793b59a 10314 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
screamer 0:c5e2f793b59a 10315 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
screamer 0:c5e2f793b59a 10316 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
screamer 0:c5e2f793b59a 10317 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
screamer 0:c5e2f793b59a 10318 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
screamer 0:c5e2f793b59a 10319 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
screamer 0:c5e2f793b59a 10320 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
screamer 0:c5e2f793b59a 10321 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
screamer 0:c5e2f793b59a 10322 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
screamer 0:c5e2f793b59a 10323 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
screamer 0:c5e2f793b59a 10324 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
screamer 0:c5e2f793b59a 10325 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
screamer 0:c5e2f793b59a 10326 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
screamer 0:c5e2f793b59a 10327 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
screamer 0:c5e2f793b59a 10328 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
screamer 0:c5e2f793b59a 10329 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
screamer 0:c5e2f793b59a 10330 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
screamer 0:c5e2f793b59a 10331 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
screamer 0:c5e2f793b59a 10332 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
screamer 0:c5e2f793b59a 10333 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
screamer 0:c5e2f793b59a 10334 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
screamer 0:c5e2f793b59a 10335 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
screamer 0:c5e2f793b59a 10336 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
screamer 0:c5e2f793b59a 10337 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
screamer 0:c5e2f793b59a 10338 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
screamer 0:c5e2f793b59a 10339 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
screamer 0:c5e2f793b59a 10340 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
screamer 0:c5e2f793b59a 10341 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
screamer 0:c5e2f793b59a 10342 #define PORTD_DFER PORT_DFER_REG(PORTD)
screamer 0:c5e2f793b59a 10343 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
screamer 0:c5e2f793b59a 10344 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
screamer 0:c5e2f793b59a 10345 /* PORTE */
screamer 0:c5e2f793b59a 10346 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
screamer 0:c5e2f793b59a 10347 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
screamer 0:c5e2f793b59a 10348 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
screamer 0:c5e2f793b59a 10349 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
screamer 0:c5e2f793b59a 10350 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
screamer 0:c5e2f793b59a 10351 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
screamer 0:c5e2f793b59a 10352 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
screamer 0:c5e2f793b59a 10353 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
screamer 0:c5e2f793b59a 10354 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
screamer 0:c5e2f793b59a 10355 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
screamer 0:c5e2f793b59a 10356 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
screamer 0:c5e2f793b59a 10357 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
screamer 0:c5e2f793b59a 10358 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
screamer 0:c5e2f793b59a 10359 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
screamer 0:c5e2f793b59a 10360 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
screamer 0:c5e2f793b59a 10361 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
screamer 0:c5e2f793b59a 10362 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
screamer 0:c5e2f793b59a 10363 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
screamer 0:c5e2f793b59a 10364 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
screamer 0:c5e2f793b59a 10365 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
screamer 0:c5e2f793b59a 10366 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
screamer 0:c5e2f793b59a 10367 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
screamer 0:c5e2f793b59a 10368 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
screamer 0:c5e2f793b59a 10369 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
screamer 0:c5e2f793b59a 10370 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
screamer 0:c5e2f793b59a 10371 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
screamer 0:c5e2f793b59a 10372 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
screamer 0:c5e2f793b59a 10373 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
screamer 0:c5e2f793b59a 10374 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
screamer 0:c5e2f793b59a 10375 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
screamer 0:c5e2f793b59a 10376 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
screamer 0:c5e2f793b59a 10377 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
screamer 0:c5e2f793b59a 10378 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
screamer 0:c5e2f793b59a 10379 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
screamer 0:c5e2f793b59a 10380 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
screamer 0:c5e2f793b59a 10381
screamer 0:c5e2f793b59a 10382 /* PORT - Register array accessors */
screamer 0:c5e2f793b59a 10383 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
screamer 0:c5e2f793b59a 10384 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
screamer 0:c5e2f793b59a 10385 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
screamer 0:c5e2f793b59a 10386 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
screamer 0:c5e2f793b59a 10387 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
screamer 0:c5e2f793b59a 10388
screamer 0:c5e2f793b59a 10389 /*!
screamer 0:c5e2f793b59a 10390 * @}
screamer 0:c5e2f793b59a 10391 */ /* end of group PORT_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10392
screamer 0:c5e2f793b59a 10393
screamer 0:c5e2f793b59a 10394 /*!
screamer 0:c5e2f793b59a 10395 * @}
screamer 0:c5e2f793b59a 10396 */ /* end of group PORT_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 10397
screamer 0:c5e2f793b59a 10398
screamer 0:c5e2f793b59a 10399 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10400 -- RCM Peripheral Access Layer
screamer 0:c5e2f793b59a 10401 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10402
screamer 0:c5e2f793b59a 10403 /*!
screamer 0:c5e2f793b59a 10404 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
screamer 0:c5e2f793b59a 10405 * @{
screamer 0:c5e2f793b59a 10406 */
screamer 0:c5e2f793b59a 10407
screamer 0:c5e2f793b59a 10408 /** RCM - Register Layout Typedef */
screamer 0:c5e2f793b59a 10409 typedef struct {
screamer 0:c5e2f793b59a 10410 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
screamer 0:c5e2f793b59a 10411 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
screamer 0:c5e2f793b59a 10412 uint8_t RESERVED_0[2];
screamer 0:c5e2f793b59a 10413 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
screamer 0:c5e2f793b59a 10414 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
screamer 0:c5e2f793b59a 10415 uint8_t RESERVED_1[1];
screamer 0:c5e2f793b59a 10416 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
screamer 0:c5e2f793b59a 10417 } RCM_Type, *RCM_MemMapPtr;
screamer 0:c5e2f793b59a 10418
screamer 0:c5e2f793b59a 10419 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10420 -- RCM - Register accessor macros
screamer 0:c5e2f793b59a 10421 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10422
screamer 0:c5e2f793b59a 10423 /*!
screamer 0:c5e2f793b59a 10424 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
screamer 0:c5e2f793b59a 10425 * @{
screamer 0:c5e2f793b59a 10426 */
screamer 0:c5e2f793b59a 10427
screamer 0:c5e2f793b59a 10428
screamer 0:c5e2f793b59a 10429 /* RCM - Register accessors */
screamer 0:c5e2f793b59a 10430 #define RCM_SRS0_REG(base) ((base)->SRS0)
screamer 0:c5e2f793b59a 10431 #define RCM_SRS1_REG(base) ((base)->SRS1)
screamer 0:c5e2f793b59a 10432 #define RCM_RPFC_REG(base) ((base)->RPFC)
screamer 0:c5e2f793b59a 10433 #define RCM_RPFW_REG(base) ((base)->RPFW)
screamer 0:c5e2f793b59a 10434 #define RCM_MR_REG(base) ((base)->MR)
screamer 0:c5e2f793b59a 10435
screamer 0:c5e2f793b59a 10436 /*!
screamer 0:c5e2f793b59a 10437 * @}
screamer 0:c5e2f793b59a 10438 */ /* end of group RCM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10439
screamer 0:c5e2f793b59a 10440
screamer 0:c5e2f793b59a 10441 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10442 -- RCM Register Masks
screamer 0:c5e2f793b59a 10443 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10444
screamer 0:c5e2f793b59a 10445 /*!
screamer 0:c5e2f793b59a 10446 * @addtogroup RCM_Register_Masks RCM Register Masks
screamer 0:c5e2f793b59a 10447 * @{
screamer 0:c5e2f793b59a 10448 */
screamer 0:c5e2f793b59a 10449
screamer 0:c5e2f793b59a 10450 /* SRS0 Bit Fields */
screamer 0:c5e2f793b59a 10451 #define RCM_SRS0_WAKEUP_MASK 0x1u
screamer 0:c5e2f793b59a 10452 #define RCM_SRS0_WAKEUP_SHIFT 0
screamer 0:c5e2f793b59a 10453 #define RCM_SRS0_LVD_MASK 0x2u
screamer 0:c5e2f793b59a 10454 #define RCM_SRS0_LVD_SHIFT 1
screamer 0:c5e2f793b59a 10455 #define RCM_SRS0_LOC_MASK 0x4u
screamer 0:c5e2f793b59a 10456 #define RCM_SRS0_LOC_SHIFT 2
screamer 0:c5e2f793b59a 10457 #define RCM_SRS0_LOL_MASK 0x8u
screamer 0:c5e2f793b59a 10458 #define RCM_SRS0_LOL_SHIFT 3
screamer 0:c5e2f793b59a 10459 #define RCM_SRS0_WDOG_MASK 0x20u
screamer 0:c5e2f793b59a 10460 #define RCM_SRS0_WDOG_SHIFT 5
screamer 0:c5e2f793b59a 10461 #define RCM_SRS0_PIN_MASK 0x40u
screamer 0:c5e2f793b59a 10462 #define RCM_SRS0_PIN_SHIFT 6
screamer 0:c5e2f793b59a 10463 #define RCM_SRS0_POR_MASK 0x80u
screamer 0:c5e2f793b59a 10464 #define RCM_SRS0_POR_SHIFT 7
screamer 0:c5e2f793b59a 10465 /* SRS1 Bit Fields */
screamer 0:c5e2f793b59a 10466 #define RCM_SRS1_JTAG_MASK 0x1u
screamer 0:c5e2f793b59a 10467 #define RCM_SRS1_JTAG_SHIFT 0
screamer 0:c5e2f793b59a 10468 #define RCM_SRS1_LOCKUP_MASK 0x2u
screamer 0:c5e2f793b59a 10469 #define RCM_SRS1_LOCKUP_SHIFT 1
screamer 0:c5e2f793b59a 10470 #define RCM_SRS1_SW_MASK 0x4u
screamer 0:c5e2f793b59a 10471 #define RCM_SRS1_SW_SHIFT 2
screamer 0:c5e2f793b59a 10472 #define RCM_SRS1_MDM_AP_MASK 0x8u
screamer 0:c5e2f793b59a 10473 #define RCM_SRS1_MDM_AP_SHIFT 3
screamer 0:c5e2f793b59a 10474 #define RCM_SRS1_EZPT_MASK 0x10u
screamer 0:c5e2f793b59a 10475 #define RCM_SRS1_EZPT_SHIFT 4
screamer 0:c5e2f793b59a 10476 #define RCM_SRS1_SACKERR_MASK 0x20u
screamer 0:c5e2f793b59a 10477 #define RCM_SRS1_SACKERR_SHIFT 5
screamer 0:c5e2f793b59a 10478 /* RPFC Bit Fields */
screamer 0:c5e2f793b59a 10479 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
screamer 0:c5e2f793b59a 10480 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
screamer 0:c5e2f793b59a 10481 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
screamer 0:c5e2f793b59a 10482 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
screamer 0:c5e2f793b59a 10483 #define RCM_RPFC_RSTFLTSS_SHIFT 2
screamer 0:c5e2f793b59a 10484 /* RPFW Bit Fields */
screamer 0:c5e2f793b59a 10485 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
screamer 0:c5e2f793b59a 10486 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
screamer 0:c5e2f793b59a 10487 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
screamer 0:c5e2f793b59a 10488 /* MR Bit Fields */
screamer 0:c5e2f793b59a 10489 #define RCM_MR_EZP_MS_MASK 0x2u
screamer 0:c5e2f793b59a 10490 #define RCM_MR_EZP_MS_SHIFT 1
screamer 0:c5e2f793b59a 10491
screamer 0:c5e2f793b59a 10492 /*!
screamer 0:c5e2f793b59a 10493 * @}
screamer 0:c5e2f793b59a 10494 */ /* end of group RCM_Register_Masks */
screamer 0:c5e2f793b59a 10495
screamer 0:c5e2f793b59a 10496
screamer 0:c5e2f793b59a 10497 /* RCM - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 10498 /** Peripheral RCM base address */
screamer 0:c5e2f793b59a 10499 #define RCM_BASE (0x4007F000u)
screamer 0:c5e2f793b59a 10500 /** Peripheral RCM base pointer */
screamer 0:c5e2f793b59a 10501 #define RCM ((RCM_Type *)RCM_BASE)
screamer 0:c5e2f793b59a 10502 #define RCM_BASE_PTR (RCM)
screamer 0:c5e2f793b59a 10503 /** Array initializer of RCM peripheral base addresses */
screamer 0:c5e2f793b59a 10504 #define RCM_BASE_ADDRS { RCM_BASE }
screamer 0:c5e2f793b59a 10505 /** Array initializer of RCM peripheral base pointers */
screamer 0:c5e2f793b59a 10506 #define RCM_BASE_PTRS { RCM }
screamer 0:c5e2f793b59a 10507
screamer 0:c5e2f793b59a 10508 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10509 -- RCM - Register accessor macros
screamer 0:c5e2f793b59a 10510 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10511
screamer 0:c5e2f793b59a 10512 /*!
screamer 0:c5e2f793b59a 10513 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
screamer 0:c5e2f793b59a 10514 * @{
screamer 0:c5e2f793b59a 10515 */
screamer 0:c5e2f793b59a 10516
screamer 0:c5e2f793b59a 10517
screamer 0:c5e2f793b59a 10518 /* RCM - Register instance definitions */
screamer 0:c5e2f793b59a 10519 /* RCM */
screamer 0:c5e2f793b59a 10520 #define RCM_SRS0 RCM_SRS0_REG(RCM)
screamer 0:c5e2f793b59a 10521 #define RCM_SRS1 RCM_SRS1_REG(RCM)
screamer 0:c5e2f793b59a 10522 #define RCM_RPFC RCM_RPFC_REG(RCM)
screamer 0:c5e2f793b59a 10523 #define RCM_RPFW RCM_RPFW_REG(RCM)
screamer 0:c5e2f793b59a 10524 #define RCM_MR RCM_MR_REG(RCM)
screamer 0:c5e2f793b59a 10525
screamer 0:c5e2f793b59a 10526 /*!
screamer 0:c5e2f793b59a 10527 * @}
screamer 0:c5e2f793b59a 10528 */ /* end of group RCM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10529
screamer 0:c5e2f793b59a 10530
screamer 0:c5e2f793b59a 10531 /*!
screamer 0:c5e2f793b59a 10532 * @}
screamer 0:c5e2f793b59a 10533 */ /* end of group RCM_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 10534
screamer 0:c5e2f793b59a 10535
screamer 0:c5e2f793b59a 10536 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10537 -- RFSYS Peripheral Access Layer
screamer 0:c5e2f793b59a 10538 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10539
screamer 0:c5e2f793b59a 10540 /*!
screamer 0:c5e2f793b59a 10541 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
screamer 0:c5e2f793b59a 10542 * @{
screamer 0:c5e2f793b59a 10543 */
screamer 0:c5e2f793b59a 10544
screamer 0:c5e2f793b59a 10545 /** RFSYS - Register Layout Typedef */
screamer 0:c5e2f793b59a 10546 typedef struct {
screamer 0:c5e2f793b59a 10547 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
screamer 0:c5e2f793b59a 10548 } RFSYS_Type, *RFSYS_MemMapPtr;
screamer 0:c5e2f793b59a 10549
screamer 0:c5e2f793b59a 10550 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10551 -- RFSYS - Register accessor macros
screamer 0:c5e2f793b59a 10552 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10553
screamer 0:c5e2f793b59a 10554 /*!
screamer 0:c5e2f793b59a 10555 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
screamer 0:c5e2f793b59a 10556 * @{
screamer 0:c5e2f793b59a 10557 */
screamer 0:c5e2f793b59a 10558
screamer 0:c5e2f793b59a 10559
screamer 0:c5e2f793b59a 10560 /* RFSYS - Register accessors */
screamer 0:c5e2f793b59a 10561 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
screamer 0:c5e2f793b59a 10562
screamer 0:c5e2f793b59a 10563 /*!
screamer 0:c5e2f793b59a 10564 * @}
screamer 0:c5e2f793b59a 10565 */ /* end of group RFSYS_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10566
screamer 0:c5e2f793b59a 10567
screamer 0:c5e2f793b59a 10568 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10569 -- RFSYS Register Masks
screamer 0:c5e2f793b59a 10570 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10571
screamer 0:c5e2f793b59a 10572 /*!
screamer 0:c5e2f793b59a 10573 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
screamer 0:c5e2f793b59a 10574 * @{
screamer 0:c5e2f793b59a 10575 */
screamer 0:c5e2f793b59a 10576
screamer 0:c5e2f793b59a 10577 /* REG Bit Fields */
screamer 0:c5e2f793b59a 10578 #define RFSYS_REG_LL_MASK 0xFFu
screamer 0:c5e2f793b59a 10579 #define RFSYS_REG_LL_SHIFT 0
screamer 0:c5e2f793b59a 10580 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
screamer 0:c5e2f793b59a 10581 #define RFSYS_REG_LH_MASK 0xFF00u
screamer 0:c5e2f793b59a 10582 #define RFSYS_REG_LH_SHIFT 8
screamer 0:c5e2f793b59a 10583 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
screamer 0:c5e2f793b59a 10584 #define RFSYS_REG_HL_MASK 0xFF0000u
screamer 0:c5e2f793b59a 10585 #define RFSYS_REG_HL_SHIFT 16
screamer 0:c5e2f793b59a 10586 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
screamer 0:c5e2f793b59a 10587 #define RFSYS_REG_HH_MASK 0xFF000000u
screamer 0:c5e2f793b59a 10588 #define RFSYS_REG_HH_SHIFT 24
screamer 0:c5e2f793b59a 10589 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
screamer 0:c5e2f793b59a 10590
screamer 0:c5e2f793b59a 10591 /*!
screamer 0:c5e2f793b59a 10592 * @}
screamer 0:c5e2f793b59a 10593 */ /* end of group RFSYS_Register_Masks */
screamer 0:c5e2f793b59a 10594
screamer 0:c5e2f793b59a 10595
screamer 0:c5e2f793b59a 10596 /* RFSYS - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 10597 /** Peripheral RFSYS base address */
screamer 0:c5e2f793b59a 10598 #define RFSYS_BASE (0x40041000u)
screamer 0:c5e2f793b59a 10599 /** Peripheral RFSYS base pointer */
screamer 0:c5e2f793b59a 10600 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
screamer 0:c5e2f793b59a 10601 #define RFSYS_BASE_PTR (RFSYS)
screamer 0:c5e2f793b59a 10602 /** Array initializer of RFSYS peripheral base addresses */
screamer 0:c5e2f793b59a 10603 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
screamer 0:c5e2f793b59a 10604 /** Array initializer of RFSYS peripheral base pointers */
screamer 0:c5e2f793b59a 10605 #define RFSYS_BASE_PTRS { RFSYS }
screamer 0:c5e2f793b59a 10606
screamer 0:c5e2f793b59a 10607 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10608 -- RFSYS - Register accessor macros
screamer 0:c5e2f793b59a 10609 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10610
screamer 0:c5e2f793b59a 10611 /*!
screamer 0:c5e2f793b59a 10612 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
screamer 0:c5e2f793b59a 10613 * @{
screamer 0:c5e2f793b59a 10614 */
screamer 0:c5e2f793b59a 10615
screamer 0:c5e2f793b59a 10616
screamer 0:c5e2f793b59a 10617 /* RFSYS - Register instance definitions */
screamer 0:c5e2f793b59a 10618 /* RFSYS */
screamer 0:c5e2f793b59a 10619 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
screamer 0:c5e2f793b59a 10620 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
screamer 0:c5e2f793b59a 10621 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
screamer 0:c5e2f793b59a 10622 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
screamer 0:c5e2f793b59a 10623 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
screamer 0:c5e2f793b59a 10624 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
screamer 0:c5e2f793b59a 10625 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
screamer 0:c5e2f793b59a 10626 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
screamer 0:c5e2f793b59a 10627
screamer 0:c5e2f793b59a 10628 /* RFSYS - Register array accessors */
screamer 0:c5e2f793b59a 10629 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
screamer 0:c5e2f793b59a 10630
screamer 0:c5e2f793b59a 10631 /*!
screamer 0:c5e2f793b59a 10632 * @}
screamer 0:c5e2f793b59a 10633 */ /* end of group RFSYS_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10634
screamer 0:c5e2f793b59a 10635
screamer 0:c5e2f793b59a 10636 /*!
screamer 0:c5e2f793b59a 10637 * @}
screamer 0:c5e2f793b59a 10638 */ /* end of group RFSYS_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 10639
screamer 0:c5e2f793b59a 10640
screamer 0:c5e2f793b59a 10641 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10642 -- RFVBAT Peripheral Access Layer
screamer 0:c5e2f793b59a 10643 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10644
screamer 0:c5e2f793b59a 10645 /*!
screamer 0:c5e2f793b59a 10646 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
screamer 0:c5e2f793b59a 10647 * @{
screamer 0:c5e2f793b59a 10648 */
screamer 0:c5e2f793b59a 10649
screamer 0:c5e2f793b59a 10650 /** RFVBAT - Register Layout Typedef */
screamer 0:c5e2f793b59a 10651 typedef struct {
screamer 0:c5e2f793b59a 10652 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
screamer 0:c5e2f793b59a 10653 } RFVBAT_Type, *RFVBAT_MemMapPtr;
screamer 0:c5e2f793b59a 10654
screamer 0:c5e2f793b59a 10655 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10656 -- RFVBAT - Register accessor macros
screamer 0:c5e2f793b59a 10657 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10658
screamer 0:c5e2f793b59a 10659 /*!
screamer 0:c5e2f793b59a 10660 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
screamer 0:c5e2f793b59a 10661 * @{
screamer 0:c5e2f793b59a 10662 */
screamer 0:c5e2f793b59a 10663
screamer 0:c5e2f793b59a 10664
screamer 0:c5e2f793b59a 10665 /* RFVBAT - Register accessors */
screamer 0:c5e2f793b59a 10666 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
screamer 0:c5e2f793b59a 10667
screamer 0:c5e2f793b59a 10668 /*!
screamer 0:c5e2f793b59a 10669 * @}
screamer 0:c5e2f793b59a 10670 */ /* end of group RFVBAT_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10671
screamer 0:c5e2f793b59a 10672
screamer 0:c5e2f793b59a 10673 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10674 -- RFVBAT Register Masks
screamer 0:c5e2f793b59a 10675 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10676
screamer 0:c5e2f793b59a 10677 /*!
screamer 0:c5e2f793b59a 10678 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
screamer 0:c5e2f793b59a 10679 * @{
screamer 0:c5e2f793b59a 10680 */
screamer 0:c5e2f793b59a 10681
screamer 0:c5e2f793b59a 10682 /* REG Bit Fields */
screamer 0:c5e2f793b59a 10683 #define RFVBAT_REG_LL_MASK 0xFFu
screamer 0:c5e2f793b59a 10684 #define RFVBAT_REG_LL_SHIFT 0
screamer 0:c5e2f793b59a 10685 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
screamer 0:c5e2f793b59a 10686 #define RFVBAT_REG_LH_MASK 0xFF00u
screamer 0:c5e2f793b59a 10687 #define RFVBAT_REG_LH_SHIFT 8
screamer 0:c5e2f793b59a 10688 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
screamer 0:c5e2f793b59a 10689 #define RFVBAT_REG_HL_MASK 0xFF0000u
screamer 0:c5e2f793b59a 10690 #define RFVBAT_REG_HL_SHIFT 16
screamer 0:c5e2f793b59a 10691 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
screamer 0:c5e2f793b59a 10692 #define RFVBAT_REG_HH_MASK 0xFF000000u
screamer 0:c5e2f793b59a 10693 #define RFVBAT_REG_HH_SHIFT 24
screamer 0:c5e2f793b59a 10694 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
screamer 0:c5e2f793b59a 10695
screamer 0:c5e2f793b59a 10696 /*!
screamer 0:c5e2f793b59a 10697 * @}
screamer 0:c5e2f793b59a 10698 */ /* end of group RFVBAT_Register_Masks */
screamer 0:c5e2f793b59a 10699
screamer 0:c5e2f793b59a 10700
screamer 0:c5e2f793b59a 10701 /* RFVBAT - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 10702 /** Peripheral RFVBAT base address */
screamer 0:c5e2f793b59a 10703 #define RFVBAT_BASE (0x4003E000u)
screamer 0:c5e2f793b59a 10704 /** Peripheral RFVBAT base pointer */
screamer 0:c5e2f793b59a 10705 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
screamer 0:c5e2f793b59a 10706 #define RFVBAT_BASE_PTR (RFVBAT)
screamer 0:c5e2f793b59a 10707 /** Array initializer of RFVBAT peripheral base addresses */
screamer 0:c5e2f793b59a 10708 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
screamer 0:c5e2f793b59a 10709 /** Array initializer of RFVBAT peripheral base pointers */
screamer 0:c5e2f793b59a 10710 #define RFVBAT_BASE_PTRS { RFVBAT }
screamer 0:c5e2f793b59a 10711
screamer 0:c5e2f793b59a 10712 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10713 -- RFVBAT - Register accessor macros
screamer 0:c5e2f793b59a 10714 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10715
screamer 0:c5e2f793b59a 10716 /*!
screamer 0:c5e2f793b59a 10717 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
screamer 0:c5e2f793b59a 10718 * @{
screamer 0:c5e2f793b59a 10719 */
screamer 0:c5e2f793b59a 10720
screamer 0:c5e2f793b59a 10721
screamer 0:c5e2f793b59a 10722 /* RFVBAT - Register instance definitions */
screamer 0:c5e2f793b59a 10723 /* RFVBAT */
screamer 0:c5e2f793b59a 10724 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
screamer 0:c5e2f793b59a 10725 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
screamer 0:c5e2f793b59a 10726 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
screamer 0:c5e2f793b59a 10727 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
screamer 0:c5e2f793b59a 10728 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
screamer 0:c5e2f793b59a 10729 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
screamer 0:c5e2f793b59a 10730 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
screamer 0:c5e2f793b59a 10731 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
screamer 0:c5e2f793b59a 10732
screamer 0:c5e2f793b59a 10733 /* RFVBAT - Register array accessors */
screamer 0:c5e2f793b59a 10734 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
screamer 0:c5e2f793b59a 10735
screamer 0:c5e2f793b59a 10736 /*!
screamer 0:c5e2f793b59a 10737 * @}
screamer 0:c5e2f793b59a 10738 */ /* end of group RFVBAT_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10739
screamer 0:c5e2f793b59a 10740
screamer 0:c5e2f793b59a 10741 /*!
screamer 0:c5e2f793b59a 10742 * @}
screamer 0:c5e2f793b59a 10743 */ /* end of group RFVBAT_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 10744
screamer 0:c5e2f793b59a 10745
screamer 0:c5e2f793b59a 10746 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10747 -- RNG Peripheral Access Layer
screamer 0:c5e2f793b59a 10748 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10749
screamer 0:c5e2f793b59a 10750 /*!
screamer 0:c5e2f793b59a 10751 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
screamer 0:c5e2f793b59a 10752 * @{
screamer 0:c5e2f793b59a 10753 */
screamer 0:c5e2f793b59a 10754
screamer 0:c5e2f793b59a 10755 /** RNG - Register Layout Typedef */
screamer 0:c5e2f793b59a 10756 typedef struct {
screamer 0:c5e2f793b59a 10757 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
screamer 0:c5e2f793b59a 10758 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
screamer 0:c5e2f793b59a 10759 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
screamer 0:c5e2f793b59a 10760 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
screamer 0:c5e2f793b59a 10761 } RNG_Type, *RNG_MemMapPtr;
screamer 0:c5e2f793b59a 10762
screamer 0:c5e2f793b59a 10763 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10764 -- RNG - Register accessor macros
screamer 0:c5e2f793b59a 10765 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10766
screamer 0:c5e2f793b59a 10767 /*!
screamer 0:c5e2f793b59a 10768 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
screamer 0:c5e2f793b59a 10769 * @{
screamer 0:c5e2f793b59a 10770 */
screamer 0:c5e2f793b59a 10771
screamer 0:c5e2f793b59a 10772
screamer 0:c5e2f793b59a 10773 /* RNG - Register accessors */
screamer 0:c5e2f793b59a 10774 #define RNG_CR_REG(base) ((base)->CR)
screamer 0:c5e2f793b59a 10775 #define RNG_SR_REG(base) ((base)->SR)
screamer 0:c5e2f793b59a 10776 #define RNG_ER_REG(base) ((base)->ER)
screamer 0:c5e2f793b59a 10777 #define RNG_OR_REG(base) ((base)->OR)
screamer 0:c5e2f793b59a 10778
screamer 0:c5e2f793b59a 10779 /*!
screamer 0:c5e2f793b59a 10780 * @}
screamer 0:c5e2f793b59a 10781 */ /* end of group RNG_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10782
screamer 0:c5e2f793b59a 10783
screamer 0:c5e2f793b59a 10784 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10785 -- RNG Register Masks
screamer 0:c5e2f793b59a 10786 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10787
screamer 0:c5e2f793b59a 10788 /*!
screamer 0:c5e2f793b59a 10789 * @addtogroup RNG_Register_Masks RNG Register Masks
screamer 0:c5e2f793b59a 10790 * @{
screamer 0:c5e2f793b59a 10791 */
screamer 0:c5e2f793b59a 10792
screamer 0:c5e2f793b59a 10793 /* CR Bit Fields */
screamer 0:c5e2f793b59a 10794 #define RNG_CR_GO_MASK 0x1u
screamer 0:c5e2f793b59a 10795 #define RNG_CR_GO_SHIFT 0
screamer 0:c5e2f793b59a 10796 #define RNG_CR_HA_MASK 0x2u
screamer 0:c5e2f793b59a 10797 #define RNG_CR_HA_SHIFT 1
screamer 0:c5e2f793b59a 10798 #define RNG_CR_INTM_MASK 0x4u
screamer 0:c5e2f793b59a 10799 #define RNG_CR_INTM_SHIFT 2
screamer 0:c5e2f793b59a 10800 #define RNG_CR_CLRI_MASK 0x8u
screamer 0:c5e2f793b59a 10801 #define RNG_CR_CLRI_SHIFT 3
screamer 0:c5e2f793b59a 10802 #define RNG_CR_SLP_MASK 0x10u
screamer 0:c5e2f793b59a 10803 #define RNG_CR_SLP_SHIFT 4
screamer 0:c5e2f793b59a 10804 /* SR Bit Fields */
screamer 0:c5e2f793b59a 10805 #define RNG_SR_SECV_MASK 0x1u
screamer 0:c5e2f793b59a 10806 #define RNG_SR_SECV_SHIFT 0
screamer 0:c5e2f793b59a 10807 #define RNG_SR_LRS_MASK 0x2u
screamer 0:c5e2f793b59a 10808 #define RNG_SR_LRS_SHIFT 1
screamer 0:c5e2f793b59a 10809 #define RNG_SR_ORU_MASK 0x4u
screamer 0:c5e2f793b59a 10810 #define RNG_SR_ORU_SHIFT 2
screamer 0:c5e2f793b59a 10811 #define RNG_SR_ERRI_MASK 0x8u
screamer 0:c5e2f793b59a 10812 #define RNG_SR_ERRI_SHIFT 3
screamer 0:c5e2f793b59a 10813 #define RNG_SR_SLP_MASK 0x10u
screamer 0:c5e2f793b59a 10814 #define RNG_SR_SLP_SHIFT 4
screamer 0:c5e2f793b59a 10815 #define RNG_SR_OREG_LVL_MASK 0xFF00u
screamer 0:c5e2f793b59a 10816 #define RNG_SR_OREG_LVL_SHIFT 8
screamer 0:c5e2f793b59a 10817 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
screamer 0:c5e2f793b59a 10818 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
screamer 0:c5e2f793b59a 10819 #define RNG_SR_OREG_SIZE_SHIFT 16
screamer 0:c5e2f793b59a 10820 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
screamer 0:c5e2f793b59a 10821 /* ER Bit Fields */
screamer 0:c5e2f793b59a 10822 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 10823 #define RNG_ER_EXT_ENT_SHIFT 0
screamer 0:c5e2f793b59a 10824 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
screamer 0:c5e2f793b59a 10825 /* OR Bit Fields */
screamer 0:c5e2f793b59a 10826 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 10827 #define RNG_OR_RANDOUT_SHIFT 0
screamer 0:c5e2f793b59a 10828 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
screamer 0:c5e2f793b59a 10829
screamer 0:c5e2f793b59a 10830 /*!
screamer 0:c5e2f793b59a 10831 * @}
screamer 0:c5e2f793b59a 10832 */ /* end of group RNG_Register_Masks */
screamer 0:c5e2f793b59a 10833
screamer 0:c5e2f793b59a 10834
screamer 0:c5e2f793b59a 10835 /* RNG - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 10836 /** Peripheral RNG base address */
screamer 0:c5e2f793b59a 10837 #define RNG_BASE (0x40029000u)
screamer 0:c5e2f793b59a 10838 /** Peripheral RNG base pointer */
screamer 0:c5e2f793b59a 10839 #define RNG ((RNG_Type *)RNG_BASE)
screamer 0:c5e2f793b59a 10840 #define RNG_BASE_PTR (RNG)
screamer 0:c5e2f793b59a 10841 /** Array initializer of RNG peripheral base addresses */
screamer 0:c5e2f793b59a 10842 #define RNG_BASE_ADDRS { RNG_BASE }
screamer 0:c5e2f793b59a 10843 /** Array initializer of RNG peripheral base pointers */
screamer 0:c5e2f793b59a 10844 #define RNG_BASE_PTRS { RNG }
screamer 0:c5e2f793b59a 10845 /** Interrupt vectors for the RNG peripheral type */
screamer 0:c5e2f793b59a 10846 #define RNG_IRQS { RNG_IRQn }
screamer 0:c5e2f793b59a 10847
screamer 0:c5e2f793b59a 10848 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10849 -- RNG - Register accessor macros
screamer 0:c5e2f793b59a 10850 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10851
screamer 0:c5e2f793b59a 10852 /*!
screamer 0:c5e2f793b59a 10853 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
screamer 0:c5e2f793b59a 10854 * @{
screamer 0:c5e2f793b59a 10855 */
screamer 0:c5e2f793b59a 10856
screamer 0:c5e2f793b59a 10857
screamer 0:c5e2f793b59a 10858 /* RNG - Register instance definitions */
screamer 0:c5e2f793b59a 10859 /* RNG */
screamer 0:c5e2f793b59a 10860 #define RNG_CR RNG_CR_REG(RNG)
screamer 0:c5e2f793b59a 10861 #define RNG_SR RNG_SR_REG(RNG)
screamer 0:c5e2f793b59a 10862 #define RNG_ER RNG_ER_REG(RNG)
screamer 0:c5e2f793b59a 10863 #define RNG_OR RNG_OR_REG(RNG)
screamer 0:c5e2f793b59a 10864
screamer 0:c5e2f793b59a 10865 /*!
screamer 0:c5e2f793b59a 10866 * @}
screamer 0:c5e2f793b59a 10867 */ /* end of group RNG_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10868
screamer 0:c5e2f793b59a 10869
screamer 0:c5e2f793b59a 10870 /*!
screamer 0:c5e2f793b59a 10871 * @}
screamer 0:c5e2f793b59a 10872 */ /* end of group RNG_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 10873
screamer 0:c5e2f793b59a 10874
screamer 0:c5e2f793b59a 10875 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10876 -- RTC Peripheral Access Layer
screamer 0:c5e2f793b59a 10877 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10878
screamer 0:c5e2f793b59a 10879 /*!
screamer 0:c5e2f793b59a 10880 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
screamer 0:c5e2f793b59a 10881 * @{
screamer 0:c5e2f793b59a 10882 */
screamer 0:c5e2f793b59a 10883
screamer 0:c5e2f793b59a 10884 /** RTC - Register Layout Typedef */
screamer 0:c5e2f793b59a 10885 typedef struct {
screamer 0:c5e2f793b59a 10886 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
screamer 0:c5e2f793b59a 10887 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
screamer 0:c5e2f793b59a 10888 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
screamer 0:c5e2f793b59a 10889 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
screamer 0:c5e2f793b59a 10890 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
screamer 0:c5e2f793b59a 10891 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
screamer 0:c5e2f793b59a 10892 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
screamer 0:c5e2f793b59a 10893 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
screamer 0:c5e2f793b59a 10894 uint8_t RESERVED_0[2016];
screamer 0:c5e2f793b59a 10895 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
screamer 0:c5e2f793b59a 10896 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
screamer 0:c5e2f793b59a 10897 } RTC_Type, *RTC_MemMapPtr;
screamer 0:c5e2f793b59a 10898
screamer 0:c5e2f793b59a 10899 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10900 -- RTC - Register accessor macros
screamer 0:c5e2f793b59a 10901 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10902
screamer 0:c5e2f793b59a 10903 /*!
screamer 0:c5e2f793b59a 10904 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
screamer 0:c5e2f793b59a 10905 * @{
screamer 0:c5e2f793b59a 10906 */
screamer 0:c5e2f793b59a 10907
screamer 0:c5e2f793b59a 10908
screamer 0:c5e2f793b59a 10909 /* RTC - Register accessors */
screamer 0:c5e2f793b59a 10910 #define RTC_TSR_REG(base) ((base)->TSR)
screamer 0:c5e2f793b59a 10911 #define RTC_TPR_REG(base) ((base)->TPR)
screamer 0:c5e2f793b59a 10912 #define RTC_TAR_REG(base) ((base)->TAR)
screamer 0:c5e2f793b59a 10913 #define RTC_TCR_REG(base) ((base)->TCR)
screamer 0:c5e2f793b59a 10914 #define RTC_CR_REG(base) ((base)->CR)
screamer 0:c5e2f793b59a 10915 #define RTC_SR_REG(base) ((base)->SR)
screamer 0:c5e2f793b59a 10916 #define RTC_LR_REG(base) ((base)->LR)
screamer 0:c5e2f793b59a 10917 #define RTC_IER_REG(base) ((base)->IER)
screamer 0:c5e2f793b59a 10918 #define RTC_WAR_REG(base) ((base)->WAR)
screamer 0:c5e2f793b59a 10919 #define RTC_RAR_REG(base) ((base)->RAR)
screamer 0:c5e2f793b59a 10920
screamer 0:c5e2f793b59a 10921 /*!
screamer 0:c5e2f793b59a 10922 * @}
screamer 0:c5e2f793b59a 10923 */ /* end of group RTC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 10924
screamer 0:c5e2f793b59a 10925
screamer 0:c5e2f793b59a 10926 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 10927 -- RTC Register Masks
screamer 0:c5e2f793b59a 10928 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 10929
screamer 0:c5e2f793b59a 10930 /*!
screamer 0:c5e2f793b59a 10931 * @addtogroup RTC_Register_Masks RTC Register Masks
screamer 0:c5e2f793b59a 10932 * @{
screamer 0:c5e2f793b59a 10933 */
screamer 0:c5e2f793b59a 10934
screamer 0:c5e2f793b59a 10935 /* TSR Bit Fields */
screamer 0:c5e2f793b59a 10936 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 10937 #define RTC_TSR_TSR_SHIFT 0
screamer 0:c5e2f793b59a 10938 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
screamer 0:c5e2f793b59a 10939 /* TPR Bit Fields */
screamer 0:c5e2f793b59a 10940 #define RTC_TPR_TPR_MASK 0xFFFFu
screamer 0:c5e2f793b59a 10941 #define RTC_TPR_TPR_SHIFT 0
screamer 0:c5e2f793b59a 10942 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
screamer 0:c5e2f793b59a 10943 /* TAR Bit Fields */
screamer 0:c5e2f793b59a 10944 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 10945 #define RTC_TAR_TAR_SHIFT 0
screamer 0:c5e2f793b59a 10946 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
screamer 0:c5e2f793b59a 10947 /* TCR Bit Fields */
screamer 0:c5e2f793b59a 10948 #define RTC_TCR_TCR_MASK 0xFFu
screamer 0:c5e2f793b59a 10949 #define RTC_TCR_TCR_SHIFT 0
screamer 0:c5e2f793b59a 10950 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
screamer 0:c5e2f793b59a 10951 #define RTC_TCR_CIR_MASK 0xFF00u
screamer 0:c5e2f793b59a 10952 #define RTC_TCR_CIR_SHIFT 8
screamer 0:c5e2f793b59a 10953 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
screamer 0:c5e2f793b59a 10954 #define RTC_TCR_TCV_MASK 0xFF0000u
screamer 0:c5e2f793b59a 10955 #define RTC_TCR_TCV_SHIFT 16
screamer 0:c5e2f793b59a 10956 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
screamer 0:c5e2f793b59a 10957 #define RTC_TCR_CIC_MASK 0xFF000000u
screamer 0:c5e2f793b59a 10958 #define RTC_TCR_CIC_SHIFT 24
screamer 0:c5e2f793b59a 10959 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
screamer 0:c5e2f793b59a 10960 /* CR Bit Fields */
screamer 0:c5e2f793b59a 10961 #define RTC_CR_SWR_MASK 0x1u
screamer 0:c5e2f793b59a 10962 #define RTC_CR_SWR_SHIFT 0
screamer 0:c5e2f793b59a 10963 #define RTC_CR_WPE_MASK 0x2u
screamer 0:c5e2f793b59a 10964 #define RTC_CR_WPE_SHIFT 1
screamer 0:c5e2f793b59a 10965 #define RTC_CR_SUP_MASK 0x4u
screamer 0:c5e2f793b59a 10966 #define RTC_CR_SUP_SHIFT 2
screamer 0:c5e2f793b59a 10967 #define RTC_CR_UM_MASK 0x8u
screamer 0:c5e2f793b59a 10968 #define RTC_CR_UM_SHIFT 3
screamer 0:c5e2f793b59a 10969 #define RTC_CR_WPS_MASK 0x10u
screamer 0:c5e2f793b59a 10970 #define RTC_CR_WPS_SHIFT 4
screamer 0:c5e2f793b59a 10971 #define RTC_CR_OSCE_MASK 0x100u
screamer 0:c5e2f793b59a 10972 #define RTC_CR_OSCE_SHIFT 8
screamer 0:c5e2f793b59a 10973 #define RTC_CR_CLKO_MASK 0x200u
screamer 0:c5e2f793b59a 10974 #define RTC_CR_CLKO_SHIFT 9
screamer 0:c5e2f793b59a 10975 #define RTC_CR_SC16P_MASK 0x400u
screamer 0:c5e2f793b59a 10976 #define RTC_CR_SC16P_SHIFT 10
screamer 0:c5e2f793b59a 10977 #define RTC_CR_SC8P_MASK 0x800u
screamer 0:c5e2f793b59a 10978 #define RTC_CR_SC8P_SHIFT 11
screamer 0:c5e2f793b59a 10979 #define RTC_CR_SC4P_MASK 0x1000u
screamer 0:c5e2f793b59a 10980 #define RTC_CR_SC4P_SHIFT 12
screamer 0:c5e2f793b59a 10981 #define RTC_CR_SC2P_MASK 0x2000u
screamer 0:c5e2f793b59a 10982 #define RTC_CR_SC2P_SHIFT 13
screamer 0:c5e2f793b59a 10983 /* SR Bit Fields */
screamer 0:c5e2f793b59a 10984 #define RTC_SR_TIF_MASK 0x1u
screamer 0:c5e2f793b59a 10985 #define RTC_SR_TIF_SHIFT 0
screamer 0:c5e2f793b59a 10986 #define RTC_SR_TOF_MASK 0x2u
screamer 0:c5e2f793b59a 10987 #define RTC_SR_TOF_SHIFT 1
screamer 0:c5e2f793b59a 10988 #define RTC_SR_TAF_MASK 0x4u
screamer 0:c5e2f793b59a 10989 #define RTC_SR_TAF_SHIFT 2
screamer 0:c5e2f793b59a 10990 #define RTC_SR_TCE_MASK 0x10u
screamer 0:c5e2f793b59a 10991 #define RTC_SR_TCE_SHIFT 4
screamer 0:c5e2f793b59a 10992 /* LR Bit Fields */
screamer 0:c5e2f793b59a 10993 #define RTC_LR_TCL_MASK 0x8u
screamer 0:c5e2f793b59a 10994 #define RTC_LR_TCL_SHIFT 3
screamer 0:c5e2f793b59a 10995 #define RTC_LR_CRL_MASK 0x10u
screamer 0:c5e2f793b59a 10996 #define RTC_LR_CRL_SHIFT 4
screamer 0:c5e2f793b59a 10997 #define RTC_LR_SRL_MASK 0x20u
screamer 0:c5e2f793b59a 10998 #define RTC_LR_SRL_SHIFT 5
screamer 0:c5e2f793b59a 10999 #define RTC_LR_LRL_MASK 0x40u
screamer 0:c5e2f793b59a 11000 #define RTC_LR_LRL_SHIFT 6
screamer 0:c5e2f793b59a 11001 /* IER Bit Fields */
screamer 0:c5e2f793b59a 11002 #define RTC_IER_TIIE_MASK 0x1u
screamer 0:c5e2f793b59a 11003 #define RTC_IER_TIIE_SHIFT 0
screamer 0:c5e2f793b59a 11004 #define RTC_IER_TOIE_MASK 0x2u
screamer 0:c5e2f793b59a 11005 #define RTC_IER_TOIE_SHIFT 1
screamer 0:c5e2f793b59a 11006 #define RTC_IER_TAIE_MASK 0x4u
screamer 0:c5e2f793b59a 11007 #define RTC_IER_TAIE_SHIFT 2
screamer 0:c5e2f793b59a 11008 #define RTC_IER_TSIE_MASK 0x10u
screamer 0:c5e2f793b59a 11009 #define RTC_IER_TSIE_SHIFT 4
screamer 0:c5e2f793b59a 11010 #define RTC_IER_WPON_MASK 0x80u
screamer 0:c5e2f793b59a 11011 #define RTC_IER_WPON_SHIFT 7
screamer 0:c5e2f793b59a 11012 /* WAR Bit Fields */
screamer 0:c5e2f793b59a 11013 #define RTC_WAR_TSRW_MASK 0x1u
screamer 0:c5e2f793b59a 11014 #define RTC_WAR_TSRW_SHIFT 0
screamer 0:c5e2f793b59a 11015 #define RTC_WAR_TPRW_MASK 0x2u
screamer 0:c5e2f793b59a 11016 #define RTC_WAR_TPRW_SHIFT 1
screamer 0:c5e2f793b59a 11017 #define RTC_WAR_TARW_MASK 0x4u
screamer 0:c5e2f793b59a 11018 #define RTC_WAR_TARW_SHIFT 2
screamer 0:c5e2f793b59a 11019 #define RTC_WAR_TCRW_MASK 0x8u
screamer 0:c5e2f793b59a 11020 #define RTC_WAR_TCRW_SHIFT 3
screamer 0:c5e2f793b59a 11021 #define RTC_WAR_CRW_MASK 0x10u
screamer 0:c5e2f793b59a 11022 #define RTC_WAR_CRW_SHIFT 4
screamer 0:c5e2f793b59a 11023 #define RTC_WAR_SRW_MASK 0x20u
screamer 0:c5e2f793b59a 11024 #define RTC_WAR_SRW_SHIFT 5
screamer 0:c5e2f793b59a 11025 #define RTC_WAR_LRW_MASK 0x40u
screamer 0:c5e2f793b59a 11026 #define RTC_WAR_LRW_SHIFT 6
screamer 0:c5e2f793b59a 11027 #define RTC_WAR_IERW_MASK 0x80u
screamer 0:c5e2f793b59a 11028 #define RTC_WAR_IERW_SHIFT 7
screamer 0:c5e2f793b59a 11029 /* RAR Bit Fields */
screamer 0:c5e2f793b59a 11030 #define RTC_RAR_TSRR_MASK 0x1u
screamer 0:c5e2f793b59a 11031 #define RTC_RAR_TSRR_SHIFT 0
screamer 0:c5e2f793b59a 11032 #define RTC_RAR_TPRR_MASK 0x2u
screamer 0:c5e2f793b59a 11033 #define RTC_RAR_TPRR_SHIFT 1
screamer 0:c5e2f793b59a 11034 #define RTC_RAR_TARR_MASK 0x4u
screamer 0:c5e2f793b59a 11035 #define RTC_RAR_TARR_SHIFT 2
screamer 0:c5e2f793b59a 11036 #define RTC_RAR_TCRR_MASK 0x8u
screamer 0:c5e2f793b59a 11037 #define RTC_RAR_TCRR_SHIFT 3
screamer 0:c5e2f793b59a 11038 #define RTC_RAR_CRR_MASK 0x10u
screamer 0:c5e2f793b59a 11039 #define RTC_RAR_CRR_SHIFT 4
screamer 0:c5e2f793b59a 11040 #define RTC_RAR_SRR_MASK 0x20u
screamer 0:c5e2f793b59a 11041 #define RTC_RAR_SRR_SHIFT 5
screamer 0:c5e2f793b59a 11042 #define RTC_RAR_LRR_MASK 0x40u
screamer 0:c5e2f793b59a 11043 #define RTC_RAR_LRR_SHIFT 6
screamer 0:c5e2f793b59a 11044 #define RTC_RAR_IERR_MASK 0x80u
screamer 0:c5e2f793b59a 11045 #define RTC_RAR_IERR_SHIFT 7
screamer 0:c5e2f793b59a 11046
screamer 0:c5e2f793b59a 11047 /*!
screamer 0:c5e2f793b59a 11048 * @}
screamer 0:c5e2f793b59a 11049 */ /* end of group RTC_Register_Masks */
screamer 0:c5e2f793b59a 11050
screamer 0:c5e2f793b59a 11051
screamer 0:c5e2f793b59a 11052 /* RTC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 11053 /** Peripheral RTC base address */
screamer 0:c5e2f793b59a 11054 #define RTC_BASE (0x4003D000u)
screamer 0:c5e2f793b59a 11055 /** Peripheral RTC base pointer */
screamer 0:c5e2f793b59a 11056 #define RTC ((RTC_Type *)RTC_BASE)
screamer 0:c5e2f793b59a 11057 #define RTC_BASE_PTR (RTC)
screamer 0:c5e2f793b59a 11058 /** Array initializer of RTC peripheral base addresses */
screamer 0:c5e2f793b59a 11059 #define RTC_BASE_ADDRS { RTC_BASE }
screamer 0:c5e2f793b59a 11060 /** Array initializer of RTC peripheral base pointers */
screamer 0:c5e2f793b59a 11061 #define RTC_BASE_PTRS { RTC }
screamer 0:c5e2f793b59a 11062 /** Interrupt vectors for the RTC peripheral type */
screamer 0:c5e2f793b59a 11063 #define RTC_IRQS { RTC_IRQn }
screamer 0:c5e2f793b59a 11064 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
screamer 0:c5e2f793b59a 11065
screamer 0:c5e2f793b59a 11066 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 11067 -- RTC - Register accessor macros
screamer 0:c5e2f793b59a 11068 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 11069
screamer 0:c5e2f793b59a 11070 /*!
screamer 0:c5e2f793b59a 11071 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
screamer 0:c5e2f793b59a 11072 * @{
screamer 0:c5e2f793b59a 11073 */
screamer 0:c5e2f793b59a 11074
screamer 0:c5e2f793b59a 11075
screamer 0:c5e2f793b59a 11076 /* RTC - Register instance definitions */
screamer 0:c5e2f793b59a 11077 /* RTC */
screamer 0:c5e2f793b59a 11078 #define RTC_TSR RTC_TSR_REG(RTC)
screamer 0:c5e2f793b59a 11079 #define RTC_TPR RTC_TPR_REG(RTC)
screamer 0:c5e2f793b59a 11080 #define RTC_TAR RTC_TAR_REG(RTC)
screamer 0:c5e2f793b59a 11081 #define RTC_TCR RTC_TCR_REG(RTC)
screamer 0:c5e2f793b59a 11082 #define RTC_CR RTC_CR_REG(RTC)
screamer 0:c5e2f793b59a 11083 #define RTC_SR RTC_SR_REG(RTC)
screamer 0:c5e2f793b59a 11084 #define RTC_LR RTC_LR_REG(RTC)
screamer 0:c5e2f793b59a 11085 #define RTC_IER RTC_IER_REG(RTC)
screamer 0:c5e2f793b59a 11086 #define RTC_WAR RTC_WAR_REG(RTC)
screamer 0:c5e2f793b59a 11087 #define RTC_RAR RTC_RAR_REG(RTC)
screamer 0:c5e2f793b59a 11088
screamer 0:c5e2f793b59a 11089 /*!
screamer 0:c5e2f793b59a 11090 * @}
screamer 0:c5e2f793b59a 11091 */ /* end of group RTC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 11092
screamer 0:c5e2f793b59a 11093
screamer 0:c5e2f793b59a 11094 /*!
screamer 0:c5e2f793b59a 11095 * @}
screamer 0:c5e2f793b59a 11096 */ /* end of group RTC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 11097
screamer 0:c5e2f793b59a 11098
screamer 0:c5e2f793b59a 11099 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 11100 -- SDHC Peripheral Access Layer
screamer 0:c5e2f793b59a 11101 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 11102
screamer 0:c5e2f793b59a 11103 /*!
screamer 0:c5e2f793b59a 11104 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
screamer 0:c5e2f793b59a 11105 * @{
screamer 0:c5e2f793b59a 11106 */
screamer 0:c5e2f793b59a 11107
screamer 0:c5e2f793b59a 11108 /** SDHC - Register Layout Typedef */
screamer 0:c5e2f793b59a 11109 typedef struct {
screamer 0:c5e2f793b59a 11110 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
screamer 0:c5e2f793b59a 11111 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
screamer 0:c5e2f793b59a 11112 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
screamer 0:c5e2f793b59a 11113 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
screamer 0:c5e2f793b59a 11114 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
screamer 0:c5e2f793b59a 11115 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
screamer 0:c5e2f793b59a 11116 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
screamer 0:c5e2f793b59a 11117 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
screamer 0:c5e2f793b59a 11118 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
screamer 0:c5e2f793b59a 11119 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
screamer 0:c5e2f793b59a 11120 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
screamer 0:c5e2f793b59a 11121 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
screamer 0:c5e2f793b59a 11122 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
screamer 0:c5e2f793b59a 11123 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
screamer 0:c5e2f793b59a 11124 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
screamer 0:c5e2f793b59a 11125 uint8_t RESERVED_0[8];
screamer 0:c5e2f793b59a 11126 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
screamer 0:c5e2f793b59a 11127 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
screamer 0:c5e2f793b59a 11128 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
screamer 0:c5e2f793b59a 11129 uint8_t RESERVED_1[100];
screamer 0:c5e2f793b59a 11130 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
screamer 0:c5e2f793b59a 11131 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
screamer 0:c5e2f793b59a 11132 uint8_t RESERVED_2[52];
screamer 0:c5e2f793b59a 11133 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
screamer 0:c5e2f793b59a 11134 } SDHC_Type, *SDHC_MemMapPtr;
screamer 0:c5e2f793b59a 11135
screamer 0:c5e2f793b59a 11136 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 11137 -- SDHC - Register accessor macros
screamer 0:c5e2f793b59a 11138 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 11139
screamer 0:c5e2f793b59a 11140 /*!
screamer 0:c5e2f793b59a 11141 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
screamer 0:c5e2f793b59a 11142 * @{
screamer 0:c5e2f793b59a 11143 */
screamer 0:c5e2f793b59a 11144
screamer 0:c5e2f793b59a 11145
screamer 0:c5e2f793b59a 11146 /* SDHC - Register accessors */
screamer 0:c5e2f793b59a 11147 #define SDHC_DSADDR_REG(base) ((base)->DSADDR)
screamer 0:c5e2f793b59a 11148 #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
screamer 0:c5e2f793b59a 11149 #define SDHC_CMDARG_REG(base) ((base)->CMDARG)
screamer 0:c5e2f793b59a 11150 #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
screamer 0:c5e2f793b59a 11151 #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
screamer 0:c5e2f793b59a 11152 #define SDHC_DATPORT_REG(base) ((base)->DATPORT)
screamer 0:c5e2f793b59a 11153 #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
screamer 0:c5e2f793b59a 11154 #define SDHC_PROCTL_REG(base) ((base)->PROCTL)
screamer 0:c5e2f793b59a 11155 #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
screamer 0:c5e2f793b59a 11156 #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
screamer 0:c5e2f793b59a 11157 #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
screamer 0:c5e2f793b59a 11158 #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
screamer 0:c5e2f793b59a 11159 #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
screamer 0:c5e2f793b59a 11160 #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
screamer 0:c5e2f793b59a 11161 #define SDHC_WML_REG(base) ((base)->WML)
screamer 0:c5e2f793b59a 11162 #define SDHC_FEVT_REG(base) ((base)->FEVT)
screamer 0:c5e2f793b59a 11163 #define SDHC_ADMAES_REG(base) ((base)->ADMAES)
screamer 0:c5e2f793b59a 11164 #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
screamer 0:c5e2f793b59a 11165 #define SDHC_VENDOR_REG(base) ((base)->VENDOR)
screamer 0:c5e2f793b59a 11166 #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
screamer 0:c5e2f793b59a 11167 #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
screamer 0:c5e2f793b59a 11168
screamer 0:c5e2f793b59a 11169 /*!
screamer 0:c5e2f793b59a 11170 * @}
screamer 0:c5e2f793b59a 11171 */ /* end of group SDHC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 11172
screamer 0:c5e2f793b59a 11173
screamer 0:c5e2f793b59a 11174 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 11175 -- SDHC Register Masks
screamer 0:c5e2f793b59a 11176 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 11177
screamer 0:c5e2f793b59a 11178 /*!
screamer 0:c5e2f793b59a 11179 * @addtogroup SDHC_Register_Masks SDHC Register Masks
screamer 0:c5e2f793b59a 11180 * @{
screamer 0:c5e2f793b59a 11181 */
screamer 0:c5e2f793b59a 11182
screamer 0:c5e2f793b59a 11183 /* DSADDR Bit Fields */
screamer 0:c5e2f793b59a 11184 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
screamer 0:c5e2f793b59a 11185 #define SDHC_DSADDR_DSADDR_SHIFT 2
screamer 0:c5e2f793b59a 11186 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
screamer 0:c5e2f793b59a 11187 /* BLKATTR Bit Fields */
screamer 0:c5e2f793b59a 11188 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
screamer 0:c5e2f793b59a 11189 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
screamer 0:c5e2f793b59a 11190 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
screamer 0:c5e2f793b59a 11191 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 11192 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
screamer 0:c5e2f793b59a 11193 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
screamer 0:c5e2f793b59a 11194 /* CMDARG Bit Fields */
screamer 0:c5e2f793b59a 11195 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11196 #define SDHC_CMDARG_CMDARG_SHIFT 0
screamer 0:c5e2f793b59a 11197 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
screamer 0:c5e2f793b59a 11198 /* XFERTYP Bit Fields */
screamer 0:c5e2f793b59a 11199 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
screamer 0:c5e2f793b59a 11200 #define SDHC_XFERTYP_DMAEN_SHIFT 0
screamer 0:c5e2f793b59a 11201 #define SDHC_XFERTYP_BCEN_MASK 0x2u
screamer 0:c5e2f793b59a 11202 #define SDHC_XFERTYP_BCEN_SHIFT 1
screamer 0:c5e2f793b59a 11203 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
screamer 0:c5e2f793b59a 11204 #define SDHC_XFERTYP_AC12EN_SHIFT 2
screamer 0:c5e2f793b59a 11205 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
screamer 0:c5e2f793b59a 11206 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
screamer 0:c5e2f793b59a 11207 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
screamer 0:c5e2f793b59a 11208 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
screamer 0:c5e2f793b59a 11209 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
screamer 0:c5e2f793b59a 11210 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
screamer 0:c5e2f793b59a 11211 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
screamer 0:c5e2f793b59a 11212 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
screamer 0:c5e2f793b59a 11213 #define SDHC_XFERTYP_CCCEN_SHIFT 19
screamer 0:c5e2f793b59a 11214 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
screamer 0:c5e2f793b59a 11215 #define SDHC_XFERTYP_CICEN_SHIFT 20
screamer 0:c5e2f793b59a 11216 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
screamer 0:c5e2f793b59a 11217 #define SDHC_XFERTYP_DPSEL_SHIFT 21
screamer 0:c5e2f793b59a 11218 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
screamer 0:c5e2f793b59a 11219 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
screamer 0:c5e2f793b59a 11220 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
screamer 0:c5e2f793b59a 11221 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
screamer 0:c5e2f793b59a 11222 #define SDHC_XFERTYP_CMDINX_SHIFT 24
screamer 0:c5e2f793b59a 11223 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
screamer 0:c5e2f793b59a 11224 /* CMDRSP Bit Fields */
screamer 0:c5e2f793b59a 11225 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11226 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
screamer 0:c5e2f793b59a 11227 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
screamer 0:c5e2f793b59a 11228 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11229 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
screamer 0:c5e2f793b59a 11230 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
screamer 0:c5e2f793b59a 11231 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11232 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
screamer 0:c5e2f793b59a 11233 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
screamer 0:c5e2f793b59a 11234 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11235 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
screamer 0:c5e2f793b59a 11236 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
screamer 0:c5e2f793b59a 11237 /* DATPORT Bit Fields */
screamer 0:c5e2f793b59a 11238 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11239 #define SDHC_DATPORT_DATCONT_SHIFT 0
screamer 0:c5e2f793b59a 11240 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
screamer 0:c5e2f793b59a 11241 /* PRSSTAT Bit Fields */
screamer 0:c5e2f793b59a 11242 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
screamer 0:c5e2f793b59a 11243 #define SDHC_PRSSTAT_CIHB_SHIFT 0
screamer 0:c5e2f793b59a 11244 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
screamer 0:c5e2f793b59a 11245 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
screamer 0:c5e2f793b59a 11246 #define SDHC_PRSSTAT_DLA_MASK 0x4u
screamer 0:c5e2f793b59a 11247 #define SDHC_PRSSTAT_DLA_SHIFT 2
screamer 0:c5e2f793b59a 11248 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
screamer 0:c5e2f793b59a 11249 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
screamer 0:c5e2f793b59a 11250 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
screamer 0:c5e2f793b59a 11251 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
screamer 0:c5e2f793b59a 11252 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
screamer 0:c5e2f793b59a 11253 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
screamer 0:c5e2f793b59a 11254 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
screamer 0:c5e2f793b59a 11255 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
screamer 0:c5e2f793b59a 11256 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
screamer 0:c5e2f793b59a 11257 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
screamer 0:c5e2f793b59a 11258 #define SDHC_PRSSTAT_WTA_MASK 0x100u
screamer 0:c5e2f793b59a 11259 #define SDHC_PRSSTAT_WTA_SHIFT 8
screamer 0:c5e2f793b59a 11260 #define SDHC_PRSSTAT_RTA_MASK 0x200u
screamer 0:c5e2f793b59a 11261 #define SDHC_PRSSTAT_RTA_SHIFT 9
screamer 0:c5e2f793b59a 11262 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
screamer 0:c5e2f793b59a 11263 #define SDHC_PRSSTAT_BWEN_SHIFT 10
screamer 0:c5e2f793b59a 11264 #define SDHC_PRSSTAT_BREN_MASK 0x800u
screamer 0:c5e2f793b59a 11265 #define SDHC_PRSSTAT_BREN_SHIFT 11
screamer 0:c5e2f793b59a 11266 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
screamer 0:c5e2f793b59a 11267 #define SDHC_PRSSTAT_CINS_SHIFT 16
screamer 0:c5e2f793b59a 11268 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
screamer 0:c5e2f793b59a 11269 #define SDHC_PRSSTAT_CLSL_SHIFT 23
screamer 0:c5e2f793b59a 11270 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
screamer 0:c5e2f793b59a 11271 #define SDHC_PRSSTAT_DLSL_SHIFT 24
screamer 0:c5e2f793b59a 11272 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
screamer 0:c5e2f793b59a 11273 /* PROCTL Bit Fields */
screamer 0:c5e2f793b59a 11274 #define SDHC_PROCTL_LCTL_MASK 0x1u
screamer 0:c5e2f793b59a 11275 #define SDHC_PROCTL_LCTL_SHIFT 0
screamer 0:c5e2f793b59a 11276 #define SDHC_PROCTL_DTW_MASK 0x6u
screamer 0:c5e2f793b59a 11277 #define SDHC_PROCTL_DTW_SHIFT 1
screamer 0:c5e2f793b59a 11278 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
screamer 0:c5e2f793b59a 11279 #define SDHC_PROCTL_D3CD_MASK 0x8u
screamer 0:c5e2f793b59a 11280 #define SDHC_PROCTL_D3CD_SHIFT 3
screamer 0:c5e2f793b59a 11281 #define SDHC_PROCTL_EMODE_MASK 0x30u
screamer 0:c5e2f793b59a 11282 #define SDHC_PROCTL_EMODE_SHIFT 4
screamer 0:c5e2f793b59a 11283 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
screamer 0:c5e2f793b59a 11284 #define SDHC_PROCTL_CDTL_MASK 0x40u
screamer 0:c5e2f793b59a 11285 #define SDHC_PROCTL_CDTL_SHIFT 6
screamer 0:c5e2f793b59a 11286 #define SDHC_PROCTL_CDSS_MASK 0x80u
screamer 0:c5e2f793b59a 11287 #define SDHC_PROCTL_CDSS_SHIFT 7
screamer 0:c5e2f793b59a 11288 #define SDHC_PROCTL_DMAS_MASK 0x300u
screamer 0:c5e2f793b59a 11289 #define SDHC_PROCTL_DMAS_SHIFT 8
screamer 0:c5e2f793b59a 11290 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
screamer 0:c5e2f793b59a 11291 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
screamer 0:c5e2f793b59a 11292 #define SDHC_PROCTL_SABGREQ_SHIFT 16
screamer 0:c5e2f793b59a 11293 #define SDHC_PROCTL_CREQ_MASK 0x20000u
screamer 0:c5e2f793b59a 11294 #define SDHC_PROCTL_CREQ_SHIFT 17
screamer 0:c5e2f793b59a 11295 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
screamer 0:c5e2f793b59a 11296 #define SDHC_PROCTL_RWCTL_SHIFT 18
screamer 0:c5e2f793b59a 11297 #define SDHC_PROCTL_IABG_MASK 0x80000u
screamer 0:c5e2f793b59a 11298 #define SDHC_PROCTL_IABG_SHIFT 19
screamer 0:c5e2f793b59a 11299 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
screamer 0:c5e2f793b59a 11300 #define SDHC_PROCTL_WECINT_SHIFT 24
screamer 0:c5e2f793b59a 11301 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
screamer 0:c5e2f793b59a 11302 #define SDHC_PROCTL_WECINS_SHIFT 25
screamer 0:c5e2f793b59a 11303 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
screamer 0:c5e2f793b59a 11304 #define SDHC_PROCTL_WECRM_SHIFT 26
screamer 0:c5e2f793b59a 11305 /* SYSCTL Bit Fields */
screamer 0:c5e2f793b59a 11306 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
screamer 0:c5e2f793b59a 11307 #define SDHC_SYSCTL_IPGEN_SHIFT 0
screamer 0:c5e2f793b59a 11308 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
screamer 0:c5e2f793b59a 11309 #define SDHC_SYSCTL_HCKEN_SHIFT 1
screamer 0:c5e2f793b59a 11310 #define SDHC_SYSCTL_PEREN_MASK 0x4u
screamer 0:c5e2f793b59a 11311 #define SDHC_SYSCTL_PEREN_SHIFT 2
screamer 0:c5e2f793b59a 11312 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
screamer 0:c5e2f793b59a 11313 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
screamer 0:c5e2f793b59a 11314 #define SDHC_SYSCTL_DVS_MASK 0xF0u
screamer 0:c5e2f793b59a 11315 #define SDHC_SYSCTL_DVS_SHIFT 4
screamer 0:c5e2f793b59a 11316 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
screamer 0:c5e2f793b59a 11317 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
screamer 0:c5e2f793b59a 11318 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
screamer 0:c5e2f793b59a 11319 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
screamer 0:c5e2f793b59a 11320 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
screamer 0:c5e2f793b59a 11321 #define SDHC_SYSCTL_DTOCV_SHIFT 16
screamer 0:c5e2f793b59a 11322 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
screamer 0:c5e2f793b59a 11323 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
screamer 0:c5e2f793b59a 11324 #define SDHC_SYSCTL_RSTA_SHIFT 24
screamer 0:c5e2f793b59a 11325 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
screamer 0:c5e2f793b59a 11326 #define SDHC_SYSCTL_RSTC_SHIFT 25
screamer 0:c5e2f793b59a 11327 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
screamer 0:c5e2f793b59a 11328 #define SDHC_SYSCTL_RSTD_SHIFT 26
screamer 0:c5e2f793b59a 11329 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
screamer 0:c5e2f793b59a 11330 #define SDHC_SYSCTL_INITA_SHIFT 27
screamer 0:c5e2f793b59a 11331 /* IRQSTAT Bit Fields */
screamer 0:c5e2f793b59a 11332 #define SDHC_IRQSTAT_CC_MASK 0x1u
screamer 0:c5e2f793b59a 11333 #define SDHC_IRQSTAT_CC_SHIFT 0
screamer 0:c5e2f793b59a 11334 #define SDHC_IRQSTAT_TC_MASK 0x2u
screamer 0:c5e2f793b59a 11335 #define SDHC_IRQSTAT_TC_SHIFT 1
screamer 0:c5e2f793b59a 11336 #define SDHC_IRQSTAT_BGE_MASK 0x4u
screamer 0:c5e2f793b59a 11337 #define SDHC_IRQSTAT_BGE_SHIFT 2
screamer 0:c5e2f793b59a 11338 #define SDHC_IRQSTAT_DINT_MASK 0x8u
screamer 0:c5e2f793b59a 11339 #define SDHC_IRQSTAT_DINT_SHIFT 3
screamer 0:c5e2f793b59a 11340 #define SDHC_IRQSTAT_BWR_MASK 0x10u
screamer 0:c5e2f793b59a 11341 #define SDHC_IRQSTAT_BWR_SHIFT 4
screamer 0:c5e2f793b59a 11342 #define SDHC_IRQSTAT_BRR_MASK 0x20u
screamer 0:c5e2f793b59a 11343 #define SDHC_IRQSTAT_BRR_SHIFT 5
screamer 0:c5e2f793b59a 11344 #define SDHC_IRQSTAT_CINS_MASK 0x40u
screamer 0:c5e2f793b59a 11345 #define SDHC_IRQSTAT_CINS_SHIFT 6
screamer 0:c5e2f793b59a 11346 #define SDHC_IRQSTAT_CRM_MASK 0x80u
screamer 0:c5e2f793b59a 11347 #define SDHC_IRQSTAT_CRM_SHIFT 7
screamer 0:c5e2f793b59a 11348 #define SDHC_IRQSTAT_CINT_MASK 0x100u
screamer 0:c5e2f793b59a 11349 #define SDHC_IRQSTAT_CINT_SHIFT 8
screamer 0:c5e2f793b59a 11350 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
screamer 0:c5e2f793b59a 11351 #define SDHC_IRQSTAT_CTOE_SHIFT 16
screamer 0:c5e2f793b59a 11352 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
screamer 0:c5e2f793b59a 11353 #define SDHC_IRQSTAT_CCE_SHIFT 17
screamer 0:c5e2f793b59a 11354 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
screamer 0:c5e2f793b59a 11355 #define SDHC_IRQSTAT_CEBE_SHIFT 18
screamer 0:c5e2f793b59a 11356 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
screamer 0:c5e2f793b59a 11357 #define SDHC_IRQSTAT_CIE_SHIFT 19
screamer 0:c5e2f793b59a 11358 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
screamer 0:c5e2f793b59a 11359 #define SDHC_IRQSTAT_DTOE_SHIFT 20
screamer 0:c5e2f793b59a 11360 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
screamer 0:c5e2f793b59a 11361 #define SDHC_IRQSTAT_DCE_SHIFT 21
screamer 0:c5e2f793b59a 11362 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
screamer 0:c5e2f793b59a 11363 #define SDHC_IRQSTAT_DEBE_SHIFT 22
screamer 0:c5e2f793b59a 11364 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
screamer 0:c5e2f793b59a 11365 #define SDHC_IRQSTAT_AC12E_SHIFT 24
screamer 0:c5e2f793b59a 11366 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
screamer 0:c5e2f793b59a 11367 #define SDHC_IRQSTAT_DMAE_SHIFT 28
screamer 0:c5e2f793b59a 11368 /* IRQSTATEN Bit Fields */
screamer 0:c5e2f793b59a 11369 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
screamer 0:c5e2f793b59a 11370 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
screamer 0:c5e2f793b59a 11371 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
screamer 0:c5e2f793b59a 11372 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
screamer 0:c5e2f793b59a 11373 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
screamer 0:c5e2f793b59a 11374 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
screamer 0:c5e2f793b59a 11375 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
screamer 0:c5e2f793b59a 11376 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
screamer 0:c5e2f793b59a 11377 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
screamer 0:c5e2f793b59a 11378 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
screamer 0:c5e2f793b59a 11379 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
screamer 0:c5e2f793b59a 11380 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
screamer 0:c5e2f793b59a 11381 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
screamer 0:c5e2f793b59a 11382 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
screamer 0:c5e2f793b59a 11383 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
screamer 0:c5e2f793b59a 11384 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
screamer 0:c5e2f793b59a 11385 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
screamer 0:c5e2f793b59a 11386 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
screamer 0:c5e2f793b59a 11387 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
screamer 0:c5e2f793b59a 11388 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
screamer 0:c5e2f793b59a 11389 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
screamer 0:c5e2f793b59a 11390 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
screamer 0:c5e2f793b59a 11391 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
screamer 0:c5e2f793b59a 11392 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
screamer 0:c5e2f793b59a 11393 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
screamer 0:c5e2f793b59a 11394 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
screamer 0:c5e2f793b59a 11395 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
screamer 0:c5e2f793b59a 11396 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
screamer 0:c5e2f793b59a 11397 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
screamer 0:c5e2f793b59a 11398 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
screamer 0:c5e2f793b59a 11399 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
screamer 0:c5e2f793b59a 11400 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
screamer 0:c5e2f793b59a 11401 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
screamer 0:c5e2f793b59a 11402 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
screamer 0:c5e2f793b59a 11403 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
screamer 0:c5e2f793b59a 11404 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
screamer 0:c5e2f793b59a 11405 /* IRQSIGEN Bit Fields */
screamer 0:c5e2f793b59a 11406 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
screamer 0:c5e2f793b59a 11407 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
screamer 0:c5e2f793b59a 11408 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
screamer 0:c5e2f793b59a 11409 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
screamer 0:c5e2f793b59a 11410 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
screamer 0:c5e2f793b59a 11411 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
screamer 0:c5e2f793b59a 11412 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
screamer 0:c5e2f793b59a 11413 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
screamer 0:c5e2f793b59a 11414 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
screamer 0:c5e2f793b59a 11415 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
screamer 0:c5e2f793b59a 11416 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
screamer 0:c5e2f793b59a 11417 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
screamer 0:c5e2f793b59a 11418 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
screamer 0:c5e2f793b59a 11419 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
screamer 0:c5e2f793b59a 11420 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
screamer 0:c5e2f793b59a 11421 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
screamer 0:c5e2f793b59a 11422 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
screamer 0:c5e2f793b59a 11423 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
screamer 0:c5e2f793b59a 11424 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
screamer 0:c5e2f793b59a 11425 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
screamer 0:c5e2f793b59a 11426 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
screamer 0:c5e2f793b59a 11427 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
screamer 0:c5e2f793b59a 11428 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
screamer 0:c5e2f793b59a 11429 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
screamer 0:c5e2f793b59a 11430 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
screamer 0:c5e2f793b59a 11431 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
screamer 0:c5e2f793b59a 11432 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
screamer 0:c5e2f793b59a 11433 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
screamer 0:c5e2f793b59a 11434 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
screamer 0:c5e2f793b59a 11435 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
screamer 0:c5e2f793b59a 11436 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
screamer 0:c5e2f793b59a 11437 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
screamer 0:c5e2f793b59a 11438 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
screamer 0:c5e2f793b59a 11439 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
screamer 0:c5e2f793b59a 11440 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
screamer 0:c5e2f793b59a 11441 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
screamer 0:c5e2f793b59a 11442 /* AC12ERR Bit Fields */
screamer 0:c5e2f793b59a 11443 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
screamer 0:c5e2f793b59a 11444 #define SDHC_AC12ERR_AC12NE_SHIFT 0
screamer 0:c5e2f793b59a 11445 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
screamer 0:c5e2f793b59a 11446 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
screamer 0:c5e2f793b59a 11447 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
screamer 0:c5e2f793b59a 11448 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
screamer 0:c5e2f793b59a 11449 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
screamer 0:c5e2f793b59a 11450 #define SDHC_AC12ERR_AC12CE_SHIFT 3
screamer 0:c5e2f793b59a 11451 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
screamer 0:c5e2f793b59a 11452 #define SDHC_AC12ERR_AC12IE_SHIFT 4
screamer 0:c5e2f793b59a 11453 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
screamer 0:c5e2f793b59a 11454 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
screamer 0:c5e2f793b59a 11455 /* HTCAPBLT Bit Fields */
screamer 0:c5e2f793b59a 11456 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
screamer 0:c5e2f793b59a 11457 #define SDHC_HTCAPBLT_MBL_SHIFT 16
screamer 0:c5e2f793b59a 11458 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
screamer 0:c5e2f793b59a 11459 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
screamer 0:c5e2f793b59a 11460 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
screamer 0:c5e2f793b59a 11461 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
screamer 0:c5e2f793b59a 11462 #define SDHC_HTCAPBLT_HSS_SHIFT 21
screamer 0:c5e2f793b59a 11463 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
screamer 0:c5e2f793b59a 11464 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
screamer 0:c5e2f793b59a 11465 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
screamer 0:c5e2f793b59a 11466 #define SDHC_HTCAPBLT_SRS_SHIFT 23
screamer 0:c5e2f793b59a 11467 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
screamer 0:c5e2f793b59a 11468 #define SDHC_HTCAPBLT_VS33_SHIFT 24
screamer 0:c5e2f793b59a 11469 /* WML Bit Fields */
screamer 0:c5e2f793b59a 11470 #define SDHC_WML_RDWML_MASK 0xFFu
screamer 0:c5e2f793b59a 11471 #define SDHC_WML_RDWML_SHIFT 0
screamer 0:c5e2f793b59a 11472 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
screamer 0:c5e2f793b59a 11473 #define SDHC_WML_WRWML_MASK 0xFF0000u
screamer 0:c5e2f793b59a 11474 #define SDHC_WML_WRWML_SHIFT 16
screamer 0:c5e2f793b59a 11475 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
screamer 0:c5e2f793b59a 11476 /* FEVT Bit Fields */
screamer 0:c5e2f793b59a 11477 #define SDHC_FEVT_AC12NE_MASK 0x1u
screamer 0:c5e2f793b59a 11478 #define SDHC_FEVT_AC12NE_SHIFT 0
screamer 0:c5e2f793b59a 11479 #define SDHC_FEVT_AC12TOE_MASK 0x2u
screamer 0:c5e2f793b59a 11480 #define SDHC_FEVT_AC12TOE_SHIFT 1
screamer 0:c5e2f793b59a 11481 #define SDHC_FEVT_AC12CE_MASK 0x4u
screamer 0:c5e2f793b59a 11482 #define SDHC_FEVT_AC12CE_SHIFT 2
screamer 0:c5e2f793b59a 11483 #define SDHC_FEVT_AC12EBE_MASK 0x8u
screamer 0:c5e2f793b59a 11484 #define SDHC_FEVT_AC12EBE_SHIFT 3
screamer 0:c5e2f793b59a 11485 #define SDHC_FEVT_AC12IE_MASK 0x10u
screamer 0:c5e2f793b59a 11486 #define SDHC_FEVT_AC12IE_SHIFT 4
screamer 0:c5e2f793b59a 11487 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
screamer 0:c5e2f793b59a 11488 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
screamer 0:c5e2f793b59a 11489 #define SDHC_FEVT_CTOE_MASK 0x10000u
screamer 0:c5e2f793b59a 11490 #define SDHC_FEVT_CTOE_SHIFT 16
screamer 0:c5e2f793b59a 11491 #define SDHC_FEVT_CCE_MASK 0x20000u
screamer 0:c5e2f793b59a 11492 #define SDHC_FEVT_CCE_SHIFT 17
screamer 0:c5e2f793b59a 11493 #define SDHC_FEVT_CEBE_MASK 0x40000u
screamer 0:c5e2f793b59a 11494 #define SDHC_FEVT_CEBE_SHIFT 18
screamer 0:c5e2f793b59a 11495 #define SDHC_FEVT_CIE_MASK 0x80000u
screamer 0:c5e2f793b59a 11496 #define SDHC_FEVT_CIE_SHIFT 19
screamer 0:c5e2f793b59a 11497 #define SDHC_FEVT_DTOE_MASK 0x100000u
screamer 0:c5e2f793b59a 11498 #define SDHC_FEVT_DTOE_SHIFT 20
screamer 0:c5e2f793b59a 11499 #define SDHC_FEVT_DCE_MASK 0x200000u
screamer 0:c5e2f793b59a 11500 #define SDHC_FEVT_DCE_SHIFT 21
screamer 0:c5e2f793b59a 11501 #define SDHC_FEVT_DEBE_MASK 0x400000u
screamer 0:c5e2f793b59a 11502 #define SDHC_FEVT_DEBE_SHIFT 22
screamer 0:c5e2f793b59a 11503 #define SDHC_FEVT_AC12E_MASK 0x1000000u
screamer 0:c5e2f793b59a 11504 #define SDHC_FEVT_AC12E_SHIFT 24
screamer 0:c5e2f793b59a 11505 #define SDHC_FEVT_DMAE_MASK 0x10000000u
screamer 0:c5e2f793b59a 11506 #define SDHC_FEVT_DMAE_SHIFT 28
screamer 0:c5e2f793b59a 11507 #define SDHC_FEVT_CINT_MASK 0x80000000u
screamer 0:c5e2f793b59a 11508 #define SDHC_FEVT_CINT_SHIFT 31
screamer 0:c5e2f793b59a 11509 /* ADMAES Bit Fields */
screamer 0:c5e2f793b59a 11510 #define SDHC_ADMAES_ADMAES_MASK 0x3u
screamer 0:c5e2f793b59a 11511 #define SDHC_ADMAES_ADMAES_SHIFT 0
screamer 0:c5e2f793b59a 11512 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
screamer 0:c5e2f793b59a 11513 #define SDHC_ADMAES_ADMALME_MASK 0x4u
screamer 0:c5e2f793b59a 11514 #define SDHC_ADMAES_ADMALME_SHIFT 2
screamer 0:c5e2f793b59a 11515 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
screamer 0:c5e2f793b59a 11516 #define SDHC_ADMAES_ADMADCE_SHIFT 3
screamer 0:c5e2f793b59a 11517 /* ADSADDR Bit Fields */
screamer 0:c5e2f793b59a 11518 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
screamer 0:c5e2f793b59a 11519 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
screamer 0:c5e2f793b59a 11520 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
screamer 0:c5e2f793b59a 11521 /* VENDOR Bit Fields */
screamer 0:c5e2f793b59a 11522 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
screamer 0:c5e2f793b59a 11523 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
screamer 0:c5e2f793b59a 11524 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
screamer 0:c5e2f793b59a 11525 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
screamer 0:c5e2f793b59a 11526 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
screamer 0:c5e2f793b59a 11527 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
screamer 0:c5e2f793b59a 11528 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
screamer 0:c5e2f793b59a 11529 /* MMCBOOT Bit Fields */
screamer 0:c5e2f793b59a 11530 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
screamer 0:c5e2f793b59a 11531 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
screamer 0:c5e2f793b59a 11532 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
screamer 0:c5e2f793b59a 11533 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
screamer 0:c5e2f793b59a 11534 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
screamer 0:c5e2f793b59a 11535 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
screamer 0:c5e2f793b59a 11536 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
screamer 0:c5e2f793b59a 11537 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
screamer 0:c5e2f793b59a 11538 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
screamer 0:c5e2f793b59a 11539 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
screamer 0:c5e2f793b59a 11540 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
screamer 0:c5e2f793b59a 11541 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 11542 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
screamer 0:c5e2f793b59a 11543 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
screamer 0:c5e2f793b59a 11544 /* HOSTVER Bit Fields */
screamer 0:c5e2f793b59a 11545 #define SDHC_HOSTVER_SVN_MASK 0xFFu
screamer 0:c5e2f793b59a 11546 #define SDHC_HOSTVER_SVN_SHIFT 0
screamer 0:c5e2f793b59a 11547 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
screamer 0:c5e2f793b59a 11548 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
screamer 0:c5e2f793b59a 11549 #define SDHC_HOSTVER_VVN_SHIFT 8
screamer 0:c5e2f793b59a 11550 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
screamer 0:c5e2f793b59a 11551
screamer 0:c5e2f793b59a 11552 /*!
screamer 0:c5e2f793b59a 11553 * @}
screamer 0:c5e2f793b59a 11554 */ /* end of group SDHC_Register_Masks */
screamer 0:c5e2f793b59a 11555
screamer 0:c5e2f793b59a 11556
screamer 0:c5e2f793b59a 11557 /* SDHC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 11558 /** Peripheral SDHC base address */
screamer 0:c5e2f793b59a 11559 #define SDHC_BASE (0x400B1000u)
screamer 0:c5e2f793b59a 11560 /** Peripheral SDHC base pointer */
screamer 0:c5e2f793b59a 11561 #define SDHC ((SDHC_Type *)SDHC_BASE)
screamer 0:c5e2f793b59a 11562 #define SDHC_BASE_PTR (SDHC)
screamer 0:c5e2f793b59a 11563 /** Array initializer of SDHC peripheral base addresses */
screamer 0:c5e2f793b59a 11564 #define SDHC_BASE_ADDRS { SDHC_BASE }
screamer 0:c5e2f793b59a 11565 /** Array initializer of SDHC peripheral base pointers */
screamer 0:c5e2f793b59a 11566 #define SDHC_BASE_PTRS { SDHC }
screamer 0:c5e2f793b59a 11567 /** Interrupt vectors for the SDHC peripheral type */
screamer 0:c5e2f793b59a 11568 #define SDHC_IRQS { SDHC_IRQn }
screamer 0:c5e2f793b59a 11569
screamer 0:c5e2f793b59a 11570 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 11571 -- SDHC - Register accessor macros
screamer 0:c5e2f793b59a 11572 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 11573
screamer 0:c5e2f793b59a 11574 /*!
screamer 0:c5e2f793b59a 11575 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
screamer 0:c5e2f793b59a 11576 * @{
screamer 0:c5e2f793b59a 11577 */
screamer 0:c5e2f793b59a 11578
screamer 0:c5e2f793b59a 11579
screamer 0:c5e2f793b59a 11580 /* SDHC - Register instance definitions */
screamer 0:c5e2f793b59a 11581 /* SDHC */
screamer 0:c5e2f793b59a 11582 #define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
screamer 0:c5e2f793b59a 11583 #define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
screamer 0:c5e2f793b59a 11584 #define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
screamer 0:c5e2f793b59a 11585 #define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
screamer 0:c5e2f793b59a 11586 #define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
screamer 0:c5e2f793b59a 11587 #define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
screamer 0:c5e2f793b59a 11588 #define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
screamer 0:c5e2f793b59a 11589 #define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
screamer 0:c5e2f793b59a 11590 #define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
screamer 0:c5e2f793b59a 11591 #define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
screamer 0:c5e2f793b59a 11592 #define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
screamer 0:c5e2f793b59a 11593 #define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
screamer 0:c5e2f793b59a 11594 #define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
screamer 0:c5e2f793b59a 11595 #define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
screamer 0:c5e2f793b59a 11596 #define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
screamer 0:c5e2f793b59a 11597 #define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
screamer 0:c5e2f793b59a 11598 #define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
screamer 0:c5e2f793b59a 11599 #define SDHC_WML SDHC_WML_REG(SDHC)
screamer 0:c5e2f793b59a 11600 #define SDHC_FEVT SDHC_FEVT_REG(SDHC)
screamer 0:c5e2f793b59a 11601 #define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
screamer 0:c5e2f793b59a 11602 #define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
screamer 0:c5e2f793b59a 11603 #define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
screamer 0:c5e2f793b59a 11604 #define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
screamer 0:c5e2f793b59a 11605 #define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
screamer 0:c5e2f793b59a 11606
screamer 0:c5e2f793b59a 11607 /* SDHC - Register array accessors */
screamer 0:c5e2f793b59a 11608 #define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
screamer 0:c5e2f793b59a 11609
screamer 0:c5e2f793b59a 11610 /*!
screamer 0:c5e2f793b59a 11611 * @}
screamer 0:c5e2f793b59a 11612 */ /* end of group SDHC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 11613
screamer 0:c5e2f793b59a 11614
screamer 0:c5e2f793b59a 11615 /*!
screamer 0:c5e2f793b59a 11616 * @}
screamer 0:c5e2f793b59a 11617 */ /* end of group SDHC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 11618
screamer 0:c5e2f793b59a 11619
screamer 0:c5e2f793b59a 11620 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 11621 -- SIM Peripheral Access Layer
screamer 0:c5e2f793b59a 11622 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 11623
screamer 0:c5e2f793b59a 11624 /*!
screamer 0:c5e2f793b59a 11625 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
screamer 0:c5e2f793b59a 11626 * @{
screamer 0:c5e2f793b59a 11627 */
screamer 0:c5e2f793b59a 11628
screamer 0:c5e2f793b59a 11629 /** SIM - Register Layout Typedef */
screamer 0:c5e2f793b59a 11630 typedef struct {
screamer 0:c5e2f793b59a 11631 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
screamer 0:c5e2f793b59a 11632 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
screamer 0:c5e2f793b59a 11633 uint8_t RESERVED_0[4092];
screamer 0:c5e2f793b59a 11634 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
screamer 0:c5e2f793b59a 11635 uint8_t RESERVED_1[4];
screamer 0:c5e2f793b59a 11636 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
screamer 0:c5e2f793b59a 11637 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
screamer 0:c5e2f793b59a 11638 uint8_t RESERVED_2[4];
screamer 0:c5e2f793b59a 11639 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
screamer 0:c5e2f793b59a 11640 uint8_t RESERVED_3[8];
screamer 0:c5e2f793b59a 11641 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
screamer 0:c5e2f793b59a 11642 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
screamer 0:c5e2f793b59a 11643 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
screamer 0:c5e2f793b59a 11644 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
screamer 0:c5e2f793b59a 11645 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
screamer 0:c5e2f793b59a 11646 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
screamer 0:c5e2f793b59a 11647 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
screamer 0:c5e2f793b59a 11648 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
screamer 0:c5e2f793b59a 11649 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
screamer 0:c5e2f793b59a 11650 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
screamer 0:c5e2f793b59a 11651 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
screamer 0:c5e2f793b59a 11652 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
screamer 0:c5e2f793b59a 11653 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
screamer 0:c5e2f793b59a 11654 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
screamer 0:c5e2f793b59a 11655 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
screamer 0:c5e2f793b59a 11656 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
screamer 0:c5e2f793b59a 11657 } SIM_Type, *SIM_MemMapPtr;
screamer 0:c5e2f793b59a 11658
screamer 0:c5e2f793b59a 11659 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 11660 -- SIM - Register accessor macros
screamer 0:c5e2f793b59a 11661 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 11662
screamer 0:c5e2f793b59a 11663 /*!
screamer 0:c5e2f793b59a 11664 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
screamer 0:c5e2f793b59a 11665 * @{
screamer 0:c5e2f793b59a 11666 */
screamer 0:c5e2f793b59a 11667
screamer 0:c5e2f793b59a 11668
screamer 0:c5e2f793b59a 11669 /* SIM - Register accessors */
screamer 0:c5e2f793b59a 11670 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
screamer 0:c5e2f793b59a 11671 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
screamer 0:c5e2f793b59a 11672 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
screamer 0:c5e2f793b59a 11673 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
screamer 0:c5e2f793b59a 11674 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
screamer 0:c5e2f793b59a 11675 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
screamer 0:c5e2f793b59a 11676 #define SIM_SDID_REG(base) ((base)->SDID)
screamer 0:c5e2f793b59a 11677 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
screamer 0:c5e2f793b59a 11678 #define SIM_SCGC2_REG(base) ((base)->SCGC2)
screamer 0:c5e2f793b59a 11679 #define SIM_SCGC3_REG(base) ((base)->SCGC3)
screamer 0:c5e2f793b59a 11680 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
screamer 0:c5e2f793b59a 11681 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
screamer 0:c5e2f793b59a 11682 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
screamer 0:c5e2f793b59a 11683 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
screamer 0:c5e2f793b59a 11684 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
screamer 0:c5e2f793b59a 11685 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
screamer 0:c5e2f793b59a 11686 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
screamer 0:c5e2f793b59a 11687 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
screamer 0:c5e2f793b59a 11688 #define SIM_UIDH_REG(base) ((base)->UIDH)
screamer 0:c5e2f793b59a 11689 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
screamer 0:c5e2f793b59a 11690 #define SIM_UIDML_REG(base) ((base)->UIDML)
screamer 0:c5e2f793b59a 11691 #define SIM_UIDL_REG(base) ((base)->UIDL)
screamer 0:c5e2f793b59a 11692
screamer 0:c5e2f793b59a 11693 /*!
screamer 0:c5e2f793b59a 11694 * @}
screamer 0:c5e2f793b59a 11695 */ /* end of group SIM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 11696
screamer 0:c5e2f793b59a 11697
screamer 0:c5e2f793b59a 11698 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 11699 -- SIM Register Masks
screamer 0:c5e2f793b59a 11700 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 11701
screamer 0:c5e2f793b59a 11702 /*!
screamer 0:c5e2f793b59a 11703 * @addtogroup SIM_Register_Masks SIM Register Masks
screamer 0:c5e2f793b59a 11704 * @{
screamer 0:c5e2f793b59a 11705 */
screamer 0:c5e2f793b59a 11706
screamer 0:c5e2f793b59a 11707 /* SOPT1 Bit Fields */
screamer 0:c5e2f793b59a 11708 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
screamer 0:c5e2f793b59a 11709 #define SIM_SOPT1_RAMSIZE_SHIFT 12
screamer 0:c5e2f793b59a 11710 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
screamer 0:c5e2f793b59a 11711 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
screamer 0:c5e2f793b59a 11712 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
screamer 0:c5e2f793b59a 11713 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
screamer 0:c5e2f793b59a 11714 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
screamer 0:c5e2f793b59a 11715 #define SIM_SOPT1_USBVSTBY_SHIFT 29
screamer 0:c5e2f793b59a 11716 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
screamer 0:c5e2f793b59a 11717 #define SIM_SOPT1_USBSSTBY_SHIFT 30
screamer 0:c5e2f793b59a 11718 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
screamer 0:c5e2f793b59a 11719 #define SIM_SOPT1_USBREGEN_SHIFT 31
screamer 0:c5e2f793b59a 11720 /* SOPT1CFG Bit Fields */
screamer 0:c5e2f793b59a 11721 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
screamer 0:c5e2f793b59a 11722 #define SIM_SOPT1CFG_URWE_SHIFT 24
screamer 0:c5e2f793b59a 11723 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
screamer 0:c5e2f793b59a 11724 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
screamer 0:c5e2f793b59a 11725 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
screamer 0:c5e2f793b59a 11726 #define SIM_SOPT1CFG_USSWE_SHIFT 26
screamer 0:c5e2f793b59a 11727 /* SOPT2 Bit Fields */
screamer 0:c5e2f793b59a 11728 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
screamer 0:c5e2f793b59a 11729 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
screamer 0:c5e2f793b59a 11730 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
screamer 0:c5e2f793b59a 11731 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
screamer 0:c5e2f793b59a 11732 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
screamer 0:c5e2f793b59a 11733 #define SIM_SOPT2_FBSL_MASK 0x300u
screamer 0:c5e2f793b59a 11734 #define SIM_SOPT2_FBSL_SHIFT 8
screamer 0:c5e2f793b59a 11735 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
screamer 0:c5e2f793b59a 11736 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
screamer 0:c5e2f793b59a 11737 #define SIM_SOPT2_PTD7PAD_SHIFT 11
screamer 0:c5e2f793b59a 11738 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
screamer 0:c5e2f793b59a 11739 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
screamer 0:c5e2f793b59a 11740 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
screamer 0:c5e2f793b59a 11741 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
screamer 0:c5e2f793b59a 11742 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
screamer 0:c5e2f793b59a 11743 #define SIM_SOPT2_USBSRC_MASK 0x40000u
screamer 0:c5e2f793b59a 11744 #define SIM_SOPT2_USBSRC_SHIFT 18
screamer 0:c5e2f793b59a 11745 #define SIM_SOPT2_RMIISRC_MASK 0x80000u
screamer 0:c5e2f793b59a 11746 #define SIM_SOPT2_RMIISRC_SHIFT 19
screamer 0:c5e2f793b59a 11747 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
screamer 0:c5e2f793b59a 11748 #define SIM_SOPT2_TIMESRC_SHIFT 20
screamer 0:c5e2f793b59a 11749 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
screamer 0:c5e2f793b59a 11750 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
screamer 0:c5e2f793b59a 11751 #define SIM_SOPT2_SDHCSRC_SHIFT 28
screamer 0:c5e2f793b59a 11752 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
screamer 0:c5e2f793b59a 11753 /* SOPT4 Bit Fields */
screamer 0:c5e2f793b59a 11754 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
screamer 0:c5e2f793b59a 11755 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
screamer 0:c5e2f793b59a 11756 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
screamer 0:c5e2f793b59a 11757 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
screamer 0:c5e2f793b59a 11758 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
screamer 0:c5e2f793b59a 11759 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
screamer 0:c5e2f793b59a 11760 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
screamer 0:c5e2f793b59a 11761 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
screamer 0:c5e2f793b59a 11762 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
screamer 0:c5e2f793b59a 11763 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
screamer 0:c5e2f793b59a 11764 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
screamer 0:c5e2f793b59a 11765 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
screamer 0:c5e2f793b59a 11766 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
screamer 0:c5e2f793b59a 11767 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
screamer 0:c5e2f793b59a 11768 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
screamer 0:c5e2f793b59a 11769 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
screamer 0:c5e2f793b59a 11770 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
screamer 0:c5e2f793b59a 11771 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
screamer 0:c5e2f793b59a 11772 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
screamer 0:c5e2f793b59a 11773 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
screamer 0:c5e2f793b59a 11774 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
screamer 0:c5e2f793b59a 11775 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
screamer 0:c5e2f793b59a 11776 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
screamer 0:c5e2f793b59a 11777 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
screamer 0:c5e2f793b59a 11778 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
screamer 0:c5e2f793b59a 11779 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
screamer 0:c5e2f793b59a 11780 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
screamer 0:c5e2f793b59a 11781 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
screamer 0:c5e2f793b59a 11782 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
screamer 0:c5e2f793b59a 11783 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
screamer 0:c5e2f793b59a 11784 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
screamer 0:c5e2f793b59a 11785 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
screamer 0:c5e2f793b59a 11786 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
screamer 0:c5e2f793b59a 11787 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
screamer 0:c5e2f793b59a 11788 /* SOPT5 Bit Fields */
screamer 0:c5e2f793b59a 11789 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
screamer 0:c5e2f793b59a 11790 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
screamer 0:c5e2f793b59a 11791 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
screamer 0:c5e2f793b59a 11792 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
screamer 0:c5e2f793b59a 11793 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
screamer 0:c5e2f793b59a 11794 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
screamer 0:c5e2f793b59a 11795 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
screamer 0:c5e2f793b59a 11796 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
screamer 0:c5e2f793b59a 11797 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
screamer 0:c5e2f793b59a 11798 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
screamer 0:c5e2f793b59a 11799 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
screamer 0:c5e2f793b59a 11800 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
screamer 0:c5e2f793b59a 11801 /* SOPT7 Bit Fields */
screamer 0:c5e2f793b59a 11802 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
screamer 0:c5e2f793b59a 11803 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
screamer 0:c5e2f793b59a 11804 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
screamer 0:c5e2f793b59a 11805 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
screamer 0:c5e2f793b59a 11806 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
screamer 0:c5e2f793b59a 11807 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
screamer 0:c5e2f793b59a 11808 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
screamer 0:c5e2f793b59a 11809 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
screamer 0:c5e2f793b59a 11810 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
screamer 0:c5e2f793b59a 11811 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
screamer 0:c5e2f793b59a 11812 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
screamer 0:c5e2f793b59a 11813 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
screamer 0:c5e2f793b59a 11814 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
screamer 0:c5e2f793b59a 11815 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
screamer 0:c5e2f793b59a 11816 /* SDID Bit Fields */
screamer 0:c5e2f793b59a 11817 #define SIM_SDID_PINID_MASK 0xFu
screamer 0:c5e2f793b59a 11818 #define SIM_SDID_PINID_SHIFT 0
screamer 0:c5e2f793b59a 11819 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
screamer 0:c5e2f793b59a 11820 #define SIM_SDID_FAMID_MASK 0x70u
screamer 0:c5e2f793b59a 11821 #define SIM_SDID_FAMID_SHIFT 4
screamer 0:c5e2f793b59a 11822 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
screamer 0:c5e2f793b59a 11823 #define SIM_SDID_DIEID_MASK 0xF80u
screamer 0:c5e2f793b59a 11824 #define SIM_SDID_DIEID_SHIFT 7
screamer 0:c5e2f793b59a 11825 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
screamer 0:c5e2f793b59a 11826 #define SIM_SDID_REVID_MASK 0xF000u
screamer 0:c5e2f793b59a 11827 #define SIM_SDID_REVID_SHIFT 12
screamer 0:c5e2f793b59a 11828 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
screamer 0:c5e2f793b59a 11829 #define SIM_SDID_SERIESID_MASK 0xF00000u
screamer 0:c5e2f793b59a 11830 #define SIM_SDID_SERIESID_SHIFT 20
screamer 0:c5e2f793b59a 11831 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
screamer 0:c5e2f793b59a 11832 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
screamer 0:c5e2f793b59a 11833 #define SIM_SDID_SUBFAMID_SHIFT 24
screamer 0:c5e2f793b59a 11834 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
screamer 0:c5e2f793b59a 11835 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
screamer 0:c5e2f793b59a 11836 #define SIM_SDID_FAMILYID_SHIFT 28
screamer 0:c5e2f793b59a 11837 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
screamer 0:c5e2f793b59a 11838 /* SCGC1 Bit Fields */
screamer 0:c5e2f793b59a 11839 #define SIM_SCGC1_I2C2_MASK 0x40u
screamer 0:c5e2f793b59a 11840 #define SIM_SCGC1_I2C2_SHIFT 6
screamer 0:c5e2f793b59a 11841 #define SIM_SCGC1_UART4_MASK 0x400u
screamer 0:c5e2f793b59a 11842 #define SIM_SCGC1_UART4_SHIFT 10
screamer 0:c5e2f793b59a 11843 #define SIM_SCGC1_UART5_MASK 0x800u
screamer 0:c5e2f793b59a 11844 #define SIM_SCGC1_UART5_SHIFT 11
screamer 0:c5e2f793b59a 11845 /* SCGC2 Bit Fields */
screamer 0:c5e2f793b59a 11846 #define SIM_SCGC2_ENET_MASK 0x1u
screamer 0:c5e2f793b59a 11847 #define SIM_SCGC2_ENET_SHIFT 0
screamer 0:c5e2f793b59a 11848 #define SIM_SCGC2_DAC0_MASK 0x1000u
screamer 0:c5e2f793b59a 11849 #define SIM_SCGC2_DAC0_SHIFT 12
screamer 0:c5e2f793b59a 11850 #define SIM_SCGC2_DAC1_MASK 0x2000u
screamer 0:c5e2f793b59a 11851 #define SIM_SCGC2_DAC1_SHIFT 13
screamer 0:c5e2f793b59a 11852 /* SCGC3 Bit Fields */
screamer 0:c5e2f793b59a 11853 #define SIM_SCGC3_RNGA_MASK 0x1u
screamer 0:c5e2f793b59a 11854 #define SIM_SCGC3_RNGA_SHIFT 0
screamer 0:c5e2f793b59a 11855 #define SIM_SCGC3_SPI2_MASK 0x1000u
screamer 0:c5e2f793b59a 11856 #define SIM_SCGC3_SPI2_SHIFT 12
screamer 0:c5e2f793b59a 11857 #define SIM_SCGC3_SDHC_MASK 0x20000u
screamer 0:c5e2f793b59a 11858 #define SIM_SCGC3_SDHC_SHIFT 17
screamer 0:c5e2f793b59a 11859 #define SIM_SCGC3_FTM2_MASK 0x1000000u
screamer 0:c5e2f793b59a 11860 #define SIM_SCGC3_FTM2_SHIFT 24
screamer 0:c5e2f793b59a 11861 #define SIM_SCGC3_FTM3_MASK 0x2000000u
screamer 0:c5e2f793b59a 11862 #define SIM_SCGC3_FTM3_SHIFT 25
screamer 0:c5e2f793b59a 11863 #define SIM_SCGC3_ADC1_MASK 0x8000000u
screamer 0:c5e2f793b59a 11864 #define SIM_SCGC3_ADC1_SHIFT 27
screamer 0:c5e2f793b59a 11865 /* SCGC4 Bit Fields */
screamer 0:c5e2f793b59a 11866 #define SIM_SCGC4_EWM_MASK 0x2u
screamer 0:c5e2f793b59a 11867 #define SIM_SCGC4_EWM_SHIFT 1
screamer 0:c5e2f793b59a 11868 #define SIM_SCGC4_CMT_MASK 0x4u
screamer 0:c5e2f793b59a 11869 #define SIM_SCGC4_CMT_SHIFT 2
screamer 0:c5e2f793b59a 11870 #define SIM_SCGC4_I2C0_MASK 0x40u
screamer 0:c5e2f793b59a 11871 #define SIM_SCGC4_I2C0_SHIFT 6
screamer 0:c5e2f793b59a 11872 #define SIM_SCGC4_I2C1_MASK 0x80u
screamer 0:c5e2f793b59a 11873 #define SIM_SCGC4_I2C1_SHIFT 7
screamer 0:c5e2f793b59a 11874 #define SIM_SCGC4_UART0_MASK 0x400u
screamer 0:c5e2f793b59a 11875 #define SIM_SCGC4_UART0_SHIFT 10
screamer 0:c5e2f793b59a 11876 #define SIM_SCGC4_UART1_MASK 0x800u
screamer 0:c5e2f793b59a 11877 #define SIM_SCGC4_UART1_SHIFT 11
screamer 0:c5e2f793b59a 11878 #define SIM_SCGC4_UART2_MASK 0x1000u
screamer 0:c5e2f793b59a 11879 #define SIM_SCGC4_UART2_SHIFT 12
screamer 0:c5e2f793b59a 11880 #define SIM_SCGC4_UART3_MASK 0x2000u
screamer 0:c5e2f793b59a 11881 #define SIM_SCGC4_UART3_SHIFT 13
screamer 0:c5e2f793b59a 11882 #define SIM_SCGC4_USBOTG_MASK 0x40000u
screamer 0:c5e2f793b59a 11883 #define SIM_SCGC4_USBOTG_SHIFT 18
screamer 0:c5e2f793b59a 11884 #define SIM_SCGC4_CMP_MASK 0x80000u
screamer 0:c5e2f793b59a 11885 #define SIM_SCGC4_CMP_SHIFT 19
screamer 0:c5e2f793b59a 11886 #define SIM_SCGC4_VREF_MASK 0x100000u
screamer 0:c5e2f793b59a 11887 #define SIM_SCGC4_VREF_SHIFT 20
screamer 0:c5e2f793b59a 11888 /* SCGC5 Bit Fields */
screamer 0:c5e2f793b59a 11889 #define SIM_SCGC5_LPTMR_MASK 0x1u
screamer 0:c5e2f793b59a 11890 #define SIM_SCGC5_LPTMR_SHIFT 0
screamer 0:c5e2f793b59a 11891 #define SIM_SCGC5_PORTA_MASK 0x200u
screamer 0:c5e2f793b59a 11892 #define SIM_SCGC5_PORTA_SHIFT 9
screamer 0:c5e2f793b59a 11893 #define SIM_SCGC5_PORTB_MASK 0x400u
screamer 0:c5e2f793b59a 11894 #define SIM_SCGC5_PORTB_SHIFT 10
screamer 0:c5e2f793b59a 11895 #define SIM_SCGC5_PORTC_MASK 0x800u
screamer 0:c5e2f793b59a 11896 #define SIM_SCGC5_PORTC_SHIFT 11
screamer 0:c5e2f793b59a 11897 #define SIM_SCGC5_PORTD_MASK 0x1000u
screamer 0:c5e2f793b59a 11898 #define SIM_SCGC5_PORTD_SHIFT 12
screamer 0:c5e2f793b59a 11899 #define SIM_SCGC5_PORTE_MASK 0x2000u
screamer 0:c5e2f793b59a 11900 #define SIM_SCGC5_PORTE_SHIFT 13
screamer 0:c5e2f793b59a 11901 /* SCGC6 Bit Fields */
screamer 0:c5e2f793b59a 11902 #define SIM_SCGC6_FTF_MASK 0x1u
screamer 0:c5e2f793b59a 11903 #define SIM_SCGC6_FTF_SHIFT 0
screamer 0:c5e2f793b59a 11904 #define SIM_SCGC6_DMAMUX_MASK 0x2u
screamer 0:c5e2f793b59a 11905 #define SIM_SCGC6_DMAMUX_SHIFT 1
screamer 0:c5e2f793b59a 11906 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
screamer 0:c5e2f793b59a 11907 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
screamer 0:c5e2f793b59a 11908 #define SIM_SCGC6_RNGA_MASK 0x200u
screamer 0:c5e2f793b59a 11909 #define SIM_SCGC6_RNGA_SHIFT 9
screamer 0:c5e2f793b59a 11910 #define SIM_SCGC6_SPI0_MASK 0x1000u
screamer 0:c5e2f793b59a 11911 #define SIM_SCGC6_SPI0_SHIFT 12
screamer 0:c5e2f793b59a 11912 #define SIM_SCGC6_SPI1_MASK 0x2000u
screamer 0:c5e2f793b59a 11913 #define SIM_SCGC6_SPI1_SHIFT 13
screamer 0:c5e2f793b59a 11914 #define SIM_SCGC6_I2S_MASK 0x8000u
screamer 0:c5e2f793b59a 11915 #define SIM_SCGC6_I2S_SHIFT 15
screamer 0:c5e2f793b59a 11916 #define SIM_SCGC6_CRC_MASK 0x40000u
screamer 0:c5e2f793b59a 11917 #define SIM_SCGC6_CRC_SHIFT 18
screamer 0:c5e2f793b59a 11918 #define SIM_SCGC6_USBDCD_MASK 0x200000u
screamer 0:c5e2f793b59a 11919 #define SIM_SCGC6_USBDCD_SHIFT 21
screamer 0:c5e2f793b59a 11920 #define SIM_SCGC6_PDB_MASK 0x400000u
screamer 0:c5e2f793b59a 11921 #define SIM_SCGC6_PDB_SHIFT 22
screamer 0:c5e2f793b59a 11922 #define SIM_SCGC6_PIT_MASK 0x800000u
screamer 0:c5e2f793b59a 11923 #define SIM_SCGC6_PIT_SHIFT 23
screamer 0:c5e2f793b59a 11924 #define SIM_SCGC6_FTM0_MASK 0x1000000u
screamer 0:c5e2f793b59a 11925 #define SIM_SCGC6_FTM0_SHIFT 24
screamer 0:c5e2f793b59a 11926 #define SIM_SCGC6_FTM1_MASK 0x2000000u
screamer 0:c5e2f793b59a 11927 #define SIM_SCGC6_FTM1_SHIFT 25
screamer 0:c5e2f793b59a 11928 #define SIM_SCGC6_FTM2_MASK 0x4000000u
screamer 0:c5e2f793b59a 11929 #define SIM_SCGC6_FTM2_SHIFT 26
screamer 0:c5e2f793b59a 11930 #define SIM_SCGC6_ADC0_MASK 0x8000000u
screamer 0:c5e2f793b59a 11931 #define SIM_SCGC6_ADC0_SHIFT 27
screamer 0:c5e2f793b59a 11932 #define SIM_SCGC6_RTC_MASK 0x20000000u
screamer 0:c5e2f793b59a 11933 #define SIM_SCGC6_RTC_SHIFT 29
screamer 0:c5e2f793b59a 11934 #define SIM_SCGC6_DAC0_MASK 0x80000000u
screamer 0:c5e2f793b59a 11935 #define SIM_SCGC6_DAC0_SHIFT 31
screamer 0:c5e2f793b59a 11936 /* SCGC7 Bit Fields */
screamer 0:c5e2f793b59a 11937 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
screamer 0:c5e2f793b59a 11938 #define SIM_SCGC7_FLEXBUS_SHIFT 0
screamer 0:c5e2f793b59a 11939 #define SIM_SCGC7_DMA_MASK 0x2u
screamer 0:c5e2f793b59a 11940 #define SIM_SCGC7_DMA_SHIFT 1
screamer 0:c5e2f793b59a 11941 #define SIM_SCGC7_MPU_MASK 0x4u
screamer 0:c5e2f793b59a 11942 #define SIM_SCGC7_MPU_SHIFT 2
screamer 0:c5e2f793b59a 11943 /* CLKDIV1 Bit Fields */
screamer 0:c5e2f793b59a 11944 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
screamer 0:c5e2f793b59a 11945 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
screamer 0:c5e2f793b59a 11946 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
screamer 0:c5e2f793b59a 11947 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
screamer 0:c5e2f793b59a 11948 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
screamer 0:c5e2f793b59a 11949 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
screamer 0:c5e2f793b59a 11950 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
screamer 0:c5e2f793b59a 11951 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
screamer 0:c5e2f793b59a 11952 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
screamer 0:c5e2f793b59a 11953 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
screamer 0:c5e2f793b59a 11954 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
screamer 0:c5e2f793b59a 11955 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
screamer 0:c5e2f793b59a 11956 /* CLKDIV2 Bit Fields */
screamer 0:c5e2f793b59a 11957 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
screamer 0:c5e2f793b59a 11958 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
screamer 0:c5e2f793b59a 11959 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
screamer 0:c5e2f793b59a 11960 #define SIM_CLKDIV2_USBDIV_SHIFT 1
screamer 0:c5e2f793b59a 11961 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
screamer 0:c5e2f793b59a 11962 /* FCFG1 Bit Fields */
screamer 0:c5e2f793b59a 11963 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
screamer 0:c5e2f793b59a 11964 #define SIM_FCFG1_FLASHDIS_SHIFT 0
screamer 0:c5e2f793b59a 11965 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
screamer 0:c5e2f793b59a 11966 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
screamer 0:c5e2f793b59a 11967 #define SIM_FCFG1_DEPART_MASK 0xF00u
screamer 0:c5e2f793b59a 11968 #define SIM_FCFG1_DEPART_SHIFT 8
screamer 0:c5e2f793b59a 11969 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
screamer 0:c5e2f793b59a 11970 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
screamer 0:c5e2f793b59a 11971 #define SIM_FCFG1_EESIZE_SHIFT 16
screamer 0:c5e2f793b59a 11972 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
screamer 0:c5e2f793b59a 11973 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
screamer 0:c5e2f793b59a 11974 #define SIM_FCFG1_PFSIZE_SHIFT 24
screamer 0:c5e2f793b59a 11975 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
screamer 0:c5e2f793b59a 11976 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
screamer 0:c5e2f793b59a 11977 #define SIM_FCFG1_NVMSIZE_SHIFT 28
screamer 0:c5e2f793b59a 11978 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
screamer 0:c5e2f793b59a 11979 /* FCFG2 Bit Fields */
screamer 0:c5e2f793b59a 11980 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
screamer 0:c5e2f793b59a 11981 #define SIM_FCFG2_MAXADDR1_SHIFT 16
screamer 0:c5e2f793b59a 11982 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
screamer 0:c5e2f793b59a 11983 #define SIM_FCFG2_PFLSH_MASK 0x800000u
screamer 0:c5e2f793b59a 11984 #define SIM_FCFG2_PFLSH_SHIFT 23
screamer 0:c5e2f793b59a 11985 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
screamer 0:c5e2f793b59a 11986 #define SIM_FCFG2_MAXADDR0_SHIFT 24
screamer 0:c5e2f793b59a 11987 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
screamer 0:c5e2f793b59a 11988 /* UIDH Bit Fields */
screamer 0:c5e2f793b59a 11989 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11990 #define SIM_UIDH_UID_SHIFT 0
screamer 0:c5e2f793b59a 11991 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
screamer 0:c5e2f793b59a 11992 /* UIDMH Bit Fields */
screamer 0:c5e2f793b59a 11993 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11994 #define SIM_UIDMH_UID_SHIFT 0
screamer 0:c5e2f793b59a 11995 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
screamer 0:c5e2f793b59a 11996 /* UIDML Bit Fields */
screamer 0:c5e2f793b59a 11997 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 11998 #define SIM_UIDML_UID_SHIFT 0
screamer 0:c5e2f793b59a 11999 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
screamer 0:c5e2f793b59a 12000 /* UIDL Bit Fields */
screamer 0:c5e2f793b59a 12001 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 12002 #define SIM_UIDL_UID_SHIFT 0
screamer 0:c5e2f793b59a 12003 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
screamer 0:c5e2f793b59a 12004
screamer 0:c5e2f793b59a 12005 /*!
screamer 0:c5e2f793b59a 12006 * @}
screamer 0:c5e2f793b59a 12007 */ /* end of group SIM_Register_Masks */
screamer 0:c5e2f793b59a 12008
screamer 0:c5e2f793b59a 12009
screamer 0:c5e2f793b59a 12010 /* SIM - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 12011 /** Peripheral SIM base address */
screamer 0:c5e2f793b59a 12012 #define SIM_BASE (0x40047000u)
screamer 0:c5e2f793b59a 12013 /** Peripheral SIM base pointer */
screamer 0:c5e2f793b59a 12014 #define SIM ((SIM_Type *)SIM_BASE)
screamer 0:c5e2f793b59a 12015 #define SIM_BASE_PTR (SIM)
screamer 0:c5e2f793b59a 12016 /** Array initializer of SIM peripheral base addresses */
screamer 0:c5e2f793b59a 12017 #define SIM_BASE_ADDRS { SIM_BASE }
screamer 0:c5e2f793b59a 12018 /** Array initializer of SIM peripheral base pointers */
screamer 0:c5e2f793b59a 12019 #define SIM_BASE_PTRS { SIM }
screamer 0:c5e2f793b59a 12020
screamer 0:c5e2f793b59a 12021 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12022 -- SIM - Register accessor macros
screamer 0:c5e2f793b59a 12023 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12024
screamer 0:c5e2f793b59a 12025 /*!
screamer 0:c5e2f793b59a 12026 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
screamer 0:c5e2f793b59a 12027 * @{
screamer 0:c5e2f793b59a 12028 */
screamer 0:c5e2f793b59a 12029
screamer 0:c5e2f793b59a 12030
screamer 0:c5e2f793b59a 12031 /* SIM - Register instance definitions */
screamer 0:c5e2f793b59a 12032 /* SIM */
screamer 0:c5e2f793b59a 12033 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
screamer 0:c5e2f793b59a 12034 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
screamer 0:c5e2f793b59a 12035 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
screamer 0:c5e2f793b59a 12036 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
screamer 0:c5e2f793b59a 12037 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
screamer 0:c5e2f793b59a 12038 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
screamer 0:c5e2f793b59a 12039 #define SIM_SDID SIM_SDID_REG(SIM)
screamer 0:c5e2f793b59a 12040 #define SIM_SCGC1 SIM_SCGC1_REG(SIM)
screamer 0:c5e2f793b59a 12041 #define SIM_SCGC2 SIM_SCGC2_REG(SIM)
screamer 0:c5e2f793b59a 12042 #define SIM_SCGC3 SIM_SCGC3_REG(SIM)
screamer 0:c5e2f793b59a 12043 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
screamer 0:c5e2f793b59a 12044 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
screamer 0:c5e2f793b59a 12045 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
screamer 0:c5e2f793b59a 12046 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
screamer 0:c5e2f793b59a 12047 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
screamer 0:c5e2f793b59a 12048 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
screamer 0:c5e2f793b59a 12049 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
screamer 0:c5e2f793b59a 12050 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
screamer 0:c5e2f793b59a 12051 #define SIM_UIDH SIM_UIDH_REG(SIM)
screamer 0:c5e2f793b59a 12052 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
screamer 0:c5e2f793b59a 12053 #define SIM_UIDML SIM_UIDML_REG(SIM)
screamer 0:c5e2f793b59a 12054 #define SIM_UIDL SIM_UIDL_REG(SIM)
screamer 0:c5e2f793b59a 12055
screamer 0:c5e2f793b59a 12056 /*!
screamer 0:c5e2f793b59a 12057 * @}
screamer 0:c5e2f793b59a 12058 */ /* end of group SIM_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 12059
screamer 0:c5e2f793b59a 12060
screamer 0:c5e2f793b59a 12061 /*!
screamer 0:c5e2f793b59a 12062 * @}
screamer 0:c5e2f793b59a 12063 */ /* end of group SIM_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 12064
screamer 0:c5e2f793b59a 12065
screamer 0:c5e2f793b59a 12066 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12067 -- SMC Peripheral Access Layer
screamer 0:c5e2f793b59a 12068 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12069
screamer 0:c5e2f793b59a 12070 /*!
screamer 0:c5e2f793b59a 12071 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
screamer 0:c5e2f793b59a 12072 * @{
screamer 0:c5e2f793b59a 12073 */
screamer 0:c5e2f793b59a 12074
screamer 0:c5e2f793b59a 12075 /** SMC - Register Layout Typedef */
screamer 0:c5e2f793b59a 12076 typedef struct {
screamer 0:c5e2f793b59a 12077 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
screamer 0:c5e2f793b59a 12078 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
screamer 0:c5e2f793b59a 12079 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
screamer 0:c5e2f793b59a 12080 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
screamer 0:c5e2f793b59a 12081 } SMC_Type, *SMC_MemMapPtr;
screamer 0:c5e2f793b59a 12082
screamer 0:c5e2f793b59a 12083 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12084 -- SMC - Register accessor macros
screamer 0:c5e2f793b59a 12085 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12086
screamer 0:c5e2f793b59a 12087 /*!
screamer 0:c5e2f793b59a 12088 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
screamer 0:c5e2f793b59a 12089 * @{
screamer 0:c5e2f793b59a 12090 */
screamer 0:c5e2f793b59a 12091
screamer 0:c5e2f793b59a 12092
screamer 0:c5e2f793b59a 12093 /* SMC - Register accessors */
screamer 0:c5e2f793b59a 12094 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
screamer 0:c5e2f793b59a 12095 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
screamer 0:c5e2f793b59a 12096 #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
screamer 0:c5e2f793b59a 12097 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
screamer 0:c5e2f793b59a 12098
screamer 0:c5e2f793b59a 12099 /*!
screamer 0:c5e2f793b59a 12100 * @}
screamer 0:c5e2f793b59a 12101 */ /* end of group SMC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 12102
screamer 0:c5e2f793b59a 12103
screamer 0:c5e2f793b59a 12104 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12105 -- SMC Register Masks
screamer 0:c5e2f793b59a 12106 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12107
screamer 0:c5e2f793b59a 12108 /*!
screamer 0:c5e2f793b59a 12109 * @addtogroup SMC_Register_Masks SMC Register Masks
screamer 0:c5e2f793b59a 12110 * @{
screamer 0:c5e2f793b59a 12111 */
screamer 0:c5e2f793b59a 12112
screamer 0:c5e2f793b59a 12113 /* PMPROT Bit Fields */
screamer 0:c5e2f793b59a 12114 #define SMC_PMPROT_AVLLS_MASK 0x2u
screamer 0:c5e2f793b59a 12115 #define SMC_PMPROT_AVLLS_SHIFT 1
screamer 0:c5e2f793b59a 12116 #define SMC_PMPROT_ALLS_MASK 0x8u
screamer 0:c5e2f793b59a 12117 #define SMC_PMPROT_ALLS_SHIFT 3
screamer 0:c5e2f793b59a 12118 #define SMC_PMPROT_AVLP_MASK 0x20u
screamer 0:c5e2f793b59a 12119 #define SMC_PMPROT_AVLP_SHIFT 5
screamer 0:c5e2f793b59a 12120 /* PMCTRL Bit Fields */
screamer 0:c5e2f793b59a 12121 #define SMC_PMCTRL_STOPM_MASK 0x7u
screamer 0:c5e2f793b59a 12122 #define SMC_PMCTRL_STOPM_SHIFT 0
screamer 0:c5e2f793b59a 12123 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
screamer 0:c5e2f793b59a 12124 #define SMC_PMCTRL_STOPA_MASK 0x8u
screamer 0:c5e2f793b59a 12125 #define SMC_PMCTRL_STOPA_SHIFT 3
screamer 0:c5e2f793b59a 12126 #define SMC_PMCTRL_RUNM_MASK 0x60u
screamer 0:c5e2f793b59a 12127 #define SMC_PMCTRL_RUNM_SHIFT 5
screamer 0:c5e2f793b59a 12128 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
screamer 0:c5e2f793b59a 12129 #define SMC_PMCTRL_LPWUI_MASK 0x80u
screamer 0:c5e2f793b59a 12130 #define SMC_PMCTRL_LPWUI_SHIFT 7
screamer 0:c5e2f793b59a 12131 /* VLLSCTRL Bit Fields */
screamer 0:c5e2f793b59a 12132 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
screamer 0:c5e2f793b59a 12133 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
screamer 0:c5e2f793b59a 12134 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
screamer 0:c5e2f793b59a 12135 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
screamer 0:c5e2f793b59a 12136 #define SMC_VLLSCTRL_PORPO_SHIFT 5
screamer 0:c5e2f793b59a 12137 /* PMSTAT Bit Fields */
screamer 0:c5e2f793b59a 12138 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
screamer 0:c5e2f793b59a 12139 #define SMC_PMSTAT_PMSTAT_SHIFT 0
screamer 0:c5e2f793b59a 12140 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
screamer 0:c5e2f793b59a 12141
screamer 0:c5e2f793b59a 12142 /*!
screamer 0:c5e2f793b59a 12143 * @}
screamer 0:c5e2f793b59a 12144 */ /* end of group SMC_Register_Masks */
screamer 0:c5e2f793b59a 12145
screamer 0:c5e2f793b59a 12146
screamer 0:c5e2f793b59a 12147 /* SMC - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 12148 /** Peripheral SMC base address */
screamer 0:c5e2f793b59a 12149 #define SMC_BASE (0x4007E000u)
screamer 0:c5e2f793b59a 12150 /** Peripheral SMC base pointer */
screamer 0:c5e2f793b59a 12151 #define SMC ((SMC_Type *)SMC_BASE)
screamer 0:c5e2f793b59a 12152 #define SMC_BASE_PTR (SMC)
screamer 0:c5e2f793b59a 12153 /** Array initializer of SMC peripheral base addresses */
screamer 0:c5e2f793b59a 12154 #define SMC_BASE_ADDRS { SMC_BASE }
screamer 0:c5e2f793b59a 12155 /** Array initializer of SMC peripheral base pointers */
screamer 0:c5e2f793b59a 12156 #define SMC_BASE_PTRS { SMC }
screamer 0:c5e2f793b59a 12157
screamer 0:c5e2f793b59a 12158 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12159 -- SMC - Register accessor macros
screamer 0:c5e2f793b59a 12160 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12161
screamer 0:c5e2f793b59a 12162 /*!
screamer 0:c5e2f793b59a 12163 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
screamer 0:c5e2f793b59a 12164 * @{
screamer 0:c5e2f793b59a 12165 */
screamer 0:c5e2f793b59a 12166
screamer 0:c5e2f793b59a 12167
screamer 0:c5e2f793b59a 12168 /* SMC - Register instance definitions */
screamer 0:c5e2f793b59a 12169 /* SMC */
screamer 0:c5e2f793b59a 12170 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
screamer 0:c5e2f793b59a 12171 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
screamer 0:c5e2f793b59a 12172 #define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
screamer 0:c5e2f793b59a 12173 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
screamer 0:c5e2f793b59a 12174
screamer 0:c5e2f793b59a 12175 /*!
screamer 0:c5e2f793b59a 12176 * @}
screamer 0:c5e2f793b59a 12177 */ /* end of group SMC_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 12178
screamer 0:c5e2f793b59a 12179
screamer 0:c5e2f793b59a 12180 /*!
screamer 0:c5e2f793b59a 12181 * @}
screamer 0:c5e2f793b59a 12182 */ /* end of group SMC_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 12183
screamer 0:c5e2f793b59a 12184
screamer 0:c5e2f793b59a 12185 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12186 -- SPI Peripheral Access Layer
screamer 0:c5e2f793b59a 12187 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12188
screamer 0:c5e2f793b59a 12189 /*!
screamer 0:c5e2f793b59a 12190 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
screamer 0:c5e2f793b59a 12191 * @{
screamer 0:c5e2f793b59a 12192 */
screamer 0:c5e2f793b59a 12193
screamer 0:c5e2f793b59a 12194 /** SPI - Register Layout Typedef */
screamer 0:c5e2f793b59a 12195 typedef struct {
screamer 0:c5e2f793b59a 12196 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
screamer 0:c5e2f793b59a 12197 uint8_t RESERVED_0[4];
screamer 0:c5e2f793b59a 12198 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
screamer 0:c5e2f793b59a 12199 union { /* offset: 0xC */
screamer 0:c5e2f793b59a 12200 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
screamer 0:c5e2f793b59a 12201 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
screamer 0:c5e2f793b59a 12202 };
screamer 0:c5e2f793b59a 12203 uint8_t RESERVED_1[24];
screamer 0:c5e2f793b59a 12204 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
screamer 0:c5e2f793b59a 12205 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
screamer 0:c5e2f793b59a 12206 union { /* offset: 0x34 */
screamer 0:c5e2f793b59a 12207 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
screamer 0:c5e2f793b59a 12208 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
screamer 0:c5e2f793b59a 12209 };
screamer 0:c5e2f793b59a 12210 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
screamer 0:c5e2f793b59a 12211 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
screamer 0:c5e2f793b59a 12212 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
screamer 0:c5e2f793b59a 12213 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
screamer 0:c5e2f793b59a 12214 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
screamer 0:c5e2f793b59a 12215 uint8_t RESERVED_2[48];
screamer 0:c5e2f793b59a 12216 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
screamer 0:c5e2f793b59a 12217 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
screamer 0:c5e2f793b59a 12218 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
screamer 0:c5e2f793b59a 12219 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
screamer 0:c5e2f793b59a 12220 } SPI_Type, *SPI_MemMapPtr;
screamer 0:c5e2f793b59a 12221
screamer 0:c5e2f793b59a 12222 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12223 -- SPI - Register accessor macros
screamer 0:c5e2f793b59a 12224 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12225
screamer 0:c5e2f793b59a 12226 /*!
screamer 0:c5e2f793b59a 12227 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
screamer 0:c5e2f793b59a 12228 * @{
screamer 0:c5e2f793b59a 12229 */
screamer 0:c5e2f793b59a 12230
screamer 0:c5e2f793b59a 12231
screamer 0:c5e2f793b59a 12232 /* SPI - Register accessors */
screamer 0:c5e2f793b59a 12233 #define SPI_MCR_REG(base) ((base)->MCR)
screamer 0:c5e2f793b59a 12234 #define SPI_TCR_REG(base) ((base)->TCR)
screamer 0:c5e2f793b59a 12235 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
screamer 0:c5e2f793b59a 12236 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
screamer 0:c5e2f793b59a 12237 #define SPI_SR_REG(base) ((base)->SR)
screamer 0:c5e2f793b59a 12238 #define SPI_RSER_REG(base) ((base)->RSER)
screamer 0:c5e2f793b59a 12239 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
screamer 0:c5e2f793b59a 12240 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
screamer 0:c5e2f793b59a 12241 #define SPI_POPR_REG(base) ((base)->POPR)
screamer 0:c5e2f793b59a 12242 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
screamer 0:c5e2f793b59a 12243 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
screamer 0:c5e2f793b59a 12244 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
screamer 0:c5e2f793b59a 12245 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
screamer 0:c5e2f793b59a 12246 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
screamer 0:c5e2f793b59a 12247 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
screamer 0:c5e2f793b59a 12248 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
screamer 0:c5e2f793b59a 12249 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
screamer 0:c5e2f793b59a 12250
screamer 0:c5e2f793b59a 12251 /*!
screamer 0:c5e2f793b59a 12252 * @}
screamer 0:c5e2f793b59a 12253 */ /* end of group SPI_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 12254
screamer 0:c5e2f793b59a 12255
screamer 0:c5e2f793b59a 12256 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12257 -- SPI Register Masks
screamer 0:c5e2f793b59a 12258 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12259
screamer 0:c5e2f793b59a 12260 /*!
screamer 0:c5e2f793b59a 12261 * @addtogroup SPI_Register_Masks SPI Register Masks
screamer 0:c5e2f793b59a 12262 * @{
screamer 0:c5e2f793b59a 12263 */
screamer 0:c5e2f793b59a 12264
screamer 0:c5e2f793b59a 12265 /* MCR Bit Fields */
screamer 0:c5e2f793b59a 12266 #define SPI_MCR_HALT_MASK 0x1u
screamer 0:c5e2f793b59a 12267 #define SPI_MCR_HALT_SHIFT 0
screamer 0:c5e2f793b59a 12268 #define SPI_MCR_SMPL_PT_MASK 0x300u
screamer 0:c5e2f793b59a 12269 #define SPI_MCR_SMPL_PT_SHIFT 8
screamer 0:c5e2f793b59a 12270 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
screamer 0:c5e2f793b59a 12271 #define SPI_MCR_CLR_RXF_MASK 0x400u
screamer 0:c5e2f793b59a 12272 #define SPI_MCR_CLR_RXF_SHIFT 10
screamer 0:c5e2f793b59a 12273 #define SPI_MCR_CLR_TXF_MASK 0x800u
screamer 0:c5e2f793b59a 12274 #define SPI_MCR_CLR_TXF_SHIFT 11
screamer 0:c5e2f793b59a 12275 #define SPI_MCR_DIS_RXF_MASK 0x1000u
screamer 0:c5e2f793b59a 12276 #define SPI_MCR_DIS_RXF_SHIFT 12
screamer 0:c5e2f793b59a 12277 #define SPI_MCR_DIS_TXF_MASK 0x2000u
screamer 0:c5e2f793b59a 12278 #define SPI_MCR_DIS_TXF_SHIFT 13
screamer 0:c5e2f793b59a 12279 #define SPI_MCR_MDIS_MASK 0x4000u
screamer 0:c5e2f793b59a 12280 #define SPI_MCR_MDIS_SHIFT 14
screamer 0:c5e2f793b59a 12281 #define SPI_MCR_DOZE_MASK 0x8000u
screamer 0:c5e2f793b59a 12282 #define SPI_MCR_DOZE_SHIFT 15
screamer 0:c5e2f793b59a 12283 #define SPI_MCR_PCSIS_MASK 0x3F0000u
screamer 0:c5e2f793b59a 12284 #define SPI_MCR_PCSIS_SHIFT 16
screamer 0:c5e2f793b59a 12285 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
screamer 0:c5e2f793b59a 12286 #define SPI_MCR_ROOE_MASK 0x1000000u
screamer 0:c5e2f793b59a 12287 #define SPI_MCR_ROOE_SHIFT 24
screamer 0:c5e2f793b59a 12288 #define SPI_MCR_PCSSE_MASK 0x2000000u
screamer 0:c5e2f793b59a 12289 #define SPI_MCR_PCSSE_SHIFT 25
screamer 0:c5e2f793b59a 12290 #define SPI_MCR_MTFE_MASK 0x4000000u
screamer 0:c5e2f793b59a 12291 #define SPI_MCR_MTFE_SHIFT 26
screamer 0:c5e2f793b59a 12292 #define SPI_MCR_FRZ_MASK 0x8000000u
screamer 0:c5e2f793b59a 12293 #define SPI_MCR_FRZ_SHIFT 27
screamer 0:c5e2f793b59a 12294 #define SPI_MCR_DCONF_MASK 0x30000000u
screamer 0:c5e2f793b59a 12295 #define SPI_MCR_DCONF_SHIFT 28
screamer 0:c5e2f793b59a 12296 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
screamer 0:c5e2f793b59a 12297 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
screamer 0:c5e2f793b59a 12298 #define SPI_MCR_CONT_SCKE_SHIFT 30
screamer 0:c5e2f793b59a 12299 #define SPI_MCR_MSTR_MASK 0x80000000u
screamer 0:c5e2f793b59a 12300 #define SPI_MCR_MSTR_SHIFT 31
screamer 0:c5e2f793b59a 12301 /* TCR Bit Fields */
screamer 0:c5e2f793b59a 12302 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 12303 #define SPI_TCR_SPI_TCNT_SHIFT 16
screamer 0:c5e2f793b59a 12304 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
screamer 0:c5e2f793b59a 12305 /* CTAR Bit Fields */
screamer 0:c5e2f793b59a 12306 #define SPI_CTAR_BR_MASK 0xFu
screamer 0:c5e2f793b59a 12307 #define SPI_CTAR_BR_SHIFT 0
screamer 0:c5e2f793b59a 12308 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
screamer 0:c5e2f793b59a 12309 #define SPI_CTAR_DT_MASK 0xF0u
screamer 0:c5e2f793b59a 12310 #define SPI_CTAR_DT_SHIFT 4
screamer 0:c5e2f793b59a 12311 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
screamer 0:c5e2f793b59a 12312 #define SPI_CTAR_ASC_MASK 0xF00u
screamer 0:c5e2f793b59a 12313 #define SPI_CTAR_ASC_SHIFT 8
screamer 0:c5e2f793b59a 12314 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
screamer 0:c5e2f793b59a 12315 #define SPI_CTAR_CSSCK_MASK 0xF000u
screamer 0:c5e2f793b59a 12316 #define SPI_CTAR_CSSCK_SHIFT 12
screamer 0:c5e2f793b59a 12317 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
screamer 0:c5e2f793b59a 12318 #define SPI_CTAR_PBR_MASK 0x30000u
screamer 0:c5e2f793b59a 12319 #define SPI_CTAR_PBR_SHIFT 16
screamer 0:c5e2f793b59a 12320 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
screamer 0:c5e2f793b59a 12321 #define SPI_CTAR_PDT_MASK 0xC0000u
screamer 0:c5e2f793b59a 12322 #define SPI_CTAR_PDT_SHIFT 18
screamer 0:c5e2f793b59a 12323 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
screamer 0:c5e2f793b59a 12324 #define SPI_CTAR_PASC_MASK 0x300000u
screamer 0:c5e2f793b59a 12325 #define SPI_CTAR_PASC_SHIFT 20
screamer 0:c5e2f793b59a 12326 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
screamer 0:c5e2f793b59a 12327 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
screamer 0:c5e2f793b59a 12328 #define SPI_CTAR_PCSSCK_SHIFT 22
screamer 0:c5e2f793b59a 12329 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
screamer 0:c5e2f793b59a 12330 #define SPI_CTAR_LSBFE_MASK 0x1000000u
screamer 0:c5e2f793b59a 12331 #define SPI_CTAR_LSBFE_SHIFT 24
screamer 0:c5e2f793b59a 12332 #define SPI_CTAR_CPHA_MASK 0x2000000u
screamer 0:c5e2f793b59a 12333 #define SPI_CTAR_CPHA_SHIFT 25
screamer 0:c5e2f793b59a 12334 #define SPI_CTAR_CPOL_MASK 0x4000000u
screamer 0:c5e2f793b59a 12335 #define SPI_CTAR_CPOL_SHIFT 26
screamer 0:c5e2f793b59a 12336 #define SPI_CTAR_FMSZ_MASK 0x78000000u
screamer 0:c5e2f793b59a 12337 #define SPI_CTAR_FMSZ_SHIFT 27
screamer 0:c5e2f793b59a 12338 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
screamer 0:c5e2f793b59a 12339 #define SPI_CTAR_DBR_MASK 0x80000000u
screamer 0:c5e2f793b59a 12340 #define SPI_CTAR_DBR_SHIFT 31
screamer 0:c5e2f793b59a 12341 /* CTAR_SLAVE Bit Fields */
screamer 0:c5e2f793b59a 12342 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
screamer 0:c5e2f793b59a 12343 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
screamer 0:c5e2f793b59a 12344 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
screamer 0:c5e2f793b59a 12345 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
screamer 0:c5e2f793b59a 12346 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
screamer 0:c5e2f793b59a 12347 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
screamer 0:c5e2f793b59a 12348 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
screamer 0:c5e2f793b59a 12349 /* SR Bit Fields */
screamer 0:c5e2f793b59a 12350 #define SPI_SR_POPNXTPTR_MASK 0xFu
screamer 0:c5e2f793b59a 12351 #define SPI_SR_POPNXTPTR_SHIFT 0
screamer 0:c5e2f793b59a 12352 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
screamer 0:c5e2f793b59a 12353 #define SPI_SR_RXCTR_MASK 0xF0u
screamer 0:c5e2f793b59a 12354 #define SPI_SR_RXCTR_SHIFT 4
screamer 0:c5e2f793b59a 12355 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
screamer 0:c5e2f793b59a 12356 #define SPI_SR_TXNXTPTR_MASK 0xF00u
screamer 0:c5e2f793b59a 12357 #define SPI_SR_TXNXTPTR_SHIFT 8
screamer 0:c5e2f793b59a 12358 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
screamer 0:c5e2f793b59a 12359 #define SPI_SR_TXCTR_MASK 0xF000u
screamer 0:c5e2f793b59a 12360 #define SPI_SR_TXCTR_SHIFT 12
screamer 0:c5e2f793b59a 12361 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
screamer 0:c5e2f793b59a 12362 #define SPI_SR_RFDF_MASK 0x20000u
screamer 0:c5e2f793b59a 12363 #define SPI_SR_RFDF_SHIFT 17
screamer 0:c5e2f793b59a 12364 #define SPI_SR_RFOF_MASK 0x80000u
screamer 0:c5e2f793b59a 12365 #define SPI_SR_RFOF_SHIFT 19
screamer 0:c5e2f793b59a 12366 #define SPI_SR_TFFF_MASK 0x2000000u
screamer 0:c5e2f793b59a 12367 #define SPI_SR_TFFF_SHIFT 25
screamer 0:c5e2f793b59a 12368 #define SPI_SR_TFUF_MASK 0x8000000u
screamer 0:c5e2f793b59a 12369 #define SPI_SR_TFUF_SHIFT 27
screamer 0:c5e2f793b59a 12370 #define SPI_SR_EOQF_MASK 0x10000000u
screamer 0:c5e2f793b59a 12371 #define SPI_SR_EOQF_SHIFT 28
screamer 0:c5e2f793b59a 12372 #define SPI_SR_TXRXS_MASK 0x40000000u
screamer 0:c5e2f793b59a 12373 #define SPI_SR_TXRXS_SHIFT 30
screamer 0:c5e2f793b59a 12374 #define SPI_SR_TCF_MASK 0x80000000u
screamer 0:c5e2f793b59a 12375 #define SPI_SR_TCF_SHIFT 31
screamer 0:c5e2f793b59a 12376 /* RSER Bit Fields */
screamer 0:c5e2f793b59a 12377 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
screamer 0:c5e2f793b59a 12378 #define SPI_RSER_RFDF_DIRS_SHIFT 16
screamer 0:c5e2f793b59a 12379 #define SPI_RSER_RFDF_RE_MASK 0x20000u
screamer 0:c5e2f793b59a 12380 #define SPI_RSER_RFDF_RE_SHIFT 17
screamer 0:c5e2f793b59a 12381 #define SPI_RSER_RFOF_RE_MASK 0x80000u
screamer 0:c5e2f793b59a 12382 #define SPI_RSER_RFOF_RE_SHIFT 19
screamer 0:c5e2f793b59a 12383 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
screamer 0:c5e2f793b59a 12384 #define SPI_RSER_TFFF_DIRS_SHIFT 24
screamer 0:c5e2f793b59a 12385 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
screamer 0:c5e2f793b59a 12386 #define SPI_RSER_TFFF_RE_SHIFT 25
screamer 0:c5e2f793b59a 12387 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
screamer 0:c5e2f793b59a 12388 #define SPI_RSER_TFUF_RE_SHIFT 27
screamer 0:c5e2f793b59a 12389 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
screamer 0:c5e2f793b59a 12390 #define SPI_RSER_EOQF_RE_SHIFT 28
screamer 0:c5e2f793b59a 12391 #define SPI_RSER_TCF_RE_MASK 0x80000000u
screamer 0:c5e2f793b59a 12392 #define SPI_RSER_TCF_RE_SHIFT 31
screamer 0:c5e2f793b59a 12393 /* PUSHR Bit Fields */
screamer 0:c5e2f793b59a 12394 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
screamer 0:c5e2f793b59a 12395 #define SPI_PUSHR_TXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12396 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
screamer 0:c5e2f793b59a 12397 #define SPI_PUSHR_PCS_MASK 0x3F0000u
screamer 0:c5e2f793b59a 12398 #define SPI_PUSHR_PCS_SHIFT 16
screamer 0:c5e2f793b59a 12399 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
screamer 0:c5e2f793b59a 12400 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
screamer 0:c5e2f793b59a 12401 #define SPI_PUSHR_CTCNT_SHIFT 26
screamer 0:c5e2f793b59a 12402 #define SPI_PUSHR_EOQ_MASK 0x8000000u
screamer 0:c5e2f793b59a 12403 #define SPI_PUSHR_EOQ_SHIFT 27
screamer 0:c5e2f793b59a 12404 #define SPI_PUSHR_CTAS_MASK 0x70000000u
screamer 0:c5e2f793b59a 12405 #define SPI_PUSHR_CTAS_SHIFT 28
screamer 0:c5e2f793b59a 12406 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
screamer 0:c5e2f793b59a 12407 #define SPI_PUSHR_CONT_MASK 0x80000000u
screamer 0:c5e2f793b59a 12408 #define SPI_PUSHR_CONT_SHIFT 31
screamer 0:c5e2f793b59a 12409 /* PUSHR_SLAVE Bit Fields */
screamer 0:c5e2f793b59a 12410 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 12411 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12412 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
screamer 0:c5e2f793b59a 12413 /* POPR Bit Fields */
screamer 0:c5e2f793b59a 12414 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 12415 #define SPI_POPR_RXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12416 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
screamer 0:c5e2f793b59a 12417 /* TXFR0 Bit Fields */
screamer 0:c5e2f793b59a 12418 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
screamer 0:c5e2f793b59a 12419 #define SPI_TXFR0_TXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12420 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
screamer 0:c5e2f793b59a 12421 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 12422 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
screamer 0:c5e2f793b59a 12423 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
screamer 0:c5e2f793b59a 12424 /* TXFR1 Bit Fields */
screamer 0:c5e2f793b59a 12425 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
screamer 0:c5e2f793b59a 12426 #define SPI_TXFR1_TXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12427 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
screamer 0:c5e2f793b59a 12428 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 12429 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
screamer 0:c5e2f793b59a 12430 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
screamer 0:c5e2f793b59a 12431 /* TXFR2 Bit Fields */
screamer 0:c5e2f793b59a 12432 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
screamer 0:c5e2f793b59a 12433 #define SPI_TXFR2_TXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12434 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
screamer 0:c5e2f793b59a 12435 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 12436 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
screamer 0:c5e2f793b59a 12437 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
screamer 0:c5e2f793b59a 12438 /* TXFR3 Bit Fields */
screamer 0:c5e2f793b59a 12439 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
screamer 0:c5e2f793b59a 12440 #define SPI_TXFR3_TXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12441 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
screamer 0:c5e2f793b59a 12442 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
screamer 0:c5e2f793b59a 12443 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
screamer 0:c5e2f793b59a 12444 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
screamer 0:c5e2f793b59a 12445 /* RXFR0 Bit Fields */
screamer 0:c5e2f793b59a 12446 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 12447 #define SPI_RXFR0_RXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12448 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
screamer 0:c5e2f793b59a 12449 /* RXFR1 Bit Fields */
screamer 0:c5e2f793b59a 12450 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 12451 #define SPI_RXFR1_RXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12452 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
screamer 0:c5e2f793b59a 12453 /* RXFR2 Bit Fields */
screamer 0:c5e2f793b59a 12454 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 12455 #define SPI_RXFR2_RXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12456 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
screamer 0:c5e2f793b59a 12457 /* RXFR3 Bit Fields */
screamer 0:c5e2f793b59a 12458 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
screamer 0:c5e2f793b59a 12459 #define SPI_RXFR3_RXDATA_SHIFT 0
screamer 0:c5e2f793b59a 12460 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
screamer 0:c5e2f793b59a 12461
screamer 0:c5e2f793b59a 12462 /*!
screamer 0:c5e2f793b59a 12463 * @}
screamer 0:c5e2f793b59a 12464 */ /* end of group SPI_Register_Masks */
screamer 0:c5e2f793b59a 12465
screamer 0:c5e2f793b59a 12466
screamer 0:c5e2f793b59a 12467 /* SPI - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 12468 /** Peripheral SPI0 base address */
screamer 0:c5e2f793b59a 12469 #define SPI0_BASE (0x4002C000u)
screamer 0:c5e2f793b59a 12470 /** Peripheral SPI0 base pointer */
screamer 0:c5e2f793b59a 12471 #define SPI0 ((SPI_Type *)SPI0_BASE)
screamer 0:c5e2f793b59a 12472 #define SPI0_BASE_PTR (SPI0)
screamer 0:c5e2f793b59a 12473 /** Peripheral SPI1 base address */
screamer 0:c5e2f793b59a 12474 #define SPI1_BASE (0x4002D000u)
screamer 0:c5e2f793b59a 12475 /** Peripheral SPI1 base pointer */
screamer 0:c5e2f793b59a 12476 #define SPI1 ((SPI_Type *)SPI1_BASE)
screamer 0:c5e2f793b59a 12477 #define SPI1_BASE_PTR (SPI1)
screamer 0:c5e2f793b59a 12478 /** Peripheral SPI2 base address */
screamer 0:c5e2f793b59a 12479 #define SPI2_BASE (0x400AC000u)
screamer 0:c5e2f793b59a 12480 /** Peripheral SPI2 base pointer */
screamer 0:c5e2f793b59a 12481 #define SPI2 ((SPI_Type *)SPI2_BASE)
screamer 0:c5e2f793b59a 12482 #define SPI2_BASE_PTR (SPI2)
screamer 0:c5e2f793b59a 12483 /** Array initializer of SPI peripheral base addresses */
screamer 0:c5e2f793b59a 12484 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
screamer 0:c5e2f793b59a 12485 /** Array initializer of SPI peripheral base pointers */
screamer 0:c5e2f793b59a 12486 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
screamer 0:c5e2f793b59a 12487 /** Interrupt vectors for the SPI peripheral type */
screamer 0:c5e2f793b59a 12488 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
screamer 0:c5e2f793b59a 12489
screamer 0:c5e2f793b59a 12490 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12491 -- SPI - Register accessor macros
screamer 0:c5e2f793b59a 12492 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12493
screamer 0:c5e2f793b59a 12494 /*!
screamer 0:c5e2f793b59a 12495 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
screamer 0:c5e2f793b59a 12496 * @{
screamer 0:c5e2f793b59a 12497 */
screamer 0:c5e2f793b59a 12498
screamer 0:c5e2f793b59a 12499
screamer 0:c5e2f793b59a 12500 /* SPI - Register instance definitions */
screamer 0:c5e2f793b59a 12501 /* SPI0 */
screamer 0:c5e2f793b59a 12502 #define SPI0_MCR SPI_MCR_REG(SPI0)
screamer 0:c5e2f793b59a 12503 #define SPI0_TCR SPI_TCR_REG(SPI0)
screamer 0:c5e2f793b59a 12504 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
screamer 0:c5e2f793b59a 12505 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
screamer 0:c5e2f793b59a 12506 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
screamer 0:c5e2f793b59a 12507 #define SPI0_SR SPI_SR_REG(SPI0)
screamer 0:c5e2f793b59a 12508 #define SPI0_RSER SPI_RSER_REG(SPI0)
screamer 0:c5e2f793b59a 12509 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
screamer 0:c5e2f793b59a 12510 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
screamer 0:c5e2f793b59a 12511 #define SPI0_POPR SPI_POPR_REG(SPI0)
screamer 0:c5e2f793b59a 12512 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
screamer 0:c5e2f793b59a 12513 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
screamer 0:c5e2f793b59a 12514 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
screamer 0:c5e2f793b59a 12515 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
screamer 0:c5e2f793b59a 12516 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
screamer 0:c5e2f793b59a 12517 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
screamer 0:c5e2f793b59a 12518 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
screamer 0:c5e2f793b59a 12519 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
screamer 0:c5e2f793b59a 12520 /* SPI1 */
screamer 0:c5e2f793b59a 12521 #define SPI1_MCR SPI_MCR_REG(SPI1)
screamer 0:c5e2f793b59a 12522 #define SPI1_TCR SPI_TCR_REG(SPI1)
screamer 0:c5e2f793b59a 12523 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
screamer 0:c5e2f793b59a 12524 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
screamer 0:c5e2f793b59a 12525 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
screamer 0:c5e2f793b59a 12526 #define SPI1_SR SPI_SR_REG(SPI1)
screamer 0:c5e2f793b59a 12527 #define SPI1_RSER SPI_RSER_REG(SPI1)
screamer 0:c5e2f793b59a 12528 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
screamer 0:c5e2f793b59a 12529 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
screamer 0:c5e2f793b59a 12530 #define SPI1_POPR SPI_POPR_REG(SPI1)
screamer 0:c5e2f793b59a 12531 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
screamer 0:c5e2f793b59a 12532 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
screamer 0:c5e2f793b59a 12533 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
screamer 0:c5e2f793b59a 12534 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
screamer 0:c5e2f793b59a 12535 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
screamer 0:c5e2f793b59a 12536 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
screamer 0:c5e2f793b59a 12537 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
screamer 0:c5e2f793b59a 12538 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
screamer 0:c5e2f793b59a 12539 /* SPI2 */
screamer 0:c5e2f793b59a 12540 #define SPI2_MCR SPI_MCR_REG(SPI2)
screamer 0:c5e2f793b59a 12541 #define SPI2_TCR SPI_TCR_REG(SPI2)
screamer 0:c5e2f793b59a 12542 #define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
screamer 0:c5e2f793b59a 12543 #define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
screamer 0:c5e2f793b59a 12544 #define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
screamer 0:c5e2f793b59a 12545 #define SPI2_SR SPI_SR_REG(SPI2)
screamer 0:c5e2f793b59a 12546 #define SPI2_RSER SPI_RSER_REG(SPI2)
screamer 0:c5e2f793b59a 12547 #define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
screamer 0:c5e2f793b59a 12548 #define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
screamer 0:c5e2f793b59a 12549 #define SPI2_POPR SPI_POPR_REG(SPI2)
screamer 0:c5e2f793b59a 12550 #define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
screamer 0:c5e2f793b59a 12551 #define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
screamer 0:c5e2f793b59a 12552 #define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
screamer 0:c5e2f793b59a 12553 #define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
screamer 0:c5e2f793b59a 12554 #define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
screamer 0:c5e2f793b59a 12555 #define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
screamer 0:c5e2f793b59a 12556 #define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
screamer 0:c5e2f793b59a 12557 #define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
screamer 0:c5e2f793b59a 12558
screamer 0:c5e2f793b59a 12559 /* SPI - Register array accessors */
screamer 0:c5e2f793b59a 12560 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
screamer 0:c5e2f793b59a 12561 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
screamer 0:c5e2f793b59a 12562 #define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
screamer 0:c5e2f793b59a 12563 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
screamer 0:c5e2f793b59a 12564 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
screamer 0:c5e2f793b59a 12565 #define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
screamer 0:c5e2f793b59a 12566
screamer 0:c5e2f793b59a 12567 /*!
screamer 0:c5e2f793b59a 12568 * @}
screamer 0:c5e2f793b59a 12569 */ /* end of group SPI_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 12570
screamer 0:c5e2f793b59a 12571
screamer 0:c5e2f793b59a 12572 /*!
screamer 0:c5e2f793b59a 12573 * @}
screamer 0:c5e2f793b59a 12574 */ /* end of group SPI_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 12575
screamer 0:c5e2f793b59a 12576
screamer 0:c5e2f793b59a 12577 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12578 -- UART Peripheral Access Layer
screamer 0:c5e2f793b59a 12579 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12580
screamer 0:c5e2f793b59a 12581 /*!
screamer 0:c5e2f793b59a 12582 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
screamer 0:c5e2f793b59a 12583 * @{
screamer 0:c5e2f793b59a 12584 */
screamer 0:c5e2f793b59a 12585
screamer 0:c5e2f793b59a 12586 /** UART - Register Layout Typedef */
screamer 0:c5e2f793b59a 12587 typedef struct {
screamer 0:c5e2f793b59a 12588 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
screamer 0:c5e2f793b59a 12589 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
screamer 0:c5e2f793b59a 12590 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
screamer 0:c5e2f793b59a 12591 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
screamer 0:c5e2f793b59a 12592 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
screamer 0:c5e2f793b59a 12593 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
screamer 0:c5e2f793b59a 12594 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
screamer 0:c5e2f793b59a 12595 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
screamer 0:c5e2f793b59a 12596 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
screamer 0:c5e2f793b59a 12597 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
screamer 0:c5e2f793b59a 12598 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
screamer 0:c5e2f793b59a 12599 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
screamer 0:c5e2f793b59a 12600 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
screamer 0:c5e2f793b59a 12601 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
screamer 0:c5e2f793b59a 12602 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
screamer 0:c5e2f793b59a 12603 uint8_t RESERVED_0[1];
screamer 0:c5e2f793b59a 12604 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
screamer 0:c5e2f793b59a 12605 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
screamer 0:c5e2f793b59a 12606 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
screamer 0:c5e2f793b59a 12607 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
screamer 0:c5e2f793b59a 12608 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
screamer 0:c5e2f793b59a 12609 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
screamer 0:c5e2f793b59a 12610 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
screamer 0:c5e2f793b59a 12611 uint8_t RESERVED_1[1];
screamer 0:c5e2f793b59a 12612 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
screamer 0:c5e2f793b59a 12613 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
screamer 0:c5e2f793b59a 12614 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
screamer 0:c5e2f793b59a 12615 union { /* offset: 0x1B */
screamer 0:c5e2f793b59a 12616 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
screamer 0:c5e2f793b59a 12617 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
screamer 0:c5e2f793b59a 12618 };
screamer 0:c5e2f793b59a 12619 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
screamer 0:c5e2f793b59a 12620 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
screamer 0:c5e2f793b59a 12621 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
screamer 0:c5e2f793b59a 12622 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
screamer 0:c5e2f793b59a 12623 } UART_Type, *UART_MemMapPtr;
screamer 0:c5e2f793b59a 12624
screamer 0:c5e2f793b59a 12625 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12626 -- UART - Register accessor macros
screamer 0:c5e2f793b59a 12627 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12628
screamer 0:c5e2f793b59a 12629 /*!
screamer 0:c5e2f793b59a 12630 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
screamer 0:c5e2f793b59a 12631 * @{
screamer 0:c5e2f793b59a 12632 */
screamer 0:c5e2f793b59a 12633
screamer 0:c5e2f793b59a 12634
screamer 0:c5e2f793b59a 12635 /* UART - Register accessors */
screamer 0:c5e2f793b59a 12636 #define UART_BDH_REG(base) ((base)->BDH)
screamer 0:c5e2f793b59a 12637 #define UART_BDL_REG(base) ((base)->BDL)
screamer 0:c5e2f793b59a 12638 #define UART_C1_REG(base) ((base)->C1)
screamer 0:c5e2f793b59a 12639 #define UART_C2_REG(base) ((base)->C2)
screamer 0:c5e2f793b59a 12640 #define UART_S1_REG(base) ((base)->S1)
screamer 0:c5e2f793b59a 12641 #define UART_S2_REG(base) ((base)->S2)
screamer 0:c5e2f793b59a 12642 #define UART_C3_REG(base) ((base)->C3)
screamer 0:c5e2f793b59a 12643 #define UART_D_REG(base) ((base)->D)
screamer 0:c5e2f793b59a 12644 #define UART_MA1_REG(base) ((base)->MA1)
screamer 0:c5e2f793b59a 12645 #define UART_MA2_REG(base) ((base)->MA2)
screamer 0:c5e2f793b59a 12646 #define UART_C4_REG(base) ((base)->C4)
screamer 0:c5e2f793b59a 12647 #define UART_C5_REG(base) ((base)->C5)
screamer 0:c5e2f793b59a 12648 #define UART_ED_REG(base) ((base)->ED)
screamer 0:c5e2f793b59a 12649 #define UART_MODEM_REG(base) ((base)->MODEM)
screamer 0:c5e2f793b59a 12650 #define UART_IR_REG(base) ((base)->IR)
screamer 0:c5e2f793b59a 12651 #define UART_PFIFO_REG(base) ((base)->PFIFO)
screamer 0:c5e2f793b59a 12652 #define UART_CFIFO_REG(base) ((base)->CFIFO)
screamer 0:c5e2f793b59a 12653 #define UART_SFIFO_REG(base) ((base)->SFIFO)
screamer 0:c5e2f793b59a 12654 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
screamer 0:c5e2f793b59a 12655 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
screamer 0:c5e2f793b59a 12656 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
screamer 0:c5e2f793b59a 12657 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
screamer 0:c5e2f793b59a 12658 #define UART_C7816_REG(base) ((base)->C7816)
screamer 0:c5e2f793b59a 12659 #define UART_IE7816_REG(base) ((base)->IE7816)
screamer 0:c5e2f793b59a 12660 #define UART_IS7816_REG(base) ((base)->IS7816)
screamer 0:c5e2f793b59a 12661 #define UART_WP7816T0_REG(base) ((base)->WP7816T0)
screamer 0:c5e2f793b59a 12662 #define UART_WP7816T1_REG(base) ((base)->WP7816T1)
screamer 0:c5e2f793b59a 12663 #define UART_WN7816_REG(base) ((base)->WN7816)
screamer 0:c5e2f793b59a 12664 #define UART_WF7816_REG(base) ((base)->WF7816)
screamer 0:c5e2f793b59a 12665 #define UART_ET7816_REG(base) ((base)->ET7816)
screamer 0:c5e2f793b59a 12666 #define UART_TL7816_REG(base) ((base)->TL7816)
screamer 0:c5e2f793b59a 12667
screamer 0:c5e2f793b59a 12668 /*!
screamer 0:c5e2f793b59a 12669 * @}
screamer 0:c5e2f793b59a 12670 */ /* end of group UART_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 12671
screamer 0:c5e2f793b59a 12672
screamer 0:c5e2f793b59a 12673 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 12674 -- UART Register Masks
screamer 0:c5e2f793b59a 12675 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 12676
screamer 0:c5e2f793b59a 12677 /*!
screamer 0:c5e2f793b59a 12678 * @addtogroup UART_Register_Masks UART Register Masks
screamer 0:c5e2f793b59a 12679 * @{
screamer 0:c5e2f793b59a 12680 */
screamer 0:c5e2f793b59a 12681
screamer 0:c5e2f793b59a 12682 /* BDH Bit Fields */
screamer 0:c5e2f793b59a 12683 #define UART_BDH_SBR_MASK 0x1Fu
screamer 0:c5e2f793b59a 12684 #define UART_BDH_SBR_SHIFT 0
screamer 0:c5e2f793b59a 12685 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
screamer 0:c5e2f793b59a 12686 #define UART_BDH_SBNS_MASK 0x20u
screamer 0:c5e2f793b59a 12687 #define UART_BDH_SBNS_SHIFT 5
screamer 0:c5e2f793b59a 12688 #define UART_BDH_RXEDGIE_MASK 0x40u
screamer 0:c5e2f793b59a 12689 #define UART_BDH_RXEDGIE_SHIFT 6
screamer 0:c5e2f793b59a 12690 #define UART_BDH_LBKDIE_MASK 0x80u
screamer 0:c5e2f793b59a 12691 #define UART_BDH_LBKDIE_SHIFT 7
screamer 0:c5e2f793b59a 12692 /* BDL Bit Fields */
screamer 0:c5e2f793b59a 12693 #define UART_BDL_SBR_MASK 0xFFu
screamer 0:c5e2f793b59a 12694 #define UART_BDL_SBR_SHIFT 0
screamer 0:c5e2f793b59a 12695 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
screamer 0:c5e2f793b59a 12696 /* C1 Bit Fields */
screamer 0:c5e2f793b59a 12697 #define UART_C1_PT_MASK 0x1u
screamer 0:c5e2f793b59a 12698 #define UART_C1_PT_SHIFT 0
screamer 0:c5e2f793b59a 12699 #define UART_C1_PE_MASK 0x2u
screamer 0:c5e2f793b59a 12700 #define UART_C1_PE_SHIFT 1
screamer 0:c5e2f793b59a 12701 #define UART_C1_ILT_MASK 0x4u
screamer 0:c5e2f793b59a 12702 #define UART_C1_ILT_SHIFT 2
screamer 0:c5e2f793b59a 12703 #define UART_C1_WAKE_MASK 0x8u
screamer 0:c5e2f793b59a 12704 #define UART_C1_WAKE_SHIFT 3
screamer 0:c5e2f793b59a 12705 #define UART_C1_M_MASK 0x10u
screamer 0:c5e2f793b59a 12706 #define UART_C1_M_SHIFT 4
screamer 0:c5e2f793b59a 12707 #define UART_C1_RSRC_MASK 0x20u
screamer 0:c5e2f793b59a 12708 #define UART_C1_RSRC_SHIFT 5
screamer 0:c5e2f793b59a 12709 #define UART_C1_UARTSWAI_MASK 0x40u
screamer 0:c5e2f793b59a 12710 #define UART_C1_UARTSWAI_SHIFT 6
screamer 0:c5e2f793b59a 12711 #define UART_C1_LOOPS_MASK 0x80u
screamer 0:c5e2f793b59a 12712 #define UART_C1_LOOPS_SHIFT 7
screamer 0:c5e2f793b59a 12713 /* C2 Bit Fields */
screamer 0:c5e2f793b59a 12714 #define UART_C2_SBK_MASK 0x1u
screamer 0:c5e2f793b59a 12715 #define UART_C2_SBK_SHIFT 0
screamer 0:c5e2f793b59a 12716 #define UART_C2_RWU_MASK 0x2u
screamer 0:c5e2f793b59a 12717 #define UART_C2_RWU_SHIFT 1
screamer 0:c5e2f793b59a 12718 #define UART_C2_RE_MASK 0x4u
screamer 0:c5e2f793b59a 12719 #define UART_C2_RE_SHIFT 2
screamer 0:c5e2f793b59a 12720 #define UART_C2_TE_MASK 0x8u
screamer 0:c5e2f793b59a 12721 #define UART_C2_TE_SHIFT 3
screamer 0:c5e2f793b59a 12722 #define UART_C2_ILIE_MASK 0x10u
screamer 0:c5e2f793b59a 12723 #define UART_C2_ILIE_SHIFT 4
screamer 0:c5e2f793b59a 12724 #define UART_C2_RIE_MASK 0x20u
screamer 0:c5e2f793b59a 12725 #define UART_C2_RIE_SHIFT 5
screamer 0:c5e2f793b59a 12726 #define UART_C2_TCIE_MASK 0x40u
screamer 0:c5e2f793b59a 12727 #define UART_C2_TCIE_SHIFT 6
screamer 0:c5e2f793b59a 12728 #define UART_C2_TIE_MASK 0x80u
screamer 0:c5e2f793b59a 12729 #define UART_C2_TIE_SHIFT 7
screamer 0:c5e2f793b59a 12730 /* S1 Bit Fields */
screamer 0:c5e2f793b59a 12731 #define UART_S1_PF_MASK 0x1u
screamer 0:c5e2f793b59a 12732 #define UART_S1_PF_SHIFT 0
screamer 0:c5e2f793b59a 12733 #define UART_S1_FE_MASK 0x2u
screamer 0:c5e2f793b59a 12734 #define UART_S1_FE_SHIFT 1
screamer 0:c5e2f793b59a 12735 #define UART_S1_NF_MASK 0x4u
screamer 0:c5e2f793b59a 12736 #define UART_S1_NF_SHIFT 2
screamer 0:c5e2f793b59a 12737 #define UART_S1_OR_MASK 0x8u
screamer 0:c5e2f793b59a 12738 #define UART_S1_OR_SHIFT 3
screamer 0:c5e2f793b59a 12739 #define UART_S1_IDLE_MASK 0x10u
screamer 0:c5e2f793b59a 12740 #define UART_S1_IDLE_SHIFT 4
screamer 0:c5e2f793b59a 12741 #define UART_S1_RDRF_MASK 0x20u
screamer 0:c5e2f793b59a 12742 #define UART_S1_RDRF_SHIFT 5
screamer 0:c5e2f793b59a 12743 #define UART_S1_TC_MASK 0x40u
screamer 0:c5e2f793b59a 12744 #define UART_S1_TC_SHIFT 6
screamer 0:c5e2f793b59a 12745 #define UART_S1_TDRE_MASK 0x80u
screamer 0:c5e2f793b59a 12746 #define UART_S1_TDRE_SHIFT 7
screamer 0:c5e2f793b59a 12747 /* S2 Bit Fields */
screamer 0:c5e2f793b59a 12748 #define UART_S2_RAF_MASK 0x1u
screamer 0:c5e2f793b59a 12749 #define UART_S2_RAF_SHIFT 0
screamer 0:c5e2f793b59a 12750 #define UART_S2_LBKDE_MASK 0x2u
screamer 0:c5e2f793b59a 12751 #define UART_S2_LBKDE_SHIFT 1
screamer 0:c5e2f793b59a 12752 #define UART_S2_BRK13_MASK 0x4u
screamer 0:c5e2f793b59a 12753 #define UART_S2_BRK13_SHIFT 2
screamer 0:c5e2f793b59a 12754 #define UART_S2_RWUID_MASK 0x8u
screamer 0:c5e2f793b59a 12755 #define UART_S2_RWUID_SHIFT 3
screamer 0:c5e2f793b59a 12756 #define UART_S2_RXINV_MASK 0x10u
screamer 0:c5e2f793b59a 12757 #define UART_S2_RXINV_SHIFT 4
screamer 0:c5e2f793b59a 12758 #define UART_S2_MSBF_MASK 0x20u
screamer 0:c5e2f793b59a 12759 #define UART_S2_MSBF_SHIFT 5
screamer 0:c5e2f793b59a 12760 #define UART_S2_RXEDGIF_MASK 0x40u
screamer 0:c5e2f793b59a 12761 #define UART_S2_RXEDGIF_SHIFT 6
screamer 0:c5e2f793b59a 12762 #define UART_S2_LBKDIF_MASK 0x80u
screamer 0:c5e2f793b59a 12763 #define UART_S2_LBKDIF_SHIFT 7
screamer 0:c5e2f793b59a 12764 /* C3 Bit Fields */
screamer 0:c5e2f793b59a 12765 #define UART_C3_PEIE_MASK 0x1u
screamer 0:c5e2f793b59a 12766 #define UART_C3_PEIE_SHIFT 0
screamer 0:c5e2f793b59a 12767 #define UART_C3_FEIE_MASK 0x2u
screamer 0:c5e2f793b59a 12768 #define UART_C3_FEIE_SHIFT 1
screamer 0:c5e2f793b59a 12769 #define UART_C3_NEIE_MASK 0x4u
screamer 0:c5e2f793b59a 12770 #define UART_C3_NEIE_SHIFT 2
screamer 0:c5e2f793b59a 12771 #define UART_C3_ORIE_MASK 0x8u
screamer 0:c5e2f793b59a 12772 #define UART_C3_ORIE_SHIFT 3
screamer 0:c5e2f793b59a 12773 #define UART_C3_TXINV_MASK 0x10u
screamer 0:c5e2f793b59a 12774 #define UART_C3_TXINV_SHIFT 4
screamer 0:c5e2f793b59a 12775 #define UART_C3_TXDIR_MASK 0x20u
screamer 0:c5e2f793b59a 12776 #define UART_C3_TXDIR_SHIFT 5
screamer 0:c5e2f793b59a 12777 #define UART_C3_T8_MASK 0x40u
screamer 0:c5e2f793b59a 12778 #define UART_C3_T8_SHIFT 6
screamer 0:c5e2f793b59a 12779 #define UART_C3_R8_MASK 0x80u
screamer 0:c5e2f793b59a 12780 #define UART_C3_R8_SHIFT 7
screamer 0:c5e2f793b59a 12781 /* D Bit Fields */
screamer 0:c5e2f793b59a 12782 #define UART_D_RT_MASK 0xFFu
screamer 0:c5e2f793b59a 12783 #define UART_D_RT_SHIFT 0
screamer 0:c5e2f793b59a 12784 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
screamer 0:c5e2f793b59a 12785 /* MA1 Bit Fields */
screamer 0:c5e2f793b59a 12786 #define UART_MA1_MA_MASK 0xFFu
screamer 0:c5e2f793b59a 12787 #define UART_MA1_MA_SHIFT 0
screamer 0:c5e2f793b59a 12788 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
screamer 0:c5e2f793b59a 12789 /* MA2 Bit Fields */
screamer 0:c5e2f793b59a 12790 #define UART_MA2_MA_MASK 0xFFu
screamer 0:c5e2f793b59a 12791 #define UART_MA2_MA_SHIFT 0
screamer 0:c5e2f793b59a 12792 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
screamer 0:c5e2f793b59a 12793 /* C4 Bit Fields */
screamer 0:c5e2f793b59a 12794 #define UART_C4_BRFA_MASK 0x1Fu
screamer 0:c5e2f793b59a 12795 #define UART_C4_BRFA_SHIFT 0
screamer 0:c5e2f793b59a 12796 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
screamer 0:c5e2f793b59a 12797 #define UART_C4_M10_MASK 0x20u
screamer 0:c5e2f793b59a 12798 #define UART_C4_M10_SHIFT 5
screamer 0:c5e2f793b59a 12799 #define UART_C4_MAEN2_MASK 0x40u
screamer 0:c5e2f793b59a 12800 #define UART_C4_MAEN2_SHIFT 6
screamer 0:c5e2f793b59a 12801 #define UART_C4_MAEN1_MASK 0x80u
screamer 0:c5e2f793b59a 12802 #define UART_C4_MAEN1_SHIFT 7
screamer 0:c5e2f793b59a 12803 /* C5 Bit Fields */
screamer 0:c5e2f793b59a 12804 #define UART_C5_LBKDDMAS_MASK 0x8u
screamer 0:c5e2f793b59a 12805 #define UART_C5_LBKDDMAS_SHIFT 3
screamer 0:c5e2f793b59a 12806 #define UART_C5_ILDMAS_MASK 0x10u
screamer 0:c5e2f793b59a 12807 #define UART_C5_ILDMAS_SHIFT 4
screamer 0:c5e2f793b59a 12808 #define UART_C5_RDMAS_MASK 0x20u
screamer 0:c5e2f793b59a 12809 #define UART_C5_RDMAS_SHIFT 5
screamer 0:c5e2f793b59a 12810 #define UART_C5_TCDMAS_MASK 0x40u
screamer 0:c5e2f793b59a 12811 #define UART_C5_TCDMAS_SHIFT 6
screamer 0:c5e2f793b59a 12812 #define UART_C5_TDMAS_MASK 0x80u
screamer 0:c5e2f793b59a 12813 #define UART_C5_TDMAS_SHIFT 7
screamer 0:c5e2f793b59a 12814 /* ED Bit Fields */
screamer 0:c5e2f793b59a 12815 #define UART_ED_PARITYE_MASK 0x40u
screamer 0:c5e2f793b59a 12816 #define UART_ED_PARITYE_SHIFT 6
screamer 0:c5e2f793b59a 12817 #define UART_ED_NOISY_MASK 0x80u
screamer 0:c5e2f793b59a 12818 #define UART_ED_NOISY_SHIFT 7
screamer 0:c5e2f793b59a 12819 /* MODEM Bit Fields */
screamer 0:c5e2f793b59a 12820 #define UART_MODEM_TXCTSE_MASK 0x1u
screamer 0:c5e2f793b59a 12821 #define UART_MODEM_TXCTSE_SHIFT 0
screamer 0:c5e2f793b59a 12822 #define UART_MODEM_TXRTSE_MASK 0x2u
screamer 0:c5e2f793b59a 12823 #define UART_MODEM_TXRTSE_SHIFT 1
screamer 0:c5e2f793b59a 12824 #define UART_MODEM_TXRTSPOL_MASK 0x4u
screamer 0:c5e2f793b59a 12825 #define UART_MODEM_TXRTSPOL_SHIFT 2
screamer 0:c5e2f793b59a 12826 #define UART_MODEM_RXRTSE_MASK 0x8u
screamer 0:c5e2f793b59a 12827 #define UART_MODEM_RXRTSE_SHIFT 3
screamer 0:c5e2f793b59a 12828 /* IR Bit Fields */
screamer 0:c5e2f793b59a 12829 #define UART_IR_TNP_MASK 0x3u
screamer 0:c5e2f793b59a 12830 #define UART_IR_TNP_SHIFT 0
screamer 0:c5e2f793b59a 12831 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
screamer 0:c5e2f793b59a 12832 #define UART_IR_IREN_MASK 0x4u
screamer 0:c5e2f793b59a 12833 #define UART_IR_IREN_SHIFT 2
screamer 0:c5e2f793b59a 12834 /* PFIFO Bit Fields */
screamer 0:c5e2f793b59a 12835 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
screamer 0:c5e2f793b59a 12836 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
screamer 0:c5e2f793b59a 12837 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
screamer 0:c5e2f793b59a 12838 #define UART_PFIFO_RXFE_MASK 0x8u
screamer 0:c5e2f793b59a 12839 #define UART_PFIFO_RXFE_SHIFT 3
screamer 0:c5e2f793b59a 12840 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
screamer 0:c5e2f793b59a 12841 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
screamer 0:c5e2f793b59a 12842 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
screamer 0:c5e2f793b59a 12843 #define UART_PFIFO_TXFE_MASK 0x80u
screamer 0:c5e2f793b59a 12844 #define UART_PFIFO_TXFE_SHIFT 7
screamer 0:c5e2f793b59a 12845 /* CFIFO Bit Fields */
screamer 0:c5e2f793b59a 12846 #define UART_CFIFO_RXUFE_MASK 0x1u
screamer 0:c5e2f793b59a 12847 #define UART_CFIFO_RXUFE_SHIFT 0
screamer 0:c5e2f793b59a 12848 #define UART_CFIFO_TXOFE_MASK 0x2u
screamer 0:c5e2f793b59a 12849 #define UART_CFIFO_TXOFE_SHIFT 1
screamer 0:c5e2f793b59a 12850 #define UART_CFIFO_RXOFE_MASK 0x4u
screamer 0:c5e2f793b59a 12851 #define UART_CFIFO_RXOFE_SHIFT 2
screamer 0:c5e2f793b59a 12852 #define UART_CFIFO_RXFLUSH_MASK 0x40u
screamer 0:c5e2f793b59a 12853 #define UART_CFIFO_RXFLUSH_SHIFT 6
screamer 0:c5e2f793b59a 12854 #define UART_CFIFO_TXFLUSH_MASK 0x80u
screamer 0:c5e2f793b59a 12855 #define UART_CFIFO_TXFLUSH_SHIFT 7
screamer 0:c5e2f793b59a 12856 /* SFIFO Bit Fields */
screamer 0:c5e2f793b59a 12857 #define UART_SFIFO_RXUF_MASK 0x1u
screamer 0:c5e2f793b59a 12858 #define UART_SFIFO_RXUF_SHIFT 0
screamer 0:c5e2f793b59a 12859 #define UART_SFIFO_TXOF_MASK 0x2u
screamer 0:c5e2f793b59a 12860 #define UART_SFIFO_TXOF_SHIFT 1
screamer 0:c5e2f793b59a 12861 #define UART_SFIFO_RXOF_MASK 0x4u
screamer 0:c5e2f793b59a 12862 #define UART_SFIFO_RXOF_SHIFT 2
screamer 0:c5e2f793b59a 12863 #define UART_SFIFO_RXEMPT_MASK 0x40u
screamer 0:c5e2f793b59a 12864 #define UART_SFIFO_RXEMPT_SHIFT 6
screamer 0:c5e2f793b59a 12865 #define UART_SFIFO_TXEMPT_MASK 0x80u
screamer 0:c5e2f793b59a 12866 #define UART_SFIFO_TXEMPT_SHIFT 7
screamer 0:c5e2f793b59a 12867 /* TWFIFO Bit Fields */
screamer 0:c5e2f793b59a 12868 #define UART_TWFIFO_TXWATER_MASK 0xFFu
screamer 0:c5e2f793b59a 12869 #define UART_TWFIFO_TXWATER_SHIFT 0
screamer 0:c5e2f793b59a 12870 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
screamer 0:c5e2f793b59a 12871 /* TCFIFO Bit Fields */
screamer 0:c5e2f793b59a 12872 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
screamer 0:c5e2f793b59a 12873 #define UART_TCFIFO_TXCOUNT_SHIFT 0
screamer 0:c5e2f793b59a 12874 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
screamer 0:c5e2f793b59a 12875 /* RWFIFO Bit Fields */
screamer 0:c5e2f793b59a 12876 #define UART_RWFIFO_RXWATER_MASK 0xFFu
screamer 0:c5e2f793b59a 12877 #define UART_RWFIFO_RXWATER_SHIFT 0
screamer 0:c5e2f793b59a 12878 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
screamer 0:c5e2f793b59a 12879 /* RCFIFO Bit Fields */
screamer 0:c5e2f793b59a 12880 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
screamer 0:c5e2f793b59a 12881 #define UART_RCFIFO_RXCOUNT_SHIFT 0
screamer 0:c5e2f793b59a 12882 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
screamer 0:c5e2f793b59a 12883 /* C7816 Bit Fields */
screamer 0:c5e2f793b59a 12884 #define UART_C7816_ISO_7816E_MASK 0x1u
screamer 0:c5e2f793b59a 12885 #define UART_C7816_ISO_7816E_SHIFT 0
screamer 0:c5e2f793b59a 12886 #define UART_C7816_TTYPE_MASK 0x2u
screamer 0:c5e2f793b59a 12887 #define UART_C7816_TTYPE_SHIFT 1
screamer 0:c5e2f793b59a 12888 #define UART_C7816_INIT_MASK 0x4u
screamer 0:c5e2f793b59a 12889 #define UART_C7816_INIT_SHIFT 2
screamer 0:c5e2f793b59a 12890 #define UART_C7816_ANACK_MASK 0x8u
screamer 0:c5e2f793b59a 12891 #define UART_C7816_ANACK_SHIFT 3
screamer 0:c5e2f793b59a 12892 #define UART_C7816_ONACK_MASK 0x10u
screamer 0:c5e2f793b59a 12893 #define UART_C7816_ONACK_SHIFT 4
screamer 0:c5e2f793b59a 12894 /* IE7816 Bit Fields */
screamer 0:c5e2f793b59a 12895 #define UART_IE7816_RXTE_MASK 0x1u
screamer 0:c5e2f793b59a 12896 #define UART_IE7816_RXTE_SHIFT 0
screamer 0:c5e2f793b59a 12897 #define UART_IE7816_TXTE_MASK 0x2u
screamer 0:c5e2f793b59a 12898 #define UART_IE7816_TXTE_SHIFT 1
screamer 0:c5e2f793b59a 12899 #define UART_IE7816_GTVE_MASK 0x4u
screamer 0:c5e2f793b59a 12900 #define UART_IE7816_GTVE_SHIFT 2
screamer 0:c5e2f793b59a 12901 #define UART_IE7816_INITDE_MASK 0x10u
screamer 0:c5e2f793b59a 12902 #define UART_IE7816_INITDE_SHIFT 4
screamer 0:c5e2f793b59a 12903 #define UART_IE7816_BWTE_MASK 0x20u
screamer 0:c5e2f793b59a 12904 #define UART_IE7816_BWTE_SHIFT 5
screamer 0:c5e2f793b59a 12905 #define UART_IE7816_CWTE_MASK 0x40u
screamer 0:c5e2f793b59a 12906 #define UART_IE7816_CWTE_SHIFT 6
screamer 0:c5e2f793b59a 12907 #define UART_IE7816_WTE_MASK 0x80u
screamer 0:c5e2f793b59a 12908 #define UART_IE7816_WTE_SHIFT 7
screamer 0:c5e2f793b59a 12909 /* IS7816 Bit Fields */
screamer 0:c5e2f793b59a 12910 #define UART_IS7816_RXT_MASK 0x1u
screamer 0:c5e2f793b59a 12911 #define UART_IS7816_RXT_SHIFT 0
screamer 0:c5e2f793b59a 12912 #define UART_IS7816_TXT_MASK 0x2u
screamer 0:c5e2f793b59a 12913 #define UART_IS7816_TXT_SHIFT 1
screamer 0:c5e2f793b59a 12914 #define UART_IS7816_GTV_MASK 0x4u
screamer 0:c5e2f793b59a 12915 #define UART_IS7816_GTV_SHIFT 2
screamer 0:c5e2f793b59a 12916 #define UART_IS7816_INITD_MASK 0x10u
screamer 0:c5e2f793b59a 12917 #define UART_IS7816_INITD_SHIFT 4
screamer 0:c5e2f793b59a 12918 #define UART_IS7816_BWT_MASK 0x20u
screamer 0:c5e2f793b59a 12919 #define UART_IS7816_BWT_SHIFT 5
screamer 0:c5e2f793b59a 12920 #define UART_IS7816_CWT_MASK 0x40u
screamer 0:c5e2f793b59a 12921 #define UART_IS7816_CWT_SHIFT 6
screamer 0:c5e2f793b59a 12922 #define UART_IS7816_WT_MASK 0x80u
screamer 0:c5e2f793b59a 12923 #define UART_IS7816_WT_SHIFT 7
screamer 0:c5e2f793b59a 12924 /* WP7816T0 Bit Fields */
screamer 0:c5e2f793b59a 12925 #define UART_WP7816T0_WI_MASK 0xFFu
screamer 0:c5e2f793b59a 12926 #define UART_WP7816T0_WI_SHIFT 0
screamer 0:c5e2f793b59a 12927 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
screamer 0:c5e2f793b59a 12928 /* WP7816T1 Bit Fields */
screamer 0:c5e2f793b59a 12929 #define UART_WP7816T1_BWI_MASK 0xFu
screamer 0:c5e2f793b59a 12930 #define UART_WP7816T1_BWI_SHIFT 0
screamer 0:c5e2f793b59a 12931 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
screamer 0:c5e2f793b59a 12932 #define UART_WP7816T1_CWI_MASK 0xF0u
screamer 0:c5e2f793b59a 12933 #define UART_WP7816T1_CWI_SHIFT 4
screamer 0:c5e2f793b59a 12934 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
screamer 0:c5e2f793b59a 12935 /* WN7816 Bit Fields */
screamer 0:c5e2f793b59a 12936 #define UART_WN7816_GTN_MASK 0xFFu
screamer 0:c5e2f793b59a 12937 #define UART_WN7816_GTN_SHIFT 0
screamer 0:c5e2f793b59a 12938 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
screamer 0:c5e2f793b59a 12939 /* WF7816 Bit Fields */
screamer 0:c5e2f793b59a 12940 #define UART_WF7816_GTFD_MASK 0xFFu
screamer 0:c5e2f793b59a 12941 #define UART_WF7816_GTFD_SHIFT 0
screamer 0:c5e2f793b59a 12942 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
screamer 0:c5e2f793b59a 12943 /* ET7816 Bit Fields */
screamer 0:c5e2f793b59a 12944 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
screamer 0:c5e2f793b59a 12945 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
screamer 0:c5e2f793b59a 12946 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
screamer 0:c5e2f793b59a 12947 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
screamer 0:c5e2f793b59a 12948 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
screamer 0:c5e2f793b59a 12949 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
screamer 0:c5e2f793b59a 12950 /* TL7816 Bit Fields */
screamer 0:c5e2f793b59a 12951 #define UART_TL7816_TLEN_MASK 0xFFu
screamer 0:c5e2f793b59a 12952 #define UART_TL7816_TLEN_SHIFT 0
screamer 0:c5e2f793b59a 12953 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
screamer 0:c5e2f793b59a 12954
screamer 0:c5e2f793b59a 12955 /*!
screamer 0:c5e2f793b59a 12956 * @}
screamer 0:c5e2f793b59a 12957 */ /* end of group UART_Register_Masks */
screamer 0:c5e2f793b59a 12958
screamer 0:c5e2f793b59a 12959
screamer 0:c5e2f793b59a 12960 /* UART - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 12961 /** Peripheral UART0 base address */
screamer 0:c5e2f793b59a 12962 #define UART0_BASE (0x4006A000u)
screamer 0:c5e2f793b59a 12963 /** Peripheral UART0 base pointer */
screamer 0:c5e2f793b59a 12964 #define UART0 ((UART_Type *)UART0_BASE)
screamer 0:c5e2f793b59a 12965 #define UART0_BASE_PTR (UART0)
screamer 0:c5e2f793b59a 12966 /** Peripheral UART1 base address */
screamer 0:c5e2f793b59a 12967 #define UART1_BASE (0x4006B000u)
screamer 0:c5e2f793b59a 12968 /** Peripheral UART1 base pointer */
screamer 0:c5e2f793b59a 12969 #define UART1 ((UART_Type *)UART1_BASE)
screamer 0:c5e2f793b59a 12970 #define UART1_BASE_PTR (UART1)
screamer 0:c5e2f793b59a 12971 /** Peripheral UART2 base address */
screamer 0:c5e2f793b59a 12972 #define UART2_BASE (0x4006C000u)
screamer 0:c5e2f793b59a 12973 /** Peripheral UART2 base pointer */
screamer 0:c5e2f793b59a 12974 #define UART2 ((UART_Type *)UART2_BASE)
screamer 0:c5e2f793b59a 12975 #define UART2_BASE_PTR (UART2)
screamer 0:c5e2f793b59a 12976 /** Peripheral UART3 base address */
screamer 0:c5e2f793b59a 12977 #define UART3_BASE (0x4006D000u)
screamer 0:c5e2f793b59a 12978 /** Peripheral UART3 base pointer */
screamer 0:c5e2f793b59a 12979 #define UART3 ((UART_Type *)UART3_BASE)
screamer 0:c5e2f793b59a 12980 #define UART3_BASE_PTR (UART3)
screamer 0:c5e2f793b59a 12981 /** Peripheral UART4 base address */
screamer 0:c5e2f793b59a 12982 #define UART4_BASE (0x400EA000u)
screamer 0:c5e2f793b59a 12983 /** Peripheral UART4 base pointer */
screamer 0:c5e2f793b59a 12984 #define UART4 ((UART_Type *)UART4_BASE)
screamer 0:c5e2f793b59a 12985 #define UART4_BASE_PTR (UART4)
screamer 0:c5e2f793b59a 12986 /** Peripheral UART5 base address */
screamer 0:c5e2f793b59a 12987 #define UART5_BASE (0x400EB000u)
screamer 0:c5e2f793b59a 12988 /** Peripheral UART5 base pointer */
screamer 0:c5e2f793b59a 12989 #define UART5 ((UART_Type *)UART5_BASE)
screamer 0:c5e2f793b59a 12990 #define UART5_BASE_PTR (UART5)
screamer 0:c5e2f793b59a 12991 /** Array initializer of UART peripheral base addresses */
screamer 0:c5e2f793b59a 12992 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
screamer 0:c5e2f793b59a 12993 /** Array initializer of UART peripheral base pointers */
screamer 0:c5e2f793b59a 12994 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
screamer 0:c5e2f793b59a 12995 /** Interrupt vectors for the UART peripheral type */
screamer 0:c5e2f793b59a 12996 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
screamer 0:c5e2f793b59a 12997 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
screamer 0:c5e2f793b59a 12998 #define UART_LON_IRQS { UART0_LON_IRQn, 0, 0, 0, 0, 0 }
screamer 0:c5e2f793b59a 12999
screamer 0:c5e2f793b59a 13000 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13001 -- UART - Register accessor macros
screamer 0:c5e2f793b59a 13002 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13003
screamer 0:c5e2f793b59a 13004 /*!
screamer 0:c5e2f793b59a 13005 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
screamer 0:c5e2f793b59a 13006 * @{
screamer 0:c5e2f793b59a 13007 */
screamer 0:c5e2f793b59a 13008
screamer 0:c5e2f793b59a 13009
screamer 0:c5e2f793b59a 13010 /* UART - Register instance definitions */
screamer 0:c5e2f793b59a 13011 /* UART0 */
screamer 0:c5e2f793b59a 13012 #define UART0_BDH UART_BDH_REG(UART0)
screamer 0:c5e2f793b59a 13013 #define UART0_BDL UART_BDL_REG(UART0)
screamer 0:c5e2f793b59a 13014 #define UART0_C1 UART_C1_REG(UART0)
screamer 0:c5e2f793b59a 13015 #define UART0_C2 UART_C2_REG(UART0)
screamer 0:c5e2f793b59a 13016 #define UART0_S1 UART_S1_REG(UART0)
screamer 0:c5e2f793b59a 13017 #define UART0_S2 UART_S2_REG(UART0)
screamer 0:c5e2f793b59a 13018 #define UART0_C3 UART_C3_REG(UART0)
screamer 0:c5e2f793b59a 13019 #define UART0_D UART_D_REG(UART0)
screamer 0:c5e2f793b59a 13020 #define UART0_MA1 UART_MA1_REG(UART0)
screamer 0:c5e2f793b59a 13021 #define UART0_MA2 UART_MA2_REG(UART0)
screamer 0:c5e2f793b59a 13022 #define UART0_C4 UART_C4_REG(UART0)
screamer 0:c5e2f793b59a 13023 #define UART0_C5 UART_C5_REG(UART0)
screamer 0:c5e2f793b59a 13024 #define UART0_ED UART_ED_REG(UART0)
screamer 0:c5e2f793b59a 13025 #define UART0_MODEM UART_MODEM_REG(UART0)
screamer 0:c5e2f793b59a 13026 #define UART0_IR UART_IR_REG(UART0)
screamer 0:c5e2f793b59a 13027 #define UART0_PFIFO UART_PFIFO_REG(UART0)
screamer 0:c5e2f793b59a 13028 #define UART0_CFIFO UART_CFIFO_REG(UART0)
screamer 0:c5e2f793b59a 13029 #define UART0_SFIFO UART_SFIFO_REG(UART0)
screamer 0:c5e2f793b59a 13030 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
screamer 0:c5e2f793b59a 13031 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
screamer 0:c5e2f793b59a 13032 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
screamer 0:c5e2f793b59a 13033 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
screamer 0:c5e2f793b59a 13034 #define UART0_C7816 UART_C7816_REG(UART0)
screamer 0:c5e2f793b59a 13035 #define UART0_IE7816 UART_IE7816_REG(UART0)
screamer 0:c5e2f793b59a 13036 #define UART0_IS7816 UART_IS7816_REG(UART0)
screamer 0:c5e2f793b59a 13037 #define UART0_WP7816T0 UART_WP7816T0_REG(UART0)
screamer 0:c5e2f793b59a 13038 #define UART0_WP7816T1 UART_WP7816T1_REG(UART0)
screamer 0:c5e2f793b59a 13039 #define UART0_WN7816 UART_WN7816_REG(UART0)
screamer 0:c5e2f793b59a 13040 #define UART0_WF7816 UART_WF7816_REG(UART0)
screamer 0:c5e2f793b59a 13041 #define UART0_ET7816 UART_ET7816_REG(UART0)
screamer 0:c5e2f793b59a 13042 #define UART0_TL7816 UART_TL7816_REG(UART0)
screamer 0:c5e2f793b59a 13043 /* UART1 */
screamer 0:c5e2f793b59a 13044 #define UART1_BDH UART_BDH_REG(UART1)
screamer 0:c5e2f793b59a 13045 #define UART1_BDL UART_BDL_REG(UART1)
screamer 0:c5e2f793b59a 13046 #define UART1_C1 UART_C1_REG(UART1)
screamer 0:c5e2f793b59a 13047 #define UART1_C2 UART_C2_REG(UART1)
screamer 0:c5e2f793b59a 13048 #define UART1_S1 UART_S1_REG(UART1)
screamer 0:c5e2f793b59a 13049 #define UART1_S2 UART_S2_REG(UART1)
screamer 0:c5e2f793b59a 13050 #define UART1_C3 UART_C3_REG(UART1)
screamer 0:c5e2f793b59a 13051 #define UART1_D UART_D_REG(UART1)
screamer 0:c5e2f793b59a 13052 #define UART1_MA1 UART_MA1_REG(UART1)
screamer 0:c5e2f793b59a 13053 #define UART1_MA2 UART_MA2_REG(UART1)
screamer 0:c5e2f793b59a 13054 #define UART1_C4 UART_C4_REG(UART1)
screamer 0:c5e2f793b59a 13055 #define UART1_C5 UART_C5_REG(UART1)
screamer 0:c5e2f793b59a 13056 #define UART1_ED UART_ED_REG(UART1)
screamer 0:c5e2f793b59a 13057 #define UART1_MODEM UART_MODEM_REG(UART1)
screamer 0:c5e2f793b59a 13058 #define UART1_IR UART_IR_REG(UART1)
screamer 0:c5e2f793b59a 13059 #define UART1_PFIFO UART_PFIFO_REG(UART1)
screamer 0:c5e2f793b59a 13060 #define UART1_CFIFO UART_CFIFO_REG(UART1)
screamer 0:c5e2f793b59a 13061 #define UART1_SFIFO UART_SFIFO_REG(UART1)
screamer 0:c5e2f793b59a 13062 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
screamer 0:c5e2f793b59a 13063 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
screamer 0:c5e2f793b59a 13064 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
screamer 0:c5e2f793b59a 13065 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
screamer 0:c5e2f793b59a 13066 /* UART2 */
screamer 0:c5e2f793b59a 13067 #define UART2_BDH UART_BDH_REG(UART2)
screamer 0:c5e2f793b59a 13068 #define UART2_BDL UART_BDL_REG(UART2)
screamer 0:c5e2f793b59a 13069 #define UART2_C1 UART_C1_REG(UART2)
screamer 0:c5e2f793b59a 13070 #define UART2_C2 UART_C2_REG(UART2)
screamer 0:c5e2f793b59a 13071 #define UART2_S1 UART_S1_REG(UART2)
screamer 0:c5e2f793b59a 13072 #define UART2_S2 UART_S2_REG(UART2)
screamer 0:c5e2f793b59a 13073 #define UART2_C3 UART_C3_REG(UART2)
screamer 0:c5e2f793b59a 13074 #define UART2_D UART_D_REG(UART2)
screamer 0:c5e2f793b59a 13075 #define UART2_MA1 UART_MA1_REG(UART2)
screamer 0:c5e2f793b59a 13076 #define UART2_MA2 UART_MA2_REG(UART2)
screamer 0:c5e2f793b59a 13077 #define UART2_C4 UART_C4_REG(UART2)
screamer 0:c5e2f793b59a 13078 #define UART2_C5 UART_C5_REG(UART2)
screamer 0:c5e2f793b59a 13079 #define UART2_ED UART_ED_REG(UART2)
screamer 0:c5e2f793b59a 13080 #define UART2_MODEM UART_MODEM_REG(UART2)
screamer 0:c5e2f793b59a 13081 #define UART2_IR UART_IR_REG(UART2)
screamer 0:c5e2f793b59a 13082 #define UART2_PFIFO UART_PFIFO_REG(UART2)
screamer 0:c5e2f793b59a 13083 #define UART2_CFIFO UART_CFIFO_REG(UART2)
screamer 0:c5e2f793b59a 13084 #define UART2_SFIFO UART_SFIFO_REG(UART2)
screamer 0:c5e2f793b59a 13085 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
screamer 0:c5e2f793b59a 13086 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
screamer 0:c5e2f793b59a 13087 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
screamer 0:c5e2f793b59a 13088 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
screamer 0:c5e2f793b59a 13089 /* UART3 */
screamer 0:c5e2f793b59a 13090 #define UART3_BDH UART_BDH_REG(UART3)
screamer 0:c5e2f793b59a 13091 #define UART3_BDL UART_BDL_REG(UART3)
screamer 0:c5e2f793b59a 13092 #define UART3_C1 UART_C1_REG(UART3)
screamer 0:c5e2f793b59a 13093 #define UART3_C2 UART_C2_REG(UART3)
screamer 0:c5e2f793b59a 13094 #define UART3_S1 UART_S1_REG(UART3)
screamer 0:c5e2f793b59a 13095 #define UART3_S2 UART_S2_REG(UART3)
screamer 0:c5e2f793b59a 13096 #define UART3_C3 UART_C3_REG(UART3)
screamer 0:c5e2f793b59a 13097 #define UART3_D UART_D_REG(UART3)
screamer 0:c5e2f793b59a 13098 #define UART3_MA1 UART_MA1_REG(UART3)
screamer 0:c5e2f793b59a 13099 #define UART3_MA2 UART_MA2_REG(UART3)
screamer 0:c5e2f793b59a 13100 #define UART3_C4 UART_C4_REG(UART3)
screamer 0:c5e2f793b59a 13101 #define UART3_C5 UART_C5_REG(UART3)
screamer 0:c5e2f793b59a 13102 #define UART3_ED UART_ED_REG(UART3)
screamer 0:c5e2f793b59a 13103 #define UART3_MODEM UART_MODEM_REG(UART3)
screamer 0:c5e2f793b59a 13104 #define UART3_IR UART_IR_REG(UART3)
screamer 0:c5e2f793b59a 13105 #define UART3_PFIFO UART_PFIFO_REG(UART3)
screamer 0:c5e2f793b59a 13106 #define UART3_CFIFO UART_CFIFO_REG(UART3)
screamer 0:c5e2f793b59a 13107 #define UART3_SFIFO UART_SFIFO_REG(UART3)
screamer 0:c5e2f793b59a 13108 #define UART3_TWFIFO UART_TWFIFO_REG(UART3)
screamer 0:c5e2f793b59a 13109 #define UART3_TCFIFO UART_TCFIFO_REG(UART3)
screamer 0:c5e2f793b59a 13110 #define UART3_RWFIFO UART_RWFIFO_REG(UART3)
screamer 0:c5e2f793b59a 13111 #define UART3_RCFIFO UART_RCFIFO_REG(UART3)
screamer 0:c5e2f793b59a 13112 /* UART4 */
screamer 0:c5e2f793b59a 13113 #define UART4_BDH UART_BDH_REG(UART4)
screamer 0:c5e2f793b59a 13114 #define UART4_BDL UART_BDL_REG(UART4)
screamer 0:c5e2f793b59a 13115 #define UART4_C1 UART_C1_REG(UART4)
screamer 0:c5e2f793b59a 13116 #define UART4_C2 UART_C2_REG(UART4)
screamer 0:c5e2f793b59a 13117 #define UART4_S1 UART_S1_REG(UART4)
screamer 0:c5e2f793b59a 13118 #define UART4_S2 UART_S2_REG(UART4)
screamer 0:c5e2f793b59a 13119 #define UART4_C3 UART_C3_REG(UART4)
screamer 0:c5e2f793b59a 13120 #define UART4_D UART_D_REG(UART4)
screamer 0:c5e2f793b59a 13121 #define UART4_MA1 UART_MA1_REG(UART4)
screamer 0:c5e2f793b59a 13122 #define UART4_MA2 UART_MA2_REG(UART4)
screamer 0:c5e2f793b59a 13123 #define UART4_C4 UART_C4_REG(UART4)
screamer 0:c5e2f793b59a 13124 #define UART4_C5 UART_C5_REG(UART4)
screamer 0:c5e2f793b59a 13125 #define UART4_ED UART_ED_REG(UART4)
screamer 0:c5e2f793b59a 13126 #define UART4_MODEM UART_MODEM_REG(UART4)
screamer 0:c5e2f793b59a 13127 #define UART4_IR UART_IR_REG(UART4)
screamer 0:c5e2f793b59a 13128 #define UART4_PFIFO UART_PFIFO_REG(UART4)
screamer 0:c5e2f793b59a 13129 #define UART4_CFIFO UART_CFIFO_REG(UART4)
screamer 0:c5e2f793b59a 13130 #define UART4_SFIFO UART_SFIFO_REG(UART4)
screamer 0:c5e2f793b59a 13131 #define UART4_TWFIFO UART_TWFIFO_REG(UART4)
screamer 0:c5e2f793b59a 13132 #define UART4_TCFIFO UART_TCFIFO_REG(UART4)
screamer 0:c5e2f793b59a 13133 #define UART4_RWFIFO UART_RWFIFO_REG(UART4)
screamer 0:c5e2f793b59a 13134 #define UART4_RCFIFO UART_RCFIFO_REG(UART4)
screamer 0:c5e2f793b59a 13135 /* UART5 */
screamer 0:c5e2f793b59a 13136 #define UART5_BDH UART_BDH_REG(UART5)
screamer 0:c5e2f793b59a 13137 #define UART5_BDL UART_BDL_REG(UART5)
screamer 0:c5e2f793b59a 13138 #define UART5_C1 UART_C1_REG(UART5)
screamer 0:c5e2f793b59a 13139 #define UART5_C2 UART_C2_REG(UART5)
screamer 0:c5e2f793b59a 13140 #define UART5_S1 UART_S1_REG(UART5)
screamer 0:c5e2f793b59a 13141 #define UART5_S2 UART_S2_REG(UART5)
screamer 0:c5e2f793b59a 13142 #define UART5_C3 UART_C3_REG(UART5)
screamer 0:c5e2f793b59a 13143 #define UART5_D UART_D_REG(UART5)
screamer 0:c5e2f793b59a 13144 #define UART5_MA1 UART_MA1_REG(UART5)
screamer 0:c5e2f793b59a 13145 #define UART5_MA2 UART_MA2_REG(UART5)
screamer 0:c5e2f793b59a 13146 #define UART5_C4 UART_C4_REG(UART5)
screamer 0:c5e2f793b59a 13147 #define UART5_C5 UART_C5_REG(UART5)
screamer 0:c5e2f793b59a 13148 #define UART5_ED UART_ED_REG(UART5)
screamer 0:c5e2f793b59a 13149 #define UART5_MODEM UART_MODEM_REG(UART5)
screamer 0:c5e2f793b59a 13150 #define UART5_IR UART_IR_REG(UART5)
screamer 0:c5e2f793b59a 13151 #define UART5_PFIFO UART_PFIFO_REG(UART5)
screamer 0:c5e2f793b59a 13152 #define UART5_CFIFO UART_CFIFO_REG(UART5)
screamer 0:c5e2f793b59a 13153 #define UART5_SFIFO UART_SFIFO_REG(UART5)
screamer 0:c5e2f793b59a 13154 #define UART5_TWFIFO UART_TWFIFO_REG(UART5)
screamer 0:c5e2f793b59a 13155 #define UART5_TCFIFO UART_TCFIFO_REG(UART5)
screamer 0:c5e2f793b59a 13156 #define UART5_RWFIFO UART_RWFIFO_REG(UART5)
screamer 0:c5e2f793b59a 13157 #define UART5_RCFIFO UART_RCFIFO_REG(UART5)
screamer 0:c5e2f793b59a 13158
screamer 0:c5e2f793b59a 13159 /*!
screamer 0:c5e2f793b59a 13160 * @}
screamer 0:c5e2f793b59a 13161 */ /* end of group UART_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 13162
screamer 0:c5e2f793b59a 13163
screamer 0:c5e2f793b59a 13164 /*!
screamer 0:c5e2f793b59a 13165 * @}
screamer 0:c5e2f793b59a 13166 */ /* end of group UART_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 13167
screamer 0:c5e2f793b59a 13168
screamer 0:c5e2f793b59a 13169 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13170 -- USB Peripheral Access Layer
screamer 0:c5e2f793b59a 13171 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13172
screamer 0:c5e2f793b59a 13173 /*!
screamer 0:c5e2f793b59a 13174 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
screamer 0:c5e2f793b59a 13175 * @{
screamer 0:c5e2f793b59a 13176 */
screamer 0:c5e2f793b59a 13177
screamer 0:c5e2f793b59a 13178 /** USB - Register Layout Typedef */
screamer 0:c5e2f793b59a 13179 typedef struct {
screamer 0:c5e2f793b59a 13180 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
screamer 0:c5e2f793b59a 13181 uint8_t RESERVED_0[3];
screamer 0:c5e2f793b59a 13182 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
screamer 0:c5e2f793b59a 13183 uint8_t RESERVED_1[3];
screamer 0:c5e2f793b59a 13184 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
screamer 0:c5e2f793b59a 13185 uint8_t RESERVED_2[3];
screamer 0:c5e2f793b59a 13186 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
screamer 0:c5e2f793b59a 13187 uint8_t RESERVED_3[3];
screamer 0:c5e2f793b59a 13188 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
screamer 0:c5e2f793b59a 13189 uint8_t RESERVED_4[3];
screamer 0:c5e2f793b59a 13190 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
screamer 0:c5e2f793b59a 13191 uint8_t RESERVED_5[3];
screamer 0:c5e2f793b59a 13192 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
screamer 0:c5e2f793b59a 13193 uint8_t RESERVED_6[3];
screamer 0:c5e2f793b59a 13194 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
screamer 0:c5e2f793b59a 13195 uint8_t RESERVED_7[99];
screamer 0:c5e2f793b59a 13196 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
screamer 0:c5e2f793b59a 13197 uint8_t RESERVED_8[3];
screamer 0:c5e2f793b59a 13198 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
screamer 0:c5e2f793b59a 13199 uint8_t RESERVED_9[3];
screamer 0:c5e2f793b59a 13200 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
screamer 0:c5e2f793b59a 13201 uint8_t RESERVED_10[3];
screamer 0:c5e2f793b59a 13202 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
screamer 0:c5e2f793b59a 13203 uint8_t RESERVED_11[3];
screamer 0:c5e2f793b59a 13204 __I uint8_t STAT; /**< Status register, offset: 0x90 */
screamer 0:c5e2f793b59a 13205 uint8_t RESERVED_12[3];
screamer 0:c5e2f793b59a 13206 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
screamer 0:c5e2f793b59a 13207 uint8_t RESERVED_13[3];
screamer 0:c5e2f793b59a 13208 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
screamer 0:c5e2f793b59a 13209 uint8_t RESERVED_14[3];
screamer 0:c5e2f793b59a 13210 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
screamer 0:c5e2f793b59a 13211 uint8_t RESERVED_15[3];
screamer 0:c5e2f793b59a 13212 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
screamer 0:c5e2f793b59a 13213 uint8_t RESERVED_16[3];
screamer 0:c5e2f793b59a 13214 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
screamer 0:c5e2f793b59a 13215 uint8_t RESERVED_17[3];
screamer 0:c5e2f793b59a 13216 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
screamer 0:c5e2f793b59a 13217 uint8_t RESERVED_18[3];
screamer 0:c5e2f793b59a 13218 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
screamer 0:c5e2f793b59a 13219 uint8_t RESERVED_19[3];
screamer 0:c5e2f793b59a 13220 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
screamer 0:c5e2f793b59a 13221 uint8_t RESERVED_20[3];
screamer 0:c5e2f793b59a 13222 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
screamer 0:c5e2f793b59a 13223 uint8_t RESERVED_21[11];
screamer 0:c5e2f793b59a 13224 struct { /* offset: 0xC0, array step: 0x4 */
screamer 0:c5e2f793b59a 13225 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
screamer 0:c5e2f793b59a 13226 uint8_t RESERVED_0[3];
screamer 0:c5e2f793b59a 13227 } ENDPOINT[16];
screamer 0:c5e2f793b59a 13228 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
screamer 0:c5e2f793b59a 13229 uint8_t RESERVED_22[3];
screamer 0:c5e2f793b59a 13230 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
screamer 0:c5e2f793b59a 13231 uint8_t RESERVED_23[3];
screamer 0:c5e2f793b59a 13232 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
screamer 0:c5e2f793b59a 13233 uint8_t RESERVED_24[3];
screamer 0:c5e2f793b59a 13234 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
screamer 0:c5e2f793b59a 13235 uint8_t RESERVED_25[7];
screamer 0:c5e2f793b59a 13236 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
screamer 0:c5e2f793b59a 13237 uint8_t RESERVED_26[43];
screamer 0:c5e2f793b59a 13238 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
screamer 0:c5e2f793b59a 13239 uint8_t RESERVED_27[3];
screamer 0:c5e2f793b59a 13240 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
screamer 0:c5e2f793b59a 13241 uint8_t RESERVED_28[23];
screamer 0:c5e2f793b59a 13242 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
screamer 0:c5e2f793b59a 13243 } USB_Type, *USB_MemMapPtr;
screamer 0:c5e2f793b59a 13244
screamer 0:c5e2f793b59a 13245 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13246 -- USB - Register accessor macros
screamer 0:c5e2f793b59a 13247 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13248
screamer 0:c5e2f793b59a 13249 /*!
screamer 0:c5e2f793b59a 13250 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
screamer 0:c5e2f793b59a 13251 * @{
screamer 0:c5e2f793b59a 13252 */
screamer 0:c5e2f793b59a 13253
screamer 0:c5e2f793b59a 13254
screamer 0:c5e2f793b59a 13255 /* USB - Register accessors */
screamer 0:c5e2f793b59a 13256 #define USB_PERID_REG(base) ((base)->PERID)
screamer 0:c5e2f793b59a 13257 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
screamer 0:c5e2f793b59a 13258 #define USB_REV_REG(base) ((base)->REV)
screamer 0:c5e2f793b59a 13259 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
screamer 0:c5e2f793b59a 13260 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
screamer 0:c5e2f793b59a 13261 #define USB_OTGICR_REG(base) ((base)->OTGICR)
screamer 0:c5e2f793b59a 13262 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
screamer 0:c5e2f793b59a 13263 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
screamer 0:c5e2f793b59a 13264 #define USB_ISTAT_REG(base) ((base)->ISTAT)
screamer 0:c5e2f793b59a 13265 #define USB_INTEN_REG(base) ((base)->INTEN)
screamer 0:c5e2f793b59a 13266 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
screamer 0:c5e2f793b59a 13267 #define USB_ERREN_REG(base) ((base)->ERREN)
screamer 0:c5e2f793b59a 13268 #define USB_STAT_REG(base) ((base)->STAT)
screamer 0:c5e2f793b59a 13269 #define USB_CTL_REG(base) ((base)->CTL)
screamer 0:c5e2f793b59a 13270 #define USB_ADDR_REG(base) ((base)->ADDR)
screamer 0:c5e2f793b59a 13271 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
screamer 0:c5e2f793b59a 13272 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
screamer 0:c5e2f793b59a 13273 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
screamer 0:c5e2f793b59a 13274 #define USB_TOKEN_REG(base) ((base)->TOKEN)
screamer 0:c5e2f793b59a 13275 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
screamer 0:c5e2f793b59a 13276 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
screamer 0:c5e2f793b59a 13277 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
screamer 0:c5e2f793b59a 13278 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
screamer 0:c5e2f793b59a 13279 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
screamer 0:c5e2f793b59a 13280 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
screamer 0:c5e2f793b59a 13281 #define USB_CONTROL_REG(base) ((base)->CONTROL)
screamer 0:c5e2f793b59a 13282 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
screamer 0:c5e2f793b59a 13283 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
screamer 0:c5e2f793b59a 13284 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
screamer 0:c5e2f793b59a 13285 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
screamer 0:c5e2f793b59a 13286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
screamer 0:c5e2f793b59a 13287
screamer 0:c5e2f793b59a 13288 /*!
screamer 0:c5e2f793b59a 13289 * @}
screamer 0:c5e2f793b59a 13290 */ /* end of group USB_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 13291
screamer 0:c5e2f793b59a 13292
screamer 0:c5e2f793b59a 13293 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13294 -- USB Register Masks
screamer 0:c5e2f793b59a 13295 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13296
screamer 0:c5e2f793b59a 13297 /*!
screamer 0:c5e2f793b59a 13298 * @addtogroup USB_Register_Masks USB Register Masks
screamer 0:c5e2f793b59a 13299 * @{
screamer 0:c5e2f793b59a 13300 */
screamer 0:c5e2f793b59a 13301
screamer 0:c5e2f793b59a 13302 /* PERID Bit Fields */
screamer 0:c5e2f793b59a 13303 #define USB_PERID_ID_MASK 0x3Fu
screamer 0:c5e2f793b59a 13304 #define USB_PERID_ID_SHIFT 0
screamer 0:c5e2f793b59a 13305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
screamer 0:c5e2f793b59a 13306 /* IDCOMP Bit Fields */
screamer 0:c5e2f793b59a 13307 #define USB_IDCOMP_NID_MASK 0x3Fu
screamer 0:c5e2f793b59a 13308 #define USB_IDCOMP_NID_SHIFT 0
screamer 0:c5e2f793b59a 13309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
screamer 0:c5e2f793b59a 13310 /* REV Bit Fields */
screamer 0:c5e2f793b59a 13311 #define USB_REV_REV_MASK 0xFFu
screamer 0:c5e2f793b59a 13312 #define USB_REV_REV_SHIFT 0
screamer 0:c5e2f793b59a 13313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
screamer 0:c5e2f793b59a 13314 /* ADDINFO Bit Fields */
screamer 0:c5e2f793b59a 13315 #define USB_ADDINFO_IEHOST_MASK 0x1u
screamer 0:c5e2f793b59a 13316 #define USB_ADDINFO_IEHOST_SHIFT 0
screamer 0:c5e2f793b59a 13317 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
screamer 0:c5e2f793b59a 13318 #define USB_ADDINFO_IRQNUM_SHIFT 3
screamer 0:c5e2f793b59a 13319 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
screamer 0:c5e2f793b59a 13320 /* OTGISTAT Bit Fields */
screamer 0:c5e2f793b59a 13321 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
screamer 0:c5e2f793b59a 13322 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
screamer 0:c5e2f793b59a 13323 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
screamer 0:c5e2f793b59a 13324 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
screamer 0:c5e2f793b59a 13325 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
screamer 0:c5e2f793b59a 13326 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
screamer 0:c5e2f793b59a 13327 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
screamer 0:c5e2f793b59a 13328 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
screamer 0:c5e2f793b59a 13329 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
screamer 0:c5e2f793b59a 13330 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
screamer 0:c5e2f793b59a 13331 #define USB_OTGISTAT_IDCHG_MASK 0x80u
screamer 0:c5e2f793b59a 13332 #define USB_OTGISTAT_IDCHG_SHIFT 7
screamer 0:c5e2f793b59a 13333 /* OTGICR Bit Fields */
screamer 0:c5e2f793b59a 13334 #define USB_OTGICR_AVBUSEN_MASK 0x1u
screamer 0:c5e2f793b59a 13335 #define USB_OTGICR_AVBUSEN_SHIFT 0
screamer 0:c5e2f793b59a 13336 #define USB_OTGICR_BSESSEN_MASK 0x4u
screamer 0:c5e2f793b59a 13337 #define USB_OTGICR_BSESSEN_SHIFT 2
screamer 0:c5e2f793b59a 13338 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
screamer 0:c5e2f793b59a 13339 #define USB_OTGICR_SESSVLDEN_SHIFT 3
screamer 0:c5e2f793b59a 13340 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
screamer 0:c5e2f793b59a 13341 #define USB_OTGICR_LINESTATEEN_SHIFT 5
screamer 0:c5e2f793b59a 13342 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
screamer 0:c5e2f793b59a 13343 #define USB_OTGICR_ONEMSECEN_SHIFT 6
screamer 0:c5e2f793b59a 13344 #define USB_OTGICR_IDEN_MASK 0x80u
screamer 0:c5e2f793b59a 13345 #define USB_OTGICR_IDEN_SHIFT 7
screamer 0:c5e2f793b59a 13346 /* OTGSTAT Bit Fields */
screamer 0:c5e2f793b59a 13347 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
screamer 0:c5e2f793b59a 13348 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
screamer 0:c5e2f793b59a 13349 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
screamer 0:c5e2f793b59a 13350 #define USB_OTGSTAT_BSESSEND_SHIFT 2
screamer 0:c5e2f793b59a 13351 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
screamer 0:c5e2f793b59a 13352 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
screamer 0:c5e2f793b59a 13353 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
screamer 0:c5e2f793b59a 13354 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
screamer 0:c5e2f793b59a 13355 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
screamer 0:c5e2f793b59a 13356 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
screamer 0:c5e2f793b59a 13357 #define USB_OTGSTAT_ID_MASK 0x80u
screamer 0:c5e2f793b59a 13358 #define USB_OTGSTAT_ID_SHIFT 7
screamer 0:c5e2f793b59a 13359 /* OTGCTL Bit Fields */
screamer 0:c5e2f793b59a 13360 #define USB_OTGCTL_OTGEN_MASK 0x4u
screamer 0:c5e2f793b59a 13361 #define USB_OTGCTL_OTGEN_SHIFT 2
screamer 0:c5e2f793b59a 13362 #define USB_OTGCTL_DMLOW_MASK 0x10u
screamer 0:c5e2f793b59a 13363 #define USB_OTGCTL_DMLOW_SHIFT 4
screamer 0:c5e2f793b59a 13364 #define USB_OTGCTL_DPLOW_MASK 0x20u
screamer 0:c5e2f793b59a 13365 #define USB_OTGCTL_DPLOW_SHIFT 5
screamer 0:c5e2f793b59a 13366 #define USB_OTGCTL_DPHIGH_MASK 0x80u
screamer 0:c5e2f793b59a 13367 #define USB_OTGCTL_DPHIGH_SHIFT 7
screamer 0:c5e2f793b59a 13368 /* ISTAT Bit Fields */
screamer 0:c5e2f793b59a 13369 #define USB_ISTAT_USBRST_MASK 0x1u
screamer 0:c5e2f793b59a 13370 #define USB_ISTAT_USBRST_SHIFT 0
screamer 0:c5e2f793b59a 13371 #define USB_ISTAT_ERROR_MASK 0x2u
screamer 0:c5e2f793b59a 13372 #define USB_ISTAT_ERROR_SHIFT 1
screamer 0:c5e2f793b59a 13373 #define USB_ISTAT_SOFTOK_MASK 0x4u
screamer 0:c5e2f793b59a 13374 #define USB_ISTAT_SOFTOK_SHIFT 2
screamer 0:c5e2f793b59a 13375 #define USB_ISTAT_TOKDNE_MASK 0x8u
screamer 0:c5e2f793b59a 13376 #define USB_ISTAT_TOKDNE_SHIFT 3
screamer 0:c5e2f793b59a 13377 #define USB_ISTAT_SLEEP_MASK 0x10u
screamer 0:c5e2f793b59a 13378 #define USB_ISTAT_SLEEP_SHIFT 4
screamer 0:c5e2f793b59a 13379 #define USB_ISTAT_RESUME_MASK 0x20u
screamer 0:c5e2f793b59a 13380 #define USB_ISTAT_RESUME_SHIFT 5
screamer 0:c5e2f793b59a 13381 #define USB_ISTAT_ATTACH_MASK 0x40u
screamer 0:c5e2f793b59a 13382 #define USB_ISTAT_ATTACH_SHIFT 6
screamer 0:c5e2f793b59a 13383 #define USB_ISTAT_STALL_MASK 0x80u
screamer 0:c5e2f793b59a 13384 #define USB_ISTAT_STALL_SHIFT 7
screamer 0:c5e2f793b59a 13385 /* INTEN Bit Fields */
screamer 0:c5e2f793b59a 13386 #define USB_INTEN_USBRSTEN_MASK 0x1u
screamer 0:c5e2f793b59a 13387 #define USB_INTEN_USBRSTEN_SHIFT 0
screamer 0:c5e2f793b59a 13388 #define USB_INTEN_ERROREN_MASK 0x2u
screamer 0:c5e2f793b59a 13389 #define USB_INTEN_ERROREN_SHIFT 1
screamer 0:c5e2f793b59a 13390 #define USB_INTEN_SOFTOKEN_MASK 0x4u
screamer 0:c5e2f793b59a 13391 #define USB_INTEN_SOFTOKEN_SHIFT 2
screamer 0:c5e2f793b59a 13392 #define USB_INTEN_TOKDNEEN_MASK 0x8u
screamer 0:c5e2f793b59a 13393 #define USB_INTEN_TOKDNEEN_SHIFT 3
screamer 0:c5e2f793b59a 13394 #define USB_INTEN_SLEEPEN_MASK 0x10u
screamer 0:c5e2f793b59a 13395 #define USB_INTEN_SLEEPEN_SHIFT 4
screamer 0:c5e2f793b59a 13396 #define USB_INTEN_RESUMEEN_MASK 0x20u
screamer 0:c5e2f793b59a 13397 #define USB_INTEN_RESUMEEN_SHIFT 5
screamer 0:c5e2f793b59a 13398 #define USB_INTEN_ATTACHEN_MASK 0x40u
screamer 0:c5e2f793b59a 13399 #define USB_INTEN_ATTACHEN_SHIFT 6
screamer 0:c5e2f793b59a 13400 #define USB_INTEN_STALLEN_MASK 0x80u
screamer 0:c5e2f793b59a 13401 #define USB_INTEN_STALLEN_SHIFT 7
screamer 0:c5e2f793b59a 13402 /* ERRSTAT Bit Fields */
screamer 0:c5e2f793b59a 13403 #define USB_ERRSTAT_PIDERR_MASK 0x1u
screamer 0:c5e2f793b59a 13404 #define USB_ERRSTAT_PIDERR_SHIFT 0
screamer 0:c5e2f793b59a 13405 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
screamer 0:c5e2f793b59a 13406 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
screamer 0:c5e2f793b59a 13407 #define USB_ERRSTAT_CRC16_MASK 0x4u
screamer 0:c5e2f793b59a 13408 #define USB_ERRSTAT_CRC16_SHIFT 2
screamer 0:c5e2f793b59a 13409 #define USB_ERRSTAT_DFN8_MASK 0x8u
screamer 0:c5e2f793b59a 13410 #define USB_ERRSTAT_DFN8_SHIFT 3
screamer 0:c5e2f793b59a 13411 #define USB_ERRSTAT_BTOERR_MASK 0x10u
screamer 0:c5e2f793b59a 13412 #define USB_ERRSTAT_BTOERR_SHIFT 4
screamer 0:c5e2f793b59a 13413 #define USB_ERRSTAT_DMAERR_MASK 0x20u
screamer 0:c5e2f793b59a 13414 #define USB_ERRSTAT_DMAERR_SHIFT 5
screamer 0:c5e2f793b59a 13415 #define USB_ERRSTAT_BTSERR_MASK 0x80u
screamer 0:c5e2f793b59a 13416 #define USB_ERRSTAT_BTSERR_SHIFT 7
screamer 0:c5e2f793b59a 13417 /* ERREN Bit Fields */
screamer 0:c5e2f793b59a 13418 #define USB_ERREN_PIDERREN_MASK 0x1u
screamer 0:c5e2f793b59a 13419 #define USB_ERREN_PIDERREN_SHIFT 0
screamer 0:c5e2f793b59a 13420 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
screamer 0:c5e2f793b59a 13421 #define USB_ERREN_CRC5EOFEN_SHIFT 1
screamer 0:c5e2f793b59a 13422 #define USB_ERREN_CRC16EN_MASK 0x4u
screamer 0:c5e2f793b59a 13423 #define USB_ERREN_CRC16EN_SHIFT 2
screamer 0:c5e2f793b59a 13424 #define USB_ERREN_DFN8EN_MASK 0x8u
screamer 0:c5e2f793b59a 13425 #define USB_ERREN_DFN8EN_SHIFT 3
screamer 0:c5e2f793b59a 13426 #define USB_ERREN_BTOERREN_MASK 0x10u
screamer 0:c5e2f793b59a 13427 #define USB_ERREN_BTOERREN_SHIFT 4
screamer 0:c5e2f793b59a 13428 #define USB_ERREN_DMAERREN_MASK 0x20u
screamer 0:c5e2f793b59a 13429 #define USB_ERREN_DMAERREN_SHIFT 5
screamer 0:c5e2f793b59a 13430 #define USB_ERREN_BTSERREN_MASK 0x80u
screamer 0:c5e2f793b59a 13431 #define USB_ERREN_BTSERREN_SHIFT 7
screamer 0:c5e2f793b59a 13432 /* STAT Bit Fields */
screamer 0:c5e2f793b59a 13433 #define USB_STAT_ODD_MASK 0x4u
screamer 0:c5e2f793b59a 13434 #define USB_STAT_ODD_SHIFT 2
screamer 0:c5e2f793b59a 13435 #define USB_STAT_TX_MASK 0x8u
screamer 0:c5e2f793b59a 13436 #define USB_STAT_TX_SHIFT 3
screamer 0:c5e2f793b59a 13437 #define USB_STAT_ENDP_MASK 0xF0u
screamer 0:c5e2f793b59a 13438 #define USB_STAT_ENDP_SHIFT 4
screamer 0:c5e2f793b59a 13439 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
screamer 0:c5e2f793b59a 13440 /* CTL Bit Fields */
screamer 0:c5e2f793b59a 13441 #define USB_CTL_USBENSOFEN_MASK 0x1u
screamer 0:c5e2f793b59a 13442 #define USB_CTL_USBENSOFEN_SHIFT 0
screamer 0:c5e2f793b59a 13443 #define USB_CTL_ODDRST_MASK 0x2u
screamer 0:c5e2f793b59a 13444 #define USB_CTL_ODDRST_SHIFT 1
screamer 0:c5e2f793b59a 13445 #define USB_CTL_RESUME_MASK 0x4u
screamer 0:c5e2f793b59a 13446 #define USB_CTL_RESUME_SHIFT 2
screamer 0:c5e2f793b59a 13447 #define USB_CTL_HOSTMODEEN_MASK 0x8u
screamer 0:c5e2f793b59a 13448 #define USB_CTL_HOSTMODEEN_SHIFT 3
screamer 0:c5e2f793b59a 13449 #define USB_CTL_RESET_MASK 0x10u
screamer 0:c5e2f793b59a 13450 #define USB_CTL_RESET_SHIFT 4
screamer 0:c5e2f793b59a 13451 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
screamer 0:c5e2f793b59a 13452 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
screamer 0:c5e2f793b59a 13453 #define USB_CTL_SE0_MASK 0x40u
screamer 0:c5e2f793b59a 13454 #define USB_CTL_SE0_SHIFT 6
screamer 0:c5e2f793b59a 13455 #define USB_CTL_JSTATE_MASK 0x80u
screamer 0:c5e2f793b59a 13456 #define USB_CTL_JSTATE_SHIFT 7
screamer 0:c5e2f793b59a 13457 /* ADDR Bit Fields */
screamer 0:c5e2f793b59a 13458 #define USB_ADDR_ADDR_MASK 0x7Fu
screamer 0:c5e2f793b59a 13459 #define USB_ADDR_ADDR_SHIFT 0
screamer 0:c5e2f793b59a 13460 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
screamer 0:c5e2f793b59a 13461 #define USB_ADDR_LSEN_MASK 0x80u
screamer 0:c5e2f793b59a 13462 #define USB_ADDR_LSEN_SHIFT 7
screamer 0:c5e2f793b59a 13463 /* BDTPAGE1 Bit Fields */
screamer 0:c5e2f793b59a 13464 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
screamer 0:c5e2f793b59a 13465 #define USB_BDTPAGE1_BDTBA_SHIFT 1
screamer 0:c5e2f793b59a 13466 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
screamer 0:c5e2f793b59a 13467 /* FRMNUML Bit Fields */
screamer 0:c5e2f793b59a 13468 #define USB_FRMNUML_FRM_MASK 0xFFu
screamer 0:c5e2f793b59a 13469 #define USB_FRMNUML_FRM_SHIFT 0
screamer 0:c5e2f793b59a 13470 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
screamer 0:c5e2f793b59a 13471 /* FRMNUMH Bit Fields */
screamer 0:c5e2f793b59a 13472 #define USB_FRMNUMH_FRM_MASK 0x7u
screamer 0:c5e2f793b59a 13473 #define USB_FRMNUMH_FRM_SHIFT 0
screamer 0:c5e2f793b59a 13474 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
screamer 0:c5e2f793b59a 13475 /* TOKEN Bit Fields */
screamer 0:c5e2f793b59a 13476 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
screamer 0:c5e2f793b59a 13477 #define USB_TOKEN_TOKENENDPT_SHIFT 0
screamer 0:c5e2f793b59a 13478 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
screamer 0:c5e2f793b59a 13479 #define USB_TOKEN_TOKENPID_MASK 0xF0u
screamer 0:c5e2f793b59a 13480 #define USB_TOKEN_TOKENPID_SHIFT 4
screamer 0:c5e2f793b59a 13481 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
screamer 0:c5e2f793b59a 13482 /* SOFTHLD Bit Fields */
screamer 0:c5e2f793b59a 13483 #define USB_SOFTHLD_CNT_MASK 0xFFu
screamer 0:c5e2f793b59a 13484 #define USB_SOFTHLD_CNT_SHIFT 0
screamer 0:c5e2f793b59a 13485 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
screamer 0:c5e2f793b59a 13486 /* BDTPAGE2 Bit Fields */
screamer 0:c5e2f793b59a 13487 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
screamer 0:c5e2f793b59a 13488 #define USB_BDTPAGE2_BDTBA_SHIFT 0
screamer 0:c5e2f793b59a 13489 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
screamer 0:c5e2f793b59a 13490 /* BDTPAGE3 Bit Fields */
screamer 0:c5e2f793b59a 13491 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
screamer 0:c5e2f793b59a 13492 #define USB_BDTPAGE3_BDTBA_SHIFT 0
screamer 0:c5e2f793b59a 13493 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
screamer 0:c5e2f793b59a 13494 /* ENDPT Bit Fields */
screamer 0:c5e2f793b59a 13495 #define USB_ENDPT_EPHSHK_MASK 0x1u
screamer 0:c5e2f793b59a 13496 #define USB_ENDPT_EPHSHK_SHIFT 0
screamer 0:c5e2f793b59a 13497 #define USB_ENDPT_EPSTALL_MASK 0x2u
screamer 0:c5e2f793b59a 13498 #define USB_ENDPT_EPSTALL_SHIFT 1
screamer 0:c5e2f793b59a 13499 #define USB_ENDPT_EPTXEN_MASK 0x4u
screamer 0:c5e2f793b59a 13500 #define USB_ENDPT_EPTXEN_SHIFT 2
screamer 0:c5e2f793b59a 13501 #define USB_ENDPT_EPRXEN_MASK 0x8u
screamer 0:c5e2f793b59a 13502 #define USB_ENDPT_EPRXEN_SHIFT 3
screamer 0:c5e2f793b59a 13503 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
screamer 0:c5e2f793b59a 13504 #define USB_ENDPT_EPCTLDIS_SHIFT 4
screamer 0:c5e2f793b59a 13505 #define USB_ENDPT_RETRYDIS_MASK 0x40u
screamer 0:c5e2f793b59a 13506 #define USB_ENDPT_RETRYDIS_SHIFT 6
screamer 0:c5e2f793b59a 13507 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
screamer 0:c5e2f793b59a 13508 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
screamer 0:c5e2f793b59a 13509 /* USBCTRL Bit Fields */
screamer 0:c5e2f793b59a 13510 #define USB_USBCTRL_PDE_MASK 0x40u
screamer 0:c5e2f793b59a 13511 #define USB_USBCTRL_PDE_SHIFT 6
screamer 0:c5e2f793b59a 13512 #define USB_USBCTRL_SUSP_MASK 0x80u
screamer 0:c5e2f793b59a 13513 #define USB_USBCTRL_SUSP_SHIFT 7
screamer 0:c5e2f793b59a 13514 /* OBSERVE Bit Fields */
screamer 0:c5e2f793b59a 13515 #define USB_OBSERVE_DMPD_MASK 0x10u
screamer 0:c5e2f793b59a 13516 #define USB_OBSERVE_DMPD_SHIFT 4
screamer 0:c5e2f793b59a 13517 #define USB_OBSERVE_DPPD_MASK 0x40u
screamer 0:c5e2f793b59a 13518 #define USB_OBSERVE_DPPD_SHIFT 6
screamer 0:c5e2f793b59a 13519 #define USB_OBSERVE_DPPU_MASK 0x80u
screamer 0:c5e2f793b59a 13520 #define USB_OBSERVE_DPPU_SHIFT 7
screamer 0:c5e2f793b59a 13521 /* CONTROL Bit Fields */
screamer 0:c5e2f793b59a 13522 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
screamer 0:c5e2f793b59a 13523 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
screamer 0:c5e2f793b59a 13524 /* USBTRC0 Bit Fields */
screamer 0:c5e2f793b59a 13525 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
screamer 0:c5e2f793b59a 13526 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
screamer 0:c5e2f793b59a 13527 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
screamer 0:c5e2f793b59a 13528 #define USB_USBTRC0_SYNC_DET_SHIFT 1
screamer 0:c5e2f793b59a 13529 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
screamer 0:c5e2f793b59a 13530 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
screamer 0:c5e2f793b59a 13531 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
screamer 0:c5e2f793b59a 13532 #define USB_USBTRC0_USBRESMEN_SHIFT 5
screamer 0:c5e2f793b59a 13533 #define USB_USBTRC0_USBRESET_MASK 0x80u
screamer 0:c5e2f793b59a 13534 #define USB_USBTRC0_USBRESET_SHIFT 7
screamer 0:c5e2f793b59a 13535 /* USBFRMADJUST Bit Fields */
screamer 0:c5e2f793b59a 13536 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
screamer 0:c5e2f793b59a 13537 #define USB_USBFRMADJUST_ADJ_SHIFT 0
screamer 0:c5e2f793b59a 13538 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
screamer 0:c5e2f793b59a 13539 /* CLK_RECOVER_CTRL Bit Fields */
screamer 0:c5e2f793b59a 13540 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
screamer 0:c5e2f793b59a 13541 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
screamer 0:c5e2f793b59a 13542 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
screamer 0:c5e2f793b59a 13543 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
screamer 0:c5e2f793b59a 13544 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
screamer 0:c5e2f793b59a 13545 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
screamer 0:c5e2f793b59a 13546 /* CLK_RECOVER_IRC_EN Bit Fields */
screamer 0:c5e2f793b59a 13547 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
screamer 0:c5e2f793b59a 13548 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
screamer 0:c5e2f793b59a 13549 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
screamer 0:c5e2f793b59a 13550 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
screamer 0:c5e2f793b59a 13551 /* CLK_RECOVER_INT_STATUS Bit Fields */
screamer 0:c5e2f793b59a 13552 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
screamer 0:c5e2f793b59a 13553 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
screamer 0:c5e2f793b59a 13554
screamer 0:c5e2f793b59a 13555 /*!
screamer 0:c5e2f793b59a 13556 * @}
screamer 0:c5e2f793b59a 13557 */ /* end of group USB_Register_Masks */
screamer 0:c5e2f793b59a 13558
screamer 0:c5e2f793b59a 13559
screamer 0:c5e2f793b59a 13560 /* USB - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 13561 /** Peripheral USB0 base address */
screamer 0:c5e2f793b59a 13562 #define USB0_BASE (0x40072000u)
screamer 0:c5e2f793b59a 13563 /** Peripheral USB0 base pointer */
screamer 0:c5e2f793b59a 13564 #define USB0 ((USB_Type *)USB0_BASE)
screamer 0:c5e2f793b59a 13565 #define USB0_BASE_PTR (USB0)
screamer 0:c5e2f793b59a 13566 /** Array initializer of USB peripheral base addresses */
screamer 0:c5e2f793b59a 13567 #define USB_BASE_ADDRS { USB0_BASE }
screamer 0:c5e2f793b59a 13568 /** Array initializer of USB peripheral base pointers */
screamer 0:c5e2f793b59a 13569 #define USB_BASE_PTRS { USB0 }
screamer 0:c5e2f793b59a 13570 /** Interrupt vectors for the USB peripheral type */
screamer 0:c5e2f793b59a 13571 #define USB_IRQS { USB0_IRQn }
screamer 0:c5e2f793b59a 13572
screamer 0:c5e2f793b59a 13573 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13574 -- USB - Register accessor macros
screamer 0:c5e2f793b59a 13575 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13576
screamer 0:c5e2f793b59a 13577 /*!
screamer 0:c5e2f793b59a 13578 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
screamer 0:c5e2f793b59a 13579 * @{
screamer 0:c5e2f793b59a 13580 */
screamer 0:c5e2f793b59a 13581
screamer 0:c5e2f793b59a 13582
screamer 0:c5e2f793b59a 13583 /* USB - Register instance definitions */
screamer 0:c5e2f793b59a 13584 /* USB0 */
screamer 0:c5e2f793b59a 13585 #define USB0_PERID USB_PERID_REG(USB0)
screamer 0:c5e2f793b59a 13586 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
screamer 0:c5e2f793b59a 13587 #define USB0_REV USB_REV_REG(USB0)
screamer 0:c5e2f793b59a 13588 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
screamer 0:c5e2f793b59a 13589 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
screamer 0:c5e2f793b59a 13590 #define USB0_OTGICR USB_OTGICR_REG(USB0)
screamer 0:c5e2f793b59a 13591 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
screamer 0:c5e2f793b59a 13592 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
screamer 0:c5e2f793b59a 13593 #define USB0_ISTAT USB_ISTAT_REG(USB0)
screamer 0:c5e2f793b59a 13594 #define USB0_INTEN USB_INTEN_REG(USB0)
screamer 0:c5e2f793b59a 13595 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
screamer 0:c5e2f793b59a 13596 #define USB0_ERREN USB_ERREN_REG(USB0)
screamer 0:c5e2f793b59a 13597 #define USB0_STAT USB_STAT_REG(USB0)
screamer 0:c5e2f793b59a 13598 #define USB0_CTL USB_CTL_REG(USB0)
screamer 0:c5e2f793b59a 13599 #define USB0_ADDR USB_ADDR_REG(USB0)
screamer 0:c5e2f793b59a 13600 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
screamer 0:c5e2f793b59a 13601 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
screamer 0:c5e2f793b59a 13602 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
screamer 0:c5e2f793b59a 13603 #define USB0_TOKEN USB_TOKEN_REG(USB0)
screamer 0:c5e2f793b59a 13604 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
screamer 0:c5e2f793b59a 13605 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
screamer 0:c5e2f793b59a 13606 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
screamer 0:c5e2f793b59a 13607 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
screamer 0:c5e2f793b59a 13608 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
screamer 0:c5e2f793b59a 13609 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
screamer 0:c5e2f793b59a 13610 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
screamer 0:c5e2f793b59a 13611 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
screamer 0:c5e2f793b59a 13612 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
screamer 0:c5e2f793b59a 13613 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
screamer 0:c5e2f793b59a 13614 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
screamer 0:c5e2f793b59a 13615 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
screamer 0:c5e2f793b59a 13616 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
screamer 0:c5e2f793b59a 13617 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
screamer 0:c5e2f793b59a 13618 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
screamer 0:c5e2f793b59a 13619 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
screamer 0:c5e2f793b59a 13620 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
screamer 0:c5e2f793b59a 13621 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
screamer 0:c5e2f793b59a 13622 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
screamer 0:c5e2f793b59a 13623 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
screamer 0:c5e2f793b59a 13624 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
screamer 0:c5e2f793b59a 13625 #define USB0_CONTROL USB_CONTROL_REG(USB0)
screamer 0:c5e2f793b59a 13626 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
screamer 0:c5e2f793b59a 13627 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
screamer 0:c5e2f793b59a 13628 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
screamer 0:c5e2f793b59a 13629 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
screamer 0:c5e2f793b59a 13630 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
screamer 0:c5e2f793b59a 13631
screamer 0:c5e2f793b59a 13632 /* USB - Register array accessors */
screamer 0:c5e2f793b59a 13633 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
screamer 0:c5e2f793b59a 13634
screamer 0:c5e2f793b59a 13635 /*!
screamer 0:c5e2f793b59a 13636 * @}
screamer 0:c5e2f793b59a 13637 */ /* end of group USB_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 13638
screamer 0:c5e2f793b59a 13639
screamer 0:c5e2f793b59a 13640 /*!
screamer 0:c5e2f793b59a 13641 * @}
screamer 0:c5e2f793b59a 13642 */ /* end of group USB_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 13643
screamer 0:c5e2f793b59a 13644
screamer 0:c5e2f793b59a 13645 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13646 -- USBDCD Peripheral Access Layer
screamer 0:c5e2f793b59a 13647 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13648
screamer 0:c5e2f793b59a 13649 /*!
screamer 0:c5e2f793b59a 13650 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
screamer 0:c5e2f793b59a 13651 * @{
screamer 0:c5e2f793b59a 13652 */
screamer 0:c5e2f793b59a 13653
screamer 0:c5e2f793b59a 13654 /** USBDCD - Register Layout Typedef */
screamer 0:c5e2f793b59a 13655 typedef struct {
screamer 0:c5e2f793b59a 13656 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
screamer 0:c5e2f793b59a 13657 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
screamer 0:c5e2f793b59a 13658 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
screamer 0:c5e2f793b59a 13659 uint8_t RESERVED_0[4];
screamer 0:c5e2f793b59a 13660 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
screamer 0:c5e2f793b59a 13661 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
screamer 0:c5e2f793b59a 13662 union { /* offset: 0x18 */
screamer 0:c5e2f793b59a 13663 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
screamer 0:c5e2f793b59a 13664 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
screamer 0:c5e2f793b59a 13665 };
screamer 0:c5e2f793b59a 13666 } USBDCD_Type, *USBDCD_MemMapPtr;
screamer 0:c5e2f793b59a 13667
screamer 0:c5e2f793b59a 13668 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13669 -- USBDCD - Register accessor macros
screamer 0:c5e2f793b59a 13670 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13671
screamer 0:c5e2f793b59a 13672 /*!
screamer 0:c5e2f793b59a 13673 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
screamer 0:c5e2f793b59a 13674 * @{
screamer 0:c5e2f793b59a 13675 */
screamer 0:c5e2f793b59a 13676
screamer 0:c5e2f793b59a 13677
screamer 0:c5e2f793b59a 13678 /* USBDCD - Register accessors */
screamer 0:c5e2f793b59a 13679 #define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
screamer 0:c5e2f793b59a 13680 #define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
screamer 0:c5e2f793b59a 13681 #define USBDCD_STATUS_REG(base) ((base)->STATUS)
screamer 0:c5e2f793b59a 13682 #define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
screamer 0:c5e2f793b59a 13683 #define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
screamer 0:c5e2f793b59a 13684 #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
screamer 0:c5e2f793b59a 13685 #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
screamer 0:c5e2f793b59a 13686
screamer 0:c5e2f793b59a 13687 /*!
screamer 0:c5e2f793b59a 13688 * @}
screamer 0:c5e2f793b59a 13689 */ /* end of group USBDCD_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 13690
screamer 0:c5e2f793b59a 13691
screamer 0:c5e2f793b59a 13692 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13693 -- USBDCD Register Masks
screamer 0:c5e2f793b59a 13694 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13695
screamer 0:c5e2f793b59a 13696 /*!
screamer 0:c5e2f793b59a 13697 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
screamer 0:c5e2f793b59a 13698 * @{
screamer 0:c5e2f793b59a 13699 */
screamer 0:c5e2f793b59a 13700
screamer 0:c5e2f793b59a 13701 /* CONTROL Bit Fields */
screamer 0:c5e2f793b59a 13702 #define USBDCD_CONTROL_IACK_MASK 0x1u
screamer 0:c5e2f793b59a 13703 #define USBDCD_CONTROL_IACK_SHIFT 0
screamer 0:c5e2f793b59a 13704 #define USBDCD_CONTROL_IF_MASK 0x100u
screamer 0:c5e2f793b59a 13705 #define USBDCD_CONTROL_IF_SHIFT 8
screamer 0:c5e2f793b59a 13706 #define USBDCD_CONTROL_IE_MASK 0x10000u
screamer 0:c5e2f793b59a 13707 #define USBDCD_CONTROL_IE_SHIFT 16
screamer 0:c5e2f793b59a 13708 #define USBDCD_CONTROL_BC12_MASK 0x20000u
screamer 0:c5e2f793b59a 13709 #define USBDCD_CONTROL_BC12_SHIFT 17
screamer 0:c5e2f793b59a 13710 #define USBDCD_CONTROL_START_MASK 0x1000000u
screamer 0:c5e2f793b59a 13711 #define USBDCD_CONTROL_START_SHIFT 24
screamer 0:c5e2f793b59a 13712 #define USBDCD_CONTROL_SR_MASK 0x2000000u
screamer 0:c5e2f793b59a 13713 #define USBDCD_CONTROL_SR_SHIFT 25
screamer 0:c5e2f793b59a 13714 /* CLOCK Bit Fields */
screamer 0:c5e2f793b59a 13715 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
screamer 0:c5e2f793b59a 13716 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
screamer 0:c5e2f793b59a 13717 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
screamer 0:c5e2f793b59a 13718 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
screamer 0:c5e2f793b59a 13719 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
screamer 0:c5e2f793b59a 13720 /* STATUS Bit Fields */
screamer 0:c5e2f793b59a 13721 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
screamer 0:c5e2f793b59a 13722 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
screamer 0:c5e2f793b59a 13723 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
screamer 0:c5e2f793b59a 13724 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
screamer 0:c5e2f793b59a 13725 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
screamer 0:c5e2f793b59a 13726 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
screamer 0:c5e2f793b59a 13727 #define USBDCD_STATUS_ERR_MASK 0x100000u
screamer 0:c5e2f793b59a 13728 #define USBDCD_STATUS_ERR_SHIFT 20
screamer 0:c5e2f793b59a 13729 #define USBDCD_STATUS_TO_MASK 0x200000u
screamer 0:c5e2f793b59a 13730 #define USBDCD_STATUS_TO_SHIFT 21
screamer 0:c5e2f793b59a 13731 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
screamer 0:c5e2f793b59a 13732 #define USBDCD_STATUS_ACTIVE_SHIFT 22
screamer 0:c5e2f793b59a 13733 /* TIMER0 Bit Fields */
screamer 0:c5e2f793b59a 13734 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
screamer 0:c5e2f793b59a 13735 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
screamer 0:c5e2f793b59a 13736 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
screamer 0:c5e2f793b59a 13737 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
screamer 0:c5e2f793b59a 13738 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
screamer 0:c5e2f793b59a 13739 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
screamer 0:c5e2f793b59a 13740 /* TIMER1 Bit Fields */
screamer 0:c5e2f793b59a 13741 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
screamer 0:c5e2f793b59a 13742 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
screamer 0:c5e2f793b59a 13743 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
screamer 0:c5e2f793b59a 13744 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
screamer 0:c5e2f793b59a 13745 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
screamer 0:c5e2f793b59a 13746 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
screamer 0:c5e2f793b59a 13747 /* TIMER2_BC11 Bit Fields */
screamer 0:c5e2f793b59a 13748 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
screamer 0:c5e2f793b59a 13749 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
screamer 0:c5e2f793b59a 13750 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
screamer 0:c5e2f793b59a 13751 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
screamer 0:c5e2f793b59a 13752 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
screamer 0:c5e2f793b59a 13753 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
screamer 0:c5e2f793b59a 13754 /* TIMER2_BC12 Bit Fields */
screamer 0:c5e2f793b59a 13755 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
screamer 0:c5e2f793b59a 13756 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
screamer 0:c5e2f793b59a 13757 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
screamer 0:c5e2f793b59a 13758 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
screamer 0:c5e2f793b59a 13759 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
screamer 0:c5e2f793b59a 13760 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
screamer 0:c5e2f793b59a 13761
screamer 0:c5e2f793b59a 13762 /*!
screamer 0:c5e2f793b59a 13763 * @}
screamer 0:c5e2f793b59a 13764 */ /* end of group USBDCD_Register_Masks */
screamer 0:c5e2f793b59a 13765
screamer 0:c5e2f793b59a 13766
screamer 0:c5e2f793b59a 13767 /* USBDCD - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 13768 /** Peripheral USBDCD base address */
screamer 0:c5e2f793b59a 13769 #define USBDCD_BASE (0x40035000u)
screamer 0:c5e2f793b59a 13770 /** Peripheral USBDCD base pointer */
screamer 0:c5e2f793b59a 13771 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
screamer 0:c5e2f793b59a 13772 #define USBDCD_BASE_PTR (USBDCD)
screamer 0:c5e2f793b59a 13773 /** Array initializer of USBDCD peripheral base addresses */
screamer 0:c5e2f793b59a 13774 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
screamer 0:c5e2f793b59a 13775 /** Array initializer of USBDCD peripheral base pointers */
screamer 0:c5e2f793b59a 13776 #define USBDCD_BASE_PTRS { USBDCD }
screamer 0:c5e2f793b59a 13777 /** Interrupt vectors for the USBDCD peripheral type */
screamer 0:c5e2f793b59a 13778 #define USBDCD_IRQS { USBDCD_IRQn }
screamer 0:c5e2f793b59a 13779
screamer 0:c5e2f793b59a 13780 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13781 -- USBDCD - Register accessor macros
screamer 0:c5e2f793b59a 13782 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13783
screamer 0:c5e2f793b59a 13784 /*!
screamer 0:c5e2f793b59a 13785 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
screamer 0:c5e2f793b59a 13786 * @{
screamer 0:c5e2f793b59a 13787 */
screamer 0:c5e2f793b59a 13788
screamer 0:c5e2f793b59a 13789
screamer 0:c5e2f793b59a 13790 /* USBDCD - Register instance definitions */
screamer 0:c5e2f793b59a 13791 /* USBDCD */
screamer 0:c5e2f793b59a 13792 #define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
screamer 0:c5e2f793b59a 13793 #define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
screamer 0:c5e2f793b59a 13794 #define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
screamer 0:c5e2f793b59a 13795 #define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
screamer 0:c5e2f793b59a 13796 #define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
screamer 0:c5e2f793b59a 13797 #define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
screamer 0:c5e2f793b59a 13798 #define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
screamer 0:c5e2f793b59a 13799
screamer 0:c5e2f793b59a 13800 /*!
screamer 0:c5e2f793b59a 13801 * @}
screamer 0:c5e2f793b59a 13802 */ /* end of group USBDCD_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 13803
screamer 0:c5e2f793b59a 13804
screamer 0:c5e2f793b59a 13805 /*!
screamer 0:c5e2f793b59a 13806 * @}
screamer 0:c5e2f793b59a 13807 */ /* end of group USBDCD_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 13808
screamer 0:c5e2f793b59a 13809
screamer 0:c5e2f793b59a 13810 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13811 -- VREF Peripheral Access Layer
screamer 0:c5e2f793b59a 13812 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13813
screamer 0:c5e2f793b59a 13814 /*!
screamer 0:c5e2f793b59a 13815 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
screamer 0:c5e2f793b59a 13816 * @{
screamer 0:c5e2f793b59a 13817 */
screamer 0:c5e2f793b59a 13818
screamer 0:c5e2f793b59a 13819 /** VREF - Register Layout Typedef */
screamer 0:c5e2f793b59a 13820 typedef struct {
screamer 0:c5e2f793b59a 13821 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
screamer 0:c5e2f793b59a 13822 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
screamer 0:c5e2f793b59a 13823 } VREF_Type, *VREF_MemMapPtr;
screamer 0:c5e2f793b59a 13824
screamer 0:c5e2f793b59a 13825 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13826 -- VREF - Register accessor macros
screamer 0:c5e2f793b59a 13827 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13828
screamer 0:c5e2f793b59a 13829 /*!
screamer 0:c5e2f793b59a 13830 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
screamer 0:c5e2f793b59a 13831 * @{
screamer 0:c5e2f793b59a 13832 */
screamer 0:c5e2f793b59a 13833
screamer 0:c5e2f793b59a 13834
screamer 0:c5e2f793b59a 13835 /* VREF - Register accessors */
screamer 0:c5e2f793b59a 13836 #define VREF_TRM_REG(base) ((base)->TRM)
screamer 0:c5e2f793b59a 13837 #define VREF_SC_REG(base) ((base)->SC)
screamer 0:c5e2f793b59a 13838
screamer 0:c5e2f793b59a 13839 /*!
screamer 0:c5e2f793b59a 13840 * @}
screamer 0:c5e2f793b59a 13841 */ /* end of group VREF_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 13842
screamer 0:c5e2f793b59a 13843
screamer 0:c5e2f793b59a 13844 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13845 -- VREF Register Masks
screamer 0:c5e2f793b59a 13846 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13847
screamer 0:c5e2f793b59a 13848 /*!
screamer 0:c5e2f793b59a 13849 * @addtogroup VREF_Register_Masks VREF Register Masks
screamer 0:c5e2f793b59a 13850 * @{
screamer 0:c5e2f793b59a 13851 */
screamer 0:c5e2f793b59a 13852
screamer 0:c5e2f793b59a 13853 /* TRM Bit Fields */
screamer 0:c5e2f793b59a 13854 #define VREF_TRM_TRIM_MASK 0x3Fu
screamer 0:c5e2f793b59a 13855 #define VREF_TRM_TRIM_SHIFT 0
screamer 0:c5e2f793b59a 13856 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
screamer 0:c5e2f793b59a 13857 #define VREF_TRM_CHOPEN_MASK 0x40u
screamer 0:c5e2f793b59a 13858 #define VREF_TRM_CHOPEN_SHIFT 6
screamer 0:c5e2f793b59a 13859 /* SC Bit Fields */
screamer 0:c5e2f793b59a 13860 #define VREF_SC_MODE_LV_MASK 0x3u
screamer 0:c5e2f793b59a 13861 #define VREF_SC_MODE_LV_SHIFT 0
screamer 0:c5e2f793b59a 13862 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
screamer 0:c5e2f793b59a 13863 #define VREF_SC_VREFST_MASK 0x4u
screamer 0:c5e2f793b59a 13864 #define VREF_SC_VREFST_SHIFT 2
screamer 0:c5e2f793b59a 13865 #define VREF_SC_ICOMPEN_MASK 0x20u
screamer 0:c5e2f793b59a 13866 #define VREF_SC_ICOMPEN_SHIFT 5
screamer 0:c5e2f793b59a 13867 #define VREF_SC_REGEN_MASK 0x40u
screamer 0:c5e2f793b59a 13868 #define VREF_SC_REGEN_SHIFT 6
screamer 0:c5e2f793b59a 13869 #define VREF_SC_VREFEN_MASK 0x80u
screamer 0:c5e2f793b59a 13870 #define VREF_SC_VREFEN_SHIFT 7
screamer 0:c5e2f793b59a 13871
screamer 0:c5e2f793b59a 13872 /*!
screamer 0:c5e2f793b59a 13873 * @}
screamer 0:c5e2f793b59a 13874 */ /* end of group VREF_Register_Masks */
screamer 0:c5e2f793b59a 13875
screamer 0:c5e2f793b59a 13876
screamer 0:c5e2f793b59a 13877 /* VREF - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 13878 /** Peripheral VREF base address */
screamer 0:c5e2f793b59a 13879 #define VREF_BASE (0x40074000u)
screamer 0:c5e2f793b59a 13880 /** Peripheral VREF base pointer */
screamer 0:c5e2f793b59a 13881 #define VREF ((VREF_Type *)VREF_BASE)
screamer 0:c5e2f793b59a 13882 #define VREF_BASE_PTR (VREF)
screamer 0:c5e2f793b59a 13883 /** Array initializer of VREF peripheral base addresses */
screamer 0:c5e2f793b59a 13884 #define VREF_BASE_ADDRS { VREF_BASE }
screamer 0:c5e2f793b59a 13885 /** Array initializer of VREF peripheral base pointers */
screamer 0:c5e2f793b59a 13886 #define VREF_BASE_PTRS { VREF }
screamer 0:c5e2f793b59a 13887
screamer 0:c5e2f793b59a 13888 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13889 -- VREF - Register accessor macros
screamer 0:c5e2f793b59a 13890 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13891
screamer 0:c5e2f793b59a 13892 /*!
screamer 0:c5e2f793b59a 13893 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
screamer 0:c5e2f793b59a 13894 * @{
screamer 0:c5e2f793b59a 13895 */
screamer 0:c5e2f793b59a 13896
screamer 0:c5e2f793b59a 13897
screamer 0:c5e2f793b59a 13898 /* VREF - Register instance definitions */
screamer 0:c5e2f793b59a 13899 /* VREF */
screamer 0:c5e2f793b59a 13900 #define VREF_TRM VREF_TRM_REG(VREF)
screamer 0:c5e2f793b59a 13901 #define VREF_SC VREF_SC_REG(VREF)
screamer 0:c5e2f793b59a 13902
screamer 0:c5e2f793b59a 13903 /*!
screamer 0:c5e2f793b59a 13904 * @}
screamer 0:c5e2f793b59a 13905 */ /* end of group VREF_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 13906
screamer 0:c5e2f793b59a 13907
screamer 0:c5e2f793b59a 13908 /*!
screamer 0:c5e2f793b59a 13909 * @}
screamer 0:c5e2f793b59a 13910 */ /* end of group VREF_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 13911
screamer 0:c5e2f793b59a 13912
screamer 0:c5e2f793b59a 13913 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13914 -- WDOG Peripheral Access Layer
screamer 0:c5e2f793b59a 13915 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13916
screamer 0:c5e2f793b59a 13917 /*!
screamer 0:c5e2f793b59a 13918 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
screamer 0:c5e2f793b59a 13919 * @{
screamer 0:c5e2f793b59a 13920 */
screamer 0:c5e2f793b59a 13921
screamer 0:c5e2f793b59a 13922 /** WDOG - Register Layout Typedef */
screamer 0:c5e2f793b59a 13923 typedef struct {
screamer 0:c5e2f793b59a 13924 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
screamer 0:c5e2f793b59a 13925 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
screamer 0:c5e2f793b59a 13926 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
screamer 0:c5e2f793b59a 13927 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
screamer 0:c5e2f793b59a 13928 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
screamer 0:c5e2f793b59a 13929 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
screamer 0:c5e2f793b59a 13930 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
screamer 0:c5e2f793b59a 13931 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
screamer 0:c5e2f793b59a 13932 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
screamer 0:c5e2f793b59a 13933 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
screamer 0:c5e2f793b59a 13934 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
screamer 0:c5e2f793b59a 13935 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
screamer 0:c5e2f793b59a 13936 } WDOG_Type, *WDOG_MemMapPtr;
screamer 0:c5e2f793b59a 13937
screamer 0:c5e2f793b59a 13938 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13939 -- WDOG - Register accessor macros
screamer 0:c5e2f793b59a 13940 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13941
screamer 0:c5e2f793b59a 13942 /*!
screamer 0:c5e2f793b59a 13943 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
screamer 0:c5e2f793b59a 13944 * @{
screamer 0:c5e2f793b59a 13945 */
screamer 0:c5e2f793b59a 13946
screamer 0:c5e2f793b59a 13947
screamer 0:c5e2f793b59a 13948 /* WDOG - Register accessors */
screamer 0:c5e2f793b59a 13949 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
screamer 0:c5e2f793b59a 13950 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
screamer 0:c5e2f793b59a 13951 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
screamer 0:c5e2f793b59a 13952 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
screamer 0:c5e2f793b59a 13953 #define WDOG_WINH_REG(base) ((base)->WINH)
screamer 0:c5e2f793b59a 13954 #define WDOG_WINL_REG(base) ((base)->WINL)
screamer 0:c5e2f793b59a 13955 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
screamer 0:c5e2f793b59a 13956 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
screamer 0:c5e2f793b59a 13957 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
screamer 0:c5e2f793b59a 13958 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
screamer 0:c5e2f793b59a 13959 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
screamer 0:c5e2f793b59a 13960 #define WDOG_PRESC_REG(base) ((base)->PRESC)
screamer 0:c5e2f793b59a 13961
screamer 0:c5e2f793b59a 13962 /*!
screamer 0:c5e2f793b59a 13963 * @}
screamer 0:c5e2f793b59a 13964 */ /* end of group WDOG_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 13965
screamer 0:c5e2f793b59a 13966
screamer 0:c5e2f793b59a 13967 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 13968 -- WDOG Register Masks
screamer 0:c5e2f793b59a 13969 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 13970
screamer 0:c5e2f793b59a 13971 /*!
screamer 0:c5e2f793b59a 13972 * @addtogroup WDOG_Register_Masks WDOG Register Masks
screamer 0:c5e2f793b59a 13973 * @{
screamer 0:c5e2f793b59a 13974 */
screamer 0:c5e2f793b59a 13975
screamer 0:c5e2f793b59a 13976 /* STCTRLH Bit Fields */
screamer 0:c5e2f793b59a 13977 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
screamer 0:c5e2f793b59a 13978 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
screamer 0:c5e2f793b59a 13979 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
screamer 0:c5e2f793b59a 13980 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
screamer 0:c5e2f793b59a 13981 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
screamer 0:c5e2f793b59a 13982 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
screamer 0:c5e2f793b59a 13983 #define WDOG_STCTRLH_WINEN_MASK 0x8u
screamer 0:c5e2f793b59a 13984 #define WDOG_STCTRLH_WINEN_SHIFT 3
screamer 0:c5e2f793b59a 13985 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
screamer 0:c5e2f793b59a 13986 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
screamer 0:c5e2f793b59a 13987 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
screamer 0:c5e2f793b59a 13988 #define WDOG_STCTRLH_DBGEN_SHIFT 5
screamer 0:c5e2f793b59a 13989 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
screamer 0:c5e2f793b59a 13990 #define WDOG_STCTRLH_STOPEN_SHIFT 6
screamer 0:c5e2f793b59a 13991 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
screamer 0:c5e2f793b59a 13992 #define WDOG_STCTRLH_WAITEN_SHIFT 7
screamer 0:c5e2f793b59a 13993 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
screamer 0:c5e2f793b59a 13994 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
screamer 0:c5e2f793b59a 13995 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
screamer 0:c5e2f793b59a 13996 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
screamer 0:c5e2f793b59a 13997 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
screamer 0:c5e2f793b59a 13998 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
screamer 0:c5e2f793b59a 13999 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
screamer 0:c5e2f793b59a 14000 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
screamer 0:c5e2f793b59a 14001 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
screamer 0:c5e2f793b59a 14002 /* STCTRLL Bit Fields */
screamer 0:c5e2f793b59a 14003 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
screamer 0:c5e2f793b59a 14004 #define WDOG_STCTRLL_INTFLG_SHIFT 15
screamer 0:c5e2f793b59a 14005 /* TOVALH Bit Fields */
screamer 0:c5e2f793b59a 14006 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14007 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
screamer 0:c5e2f793b59a 14008 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
screamer 0:c5e2f793b59a 14009 /* TOVALL Bit Fields */
screamer 0:c5e2f793b59a 14010 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14011 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
screamer 0:c5e2f793b59a 14012 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
screamer 0:c5e2f793b59a 14013 /* WINH Bit Fields */
screamer 0:c5e2f793b59a 14014 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14015 #define WDOG_WINH_WINHIGH_SHIFT 0
screamer 0:c5e2f793b59a 14016 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
screamer 0:c5e2f793b59a 14017 /* WINL Bit Fields */
screamer 0:c5e2f793b59a 14018 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14019 #define WDOG_WINL_WINLOW_SHIFT 0
screamer 0:c5e2f793b59a 14020 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
screamer 0:c5e2f793b59a 14021 /* REFRESH Bit Fields */
screamer 0:c5e2f793b59a 14022 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14023 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
screamer 0:c5e2f793b59a 14024 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
screamer 0:c5e2f793b59a 14025 /* UNLOCK Bit Fields */
screamer 0:c5e2f793b59a 14026 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14027 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
screamer 0:c5e2f793b59a 14028 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
screamer 0:c5e2f793b59a 14029 /* TMROUTH Bit Fields */
screamer 0:c5e2f793b59a 14030 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14031 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
screamer 0:c5e2f793b59a 14032 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
screamer 0:c5e2f793b59a 14033 /* TMROUTL Bit Fields */
screamer 0:c5e2f793b59a 14034 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14035 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
screamer 0:c5e2f793b59a 14036 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
screamer 0:c5e2f793b59a 14037 /* RSTCNT Bit Fields */
screamer 0:c5e2f793b59a 14038 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
screamer 0:c5e2f793b59a 14039 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
screamer 0:c5e2f793b59a 14040 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
screamer 0:c5e2f793b59a 14041 /* PRESC Bit Fields */
screamer 0:c5e2f793b59a 14042 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
screamer 0:c5e2f793b59a 14043 #define WDOG_PRESC_PRESCVAL_SHIFT 8
screamer 0:c5e2f793b59a 14044 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
screamer 0:c5e2f793b59a 14045
screamer 0:c5e2f793b59a 14046 /*!
screamer 0:c5e2f793b59a 14047 * @}
screamer 0:c5e2f793b59a 14048 */ /* end of group WDOG_Register_Masks */
screamer 0:c5e2f793b59a 14049
screamer 0:c5e2f793b59a 14050
screamer 0:c5e2f793b59a 14051 /* WDOG - Peripheral instance base addresses */
screamer 0:c5e2f793b59a 14052 /** Peripheral WDOG base address */
screamer 0:c5e2f793b59a 14053 #define WDOG_BASE (0x40052000u)
screamer 0:c5e2f793b59a 14054 /** Peripheral WDOG base pointer */
screamer 0:c5e2f793b59a 14055 #define WDOG ((WDOG_Type *)WDOG_BASE)
screamer 0:c5e2f793b59a 14056 #define WDOG_BASE_PTR (WDOG)
screamer 0:c5e2f793b59a 14057 /** Array initializer of WDOG peripheral base addresses */
screamer 0:c5e2f793b59a 14058 #define WDOG_BASE_ADDRS { WDOG_BASE }
screamer 0:c5e2f793b59a 14059 /** Array initializer of WDOG peripheral base pointers */
screamer 0:c5e2f793b59a 14060 #define WDOG_BASE_PTRS { WDOG }
screamer 0:c5e2f793b59a 14061 /** Interrupt vectors for the WDOG peripheral type */
screamer 0:c5e2f793b59a 14062 #define WDOG_IRQS { Watchdog_IRQn }
screamer 0:c5e2f793b59a 14063
screamer 0:c5e2f793b59a 14064 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 14065 -- WDOG - Register accessor macros
screamer 0:c5e2f793b59a 14066 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 14067
screamer 0:c5e2f793b59a 14068 /*!
screamer 0:c5e2f793b59a 14069 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
screamer 0:c5e2f793b59a 14070 * @{
screamer 0:c5e2f793b59a 14071 */
screamer 0:c5e2f793b59a 14072
screamer 0:c5e2f793b59a 14073
screamer 0:c5e2f793b59a 14074 /* WDOG - Register instance definitions */
screamer 0:c5e2f793b59a 14075 /* WDOG */
screamer 0:c5e2f793b59a 14076 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
screamer 0:c5e2f793b59a 14077 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
screamer 0:c5e2f793b59a 14078 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
screamer 0:c5e2f793b59a 14079 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
screamer 0:c5e2f793b59a 14080 #define WDOG_WINH WDOG_WINH_REG(WDOG)
screamer 0:c5e2f793b59a 14081 #define WDOG_WINL WDOG_WINL_REG(WDOG)
screamer 0:c5e2f793b59a 14082 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
screamer 0:c5e2f793b59a 14083 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
screamer 0:c5e2f793b59a 14084 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
screamer 0:c5e2f793b59a 14085 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
screamer 0:c5e2f793b59a 14086 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
screamer 0:c5e2f793b59a 14087 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
screamer 0:c5e2f793b59a 14088
screamer 0:c5e2f793b59a 14089 /*!
screamer 0:c5e2f793b59a 14090 * @}
screamer 0:c5e2f793b59a 14091 */ /* end of group WDOG_Register_Accessor_Macros */
screamer 0:c5e2f793b59a 14092
screamer 0:c5e2f793b59a 14093
screamer 0:c5e2f793b59a 14094 /*!
screamer 0:c5e2f793b59a 14095 * @}
screamer 0:c5e2f793b59a 14096 */ /* end of group WDOG_Peripheral_Access_Layer */
screamer 0:c5e2f793b59a 14097
screamer 0:c5e2f793b59a 14098
screamer 0:c5e2f793b59a 14099 /*
screamer 0:c5e2f793b59a 14100 ** End of section using anonymous unions
screamer 0:c5e2f793b59a 14101 */
screamer 0:c5e2f793b59a 14102
screamer 0:c5e2f793b59a 14103 #if defined(__ARMCC_VERSION)
screamer 0:c5e2f793b59a 14104 #pragma pop
screamer 0:c5e2f793b59a 14105 #elif defined(__CWCC__)
screamer 0:c5e2f793b59a 14106 #pragma pop
screamer 0:c5e2f793b59a 14107 #elif defined(__GNUC__)
screamer 0:c5e2f793b59a 14108 /* leave anonymous unions enabled */
screamer 0:c5e2f793b59a 14109 #elif defined(__IAR_SYSTEMS_ICC__)
screamer 0:c5e2f793b59a 14110 #pragma language=default
screamer 0:c5e2f793b59a 14111 #else
screamer 0:c5e2f793b59a 14112 #error Not supported compiler type
screamer 0:c5e2f793b59a 14113 #endif
screamer 0:c5e2f793b59a 14114
screamer 0:c5e2f793b59a 14115 /*!
screamer 0:c5e2f793b59a 14116 * @}
screamer 0:c5e2f793b59a 14117 */ /* end of group Peripheral_access_layer */
screamer 0:c5e2f793b59a 14118
screamer 0:c5e2f793b59a 14119
screamer 0:c5e2f793b59a 14120 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 14121 -- Backward Compatibility
screamer 0:c5e2f793b59a 14122 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 14123
screamer 0:c5e2f793b59a 14124 /*!
screamer 0:c5e2f793b59a 14125 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
screamer 0:c5e2f793b59a 14126 * @{
screamer 0:c5e2f793b59a 14127 */
screamer 0:c5e2f793b59a 14128
screamer 0:c5e2f793b59a 14129 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14130 #define DMA_EARS This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14131 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14132 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14133 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14134 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14135 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14136 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14137 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14138 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14139 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14140 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14141 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14142 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14143 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14144 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14145 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14146 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14147 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14148 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14149 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14150 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14151 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14152 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14153 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14154 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14155 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14156 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14157 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14158 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14159 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14160 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14161 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14162 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14163 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14164 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14165 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14166 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14167 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
screamer 0:c5e2f793b59a 14168 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
screamer 0:c5e2f793b59a 14169 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14170 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14171 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14172 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14173 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14174 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
screamer 0:c5e2f793b59a 14175 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
screamer 0:c5e2f793b59a 14176 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
screamer 0:c5e2f793b59a 14177 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
screamer 0:c5e2f793b59a 14178 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
screamer 0:c5e2f793b59a 14179 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
screamer 0:c5e2f793b59a 14180 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
screamer 0:c5e2f793b59a 14181 #define MCG_C9 This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14182 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14183 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14184 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14185 #define MCM_PLACR This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14186 #define ADC_BASES ADC_BASE_PTRS
screamer 0:c5e2f793b59a 14187 #define AIPS_BASES AIPS_BASE_PTRS
screamer 0:c5e2f793b59a 14188 #define AXBS_BASES AXBS_BASE_PTRS
screamer 0:c5e2f793b59a 14189 #define CAN_BASES CAN_BASE_PTRS
screamer 0:c5e2f793b59a 14190 #define CAU_BASES CAU_BASE_PTRS
screamer 0:c5e2f793b59a 14191 #define CMP_BASES CMP_BASE_PTRS
screamer 0:c5e2f793b59a 14192 #define CMT_BASES CMT_BASE_PTRS
screamer 0:c5e2f793b59a 14193 #define CRC_BASES CRC_BASE_PTRS
screamer 0:c5e2f793b59a 14194 #define DAC_BASES DAC_BASE_PTRS
screamer 0:c5e2f793b59a 14195 #define DMA_BASES DMA_BASE_PTRS
screamer 0:c5e2f793b59a 14196 #define DMAMUX_BASES DMAMUX_BASE_PTRS
screamer 0:c5e2f793b59a 14197 #define ENET_BASES ENET_BASE_PTRS
screamer 0:c5e2f793b59a 14198 #define EWM_BASES EWM_BASE_PTRS
screamer 0:c5e2f793b59a 14199 #define FB_BASES FB_BASE_PTRS
screamer 0:c5e2f793b59a 14200 #define FMC_BASES FMC_BASE_PTRS
screamer 0:c5e2f793b59a 14201 #define FTFE_BASES FTFE_BASE_PTRS
screamer 0:c5e2f793b59a 14202 #define FTM_BASES FTM_BASE_PTRS
screamer 0:c5e2f793b59a 14203 #define GPIO_BASES GPIO_BASE_PTRS
screamer 0:c5e2f793b59a 14204 #define I2C_BASES I2C_BASE_PTRS
screamer 0:c5e2f793b59a 14205 #define I2S_BASES I2S_BASE_PTRS
screamer 0:c5e2f793b59a 14206 #define LLWU_BASES LLWU_BASE_PTRS
screamer 0:c5e2f793b59a 14207 #define LPTMR_BASES LPTMR_BASE_PTRS
screamer 0:c5e2f793b59a 14208 #define MCG_BASES MCG_BASE_PTRS
screamer 0:c5e2f793b59a 14209 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
screamer 0:c5e2f793b59a 14210 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
screamer 0:c5e2f793b59a 14211 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
screamer 0:c5e2f793b59a 14212 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
screamer 0:c5e2f793b59a 14213 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
screamer 0:c5e2f793b59a 14214 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
screamer 0:c5e2f793b59a 14215 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
screamer 0:c5e2f793b59a 14216 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
screamer 0:c5e2f793b59a 14217 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
screamer 0:c5e2f793b59a 14218 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
screamer 0:c5e2f793b59a 14219 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
screamer 0:c5e2f793b59a 14220 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
screamer 0:c5e2f793b59a 14221 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
screamer 0:c5e2f793b59a 14222 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
screamer 0:c5e2f793b59a 14223 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
screamer 0:c5e2f793b59a 14224 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
screamer 0:c5e2f793b59a 14225 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
screamer 0:c5e2f793b59a 14226 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
screamer 0:c5e2f793b59a 14227 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
screamer 0:c5e2f793b59a 14228 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
screamer 0:c5e2f793b59a 14229 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
screamer 0:c5e2f793b59a 14230 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
screamer 0:c5e2f793b59a 14231 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
screamer 0:c5e2f793b59a 14232 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
screamer 0:c5e2f793b59a 14233 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
screamer 0:c5e2f793b59a 14234 #define MCM_BASES MCM_BASE_PTRS
screamer 0:c5e2f793b59a 14235 #define MPU_BASES MPU_BASE_PTRS
screamer 0:c5e2f793b59a 14236 #define NV_BASES NV_BASE_PTRS
screamer 0:c5e2f793b59a 14237 #define OSC_BASES OSC_BASE_PTRS
screamer 0:c5e2f793b59a 14238 #define PDB_BASES PDB_BASE_PTRS
screamer 0:c5e2f793b59a 14239 #define PIT_BASES PIT_BASE_PTRS
screamer 0:c5e2f793b59a 14240 #define PMC_BASES PMC_BASE_PTRS
screamer 0:c5e2f793b59a 14241 #define PORT_BASES PORT_BASE_PTRS
screamer 0:c5e2f793b59a 14242 #define RCM_BASES RCM_BASE_PTRS
screamer 0:c5e2f793b59a 14243 #define RFSYS_BASES RFSYS_BASE_PTRS
screamer 0:c5e2f793b59a 14244 #define RFVBAT_BASES RFVBAT_BASE_PTRS
screamer 0:c5e2f793b59a 14245 #define RNG_BASES RNG_BASE_PTRS
screamer 0:c5e2f793b59a 14246 #define RTC_BASES RTC_BASE_PTRS
screamer 0:c5e2f793b59a 14247 #define SDHC_BASES SDHC_BASE_PTRS
screamer 0:c5e2f793b59a 14248 #define SIM_BASES SIM_BASE_PTRS
screamer 0:c5e2f793b59a 14249 #define SMC_BASES SMC_BASE_PTRS
screamer 0:c5e2f793b59a 14250 #define SPI_BASES SPI_BASE_PTRS
screamer 0:c5e2f793b59a 14251 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
screamer 0:c5e2f793b59a 14252 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
screamer 0:c5e2f793b59a 14253 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
screamer 0:c5e2f793b59a 14254 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
screamer 0:c5e2f793b59a 14255 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
screamer 0:c5e2f793b59a 14256 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
screamer 0:c5e2f793b59a 14257 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
screamer 0:c5e2f793b59a 14258 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
screamer 0:c5e2f793b59a 14259 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
screamer 0:c5e2f793b59a 14260 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
screamer 0:c5e2f793b59a 14261 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
screamer 0:c5e2f793b59a 14262 #define UART_BASES UART_BASE_PTRS
screamer 0:c5e2f793b59a 14263 #define USB_BASES USB_BASE_PTRS
screamer 0:c5e2f793b59a 14264 #define USBDCD_BASES USBDCD_BASE_PTRS
screamer 0:c5e2f793b59a 14265 #define VREF_BASES VREF_BASE_PTRS
screamer 0:c5e2f793b59a 14266 #define WDOG_BASES WDOG_BASE_PTRS
screamer 0:c5e2f793b59a 14267 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14268 #define DMA_EARS This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14269 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14270 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14271 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14272 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14273 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14274 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14275 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14276 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14277 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14278 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14279 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14280 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14281 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14282 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14283 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14284 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14285 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14286 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14287 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14288 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14289 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14290 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14291 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14292 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14293 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14294 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14295 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14296 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14297 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14298 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14299 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14300 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14301 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14302 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14303 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14304 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14305 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
screamer 0:c5e2f793b59a 14306 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
screamer 0:c5e2f793b59a 14307 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14308 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14309 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14310 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14311 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14312 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
screamer 0:c5e2f793b59a 14313 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
screamer 0:c5e2f793b59a 14314 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
screamer 0:c5e2f793b59a 14315 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
screamer 0:c5e2f793b59a 14316 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
screamer 0:c5e2f793b59a 14317 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
screamer 0:c5e2f793b59a 14318 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
screamer 0:c5e2f793b59a 14319 #define MCG_C9 This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14320 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14321 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14322 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14323 #define MCM_PLACR This_symbol_has_been_deprecated
screamer 0:c5e2f793b59a 14324 #define ADC_BASES ADC_BASE_PTRS
screamer 0:c5e2f793b59a 14325 #define AIPS_BASES AIPS_BASE_PTRS
screamer 0:c5e2f793b59a 14326 #define AXBS_BASES AXBS_BASE_PTRS
screamer 0:c5e2f793b59a 14327 #define CAN_BASES CAN_BASE_PTRS
screamer 0:c5e2f793b59a 14328 #define CAU_BASES CAU_BASE_PTRS
screamer 0:c5e2f793b59a 14329 #define CMP_BASES CMP_BASE_PTRS
screamer 0:c5e2f793b59a 14330 #define CMT_BASES CMT_BASE_PTRS
screamer 0:c5e2f793b59a 14331 #define CRC_BASES CRC_BASE_PTRS
screamer 0:c5e2f793b59a 14332 #define DAC_BASES DAC_BASE_PTRS
screamer 0:c5e2f793b59a 14333 #define DMA_BASES DMA_BASE_PTRS
screamer 0:c5e2f793b59a 14334 #define DMAMUX_BASES DMAMUX_BASE_PTRS
screamer 0:c5e2f793b59a 14335 #define ENET_BASES ENET_BASE_PTRS
screamer 0:c5e2f793b59a 14336 #define EWM_BASES EWM_BASE_PTRS
screamer 0:c5e2f793b59a 14337 #define FB_BASES FB_BASE_PTRS
screamer 0:c5e2f793b59a 14338 #define FMC_BASES FMC_BASE_PTRS
screamer 0:c5e2f793b59a 14339 #define FTFE_BASES FTFE_BASE_PTRS
screamer 0:c5e2f793b59a 14340 #define FTM_BASES FTM_BASE_PTRS
screamer 0:c5e2f793b59a 14341 #define GPIO_BASES GPIO_BASE_PTRS
screamer 0:c5e2f793b59a 14342 #define I2C_BASES I2C_BASE_PTRS
screamer 0:c5e2f793b59a 14343 #define I2S_BASES I2S_BASE_PTRS
screamer 0:c5e2f793b59a 14344 #define LLWU_BASES LLWU_BASE_PTRS
screamer 0:c5e2f793b59a 14345 #define LPTMR_BASES LPTMR_BASE_PTRS
screamer 0:c5e2f793b59a 14346 #define MCG_BASES MCG_BASE_PTRS
screamer 0:c5e2f793b59a 14347 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
screamer 0:c5e2f793b59a 14348 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
screamer 0:c5e2f793b59a 14349 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
screamer 0:c5e2f793b59a 14350 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
screamer 0:c5e2f793b59a 14351 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
screamer 0:c5e2f793b59a 14352 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
screamer 0:c5e2f793b59a 14353 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
screamer 0:c5e2f793b59a 14354 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
screamer 0:c5e2f793b59a 14355 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
screamer 0:c5e2f793b59a 14356 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
screamer 0:c5e2f793b59a 14357 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
screamer 0:c5e2f793b59a 14358 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
screamer 0:c5e2f793b59a 14359 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
screamer 0:c5e2f793b59a 14360 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
screamer 0:c5e2f793b59a 14361 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
screamer 0:c5e2f793b59a 14362 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
screamer 0:c5e2f793b59a 14363 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
screamer 0:c5e2f793b59a 14364 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
screamer 0:c5e2f793b59a 14365 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
screamer 0:c5e2f793b59a 14366 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
screamer 0:c5e2f793b59a 14367 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
screamer 0:c5e2f793b59a 14368 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
screamer 0:c5e2f793b59a 14369 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
screamer 0:c5e2f793b59a 14370 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
screamer 0:c5e2f793b59a 14371 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
screamer 0:c5e2f793b59a 14372 #define MCM_BASES MCM_BASE_PTRS
screamer 0:c5e2f793b59a 14373 #define MPU_BASES MPU_BASE_PTRS
screamer 0:c5e2f793b59a 14374 #define NV_BASES NV_BASE_PTRS
screamer 0:c5e2f793b59a 14375 #define OSC_BASES OSC_BASE_PTRS
screamer 0:c5e2f793b59a 14376 #define PDB_BASES PDB_BASE_PTRS
screamer 0:c5e2f793b59a 14377 #define PIT_BASES PIT_BASE_PTRS
screamer 0:c5e2f793b59a 14378 #define PMC_BASES PMC_BASE_PTRS
screamer 0:c5e2f793b59a 14379 #define PORT_BASES PORT_BASE_PTRS
screamer 0:c5e2f793b59a 14380 #define RCM_BASES RCM_BASE_PTRS
screamer 0:c5e2f793b59a 14381 #define RFSYS_BASES RFSYS_BASE_PTRS
screamer 0:c5e2f793b59a 14382 #define RFVBAT_BASES RFVBAT_BASE_PTRS
screamer 0:c5e2f793b59a 14383 #define RNG_BASES RNG_BASE_PTRS
screamer 0:c5e2f793b59a 14384 #define RTC_BASES RTC_BASE_PTRS
screamer 0:c5e2f793b59a 14385 #define SDHC_BASES SDHC_BASE_PTRS
screamer 0:c5e2f793b59a 14386 #define SIM_BASES SIM_BASE_PTRS
screamer 0:c5e2f793b59a 14387 #define SMC_BASES SMC_BASE_PTRS
screamer 0:c5e2f793b59a 14388 #define SPI_BASES SPI_BASE_PTRS
screamer 0:c5e2f793b59a 14389 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
screamer 0:c5e2f793b59a 14390 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
screamer 0:c5e2f793b59a 14391 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
screamer 0:c5e2f793b59a 14392 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
screamer 0:c5e2f793b59a 14393 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
screamer 0:c5e2f793b59a 14394 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
screamer 0:c5e2f793b59a 14395 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
screamer 0:c5e2f793b59a 14396 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
screamer 0:c5e2f793b59a 14397 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
screamer 0:c5e2f793b59a 14398 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
screamer 0:c5e2f793b59a 14399 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
screamer 0:c5e2f793b59a 14400 #define UART_BASES UART_BASE_PTRS
screamer 0:c5e2f793b59a 14401 #define USB_BASES USB_BASE_PTRS
screamer 0:c5e2f793b59a 14402 #define USBDCD_BASES USBDCD_BASE_PTRS
screamer 0:c5e2f793b59a 14403 #define VREF_BASES VREF_BASE_PTRS
screamer 0:c5e2f793b59a 14404 #define WDOG_BASES WDOG_BASE_PTRS
screamer 0:c5e2f793b59a 14405
screamer 0:c5e2f793b59a 14406 /*!
screamer 0:c5e2f793b59a 14407 * @}
screamer 0:c5e2f793b59a 14408 */ /* end of group Backward_Compatibility_Symbols */
screamer 0:c5e2f793b59a 14409
screamer 0:c5e2f793b59a 14410
screamer 0:c5e2f793b59a 14411 #else /* #if !defined(MK64F12_H_) */
screamer 0:c5e2f793b59a 14412 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
screamer 0:c5e2f793b59a 14413 #if (MCU_MEM_MAP_VERSION != 0x0200u)
screamer 0:c5e2f793b59a 14414 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
screamer 0:c5e2f793b59a 14415 #warning There are included two not compatible versions of memory maps. Please check possible differences.
screamer 0:c5e2f793b59a 14416 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
screamer 0:c5e2f793b59a 14417 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
screamer 0:c5e2f793b59a 14418 #endif /* #if !defined(MK64F12_H_) */
screamer 0:c5e2f793b59a 14419
screamer 0:c5e2f793b59a 14420 /* MK64F12.h, eof. */