Morpheus / target-mcu-k64f

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of target-mcu-k64f by -deleted-

hal/device/device/MK64F12/MK64F12_rng.h@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 4 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 5 ** GNU C Compiler
screamer 0:c5e2f793b59a 6 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 9 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 10 ** Build: b140604
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Abstract:
screamer 0:c5e2f793b59a 13 ** Extension to the CMSIS register access layer header.
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 16 ** All rights reserved.
screamer 0:c5e2f793b59a 17 **
screamer 0:c5e2f793b59a 18 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 19 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 20 **
screamer 0:c5e2f793b59a 21 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 22 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 25 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 26 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 27 **
screamer 0:c5e2f793b59a 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 29 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 30 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 31 **
screamer 0:c5e2f793b59a 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 42 **
screamer 0:c5e2f793b59a 43 ** http: www.freescale.com
screamer 0:c5e2f793b59a 44 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 45 **
screamer 0:c5e2f793b59a 46 ** Revisions:
screamer 0:c5e2f793b59a 47 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 48 ** Initial version.
screamer 0:c5e2f793b59a 49 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 50 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 53 ** System initialization updated.
screamer 0:c5e2f793b59a 54 ** MCG - registers updated.
screamer 0:c5e2f793b59a 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 56 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 58 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 59 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 60 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 61 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 62 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 63 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 64 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 67 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 71 **
screamer 0:c5e2f793b59a 72 ** ###################################################################
screamer 0:c5e2f793b59a 73 */
screamer 0:c5e2f793b59a 74
screamer 0:c5e2f793b59a 75 /*
screamer 0:c5e2f793b59a 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
screamer 0:c5e2f793b59a 77 *
screamer 0:c5e2f793b59a 78 * This file was generated automatically and any changes may be lost.
screamer 0:c5e2f793b59a 79 */
screamer 0:c5e2f793b59a 80 #ifndef __HW_RNG_REGISTERS_H__
screamer 0:c5e2f793b59a 81 #define __HW_RNG_REGISTERS_H__
screamer 0:c5e2f793b59a 82
screamer 0:c5e2f793b59a 83 #include "MK64F12.h"
screamer 0:c5e2f793b59a 84 #include "fsl_bitaccess.h"
screamer 0:c5e2f793b59a 85
screamer 0:c5e2f793b59a 86 /*
screamer 0:c5e2f793b59a 87 * MK64F12 RNG
screamer 0:c5e2f793b59a 88 *
screamer 0:c5e2f793b59a 89 * Random Number Generator Accelerator
screamer 0:c5e2f793b59a 90 *
screamer 0:c5e2f793b59a 91 * Registers defined in this header file:
screamer 0:c5e2f793b59a 92 * - HW_RNG_CR - RNGA Control Register
screamer 0:c5e2f793b59a 93 * - HW_RNG_SR - RNGA Status Register
screamer 0:c5e2f793b59a 94 * - HW_RNG_ER - RNGA Entropy Register
screamer 0:c5e2f793b59a 95 * - HW_RNG_OR - RNGA Output Register
screamer 0:c5e2f793b59a 96 *
screamer 0:c5e2f793b59a 97 * - hw_rng_t - Struct containing all module registers.
screamer 0:c5e2f793b59a 98 */
screamer 0:c5e2f793b59a 99
screamer 0:c5e2f793b59a 100 #define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
screamer 0:c5e2f793b59a 101
screamer 0:c5e2f793b59a 102 /*******************************************************************************
screamer 0:c5e2f793b59a 103 * HW_RNG_CR - RNGA Control Register
screamer 0:c5e2f793b59a 104 ******************************************************************************/
screamer 0:c5e2f793b59a 105
screamer 0:c5e2f793b59a 106 /*!
screamer 0:c5e2f793b59a 107 * @brief HW_RNG_CR - RNGA Control Register (RW)
screamer 0:c5e2f793b59a 108 *
screamer 0:c5e2f793b59a 109 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 110 *
screamer 0:c5e2f793b59a 111 * Controls the operation of RNGA.
screamer 0:c5e2f793b59a 112 */
screamer 0:c5e2f793b59a 113 typedef union _hw_rng_cr
screamer 0:c5e2f793b59a 114 {
screamer 0:c5e2f793b59a 115 uint32_t U;
screamer 0:c5e2f793b59a 116 struct _hw_rng_cr_bitfields
screamer 0:c5e2f793b59a 117 {
screamer 0:c5e2f793b59a 118 uint32_t GO : 1; /*!< [0] Go */
screamer 0:c5e2f793b59a 119 uint32_t HA : 1; /*!< [1] High Assurance */
screamer 0:c5e2f793b59a 120 uint32_t INTM : 1; /*!< [2] Interrupt Mask */
screamer 0:c5e2f793b59a 121 uint32_t CLRI : 1; /*!< [3] Clear Interrupt */
screamer 0:c5e2f793b59a 122 uint32_t SLP : 1; /*!< [4] Sleep */
screamer 0:c5e2f793b59a 123 uint32_t RESERVED0 : 27; /*!< [31:5] */
screamer 0:c5e2f793b59a 124 } B;
screamer 0:c5e2f793b59a 125 } hw_rng_cr_t;
screamer 0:c5e2f793b59a 126
screamer 0:c5e2f793b59a 127 /*!
screamer 0:c5e2f793b59a 128 * @name Constants and macros for entire RNG_CR register
screamer 0:c5e2f793b59a 129 */
screamer 0:c5e2f793b59a 130 /*@{*/
screamer 0:c5e2f793b59a 131 #define HW_RNG_CR_ADDR(x) ((x) + 0x0U)
screamer 0:c5e2f793b59a 132
screamer 0:c5e2f793b59a 133 #define HW_RNG_CR(x) (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x))
screamer 0:c5e2f793b59a 134 #define HW_RNG_CR_RD(x) (HW_RNG_CR(x).U)
screamer 0:c5e2f793b59a 135 #define HW_RNG_CR_WR(x, v) (HW_RNG_CR(x).U = (v))
screamer 0:c5e2f793b59a 136 #define HW_RNG_CR_SET(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) | (v)))
screamer 0:c5e2f793b59a 137 #define HW_RNG_CR_CLR(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 138 #define HW_RNG_CR_TOG(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 139 /*@}*/
screamer 0:c5e2f793b59a 140
screamer 0:c5e2f793b59a 141 /*
screamer 0:c5e2f793b59a 142 * Constants & macros for individual RNG_CR bitfields
screamer 0:c5e2f793b59a 143 */
screamer 0:c5e2f793b59a 144
screamer 0:c5e2f793b59a 145 /*!
screamer 0:c5e2f793b59a 146 * @name Register RNG_CR, field GO[0] (RW)
screamer 0:c5e2f793b59a 147 *
screamer 0:c5e2f793b59a 148 * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
screamer 0:c5e2f793b59a 149 * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
screamer 0:c5e2f793b59a 150 * OR[RANDOUT] with data.
screamer 0:c5e2f793b59a 151 *
screamer 0:c5e2f793b59a 152 * Values:
screamer 0:c5e2f793b59a 153 * - 0 - Disabled
screamer 0:c5e2f793b59a 154 * - 1 - Enabled
screamer 0:c5e2f793b59a 155 */
screamer 0:c5e2f793b59a 156 /*@{*/
screamer 0:c5e2f793b59a 157 #define BP_RNG_CR_GO (0U) /*!< Bit position for RNG_CR_GO. */
screamer 0:c5e2f793b59a 158 #define BM_RNG_CR_GO (0x00000001U) /*!< Bit mask for RNG_CR_GO. */
screamer 0:c5e2f793b59a 159 #define BS_RNG_CR_GO (1U) /*!< Bit field size in bits for RNG_CR_GO. */
screamer 0:c5e2f793b59a 160
screamer 0:c5e2f793b59a 161 /*! @brief Read current value of the RNG_CR_GO field. */
screamer 0:c5e2f793b59a 162 #define BR_RNG_CR_GO(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO))
screamer 0:c5e2f793b59a 163
screamer 0:c5e2f793b59a 164 /*! @brief Format value for bitfield RNG_CR_GO. */
screamer 0:c5e2f793b59a 165 #define BF_RNG_CR_GO(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO)
screamer 0:c5e2f793b59a 166
screamer 0:c5e2f793b59a 167 /*! @brief Set the GO field to a new value. */
screamer 0:c5e2f793b59a 168 #define BW_RNG_CR_GO(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v))
screamer 0:c5e2f793b59a 169 /*@}*/
screamer 0:c5e2f793b59a 170
screamer 0:c5e2f793b59a 171 /*!
screamer 0:c5e2f793b59a 172 * @name Register RNG_CR, field HA[1] (RW)
screamer 0:c5e2f793b59a 173 *
screamer 0:c5e2f793b59a 174 * Enables notification of security violations (via SR[SECV]). A security
screamer 0:c5e2f793b59a 175 * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
screamer 0:c5e2f793b59a 176 * After enabling notification of security violations, you must reset RNGA to
screamer 0:c5e2f793b59a 177 * disable them again.
screamer 0:c5e2f793b59a 178 *
screamer 0:c5e2f793b59a 179 * Values:
screamer 0:c5e2f793b59a 180 * - 0 - Disabled
screamer 0:c5e2f793b59a 181 * - 1 - Enabled
screamer 0:c5e2f793b59a 182 */
screamer 0:c5e2f793b59a 183 /*@{*/
screamer 0:c5e2f793b59a 184 #define BP_RNG_CR_HA (1U) /*!< Bit position for RNG_CR_HA. */
screamer 0:c5e2f793b59a 185 #define BM_RNG_CR_HA (0x00000002U) /*!< Bit mask for RNG_CR_HA. */
screamer 0:c5e2f793b59a 186 #define BS_RNG_CR_HA (1U) /*!< Bit field size in bits for RNG_CR_HA. */
screamer 0:c5e2f793b59a 187
screamer 0:c5e2f793b59a 188 /*! @brief Read current value of the RNG_CR_HA field. */
screamer 0:c5e2f793b59a 189 #define BR_RNG_CR_HA(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA))
screamer 0:c5e2f793b59a 190
screamer 0:c5e2f793b59a 191 /*! @brief Format value for bitfield RNG_CR_HA. */
screamer 0:c5e2f793b59a 192 #define BF_RNG_CR_HA(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA)
screamer 0:c5e2f793b59a 193
screamer 0:c5e2f793b59a 194 /*! @brief Set the HA field to a new value. */
screamer 0:c5e2f793b59a 195 #define BW_RNG_CR_HA(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v))
screamer 0:c5e2f793b59a 196 /*@}*/
screamer 0:c5e2f793b59a 197
screamer 0:c5e2f793b59a 198 /*!
screamer 0:c5e2f793b59a 199 * @name Register RNG_CR, field INTM[2] (RW)
screamer 0:c5e2f793b59a 200 *
screamer 0:c5e2f793b59a 201 * Masks the triggering of an error interrupt to the interrupt controller when
screamer 0:c5e2f793b59a 202 * an OR underflow condition occurs. An OR underflow condition occurs when you
screamer 0:c5e2f793b59a 203 * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
screamer 0:c5e2f793b59a 204 *
screamer 0:c5e2f793b59a 205 * Values:
screamer 0:c5e2f793b59a 206 * - 0 - Not masked
screamer 0:c5e2f793b59a 207 * - 1 - Masked
screamer 0:c5e2f793b59a 208 */
screamer 0:c5e2f793b59a 209 /*@{*/
screamer 0:c5e2f793b59a 210 #define BP_RNG_CR_INTM (2U) /*!< Bit position for RNG_CR_INTM. */
screamer 0:c5e2f793b59a 211 #define BM_RNG_CR_INTM (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */
screamer 0:c5e2f793b59a 212 #define BS_RNG_CR_INTM (1U) /*!< Bit field size in bits for RNG_CR_INTM. */
screamer 0:c5e2f793b59a 213
screamer 0:c5e2f793b59a 214 /*! @brief Read current value of the RNG_CR_INTM field. */
screamer 0:c5e2f793b59a 215 #define BR_RNG_CR_INTM(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM))
screamer 0:c5e2f793b59a 216
screamer 0:c5e2f793b59a 217 /*! @brief Format value for bitfield RNG_CR_INTM. */
screamer 0:c5e2f793b59a 218 #define BF_RNG_CR_INTM(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM)
screamer 0:c5e2f793b59a 219
screamer 0:c5e2f793b59a 220 /*! @brief Set the INTM field to a new value. */
screamer 0:c5e2f793b59a 221 #define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v))
screamer 0:c5e2f793b59a 222 /*@}*/
screamer 0:c5e2f793b59a 223
screamer 0:c5e2f793b59a 224 /*!
screamer 0:c5e2f793b59a 225 * @name Register RNG_CR, field CLRI[3] (WORZ)
screamer 0:c5e2f793b59a 226 *
screamer 0:c5e2f793b59a 227 * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
screamer 0:c5e2f793b59a 228 *
screamer 0:c5e2f793b59a 229 * Values:
screamer 0:c5e2f793b59a 230 * - 0 - Do not clear the interrupt.
screamer 0:c5e2f793b59a 231 * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
screamer 0:c5e2f793b59a 232 * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
screamer 0:c5e2f793b59a 233 */
screamer 0:c5e2f793b59a 234 /*@{*/
screamer 0:c5e2f793b59a 235 #define BP_RNG_CR_CLRI (3U) /*!< Bit position for RNG_CR_CLRI. */
screamer 0:c5e2f793b59a 236 #define BM_RNG_CR_CLRI (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */
screamer 0:c5e2f793b59a 237 #define BS_RNG_CR_CLRI (1U) /*!< Bit field size in bits for RNG_CR_CLRI. */
screamer 0:c5e2f793b59a 238
screamer 0:c5e2f793b59a 239 /*! @brief Format value for bitfield RNG_CR_CLRI. */
screamer 0:c5e2f793b59a 240 #define BF_RNG_CR_CLRI(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI)
screamer 0:c5e2f793b59a 241
screamer 0:c5e2f793b59a 242 /*! @brief Set the CLRI field to a new value. */
screamer 0:c5e2f793b59a 243 #define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v))
screamer 0:c5e2f793b59a 244 /*@}*/
screamer 0:c5e2f793b59a 245
screamer 0:c5e2f793b59a 246 /*!
screamer 0:c5e2f793b59a 247 * @name Register RNG_CR, field SLP[4] (RW)
screamer 0:c5e2f793b59a 248 *
screamer 0:c5e2f793b59a 249 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
screamer 0:c5e2f793b59a 250 * mode by asserting the DOZE signal.
screamer 0:c5e2f793b59a 251 *
screamer 0:c5e2f793b59a 252 * Values:
screamer 0:c5e2f793b59a 253 * - 0 - Normal mode
screamer 0:c5e2f793b59a 254 * - 1 - Sleep (low-power) mode
screamer 0:c5e2f793b59a 255 */
screamer 0:c5e2f793b59a 256 /*@{*/
screamer 0:c5e2f793b59a 257 #define BP_RNG_CR_SLP (4U) /*!< Bit position for RNG_CR_SLP. */
screamer 0:c5e2f793b59a 258 #define BM_RNG_CR_SLP (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */
screamer 0:c5e2f793b59a 259 #define BS_RNG_CR_SLP (1U) /*!< Bit field size in bits for RNG_CR_SLP. */
screamer 0:c5e2f793b59a 260
screamer 0:c5e2f793b59a 261 /*! @brief Read current value of the RNG_CR_SLP field. */
screamer 0:c5e2f793b59a 262 #define BR_RNG_CR_SLP(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP))
screamer 0:c5e2f793b59a 263
screamer 0:c5e2f793b59a 264 /*! @brief Format value for bitfield RNG_CR_SLP. */
screamer 0:c5e2f793b59a 265 #define BF_RNG_CR_SLP(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP)
screamer 0:c5e2f793b59a 266
screamer 0:c5e2f793b59a 267 /*! @brief Set the SLP field to a new value. */
screamer 0:c5e2f793b59a 268 #define BW_RNG_CR_SLP(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v))
screamer 0:c5e2f793b59a 269 /*@}*/
screamer 0:c5e2f793b59a 270
screamer 0:c5e2f793b59a 271 /*******************************************************************************
screamer 0:c5e2f793b59a 272 * HW_RNG_SR - RNGA Status Register
screamer 0:c5e2f793b59a 273 ******************************************************************************/
screamer 0:c5e2f793b59a 274
screamer 0:c5e2f793b59a 275 /*!
screamer 0:c5e2f793b59a 276 * @brief HW_RNG_SR - RNGA Status Register (RO)
screamer 0:c5e2f793b59a 277 *
screamer 0:c5e2f793b59a 278 * Reset value: 0x00010000U
screamer 0:c5e2f793b59a 279 *
screamer 0:c5e2f793b59a 280 * Indicates the status of RNGA. This register is read-only.
screamer 0:c5e2f793b59a 281 */
screamer 0:c5e2f793b59a 282 typedef union _hw_rng_sr
screamer 0:c5e2f793b59a 283 {
screamer 0:c5e2f793b59a 284 uint32_t U;
screamer 0:c5e2f793b59a 285 struct _hw_rng_sr_bitfields
screamer 0:c5e2f793b59a 286 {
screamer 0:c5e2f793b59a 287 uint32_t SECV : 1; /*!< [0] Security Violation */
screamer 0:c5e2f793b59a 288 uint32_t LRS : 1; /*!< [1] Last Read Status */
screamer 0:c5e2f793b59a 289 uint32_t ORU : 1; /*!< [2] Output Register Underflow */
screamer 0:c5e2f793b59a 290 uint32_t ERRI : 1; /*!< [3] Error Interrupt */
screamer 0:c5e2f793b59a 291 uint32_t SLP : 1; /*!< [4] Sleep */
screamer 0:c5e2f793b59a 292 uint32_t RESERVED0 : 3; /*!< [7:5] */
screamer 0:c5e2f793b59a 293 uint32_t OREG_LVL : 8; /*!< [15:8] Output Register Level */
screamer 0:c5e2f793b59a 294 uint32_t OREG_SIZE : 8; /*!< [23:16] Output Register Size */
screamer 0:c5e2f793b59a 295 uint32_t RESERVED1 : 8; /*!< [31:24] */
screamer 0:c5e2f793b59a 296 } B;
screamer 0:c5e2f793b59a 297 } hw_rng_sr_t;
screamer 0:c5e2f793b59a 298
screamer 0:c5e2f793b59a 299 /*!
screamer 0:c5e2f793b59a 300 * @name Constants and macros for entire RNG_SR register
screamer 0:c5e2f793b59a 301 */
screamer 0:c5e2f793b59a 302 /*@{*/
screamer 0:c5e2f793b59a 303 #define HW_RNG_SR_ADDR(x) ((x) + 0x4U)
screamer 0:c5e2f793b59a 304
screamer 0:c5e2f793b59a 305 #define HW_RNG_SR(x) (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x))
screamer 0:c5e2f793b59a 306 #define HW_RNG_SR_RD(x) (HW_RNG_SR(x).U)
screamer 0:c5e2f793b59a 307 /*@}*/
screamer 0:c5e2f793b59a 308
screamer 0:c5e2f793b59a 309 /*
screamer 0:c5e2f793b59a 310 * Constants & macros for individual RNG_SR bitfields
screamer 0:c5e2f793b59a 311 */
screamer 0:c5e2f793b59a 312
screamer 0:c5e2f793b59a 313 /*!
screamer 0:c5e2f793b59a 314 * @name Register RNG_SR, field SECV[0] (RO)
screamer 0:c5e2f793b59a 315 *
screamer 0:c5e2f793b59a 316 * Used only when high assurance is enabled (CR[HA]). Indicates that a security
screamer 0:c5e2f793b59a 317 * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
screamer 0:c5e2f793b59a 318 * RNGA.
screamer 0:c5e2f793b59a 319 *
screamer 0:c5e2f793b59a 320 * Values:
screamer 0:c5e2f793b59a 321 * - 0 - No security violation
screamer 0:c5e2f793b59a 322 * - 1 - Security violation
screamer 0:c5e2f793b59a 323 */
screamer 0:c5e2f793b59a 324 /*@{*/
screamer 0:c5e2f793b59a 325 #define BP_RNG_SR_SECV (0U) /*!< Bit position for RNG_SR_SECV. */
screamer 0:c5e2f793b59a 326 #define BM_RNG_SR_SECV (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */
screamer 0:c5e2f793b59a 327 #define BS_RNG_SR_SECV (1U) /*!< Bit field size in bits for RNG_SR_SECV. */
screamer 0:c5e2f793b59a 328
screamer 0:c5e2f793b59a 329 /*! @brief Read current value of the RNG_SR_SECV field. */
screamer 0:c5e2f793b59a 330 #define BR_RNG_SR_SECV(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV))
screamer 0:c5e2f793b59a 331 /*@}*/
screamer 0:c5e2f793b59a 332
screamer 0:c5e2f793b59a 333 /*!
screamer 0:c5e2f793b59a 334 * @name Register RNG_SR, field LRS[1] (RO)
screamer 0:c5e2f793b59a 335 *
screamer 0:c5e2f793b59a 336 * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
screamer 0:c5e2f793b59a 337 * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
screamer 0:c5e2f793b59a 338 * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
screamer 0:c5e2f793b59a 339 * After you read this register, RNGA writes 0 to this field.
screamer 0:c5e2f793b59a 340 *
screamer 0:c5e2f793b59a 341 * Values:
screamer 0:c5e2f793b59a 342 * - 0 - No underflow
screamer 0:c5e2f793b59a 343 * - 1 - Underflow
screamer 0:c5e2f793b59a 344 */
screamer 0:c5e2f793b59a 345 /*@{*/
screamer 0:c5e2f793b59a 346 #define BP_RNG_SR_LRS (1U) /*!< Bit position for RNG_SR_LRS. */
screamer 0:c5e2f793b59a 347 #define BM_RNG_SR_LRS (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */
screamer 0:c5e2f793b59a 348 #define BS_RNG_SR_LRS (1U) /*!< Bit field size in bits for RNG_SR_LRS. */
screamer 0:c5e2f793b59a 349
screamer 0:c5e2f793b59a 350 /*! @brief Read current value of the RNG_SR_LRS field. */
screamer 0:c5e2f793b59a 351 #define BR_RNG_SR_LRS(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS))
screamer 0:c5e2f793b59a 352 /*@}*/
screamer 0:c5e2f793b59a 353
screamer 0:c5e2f793b59a 354 /*!
screamer 0:c5e2f793b59a 355 * @name Register RNG_SR, field ORU[2] (RO)
screamer 0:c5e2f793b59a 356 *
screamer 0:c5e2f793b59a 357 * Indicates whether an OR underflow condition has occurred since you last read
screamer 0:c5e2f793b59a 358 * this register (SR) or RNGA was reset, regardless of whether the error
screamer 0:c5e2f793b59a 359 * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
screamer 0:c5e2f793b59a 360 * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
screamer 0:c5e2f793b59a 361 * field.
screamer 0:c5e2f793b59a 362 *
screamer 0:c5e2f793b59a 363 * Values:
screamer 0:c5e2f793b59a 364 * - 0 - No underflow
screamer 0:c5e2f793b59a 365 * - 1 - Underflow
screamer 0:c5e2f793b59a 366 */
screamer 0:c5e2f793b59a 367 /*@{*/
screamer 0:c5e2f793b59a 368 #define BP_RNG_SR_ORU (2U) /*!< Bit position for RNG_SR_ORU. */
screamer 0:c5e2f793b59a 369 #define BM_RNG_SR_ORU (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */
screamer 0:c5e2f793b59a 370 #define BS_RNG_SR_ORU (1U) /*!< Bit field size in bits for RNG_SR_ORU. */
screamer 0:c5e2f793b59a 371
screamer 0:c5e2f793b59a 372 /*! @brief Read current value of the RNG_SR_ORU field. */
screamer 0:c5e2f793b59a 373 #define BR_RNG_SR_ORU(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU))
screamer 0:c5e2f793b59a 374 /*@}*/
screamer 0:c5e2f793b59a 375
screamer 0:c5e2f793b59a 376 /*!
screamer 0:c5e2f793b59a 377 * @name Register RNG_SR, field ERRI[3] (RO)
screamer 0:c5e2f793b59a 378 *
screamer 0:c5e2f793b59a 379 * Indicates whether an OR underflow condition has occurred since you last
screamer 0:c5e2f793b59a 380 * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
screamer 0:c5e2f793b59a 381 * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
screamer 0:c5e2f793b59a 382 * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
screamer 0:c5e2f793b59a 383 * indicator (via CR[CLRI]), RNGA writes 0 to this field.
screamer 0:c5e2f793b59a 384 *
screamer 0:c5e2f793b59a 385 * Values:
screamer 0:c5e2f793b59a 386 * - 0 - No underflow
screamer 0:c5e2f793b59a 387 * - 1 - Underflow
screamer 0:c5e2f793b59a 388 */
screamer 0:c5e2f793b59a 389 /*@{*/
screamer 0:c5e2f793b59a 390 #define BP_RNG_SR_ERRI (3U) /*!< Bit position for RNG_SR_ERRI. */
screamer 0:c5e2f793b59a 391 #define BM_RNG_SR_ERRI (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */
screamer 0:c5e2f793b59a 392 #define BS_RNG_SR_ERRI (1U) /*!< Bit field size in bits for RNG_SR_ERRI. */
screamer 0:c5e2f793b59a 393
screamer 0:c5e2f793b59a 394 /*! @brief Read current value of the RNG_SR_ERRI field. */
screamer 0:c5e2f793b59a 395 #define BR_RNG_SR_ERRI(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI))
screamer 0:c5e2f793b59a 396 /*@}*/
screamer 0:c5e2f793b59a 397
screamer 0:c5e2f793b59a 398 /*!
screamer 0:c5e2f793b59a 399 * @name Register RNG_SR, field SLP[4] (RO)
screamer 0:c5e2f793b59a 400 *
screamer 0:c5e2f793b59a 401 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
screamer 0:c5e2f793b59a 402 * mode by asserting the DOZE signal.
screamer 0:c5e2f793b59a 403 *
screamer 0:c5e2f793b59a 404 * Values:
screamer 0:c5e2f793b59a 405 * - 0 - Normal mode
screamer 0:c5e2f793b59a 406 * - 1 - Sleep (low-power) mode
screamer 0:c5e2f793b59a 407 */
screamer 0:c5e2f793b59a 408 /*@{*/
screamer 0:c5e2f793b59a 409 #define BP_RNG_SR_SLP (4U) /*!< Bit position for RNG_SR_SLP. */
screamer 0:c5e2f793b59a 410 #define BM_RNG_SR_SLP (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */
screamer 0:c5e2f793b59a 411 #define BS_RNG_SR_SLP (1U) /*!< Bit field size in bits for RNG_SR_SLP. */
screamer 0:c5e2f793b59a 412
screamer 0:c5e2f793b59a 413 /*! @brief Read current value of the RNG_SR_SLP field. */
screamer 0:c5e2f793b59a 414 #define BR_RNG_SR_SLP(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP))
screamer 0:c5e2f793b59a 415 /*@}*/
screamer 0:c5e2f793b59a 416
screamer 0:c5e2f793b59a 417 /*!
screamer 0:c5e2f793b59a 418 * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
screamer 0:c5e2f793b59a 419 *
screamer 0:c5e2f793b59a 420 * Indicates the number of random-data words that are in OR[RANDOUT], which
screamer 0:c5e2f793b59a 421 * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
screamer 0:c5e2f793b59a 422 * is not 0, then the contents of a random number contained in OR[RANDOUT] are
screamer 0:c5e2f793b59a 423 * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
screamer 0:c5e2f793b59a 424 *
screamer 0:c5e2f793b59a 425 * Values:
screamer 0:c5e2f793b59a 426 * - 0 - No words (empty)
screamer 0:c5e2f793b59a 427 * - 1 - One word (valid)
screamer 0:c5e2f793b59a 428 */
screamer 0:c5e2f793b59a 429 /*@{*/
screamer 0:c5e2f793b59a 430 #define BP_RNG_SR_OREG_LVL (8U) /*!< Bit position for RNG_SR_OREG_LVL. */
screamer 0:c5e2f793b59a 431 #define BM_RNG_SR_OREG_LVL (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */
screamer 0:c5e2f793b59a 432 #define BS_RNG_SR_OREG_LVL (8U) /*!< Bit field size in bits for RNG_SR_OREG_LVL. */
screamer 0:c5e2f793b59a 433
screamer 0:c5e2f793b59a 434 /*! @brief Read current value of the RNG_SR_OREG_LVL field. */
screamer 0:c5e2f793b59a 435 #define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL)
screamer 0:c5e2f793b59a 436 /*@}*/
screamer 0:c5e2f793b59a 437
screamer 0:c5e2f793b59a 438 /*!
screamer 0:c5e2f793b59a 439 * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
screamer 0:c5e2f793b59a 440 *
screamer 0:c5e2f793b59a 441 * Indicates the size of the Output (OR) register in terms of the number of
screamer 0:c5e2f793b59a 442 * 32-bit random-data words it can hold.
screamer 0:c5e2f793b59a 443 *
screamer 0:c5e2f793b59a 444 * Values:
screamer 0:c5e2f793b59a 445 * - 1 - One word (this value is fixed)
screamer 0:c5e2f793b59a 446 */
screamer 0:c5e2f793b59a 447 /*@{*/
screamer 0:c5e2f793b59a 448 #define BP_RNG_SR_OREG_SIZE (16U) /*!< Bit position for RNG_SR_OREG_SIZE. */
screamer 0:c5e2f793b59a 449 #define BM_RNG_SR_OREG_SIZE (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */
screamer 0:c5e2f793b59a 450 #define BS_RNG_SR_OREG_SIZE (8U) /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */
screamer 0:c5e2f793b59a 451
screamer 0:c5e2f793b59a 452 /*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
screamer 0:c5e2f793b59a 453 #define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE)
screamer 0:c5e2f793b59a 454 /*@}*/
screamer 0:c5e2f793b59a 455
screamer 0:c5e2f793b59a 456 /*******************************************************************************
screamer 0:c5e2f793b59a 457 * HW_RNG_ER - RNGA Entropy Register
screamer 0:c5e2f793b59a 458 ******************************************************************************/
screamer 0:c5e2f793b59a 459
screamer 0:c5e2f793b59a 460 /*!
screamer 0:c5e2f793b59a 461 * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
screamer 0:c5e2f793b59a 462 *
screamer 0:c5e2f793b59a 463 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 464 *
screamer 0:c5e2f793b59a 465 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
screamer 0:c5e2f793b59a 466 * to seed its pseudorandom algorithm. This is a write-only register; reads
screamer 0:c5e2f793b59a 467 * return all zeros.
screamer 0:c5e2f793b59a 468 */
screamer 0:c5e2f793b59a 469 typedef union _hw_rng_er
screamer 0:c5e2f793b59a 470 {
screamer 0:c5e2f793b59a 471 uint32_t U;
screamer 0:c5e2f793b59a 472 struct _hw_rng_er_bitfields
screamer 0:c5e2f793b59a 473 {
screamer 0:c5e2f793b59a 474 uint32_t EXT_ENT : 32; /*!< [31:0] External Entropy */
screamer 0:c5e2f793b59a 475 } B;
screamer 0:c5e2f793b59a 476 } hw_rng_er_t;
screamer 0:c5e2f793b59a 477
screamer 0:c5e2f793b59a 478 /*!
screamer 0:c5e2f793b59a 479 * @name Constants and macros for entire RNG_ER register
screamer 0:c5e2f793b59a 480 */
screamer 0:c5e2f793b59a 481 /*@{*/
screamer 0:c5e2f793b59a 482 #define HW_RNG_ER_ADDR(x) ((x) + 0x8U)
screamer 0:c5e2f793b59a 483
screamer 0:c5e2f793b59a 484 #define HW_RNG_ER(x) (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x))
screamer 0:c5e2f793b59a 485 #define HW_RNG_ER_RD(x) (HW_RNG_ER(x).U)
screamer 0:c5e2f793b59a 486 #define HW_RNG_ER_WR(x, v) (HW_RNG_ER(x).U = (v))
screamer 0:c5e2f793b59a 487 /*@}*/
screamer 0:c5e2f793b59a 488
screamer 0:c5e2f793b59a 489 /*
screamer 0:c5e2f793b59a 490 * Constants & macros for individual RNG_ER bitfields
screamer 0:c5e2f793b59a 491 */
screamer 0:c5e2f793b59a 492
screamer 0:c5e2f793b59a 493 /*!
screamer 0:c5e2f793b59a 494 * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
screamer 0:c5e2f793b59a 495 *
screamer 0:c5e2f793b59a 496 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
screamer 0:c5e2f793b59a 497 * to seed its pseudorandom algorithm.Specifying a value for this field is
screamer 0:c5e2f793b59a 498 * optional but recommended. You can write to this field at any time during operation.
screamer 0:c5e2f793b59a 499 */
screamer 0:c5e2f793b59a 500 /*@{*/
screamer 0:c5e2f793b59a 501 #define BP_RNG_ER_EXT_ENT (0U) /*!< Bit position for RNG_ER_EXT_ENT. */
screamer 0:c5e2f793b59a 502 #define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */
screamer 0:c5e2f793b59a 503 #define BS_RNG_ER_EXT_ENT (32U) /*!< Bit field size in bits for RNG_ER_EXT_ENT. */
screamer 0:c5e2f793b59a 504
screamer 0:c5e2f793b59a 505 /*! @brief Format value for bitfield RNG_ER_EXT_ENT. */
screamer 0:c5e2f793b59a 506 #define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT)
screamer 0:c5e2f793b59a 507
screamer 0:c5e2f793b59a 508 /*! @brief Set the EXT_ENT field to a new value. */
screamer 0:c5e2f793b59a 509 #define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v))
screamer 0:c5e2f793b59a 510 /*@}*/
screamer 0:c5e2f793b59a 511
screamer 0:c5e2f793b59a 512 /*******************************************************************************
screamer 0:c5e2f793b59a 513 * HW_RNG_OR - RNGA Output Register
screamer 0:c5e2f793b59a 514 ******************************************************************************/
screamer 0:c5e2f793b59a 515
screamer 0:c5e2f793b59a 516 /*!
screamer 0:c5e2f793b59a 517 * @brief HW_RNG_OR - RNGA Output Register (RO)
screamer 0:c5e2f793b59a 518 *
screamer 0:c5e2f793b59a 519 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 520 *
screamer 0:c5e2f793b59a 521 * Stores a random-data word generated by RNGA.
screamer 0:c5e2f793b59a 522 */
screamer 0:c5e2f793b59a 523 typedef union _hw_rng_or
screamer 0:c5e2f793b59a 524 {
screamer 0:c5e2f793b59a 525 uint32_t U;
screamer 0:c5e2f793b59a 526 struct _hw_rng_or_bitfields
screamer 0:c5e2f793b59a 527 {
screamer 0:c5e2f793b59a 528 uint32_t RANDOUT : 32; /*!< [31:0] Random Output */
screamer 0:c5e2f793b59a 529 } B;
screamer 0:c5e2f793b59a 530 } hw_rng_or_t;
screamer 0:c5e2f793b59a 531
screamer 0:c5e2f793b59a 532 /*!
screamer 0:c5e2f793b59a 533 * @name Constants and macros for entire RNG_OR register
screamer 0:c5e2f793b59a 534 */
screamer 0:c5e2f793b59a 535 /*@{*/
screamer 0:c5e2f793b59a 536 #define HW_RNG_OR_ADDR(x) ((x) + 0xCU)
screamer 0:c5e2f793b59a 537
screamer 0:c5e2f793b59a 538 #define HW_RNG_OR(x) (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x))
screamer 0:c5e2f793b59a 539 #define HW_RNG_OR_RD(x) (HW_RNG_OR(x).U)
screamer 0:c5e2f793b59a 540 /*@}*/
screamer 0:c5e2f793b59a 541
screamer 0:c5e2f793b59a 542 /*
screamer 0:c5e2f793b59a 543 * Constants & macros for individual RNG_OR bitfields
screamer 0:c5e2f793b59a 544 */
screamer 0:c5e2f793b59a 545
screamer 0:c5e2f793b59a 546 /*!
screamer 0:c5e2f793b59a 547 * @name Register RNG_OR, field RANDOUT[31:0] (RO)
screamer 0:c5e2f793b59a 548 *
screamer 0:c5e2f793b59a 549 * Stores a random-data word generated by RNGA. This is a read-only field.Before
screamer 0:c5e2f793b59a 550 * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
screamer 0:c5e2f793b59a 551 *
screamer 0:c5e2f793b59a 552 * Values:
screamer 0:c5e2f793b59a 553 * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
screamer 0:c5e2f793b59a 554 * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
screamer 0:c5e2f793b59a 555 * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
screamer 0:c5e2f793b59a 556 * request to the interrupt controller).
screamer 0:c5e2f793b59a 557 */
screamer 0:c5e2f793b59a 558 /*@{*/
screamer 0:c5e2f793b59a 559 #define BP_RNG_OR_RANDOUT (0U) /*!< Bit position for RNG_OR_RANDOUT. */
screamer 0:c5e2f793b59a 560 #define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */
screamer 0:c5e2f793b59a 561 #define BS_RNG_OR_RANDOUT (32U) /*!< Bit field size in bits for RNG_OR_RANDOUT. */
screamer 0:c5e2f793b59a 562
screamer 0:c5e2f793b59a 563 /*! @brief Read current value of the RNG_OR_RANDOUT field. */
screamer 0:c5e2f793b59a 564 #define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U)
screamer 0:c5e2f793b59a 565 /*@}*/
screamer 0:c5e2f793b59a 566
screamer 0:c5e2f793b59a 567 /*******************************************************************************
screamer 0:c5e2f793b59a 568 * hw_rng_t - module struct
screamer 0:c5e2f793b59a 569 ******************************************************************************/
screamer 0:c5e2f793b59a 570 /*!
screamer 0:c5e2f793b59a 571 * @brief All RNG module registers.
screamer 0:c5e2f793b59a 572 */
screamer 0:c5e2f793b59a 573 #pragma pack(1)
screamer 0:c5e2f793b59a 574 typedef struct _hw_rng
screamer 0:c5e2f793b59a 575 {
screamer 0:c5e2f793b59a 576 __IO hw_rng_cr_t CR; /*!< [0x0] RNGA Control Register */
screamer 0:c5e2f793b59a 577 __I hw_rng_sr_t SR; /*!< [0x4] RNGA Status Register */
screamer 0:c5e2f793b59a 578 __O hw_rng_er_t ER; /*!< [0x8] RNGA Entropy Register */
screamer 0:c5e2f793b59a 579 __I hw_rng_or_t OR; /*!< [0xC] RNGA Output Register */
screamer 0:c5e2f793b59a 580 } hw_rng_t;
screamer 0:c5e2f793b59a 581 #pragma pack()
screamer 0:c5e2f793b59a 582
screamer 0:c5e2f793b59a 583 /*! @brief Macro to access all RNG registers. */
screamer 0:c5e2f793b59a 584 /*! @param x RNG module instance base address. */
screamer 0:c5e2f793b59a 585 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
screamer 0:c5e2f793b59a 586 * use the '&' operator, like <code>&HW_RNG(RNG_BASE)</code>. */
screamer 0:c5e2f793b59a 587 #define HW_RNG(x) (*(hw_rng_t *)(x))
screamer 0:c5e2f793b59a 588
screamer 0:c5e2f793b59a 589 #endif /* __HW_RNG_REGISTERS_H__ */
screamer 0:c5e2f793b59a 590 /* EOF */