Morpheus / target-mcu-k64f

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hal/device/device/MK64F12/MK64F12_pmc.h@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 4 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 5 ** GNU C Compiler
screamer 0:c5e2f793b59a 6 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 9 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 10 ** Build: b140604
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Abstract:
screamer 0:c5e2f793b59a 13 ** Extension to the CMSIS register access layer header.
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 16 ** All rights reserved.
screamer 0:c5e2f793b59a 17 **
screamer 0:c5e2f793b59a 18 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 19 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 20 **
screamer 0:c5e2f793b59a 21 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 22 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 25 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 26 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 27 **
screamer 0:c5e2f793b59a 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 29 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 30 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 31 **
screamer 0:c5e2f793b59a 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 42 **
screamer 0:c5e2f793b59a 43 ** http: www.freescale.com
screamer 0:c5e2f793b59a 44 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 45 **
screamer 0:c5e2f793b59a 46 ** Revisions:
screamer 0:c5e2f793b59a 47 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 48 ** Initial version.
screamer 0:c5e2f793b59a 49 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 50 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 53 ** System initialization updated.
screamer 0:c5e2f793b59a 54 ** MCG - registers updated.
screamer 0:c5e2f793b59a 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 56 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 58 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 59 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 60 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 61 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 62 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 63 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 64 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 67 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 71 **
screamer 0:c5e2f793b59a 72 ** ###################################################################
screamer 0:c5e2f793b59a 73 */
screamer 0:c5e2f793b59a 74
screamer 0:c5e2f793b59a 75 /*
screamer 0:c5e2f793b59a 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
screamer 0:c5e2f793b59a 77 *
screamer 0:c5e2f793b59a 78 * This file was generated automatically and any changes may be lost.
screamer 0:c5e2f793b59a 79 */
screamer 0:c5e2f793b59a 80 #ifndef __HW_PMC_REGISTERS_H__
screamer 0:c5e2f793b59a 81 #define __HW_PMC_REGISTERS_H__
screamer 0:c5e2f793b59a 82
screamer 0:c5e2f793b59a 83 #include "MK64F12.h"
screamer 0:c5e2f793b59a 84 #include "fsl_bitaccess.h"
screamer 0:c5e2f793b59a 85
screamer 0:c5e2f793b59a 86 /*
screamer 0:c5e2f793b59a 87 * MK64F12 PMC
screamer 0:c5e2f793b59a 88 *
screamer 0:c5e2f793b59a 89 * Power Management Controller
screamer 0:c5e2f793b59a 90 *
screamer 0:c5e2f793b59a 91 * Registers defined in this header file:
screamer 0:c5e2f793b59a 92 * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
screamer 0:c5e2f793b59a 93 * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
screamer 0:c5e2f793b59a 94 * - HW_PMC_REGSC - Regulator Status And Control register
screamer 0:c5e2f793b59a 95 *
screamer 0:c5e2f793b59a 96 * - hw_pmc_t - Struct containing all module registers.
screamer 0:c5e2f793b59a 97 */
screamer 0:c5e2f793b59a 98
screamer 0:c5e2f793b59a 99 #define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
screamer 0:c5e2f793b59a 100
screamer 0:c5e2f793b59a 101 /*******************************************************************************
screamer 0:c5e2f793b59a 102 * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
screamer 0:c5e2f793b59a 103 ******************************************************************************/
screamer 0:c5e2f793b59a 104
screamer 0:c5e2f793b59a 105 /*!
screamer 0:c5e2f793b59a 106 * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
screamer 0:c5e2f793b59a 107 *
screamer 0:c5e2f793b59a 108 * Reset value: 0x10U
screamer 0:c5e2f793b59a 109 *
screamer 0:c5e2f793b59a 110 * This register contains status and control bits to support the low voltage
screamer 0:c5e2f793b59a 111 * detect function. This register should be written during the reset initialization
screamer 0:c5e2f793b59a 112 * program to set the desired controls even if the desired settings are the same
screamer 0:c5e2f793b59a 113 * as the reset settings. While the device is in the very low power or low
screamer 0:c5e2f793b59a 114 * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
screamer 0:c5e2f793b59a 115 * systems that must have LVD always on, configure the Power Mode Protection
screamer 0:c5e2f793b59a 116 * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
screamer 0:c5e2f793b59a 117 * low leakage modes from being enabled. See the device's data sheet for the
screamer 0:c5e2f793b59a 118 * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
screamer 0:c5e2f793b59a 119 * register's other bits are reset on Chip Reset Not VLLS. For more information
screamer 0:c5e2f793b59a 120 * about these reset types, refer to the Reset section details.
screamer 0:c5e2f793b59a 121 */
screamer 0:c5e2f793b59a 122 typedef union _hw_pmc_lvdsc1
screamer 0:c5e2f793b59a 123 {
screamer 0:c5e2f793b59a 124 uint8_t U;
screamer 0:c5e2f793b59a 125 struct _hw_pmc_lvdsc1_bitfields
screamer 0:c5e2f793b59a 126 {
screamer 0:c5e2f793b59a 127 uint8_t LVDV : 2; /*!< [1:0] Low-Voltage Detect Voltage Select */
screamer 0:c5e2f793b59a 128 uint8_t RESERVED0 : 2; /*!< [3:2] */
screamer 0:c5e2f793b59a 129 uint8_t LVDRE : 1; /*!< [4] Low-Voltage Detect Reset Enable */
screamer 0:c5e2f793b59a 130 uint8_t LVDIE : 1; /*!< [5] Low-Voltage Detect Interrupt Enable */
screamer 0:c5e2f793b59a 131 uint8_t LVDACK : 1; /*!< [6] Low-Voltage Detect Acknowledge */
screamer 0:c5e2f793b59a 132 uint8_t LVDF : 1; /*!< [7] Low-Voltage Detect Flag */
screamer 0:c5e2f793b59a 133 } B;
screamer 0:c5e2f793b59a 134 } hw_pmc_lvdsc1_t;
screamer 0:c5e2f793b59a 135
screamer 0:c5e2f793b59a 136 /*!
screamer 0:c5e2f793b59a 137 * @name Constants and macros for entire PMC_LVDSC1 register
screamer 0:c5e2f793b59a 138 */
screamer 0:c5e2f793b59a 139 /*@{*/
screamer 0:c5e2f793b59a 140 #define HW_PMC_LVDSC1_ADDR(x) ((x) + 0x0U)
screamer 0:c5e2f793b59a 141
screamer 0:c5e2f793b59a 142 #define HW_PMC_LVDSC1(x) (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
screamer 0:c5e2f793b59a 143 #define HW_PMC_LVDSC1_RD(x) (HW_PMC_LVDSC1(x).U)
screamer 0:c5e2f793b59a 144 #define HW_PMC_LVDSC1_WR(x, v) (HW_PMC_LVDSC1(x).U = (v))
screamer 0:c5e2f793b59a 145 #define HW_PMC_LVDSC1_SET(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) | (v)))
screamer 0:c5e2f793b59a 146 #define HW_PMC_LVDSC1_CLR(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 147 #define HW_PMC_LVDSC1_TOG(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 148 /*@}*/
screamer 0:c5e2f793b59a 149
screamer 0:c5e2f793b59a 150 /*
screamer 0:c5e2f793b59a 151 * Constants & macros for individual PMC_LVDSC1 bitfields
screamer 0:c5e2f793b59a 152 */
screamer 0:c5e2f793b59a 153
screamer 0:c5e2f793b59a 154 /*!
screamer 0:c5e2f793b59a 155 * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
screamer 0:c5e2f793b59a 156 *
screamer 0:c5e2f793b59a 157 * Selects the LVD trip point voltage (V LVD ).
screamer 0:c5e2f793b59a 158 *
screamer 0:c5e2f793b59a 159 * Values:
screamer 0:c5e2f793b59a 160 * - 00 - Low trip point selected (V LVD = V LVDL )
screamer 0:c5e2f793b59a 161 * - 01 - High trip point selected (V LVD = V LVDH )
screamer 0:c5e2f793b59a 162 * - 10 - Reserved
screamer 0:c5e2f793b59a 163 * - 11 - Reserved
screamer 0:c5e2f793b59a 164 */
screamer 0:c5e2f793b59a 165 /*@{*/
screamer 0:c5e2f793b59a 166 #define BP_PMC_LVDSC1_LVDV (0U) /*!< Bit position for PMC_LVDSC1_LVDV. */
screamer 0:c5e2f793b59a 167 #define BM_PMC_LVDSC1_LVDV (0x03U) /*!< Bit mask for PMC_LVDSC1_LVDV. */
screamer 0:c5e2f793b59a 168 #define BS_PMC_LVDSC1_LVDV (2U) /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
screamer 0:c5e2f793b59a 169
screamer 0:c5e2f793b59a 170 /*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
screamer 0:c5e2f793b59a 171 #define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV)
screamer 0:c5e2f793b59a 172
screamer 0:c5e2f793b59a 173 /*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
screamer 0:c5e2f793b59a 174 #define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
screamer 0:c5e2f793b59a 175
screamer 0:c5e2f793b59a 176 /*! @brief Set the LVDV field to a new value. */
screamer 0:c5e2f793b59a 177 #define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
screamer 0:c5e2f793b59a 178 /*@}*/
screamer 0:c5e2f793b59a 179
screamer 0:c5e2f793b59a 180 /*!
screamer 0:c5e2f793b59a 181 * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
screamer 0:c5e2f793b59a 182 *
screamer 0:c5e2f793b59a 183 * This write-once bit enables LVDF events to generate a hardware reset.
screamer 0:c5e2f793b59a 184 * Additional writes are ignored.
screamer 0:c5e2f793b59a 185 *
screamer 0:c5e2f793b59a 186 * Values:
screamer 0:c5e2f793b59a 187 * - 0 - LVDF does not generate hardware resets
screamer 0:c5e2f793b59a 188 * - 1 - Force an MCU reset when LVDF = 1
screamer 0:c5e2f793b59a 189 */
screamer 0:c5e2f793b59a 190 /*@{*/
screamer 0:c5e2f793b59a 191 #define BP_PMC_LVDSC1_LVDRE (4U) /*!< Bit position for PMC_LVDSC1_LVDRE. */
screamer 0:c5e2f793b59a 192 #define BM_PMC_LVDSC1_LVDRE (0x10U) /*!< Bit mask for PMC_LVDSC1_LVDRE. */
screamer 0:c5e2f793b59a 193 #define BS_PMC_LVDSC1_LVDRE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
screamer 0:c5e2f793b59a 194
screamer 0:c5e2f793b59a 195 /*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
screamer 0:c5e2f793b59a 196 #define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE))
screamer 0:c5e2f793b59a 197
screamer 0:c5e2f793b59a 198 /*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
screamer 0:c5e2f793b59a 199 #define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
screamer 0:c5e2f793b59a 200
screamer 0:c5e2f793b59a 201 /*! @brief Set the LVDRE field to a new value. */
screamer 0:c5e2f793b59a 202 #define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v))
screamer 0:c5e2f793b59a 203 /*@}*/
screamer 0:c5e2f793b59a 204
screamer 0:c5e2f793b59a 205 /*!
screamer 0:c5e2f793b59a 206 * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
screamer 0:c5e2f793b59a 207 *
screamer 0:c5e2f793b59a 208 * Enables hardware interrupt requests for LVDF.
screamer 0:c5e2f793b59a 209 *
screamer 0:c5e2f793b59a 210 * Values:
screamer 0:c5e2f793b59a 211 * - 0 - Hardware interrupt disabled (use polling)
screamer 0:c5e2f793b59a 212 * - 1 - Request a hardware interrupt when LVDF = 1
screamer 0:c5e2f793b59a 213 */
screamer 0:c5e2f793b59a 214 /*@{*/
screamer 0:c5e2f793b59a 215 #define BP_PMC_LVDSC1_LVDIE (5U) /*!< Bit position for PMC_LVDSC1_LVDIE. */
screamer 0:c5e2f793b59a 216 #define BM_PMC_LVDSC1_LVDIE (0x20U) /*!< Bit mask for PMC_LVDSC1_LVDIE. */
screamer 0:c5e2f793b59a 217 #define BS_PMC_LVDSC1_LVDIE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
screamer 0:c5e2f793b59a 218
screamer 0:c5e2f793b59a 219 /*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
screamer 0:c5e2f793b59a 220 #define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE))
screamer 0:c5e2f793b59a 221
screamer 0:c5e2f793b59a 222 /*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
screamer 0:c5e2f793b59a 223 #define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
screamer 0:c5e2f793b59a 224
screamer 0:c5e2f793b59a 225 /*! @brief Set the LVDIE field to a new value. */
screamer 0:c5e2f793b59a 226 #define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v))
screamer 0:c5e2f793b59a 227 /*@}*/
screamer 0:c5e2f793b59a 228
screamer 0:c5e2f793b59a 229 /*!
screamer 0:c5e2f793b59a 230 * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
screamer 0:c5e2f793b59a 231 *
screamer 0:c5e2f793b59a 232 * This write-only field is used to acknowledge low voltage detection errors.
screamer 0:c5e2f793b59a 233 * Write 1 to clear LVDF. Reads always return 0.
screamer 0:c5e2f793b59a 234 */
screamer 0:c5e2f793b59a 235 /*@{*/
screamer 0:c5e2f793b59a 236 #define BP_PMC_LVDSC1_LVDACK (6U) /*!< Bit position for PMC_LVDSC1_LVDACK. */
screamer 0:c5e2f793b59a 237 #define BM_PMC_LVDSC1_LVDACK (0x40U) /*!< Bit mask for PMC_LVDSC1_LVDACK. */
screamer 0:c5e2f793b59a 238 #define BS_PMC_LVDSC1_LVDACK (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
screamer 0:c5e2f793b59a 239
screamer 0:c5e2f793b59a 240 /*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
screamer 0:c5e2f793b59a 241 #define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
screamer 0:c5e2f793b59a 242
screamer 0:c5e2f793b59a 243 /*! @brief Set the LVDACK field to a new value. */
screamer 0:c5e2f793b59a 244 #define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v))
screamer 0:c5e2f793b59a 245 /*@}*/
screamer 0:c5e2f793b59a 246
screamer 0:c5e2f793b59a 247 /*!
screamer 0:c5e2f793b59a 248 * @name Register PMC_LVDSC1, field LVDF[7] (RO)
screamer 0:c5e2f793b59a 249 *
screamer 0:c5e2f793b59a 250 * This read-only status field indicates a low-voltage detect event.
screamer 0:c5e2f793b59a 251 *
screamer 0:c5e2f793b59a 252 * Values:
screamer 0:c5e2f793b59a 253 * - 0 - Low-voltage event not detected
screamer 0:c5e2f793b59a 254 * - 1 - Low-voltage event detected
screamer 0:c5e2f793b59a 255 */
screamer 0:c5e2f793b59a 256 /*@{*/
screamer 0:c5e2f793b59a 257 #define BP_PMC_LVDSC1_LVDF (7U) /*!< Bit position for PMC_LVDSC1_LVDF. */
screamer 0:c5e2f793b59a 258 #define BM_PMC_LVDSC1_LVDF (0x80U) /*!< Bit mask for PMC_LVDSC1_LVDF. */
screamer 0:c5e2f793b59a 259 #define BS_PMC_LVDSC1_LVDF (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
screamer 0:c5e2f793b59a 260
screamer 0:c5e2f793b59a 261 /*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
screamer 0:c5e2f793b59a 262 #define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF))
screamer 0:c5e2f793b59a 263 /*@}*/
screamer 0:c5e2f793b59a 264
screamer 0:c5e2f793b59a 265 /*******************************************************************************
screamer 0:c5e2f793b59a 266 * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
screamer 0:c5e2f793b59a 267 ******************************************************************************/
screamer 0:c5e2f793b59a 268
screamer 0:c5e2f793b59a 269 /*!
screamer 0:c5e2f793b59a 270 * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
screamer 0:c5e2f793b59a 271 *
screamer 0:c5e2f793b59a 272 * Reset value: 0x00U
screamer 0:c5e2f793b59a 273 *
screamer 0:c5e2f793b59a 274 * This register contains status and control bits to support the low voltage
screamer 0:c5e2f793b59a 275 * warning function. While the device is in the very low power or low leakage modes,
screamer 0:c5e2f793b59a 276 * the LVD system is disabled regardless of LVDSC2 settings. See the device's
screamer 0:c5e2f793b59a 277 * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
screamer 0:c5e2f793b59a 278 * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
screamer 0:c5e2f793b59a 279 * register are reset on Chip Reset Not VLLS. For more information about these
screamer 0:c5e2f793b59a 280 * reset types, refer to the Reset section details.
screamer 0:c5e2f793b59a 281 */
screamer 0:c5e2f793b59a 282 typedef union _hw_pmc_lvdsc2
screamer 0:c5e2f793b59a 283 {
screamer 0:c5e2f793b59a 284 uint8_t U;
screamer 0:c5e2f793b59a 285 struct _hw_pmc_lvdsc2_bitfields
screamer 0:c5e2f793b59a 286 {
screamer 0:c5e2f793b59a 287 uint8_t LVWV : 2; /*!< [1:0] Low-Voltage Warning Voltage Select */
screamer 0:c5e2f793b59a 288 uint8_t RESERVED0 : 3; /*!< [4:2] */
screamer 0:c5e2f793b59a 289 uint8_t LVWIE : 1; /*!< [5] Low-Voltage Warning Interrupt Enable */
screamer 0:c5e2f793b59a 290 uint8_t LVWACK : 1; /*!< [6] Low-Voltage Warning Acknowledge */
screamer 0:c5e2f793b59a 291 uint8_t LVWF : 1; /*!< [7] Low-Voltage Warning Flag */
screamer 0:c5e2f793b59a 292 } B;
screamer 0:c5e2f793b59a 293 } hw_pmc_lvdsc2_t;
screamer 0:c5e2f793b59a 294
screamer 0:c5e2f793b59a 295 /*!
screamer 0:c5e2f793b59a 296 * @name Constants and macros for entire PMC_LVDSC2 register
screamer 0:c5e2f793b59a 297 */
screamer 0:c5e2f793b59a 298 /*@{*/
screamer 0:c5e2f793b59a 299 #define HW_PMC_LVDSC2_ADDR(x) ((x) + 0x1U)
screamer 0:c5e2f793b59a 300
screamer 0:c5e2f793b59a 301 #define HW_PMC_LVDSC2(x) (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
screamer 0:c5e2f793b59a 302 #define HW_PMC_LVDSC2_RD(x) (HW_PMC_LVDSC2(x).U)
screamer 0:c5e2f793b59a 303 #define HW_PMC_LVDSC2_WR(x, v) (HW_PMC_LVDSC2(x).U = (v))
screamer 0:c5e2f793b59a 304 #define HW_PMC_LVDSC2_SET(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) | (v)))
screamer 0:c5e2f793b59a 305 #define HW_PMC_LVDSC2_CLR(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 306 #define HW_PMC_LVDSC2_TOG(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 307 /*@}*/
screamer 0:c5e2f793b59a 308
screamer 0:c5e2f793b59a 309 /*
screamer 0:c5e2f793b59a 310 * Constants & macros for individual PMC_LVDSC2 bitfields
screamer 0:c5e2f793b59a 311 */
screamer 0:c5e2f793b59a 312
screamer 0:c5e2f793b59a 313 /*!
screamer 0:c5e2f793b59a 314 * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
screamer 0:c5e2f793b59a 315 *
screamer 0:c5e2f793b59a 316 * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
screamer 0:c5e2f793b59a 317 * depends on LVDSC1[LVDV].
screamer 0:c5e2f793b59a 318 *
screamer 0:c5e2f793b59a 319 * Values:
screamer 0:c5e2f793b59a 320 * - 00 - Low trip point selected (VLVW = VLVW1)
screamer 0:c5e2f793b59a 321 * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
screamer 0:c5e2f793b59a 322 * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
screamer 0:c5e2f793b59a 323 * - 11 - High trip point selected (VLVW = VLVW4)
screamer 0:c5e2f793b59a 324 */
screamer 0:c5e2f793b59a 325 /*@{*/
screamer 0:c5e2f793b59a 326 #define BP_PMC_LVDSC2_LVWV (0U) /*!< Bit position for PMC_LVDSC2_LVWV. */
screamer 0:c5e2f793b59a 327 #define BM_PMC_LVDSC2_LVWV (0x03U) /*!< Bit mask for PMC_LVDSC2_LVWV. */
screamer 0:c5e2f793b59a 328 #define BS_PMC_LVDSC2_LVWV (2U) /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
screamer 0:c5e2f793b59a 329
screamer 0:c5e2f793b59a 330 /*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
screamer 0:c5e2f793b59a 331 #define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV)
screamer 0:c5e2f793b59a 332
screamer 0:c5e2f793b59a 333 /*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
screamer 0:c5e2f793b59a 334 #define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
screamer 0:c5e2f793b59a 335
screamer 0:c5e2f793b59a 336 /*! @brief Set the LVWV field to a new value. */
screamer 0:c5e2f793b59a 337 #define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
screamer 0:c5e2f793b59a 338 /*@}*/
screamer 0:c5e2f793b59a 339
screamer 0:c5e2f793b59a 340 /*!
screamer 0:c5e2f793b59a 341 * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
screamer 0:c5e2f793b59a 342 *
screamer 0:c5e2f793b59a 343 * Enables hardware interrupt requests for LVWF.
screamer 0:c5e2f793b59a 344 *
screamer 0:c5e2f793b59a 345 * Values:
screamer 0:c5e2f793b59a 346 * - 0 - Hardware interrupt disabled (use polling)
screamer 0:c5e2f793b59a 347 * - 1 - Request a hardware interrupt when LVWF = 1
screamer 0:c5e2f793b59a 348 */
screamer 0:c5e2f793b59a 349 /*@{*/
screamer 0:c5e2f793b59a 350 #define BP_PMC_LVDSC2_LVWIE (5U) /*!< Bit position for PMC_LVDSC2_LVWIE. */
screamer 0:c5e2f793b59a 351 #define BM_PMC_LVDSC2_LVWIE (0x20U) /*!< Bit mask for PMC_LVDSC2_LVWIE. */
screamer 0:c5e2f793b59a 352 #define BS_PMC_LVDSC2_LVWIE (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
screamer 0:c5e2f793b59a 353
screamer 0:c5e2f793b59a 354 /*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
screamer 0:c5e2f793b59a 355 #define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE))
screamer 0:c5e2f793b59a 356
screamer 0:c5e2f793b59a 357 /*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
screamer 0:c5e2f793b59a 358 #define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
screamer 0:c5e2f793b59a 359
screamer 0:c5e2f793b59a 360 /*! @brief Set the LVWIE field to a new value. */
screamer 0:c5e2f793b59a 361 #define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v))
screamer 0:c5e2f793b59a 362 /*@}*/
screamer 0:c5e2f793b59a 363
screamer 0:c5e2f793b59a 364 /*!
screamer 0:c5e2f793b59a 365 * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
screamer 0:c5e2f793b59a 366 *
screamer 0:c5e2f793b59a 367 * This write-only field is used to acknowledge low voltage warning errors.
screamer 0:c5e2f793b59a 368 * Write 1 to clear LVWF. Reads always return 0.
screamer 0:c5e2f793b59a 369 */
screamer 0:c5e2f793b59a 370 /*@{*/
screamer 0:c5e2f793b59a 371 #define BP_PMC_LVDSC2_LVWACK (6U) /*!< Bit position for PMC_LVDSC2_LVWACK. */
screamer 0:c5e2f793b59a 372 #define BM_PMC_LVDSC2_LVWACK (0x40U) /*!< Bit mask for PMC_LVDSC2_LVWACK. */
screamer 0:c5e2f793b59a 373 #define BS_PMC_LVDSC2_LVWACK (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
screamer 0:c5e2f793b59a 374
screamer 0:c5e2f793b59a 375 /*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
screamer 0:c5e2f793b59a 376 #define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
screamer 0:c5e2f793b59a 377
screamer 0:c5e2f793b59a 378 /*! @brief Set the LVWACK field to a new value. */
screamer 0:c5e2f793b59a 379 #define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v))
screamer 0:c5e2f793b59a 380 /*@}*/
screamer 0:c5e2f793b59a 381
screamer 0:c5e2f793b59a 382 /*!
screamer 0:c5e2f793b59a 383 * @name Register PMC_LVDSC2, field LVWF[7] (RO)
screamer 0:c5e2f793b59a 384 *
screamer 0:c5e2f793b59a 385 * This read-only status field indicates a low-voltage warning event. LVWF is
screamer 0:c5e2f793b59a 386 * set when VSupply transitions below the trip point, or after reset and VSupply is
screamer 0:c5e2f793b59a 387 * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
screamer 0:c5e2f793b59a 388 * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
screamer 0:c5e2f793b59a 389 * LVWACK first.
screamer 0:c5e2f793b59a 390 *
screamer 0:c5e2f793b59a 391 * Values:
screamer 0:c5e2f793b59a 392 * - 0 - Low-voltage warning event not detected
screamer 0:c5e2f793b59a 393 * - 1 - Low-voltage warning event detected
screamer 0:c5e2f793b59a 394 */
screamer 0:c5e2f793b59a 395 /*@{*/
screamer 0:c5e2f793b59a 396 #define BP_PMC_LVDSC2_LVWF (7U) /*!< Bit position for PMC_LVDSC2_LVWF. */
screamer 0:c5e2f793b59a 397 #define BM_PMC_LVDSC2_LVWF (0x80U) /*!< Bit mask for PMC_LVDSC2_LVWF. */
screamer 0:c5e2f793b59a 398 #define BS_PMC_LVDSC2_LVWF (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
screamer 0:c5e2f793b59a 399
screamer 0:c5e2f793b59a 400 /*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
screamer 0:c5e2f793b59a 401 #define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF))
screamer 0:c5e2f793b59a 402 /*@}*/
screamer 0:c5e2f793b59a 403
screamer 0:c5e2f793b59a 404 /*******************************************************************************
screamer 0:c5e2f793b59a 405 * HW_PMC_REGSC - Regulator Status And Control register
screamer 0:c5e2f793b59a 406 ******************************************************************************/
screamer 0:c5e2f793b59a 407
screamer 0:c5e2f793b59a 408 /*!
screamer 0:c5e2f793b59a 409 * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
screamer 0:c5e2f793b59a 410 *
screamer 0:c5e2f793b59a 411 * Reset value: 0x04U
screamer 0:c5e2f793b59a 412 *
screamer 0:c5e2f793b59a 413 * The PMC contains an internal voltage regulator. The voltage regulator design
screamer 0:c5e2f793b59a 414 * uses a bandgap reference that is also available through a buffer as input to
screamer 0:c5e2f793b59a 415 * certain internal peripherals, such as the CMP and ADC. The internal regulator
screamer 0:c5e2f793b59a 416 * provides a status bit (REGONS) indicating the regulator is in run regulation.
screamer 0:c5e2f793b59a 417 * This register is reset on Chip Reset Not VLLS and by reset types that trigger
screamer 0:c5e2f793b59a 418 * Chip Reset not VLLS. See the Reset section details for more information.
screamer 0:c5e2f793b59a 419 */
screamer 0:c5e2f793b59a 420 typedef union _hw_pmc_regsc
screamer 0:c5e2f793b59a 421 {
screamer 0:c5e2f793b59a 422 uint8_t U;
screamer 0:c5e2f793b59a 423 struct _hw_pmc_regsc_bitfields
screamer 0:c5e2f793b59a 424 {
screamer 0:c5e2f793b59a 425 uint8_t BGBE : 1; /*!< [0] Bandgap Buffer Enable */
screamer 0:c5e2f793b59a 426 uint8_t RESERVED0 : 1; /*!< [1] */
screamer 0:c5e2f793b59a 427 uint8_t REGONS : 1; /*!< [2] Regulator In Run Regulation Status */
screamer 0:c5e2f793b59a 428 uint8_t ACKISO : 1; /*!< [3] Acknowledge Isolation */
screamer 0:c5e2f793b59a 429 uint8_t BGEN : 1; /*!< [4] Bandgap Enable In VLPx Operation */
screamer 0:c5e2f793b59a 430 uint8_t RESERVED1 : 3; /*!< [7:5] */
screamer 0:c5e2f793b59a 431 } B;
screamer 0:c5e2f793b59a 432 } hw_pmc_regsc_t;
screamer 0:c5e2f793b59a 433
screamer 0:c5e2f793b59a 434 /*!
screamer 0:c5e2f793b59a 435 * @name Constants and macros for entire PMC_REGSC register
screamer 0:c5e2f793b59a 436 */
screamer 0:c5e2f793b59a 437 /*@{*/
screamer 0:c5e2f793b59a 438 #define HW_PMC_REGSC_ADDR(x) ((x) + 0x2U)
screamer 0:c5e2f793b59a 439
screamer 0:c5e2f793b59a 440 #define HW_PMC_REGSC(x) (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
screamer 0:c5e2f793b59a 441 #define HW_PMC_REGSC_RD(x) (HW_PMC_REGSC(x).U)
screamer 0:c5e2f793b59a 442 #define HW_PMC_REGSC_WR(x, v) (HW_PMC_REGSC(x).U = (v))
screamer 0:c5e2f793b59a 443 #define HW_PMC_REGSC_SET(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) | (v)))
screamer 0:c5e2f793b59a 444 #define HW_PMC_REGSC_CLR(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 445 #define HW_PMC_REGSC_TOG(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 446 /*@}*/
screamer 0:c5e2f793b59a 447
screamer 0:c5e2f793b59a 448 /*
screamer 0:c5e2f793b59a 449 * Constants & macros for individual PMC_REGSC bitfields
screamer 0:c5e2f793b59a 450 */
screamer 0:c5e2f793b59a 451
screamer 0:c5e2f793b59a 452 /*!
screamer 0:c5e2f793b59a 453 * @name Register PMC_REGSC, field BGBE[0] (RW)
screamer 0:c5e2f793b59a 454 *
screamer 0:c5e2f793b59a 455 * Enables the bandgap buffer.
screamer 0:c5e2f793b59a 456 *
screamer 0:c5e2f793b59a 457 * Values:
screamer 0:c5e2f793b59a 458 * - 0 - Bandgap buffer not enabled
screamer 0:c5e2f793b59a 459 * - 1 - Bandgap buffer enabled
screamer 0:c5e2f793b59a 460 */
screamer 0:c5e2f793b59a 461 /*@{*/
screamer 0:c5e2f793b59a 462 #define BP_PMC_REGSC_BGBE (0U) /*!< Bit position for PMC_REGSC_BGBE. */
screamer 0:c5e2f793b59a 463 #define BM_PMC_REGSC_BGBE (0x01U) /*!< Bit mask for PMC_REGSC_BGBE. */
screamer 0:c5e2f793b59a 464 #define BS_PMC_REGSC_BGBE (1U) /*!< Bit field size in bits for PMC_REGSC_BGBE. */
screamer 0:c5e2f793b59a 465
screamer 0:c5e2f793b59a 466 /*! @brief Read current value of the PMC_REGSC_BGBE field. */
screamer 0:c5e2f793b59a 467 #define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE))
screamer 0:c5e2f793b59a 468
screamer 0:c5e2f793b59a 469 /*! @brief Format value for bitfield PMC_REGSC_BGBE. */
screamer 0:c5e2f793b59a 470 #define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
screamer 0:c5e2f793b59a 471
screamer 0:c5e2f793b59a 472 /*! @brief Set the BGBE field to a new value. */
screamer 0:c5e2f793b59a 473 #define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v))
screamer 0:c5e2f793b59a 474 /*@}*/
screamer 0:c5e2f793b59a 475
screamer 0:c5e2f793b59a 476 /*!
screamer 0:c5e2f793b59a 477 * @name Register PMC_REGSC, field REGONS[2] (RO)
screamer 0:c5e2f793b59a 478 *
screamer 0:c5e2f793b59a 479 * This read-only field provides the current status of the internal voltage
screamer 0:c5e2f793b59a 480 * regulator.
screamer 0:c5e2f793b59a 481 *
screamer 0:c5e2f793b59a 482 * Values:
screamer 0:c5e2f793b59a 483 * - 0 - Regulator is in stop regulation or in transition to/from it
screamer 0:c5e2f793b59a 484 * - 1 - Regulator is in run regulation
screamer 0:c5e2f793b59a 485 */
screamer 0:c5e2f793b59a 486 /*@{*/
screamer 0:c5e2f793b59a 487 #define BP_PMC_REGSC_REGONS (2U) /*!< Bit position for PMC_REGSC_REGONS. */
screamer 0:c5e2f793b59a 488 #define BM_PMC_REGSC_REGONS (0x04U) /*!< Bit mask for PMC_REGSC_REGONS. */
screamer 0:c5e2f793b59a 489 #define BS_PMC_REGSC_REGONS (1U) /*!< Bit field size in bits for PMC_REGSC_REGONS. */
screamer 0:c5e2f793b59a 490
screamer 0:c5e2f793b59a 491 /*! @brief Read current value of the PMC_REGSC_REGONS field. */
screamer 0:c5e2f793b59a 492 #define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS))
screamer 0:c5e2f793b59a 493 /*@}*/
screamer 0:c5e2f793b59a 494
screamer 0:c5e2f793b59a 495 /*!
screamer 0:c5e2f793b59a 496 * @name Register PMC_REGSC, field ACKISO[3] (W1C)
screamer 0:c5e2f793b59a 497 *
screamer 0:c5e2f793b59a 498 * Reading this field indicates whether certain peripherals and the I/O pads are
screamer 0:c5e2f793b59a 499 * in a latched state as a result of having been in a VLLS mode. Writing 1 to
screamer 0:c5e2f793b59a 500 * this field when it is set releases the I/O pads and certain peripherals to their
screamer 0:c5e2f793b59a 501 * normal run mode state. After recovering from a VLLS mode, user should restore
screamer 0:c5e2f793b59a 502 * chip configuration before clearing ACKISO. In particular, pin configuration
screamer 0:c5e2f793b59a 503 * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
screamer 0:c5e2f793b59a 504 * being falsely set when ACKISO is cleared.
screamer 0:c5e2f793b59a 505 *
screamer 0:c5e2f793b59a 506 * Values:
screamer 0:c5e2f793b59a 507 * - 0 - Peripherals and I/O pads are in normal run state.
screamer 0:c5e2f793b59a 508 * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
screamer 0:c5e2f793b59a 509 */
screamer 0:c5e2f793b59a 510 /*@{*/
screamer 0:c5e2f793b59a 511 #define BP_PMC_REGSC_ACKISO (3U) /*!< Bit position for PMC_REGSC_ACKISO. */
screamer 0:c5e2f793b59a 512 #define BM_PMC_REGSC_ACKISO (0x08U) /*!< Bit mask for PMC_REGSC_ACKISO. */
screamer 0:c5e2f793b59a 513 #define BS_PMC_REGSC_ACKISO (1U) /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
screamer 0:c5e2f793b59a 514
screamer 0:c5e2f793b59a 515 /*! @brief Read current value of the PMC_REGSC_ACKISO field. */
screamer 0:c5e2f793b59a 516 #define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO))
screamer 0:c5e2f793b59a 517
screamer 0:c5e2f793b59a 518 /*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
screamer 0:c5e2f793b59a 519 #define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
screamer 0:c5e2f793b59a 520
screamer 0:c5e2f793b59a 521 /*! @brief Set the ACKISO field to a new value. */
screamer 0:c5e2f793b59a 522 #define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v))
screamer 0:c5e2f793b59a 523 /*@}*/
screamer 0:c5e2f793b59a 524
screamer 0:c5e2f793b59a 525 /*!
screamer 0:c5e2f793b59a 526 * @name Register PMC_REGSC, field BGEN[4] (RW)
screamer 0:c5e2f793b59a 527 *
screamer 0:c5e2f793b59a 528 * BGEN controls whether the bandgap is enabled in lower power modes of
screamer 0:c5e2f793b59a 529 * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
screamer 0:c5e2f793b59a 530 * reference in low power modes of operation, set BGEN to continue to enable the
screamer 0:c5e2f793b59a 531 * bandgap operation. When the bandgap voltage reference is not needed in low
screamer 0:c5e2f793b59a 532 * power modes, clear BGEN to avoid excess power consumption.
screamer 0:c5e2f793b59a 533 *
screamer 0:c5e2f793b59a 534 * Values:
screamer 0:c5e2f793b59a 535 * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
screamer 0:c5e2f793b59a 536 * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
screamer 0:c5e2f793b59a 537 */
screamer 0:c5e2f793b59a 538 /*@{*/
screamer 0:c5e2f793b59a 539 #define BP_PMC_REGSC_BGEN (4U) /*!< Bit position for PMC_REGSC_BGEN. */
screamer 0:c5e2f793b59a 540 #define BM_PMC_REGSC_BGEN (0x10U) /*!< Bit mask for PMC_REGSC_BGEN. */
screamer 0:c5e2f793b59a 541 #define BS_PMC_REGSC_BGEN (1U) /*!< Bit field size in bits for PMC_REGSC_BGEN. */
screamer 0:c5e2f793b59a 542
screamer 0:c5e2f793b59a 543 /*! @brief Read current value of the PMC_REGSC_BGEN field. */
screamer 0:c5e2f793b59a 544 #define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN))
screamer 0:c5e2f793b59a 545
screamer 0:c5e2f793b59a 546 /*! @brief Format value for bitfield PMC_REGSC_BGEN. */
screamer 0:c5e2f793b59a 547 #define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
screamer 0:c5e2f793b59a 548
screamer 0:c5e2f793b59a 549 /*! @brief Set the BGEN field to a new value. */
screamer 0:c5e2f793b59a 550 #define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v))
screamer 0:c5e2f793b59a 551 /*@}*/
screamer 0:c5e2f793b59a 552
screamer 0:c5e2f793b59a 553 /*******************************************************************************
screamer 0:c5e2f793b59a 554 * hw_pmc_t - module struct
screamer 0:c5e2f793b59a 555 ******************************************************************************/
screamer 0:c5e2f793b59a 556 /*!
screamer 0:c5e2f793b59a 557 * @brief All PMC module registers.
screamer 0:c5e2f793b59a 558 */
screamer 0:c5e2f793b59a 559 #pragma pack(1)
screamer 0:c5e2f793b59a 560 typedef struct _hw_pmc
screamer 0:c5e2f793b59a 561 {
screamer 0:c5e2f793b59a 562 __IO hw_pmc_lvdsc1_t LVDSC1; /*!< [0x0] Low Voltage Detect Status And Control 1 register */
screamer 0:c5e2f793b59a 563 __IO hw_pmc_lvdsc2_t LVDSC2; /*!< [0x1] Low Voltage Detect Status And Control 2 register */
screamer 0:c5e2f793b59a 564 __IO hw_pmc_regsc_t REGSC; /*!< [0x2] Regulator Status And Control register */
screamer 0:c5e2f793b59a 565 } hw_pmc_t;
screamer 0:c5e2f793b59a 566 #pragma pack()
screamer 0:c5e2f793b59a 567
screamer 0:c5e2f793b59a 568 /*! @brief Macro to access all PMC registers. */
screamer 0:c5e2f793b59a 569 /*! @param x PMC module instance base address. */
screamer 0:c5e2f793b59a 570 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
screamer 0:c5e2f793b59a 571 * use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
screamer 0:c5e2f793b59a 572 #define HW_PMC(x) (*(hw_pmc_t *)(x))
screamer 0:c5e2f793b59a 573
screamer 0:c5e2f793b59a 574 #endif /* __HW_PMC_REGISTERS_H__ */
screamer 0:c5e2f793b59a 575 /* EOF */