Morpheus / target-mcu-k64f

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hal/device/device/MK64F12/MK64F12_llwu.h@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 4 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 5 ** GNU C Compiler
screamer 0:c5e2f793b59a 6 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 9 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 10 ** Build: b140604
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Abstract:
screamer 0:c5e2f793b59a 13 ** Extension to the CMSIS register access layer header.
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 16 ** All rights reserved.
screamer 0:c5e2f793b59a 17 **
screamer 0:c5e2f793b59a 18 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 19 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 20 **
screamer 0:c5e2f793b59a 21 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 22 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 25 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 26 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 27 **
screamer 0:c5e2f793b59a 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 29 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 30 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 31 **
screamer 0:c5e2f793b59a 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 42 **
screamer 0:c5e2f793b59a 43 ** http: www.freescale.com
screamer 0:c5e2f793b59a 44 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 45 **
screamer 0:c5e2f793b59a 46 ** Revisions:
screamer 0:c5e2f793b59a 47 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 48 ** Initial version.
screamer 0:c5e2f793b59a 49 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 50 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 53 ** System initialization updated.
screamer 0:c5e2f793b59a 54 ** MCG - registers updated.
screamer 0:c5e2f793b59a 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 56 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 58 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 59 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 60 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 61 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 62 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 63 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 64 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 67 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 71 **
screamer 0:c5e2f793b59a 72 ** ###################################################################
screamer 0:c5e2f793b59a 73 */
screamer 0:c5e2f793b59a 74
screamer 0:c5e2f793b59a 75 /*
screamer 0:c5e2f793b59a 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
screamer 0:c5e2f793b59a 77 *
screamer 0:c5e2f793b59a 78 * This file was generated automatically and any changes may be lost.
screamer 0:c5e2f793b59a 79 */
screamer 0:c5e2f793b59a 80 #ifndef __HW_LLWU_REGISTERS_H__
screamer 0:c5e2f793b59a 81 #define __HW_LLWU_REGISTERS_H__
screamer 0:c5e2f793b59a 82
screamer 0:c5e2f793b59a 83 #include "MK64F12.h"
screamer 0:c5e2f793b59a 84 #include "fsl_bitaccess.h"
screamer 0:c5e2f793b59a 85
screamer 0:c5e2f793b59a 86 /*
screamer 0:c5e2f793b59a 87 * MK64F12 LLWU
screamer 0:c5e2f793b59a 88 *
screamer 0:c5e2f793b59a 89 * Low leakage wakeup unit
screamer 0:c5e2f793b59a 90 *
screamer 0:c5e2f793b59a 91 * Registers defined in this header file:
screamer 0:c5e2f793b59a 92 * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
screamer 0:c5e2f793b59a 93 * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
screamer 0:c5e2f793b59a 94 * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
screamer 0:c5e2f793b59a 95 * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
screamer 0:c5e2f793b59a 96 * - HW_LLWU_ME - LLWU Module Enable register
screamer 0:c5e2f793b59a 97 * - HW_LLWU_F1 - LLWU Flag 1 register
screamer 0:c5e2f793b59a 98 * - HW_LLWU_F2 - LLWU Flag 2 register
screamer 0:c5e2f793b59a 99 * - HW_LLWU_F3 - LLWU Flag 3 register
screamer 0:c5e2f793b59a 100 * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
screamer 0:c5e2f793b59a 101 * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
screamer 0:c5e2f793b59a 102 * - HW_LLWU_RST - LLWU Reset Enable register
screamer 0:c5e2f793b59a 103 *
screamer 0:c5e2f793b59a 104 * - hw_llwu_t - Struct containing all module registers.
screamer 0:c5e2f793b59a 105 */
screamer 0:c5e2f793b59a 106
screamer 0:c5e2f793b59a 107 #define HW_LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
screamer 0:c5e2f793b59a 108
screamer 0:c5e2f793b59a 109 /*******************************************************************************
screamer 0:c5e2f793b59a 110 * HW_LLWU_PE1 - LLWU Pin Enable 1 register
screamer 0:c5e2f793b59a 111 ******************************************************************************/
screamer 0:c5e2f793b59a 112
screamer 0:c5e2f793b59a 113 /*!
screamer 0:c5e2f793b59a 114 * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
screamer 0:c5e2f793b59a 115 *
screamer 0:c5e2f793b59a 116 * Reset value: 0x00U
screamer 0:c5e2f793b59a 117 *
screamer 0:c5e2f793b59a 118 * LLWU_PE1 contains the field to enable and select the edge detect type for the
screamer 0:c5e2f793b59a 119 * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
screamer 0:c5e2f793b59a 120 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 121 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 122 * IntroductionInformation found here describes the registers of the Reset Control Module
screamer 0:c5e2f793b59a 123 * (RCM). The RCM implements many of the reset functions for the chip. See the
screamer 0:c5e2f793b59a 124 * chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 125 */
screamer 0:c5e2f793b59a 126 typedef union _hw_llwu_pe1
screamer 0:c5e2f793b59a 127 {
screamer 0:c5e2f793b59a 128 uint8_t U;
screamer 0:c5e2f793b59a 129 struct _hw_llwu_pe1_bitfields
screamer 0:c5e2f793b59a 130 {
screamer 0:c5e2f793b59a 131 uint8_t WUPE0 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P0 */
screamer 0:c5e2f793b59a 132 uint8_t WUPE1 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P1 */
screamer 0:c5e2f793b59a 133 uint8_t WUPE2 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P2 */
screamer 0:c5e2f793b59a 134 uint8_t WUPE3 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P3 */
screamer 0:c5e2f793b59a 135 } B;
screamer 0:c5e2f793b59a 136 } hw_llwu_pe1_t;
screamer 0:c5e2f793b59a 137
screamer 0:c5e2f793b59a 138 /*!
screamer 0:c5e2f793b59a 139 * @name Constants and macros for entire LLWU_PE1 register
screamer 0:c5e2f793b59a 140 */
screamer 0:c5e2f793b59a 141 /*@{*/
screamer 0:c5e2f793b59a 142 #define HW_LLWU_PE1_ADDR(x) ((x) + 0x0U)
screamer 0:c5e2f793b59a 143
screamer 0:c5e2f793b59a 144 #define HW_LLWU_PE1(x) (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR(x))
screamer 0:c5e2f793b59a 145 #define HW_LLWU_PE1_RD(x) (HW_LLWU_PE1(x).U)
screamer 0:c5e2f793b59a 146 #define HW_LLWU_PE1_WR(x, v) (HW_LLWU_PE1(x).U = (v))
screamer 0:c5e2f793b59a 147 #define HW_LLWU_PE1_SET(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) | (v)))
screamer 0:c5e2f793b59a 148 #define HW_LLWU_PE1_CLR(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 149 #define HW_LLWU_PE1_TOG(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 150 /*@}*/
screamer 0:c5e2f793b59a 151
screamer 0:c5e2f793b59a 152 /*
screamer 0:c5e2f793b59a 153 * Constants & macros for individual LLWU_PE1 bitfields
screamer 0:c5e2f793b59a 154 */
screamer 0:c5e2f793b59a 155
screamer 0:c5e2f793b59a 156 /*!
screamer 0:c5e2f793b59a 157 * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
screamer 0:c5e2f793b59a 158 *
screamer 0:c5e2f793b59a 159 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 160 *
screamer 0:c5e2f793b59a 161 * Values:
screamer 0:c5e2f793b59a 162 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 163 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 164 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 165 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 166 */
screamer 0:c5e2f793b59a 167 /*@{*/
screamer 0:c5e2f793b59a 168 #define BP_LLWU_PE1_WUPE0 (0U) /*!< Bit position for LLWU_PE1_WUPE0. */
screamer 0:c5e2f793b59a 169 #define BM_LLWU_PE1_WUPE0 (0x03U) /*!< Bit mask for LLWU_PE1_WUPE0. */
screamer 0:c5e2f793b59a 170 #define BS_LLWU_PE1_WUPE0 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE0. */
screamer 0:c5e2f793b59a 171
screamer 0:c5e2f793b59a 172 /*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
screamer 0:c5e2f793b59a 173 #define BR_LLWU_PE1_WUPE0(x) (HW_LLWU_PE1(x).B.WUPE0)
screamer 0:c5e2f793b59a 174
screamer 0:c5e2f793b59a 175 /*! @brief Format value for bitfield LLWU_PE1_WUPE0. */
screamer 0:c5e2f793b59a 176 #define BF_LLWU_PE1_WUPE0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE0) & BM_LLWU_PE1_WUPE0)
screamer 0:c5e2f793b59a 177
screamer 0:c5e2f793b59a 178 /*! @brief Set the WUPE0 field to a new value. */
screamer 0:c5e2f793b59a 179 #define BW_LLWU_PE1_WUPE0(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
screamer 0:c5e2f793b59a 180 /*@}*/
screamer 0:c5e2f793b59a 181
screamer 0:c5e2f793b59a 182 /*!
screamer 0:c5e2f793b59a 183 * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
screamer 0:c5e2f793b59a 184 *
screamer 0:c5e2f793b59a 185 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 186 *
screamer 0:c5e2f793b59a 187 * Values:
screamer 0:c5e2f793b59a 188 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 189 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 190 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 191 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 192 */
screamer 0:c5e2f793b59a 193 /*@{*/
screamer 0:c5e2f793b59a 194 #define BP_LLWU_PE1_WUPE1 (2U) /*!< Bit position for LLWU_PE1_WUPE1. */
screamer 0:c5e2f793b59a 195 #define BM_LLWU_PE1_WUPE1 (0x0CU) /*!< Bit mask for LLWU_PE1_WUPE1. */
screamer 0:c5e2f793b59a 196 #define BS_LLWU_PE1_WUPE1 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE1. */
screamer 0:c5e2f793b59a 197
screamer 0:c5e2f793b59a 198 /*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
screamer 0:c5e2f793b59a 199 #define BR_LLWU_PE1_WUPE1(x) (HW_LLWU_PE1(x).B.WUPE1)
screamer 0:c5e2f793b59a 200
screamer 0:c5e2f793b59a 201 /*! @brief Format value for bitfield LLWU_PE1_WUPE1. */
screamer 0:c5e2f793b59a 202 #define BF_LLWU_PE1_WUPE1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE1) & BM_LLWU_PE1_WUPE1)
screamer 0:c5e2f793b59a 203
screamer 0:c5e2f793b59a 204 /*! @brief Set the WUPE1 field to a new value. */
screamer 0:c5e2f793b59a 205 #define BW_LLWU_PE1_WUPE1(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
screamer 0:c5e2f793b59a 206 /*@}*/
screamer 0:c5e2f793b59a 207
screamer 0:c5e2f793b59a 208 /*!
screamer 0:c5e2f793b59a 209 * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
screamer 0:c5e2f793b59a 210 *
screamer 0:c5e2f793b59a 211 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 212 *
screamer 0:c5e2f793b59a 213 * Values:
screamer 0:c5e2f793b59a 214 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 215 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 216 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 217 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 218 */
screamer 0:c5e2f793b59a 219 /*@{*/
screamer 0:c5e2f793b59a 220 #define BP_LLWU_PE1_WUPE2 (4U) /*!< Bit position for LLWU_PE1_WUPE2. */
screamer 0:c5e2f793b59a 221 #define BM_LLWU_PE1_WUPE2 (0x30U) /*!< Bit mask for LLWU_PE1_WUPE2. */
screamer 0:c5e2f793b59a 222 #define BS_LLWU_PE1_WUPE2 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE2. */
screamer 0:c5e2f793b59a 223
screamer 0:c5e2f793b59a 224 /*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
screamer 0:c5e2f793b59a 225 #define BR_LLWU_PE1_WUPE2(x) (HW_LLWU_PE1(x).B.WUPE2)
screamer 0:c5e2f793b59a 226
screamer 0:c5e2f793b59a 227 /*! @brief Format value for bitfield LLWU_PE1_WUPE2. */
screamer 0:c5e2f793b59a 228 #define BF_LLWU_PE1_WUPE2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE2) & BM_LLWU_PE1_WUPE2)
screamer 0:c5e2f793b59a 229
screamer 0:c5e2f793b59a 230 /*! @brief Set the WUPE2 field to a new value. */
screamer 0:c5e2f793b59a 231 #define BW_LLWU_PE1_WUPE2(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
screamer 0:c5e2f793b59a 232 /*@}*/
screamer 0:c5e2f793b59a 233
screamer 0:c5e2f793b59a 234 /*!
screamer 0:c5e2f793b59a 235 * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
screamer 0:c5e2f793b59a 236 *
screamer 0:c5e2f793b59a 237 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 238 *
screamer 0:c5e2f793b59a 239 * Values:
screamer 0:c5e2f793b59a 240 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 241 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 242 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 243 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 244 */
screamer 0:c5e2f793b59a 245 /*@{*/
screamer 0:c5e2f793b59a 246 #define BP_LLWU_PE1_WUPE3 (6U) /*!< Bit position for LLWU_PE1_WUPE3. */
screamer 0:c5e2f793b59a 247 #define BM_LLWU_PE1_WUPE3 (0xC0U) /*!< Bit mask for LLWU_PE1_WUPE3. */
screamer 0:c5e2f793b59a 248 #define BS_LLWU_PE1_WUPE3 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE3. */
screamer 0:c5e2f793b59a 249
screamer 0:c5e2f793b59a 250 /*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
screamer 0:c5e2f793b59a 251 #define BR_LLWU_PE1_WUPE3(x) (HW_LLWU_PE1(x).B.WUPE3)
screamer 0:c5e2f793b59a 252
screamer 0:c5e2f793b59a 253 /*! @brief Format value for bitfield LLWU_PE1_WUPE3. */
screamer 0:c5e2f793b59a 254 #define BF_LLWU_PE1_WUPE3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE3) & BM_LLWU_PE1_WUPE3)
screamer 0:c5e2f793b59a 255
screamer 0:c5e2f793b59a 256 /*! @brief Set the WUPE3 field to a new value. */
screamer 0:c5e2f793b59a 257 #define BW_LLWU_PE1_WUPE3(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
screamer 0:c5e2f793b59a 258 /*@}*/
screamer 0:c5e2f793b59a 259
screamer 0:c5e2f793b59a 260 /*******************************************************************************
screamer 0:c5e2f793b59a 261 * HW_LLWU_PE2 - LLWU Pin Enable 2 register
screamer 0:c5e2f793b59a 262 ******************************************************************************/
screamer 0:c5e2f793b59a 263
screamer 0:c5e2f793b59a 264 /*!
screamer 0:c5e2f793b59a 265 * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
screamer 0:c5e2f793b59a 266 *
screamer 0:c5e2f793b59a 267 * Reset value: 0x00U
screamer 0:c5e2f793b59a 268 *
screamer 0:c5e2f793b59a 269 * LLWU_PE2 contains the field to enable and select the edge detect type for the
screamer 0:c5e2f793b59a 270 * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
screamer 0:c5e2f793b59a 271 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 272 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 273 * IntroductionInformation found here describes the registers of the Reset Control Module
screamer 0:c5e2f793b59a 274 * (RCM). The RCM implements many of the reset functions for the chip. See the
screamer 0:c5e2f793b59a 275 * chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 276 */
screamer 0:c5e2f793b59a 277 typedef union _hw_llwu_pe2
screamer 0:c5e2f793b59a 278 {
screamer 0:c5e2f793b59a 279 uint8_t U;
screamer 0:c5e2f793b59a 280 struct _hw_llwu_pe2_bitfields
screamer 0:c5e2f793b59a 281 {
screamer 0:c5e2f793b59a 282 uint8_t WUPE4 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P4 */
screamer 0:c5e2f793b59a 283 uint8_t WUPE5 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P5 */
screamer 0:c5e2f793b59a 284 uint8_t WUPE6 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P6 */
screamer 0:c5e2f793b59a 285 uint8_t WUPE7 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P7 */
screamer 0:c5e2f793b59a 286 } B;
screamer 0:c5e2f793b59a 287 } hw_llwu_pe2_t;
screamer 0:c5e2f793b59a 288
screamer 0:c5e2f793b59a 289 /*!
screamer 0:c5e2f793b59a 290 * @name Constants and macros for entire LLWU_PE2 register
screamer 0:c5e2f793b59a 291 */
screamer 0:c5e2f793b59a 292 /*@{*/
screamer 0:c5e2f793b59a 293 #define HW_LLWU_PE2_ADDR(x) ((x) + 0x1U)
screamer 0:c5e2f793b59a 294
screamer 0:c5e2f793b59a 295 #define HW_LLWU_PE2(x) (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR(x))
screamer 0:c5e2f793b59a 296 #define HW_LLWU_PE2_RD(x) (HW_LLWU_PE2(x).U)
screamer 0:c5e2f793b59a 297 #define HW_LLWU_PE2_WR(x, v) (HW_LLWU_PE2(x).U = (v))
screamer 0:c5e2f793b59a 298 #define HW_LLWU_PE2_SET(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) | (v)))
screamer 0:c5e2f793b59a 299 #define HW_LLWU_PE2_CLR(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 300 #define HW_LLWU_PE2_TOG(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 301 /*@}*/
screamer 0:c5e2f793b59a 302
screamer 0:c5e2f793b59a 303 /*
screamer 0:c5e2f793b59a 304 * Constants & macros for individual LLWU_PE2 bitfields
screamer 0:c5e2f793b59a 305 */
screamer 0:c5e2f793b59a 306
screamer 0:c5e2f793b59a 307 /*!
screamer 0:c5e2f793b59a 308 * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
screamer 0:c5e2f793b59a 309 *
screamer 0:c5e2f793b59a 310 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 311 *
screamer 0:c5e2f793b59a 312 * Values:
screamer 0:c5e2f793b59a 313 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 314 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 315 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 316 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 317 */
screamer 0:c5e2f793b59a 318 /*@{*/
screamer 0:c5e2f793b59a 319 #define BP_LLWU_PE2_WUPE4 (0U) /*!< Bit position for LLWU_PE2_WUPE4. */
screamer 0:c5e2f793b59a 320 #define BM_LLWU_PE2_WUPE4 (0x03U) /*!< Bit mask for LLWU_PE2_WUPE4. */
screamer 0:c5e2f793b59a 321 #define BS_LLWU_PE2_WUPE4 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE4. */
screamer 0:c5e2f793b59a 322
screamer 0:c5e2f793b59a 323 /*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
screamer 0:c5e2f793b59a 324 #define BR_LLWU_PE2_WUPE4(x) (HW_LLWU_PE2(x).B.WUPE4)
screamer 0:c5e2f793b59a 325
screamer 0:c5e2f793b59a 326 /*! @brief Format value for bitfield LLWU_PE2_WUPE4. */
screamer 0:c5e2f793b59a 327 #define BF_LLWU_PE2_WUPE4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE4) & BM_LLWU_PE2_WUPE4)
screamer 0:c5e2f793b59a 328
screamer 0:c5e2f793b59a 329 /*! @brief Set the WUPE4 field to a new value. */
screamer 0:c5e2f793b59a 330 #define BW_LLWU_PE2_WUPE4(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
screamer 0:c5e2f793b59a 331 /*@}*/
screamer 0:c5e2f793b59a 332
screamer 0:c5e2f793b59a 333 /*!
screamer 0:c5e2f793b59a 334 * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
screamer 0:c5e2f793b59a 335 *
screamer 0:c5e2f793b59a 336 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 337 *
screamer 0:c5e2f793b59a 338 * Values:
screamer 0:c5e2f793b59a 339 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 340 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 341 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 342 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 343 */
screamer 0:c5e2f793b59a 344 /*@{*/
screamer 0:c5e2f793b59a 345 #define BP_LLWU_PE2_WUPE5 (2U) /*!< Bit position for LLWU_PE2_WUPE5. */
screamer 0:c5e2f793b59a 346 #define BM_LLWU_PE2_WUPE5 (0x0CU) /*!< Bit mask for LLWU_PE2_WUPE5. */
screamer 0:c5e2f793b59a 347 #define BS_LLWU_PE2_WUPE5 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE5. */
screamer 0:c5e2f793b59a 348
screamer 0:c5e2f793b59a 349 /*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
screamer 0:c5e2f793b59a 350 #define BR_LLWU_PE2_WUPE5(x) (HW_LLWU_PE2(x).B.WUPE5)
screamer 0:c5e2f793b59a 351
screamer 0:c5e2f793b59a 352 /*! @brief Format value for bitfield LLWU_PE2_WUPE5. */
screamer 0:c5e2f793b59a 353 #define BF_LLWU_PE2_WUPE5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE5) & BM_LLWU_PE2_WUPE5)
screamer 0:c5e2f793b59a 354
screamer 0:c5e2f793b59a 355 /*! @brief Set the WUPE5 field to a new value. */
screamer 0:c5e2f793b59a 356 #define BW_LLWU_PE2_WUPE5(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
screamer 0:c5e2f793b59a 357 /*@}*/
screamer 0:c5e2f793b59a 358
screamer 0:c5e2f793b59a 359 /*!
screamer 0:c5e2f793b59a 360 * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
screamer 0:c5e2f793b59a 361 *
screamer 0:c5e2f793b59a 362 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 363 *
screamer 0:c5e2f793b59a 364 * Values:
screamer 0:c5e2f793b59a 365 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 366 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 367 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 368 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 369 */
screamer 0:c5e2f793b59a 370 /*@{*/
screamer 0:c5e2f793b59a 371 #define BP_LLWU_PE2_WUPE6 (4U) /*!< Bit position for LLWU_PE2_WUPE6. */
screamer 0:c5e2f793b59a 372 #define BM_LLWU_PE2_WUPE6 (0x30U) /*!< Bit mask for LLWU_PE2_WUPE6. */
screamer 0:c5e2f793b59a 373 #define BS_LLWU_PE2_WUPE6 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE6. */
screamer 0:c5e2f793b59a 374
screamer 0:c5e2f793b59a 375 /*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
screamer 0:c5e2f793b59a 376 #define BR_LLWU_PE2_WUPE6(x) (HW_LLWU_PE2(x).B.WUPE6)
screamer 0:c5e2f793b59a 377
screamer 0:c5e2f793b59a 378 /*! @brief Format value for bitfield LLWU_PE2_WUPE6. */
screamer 0:c5e2f793b59a 379 #define BF_LLWU_PE2_WUPE6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE6) & BM_LLWU_PE2_WUPE6)
screamer 0:c5e2f793b59a 380
screamer 0:c5e2f793b59a 381 /*! @brief Set the WUPE6 field to a new value. */
screamer 0:c5e2f793b59a 382 #define BW_LLWU_PE2_WUPE6(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
screamer 0:c5e2f793b59a 383 /*@}*/
screamer 0:c5e2f793b59a 384
screamer 0:c5e2f793b59a 385 /*!
screamer 0:c5e2f793b59a 386 * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
screamer 0:c5e2f793b59a 387 *
screamer 0:c5e2f793b59a 388 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 389 *
screamer 0:c5e2f793b59a 390 * Values:
screamer 0:c5e2f793b59a 391 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 392 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 393 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 394 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 395 */
screamer 0:c5e2f793b59a 396 /*@{*/
screamer 0:c5e2f793b59a 397 #define BP_LLWU_PE2_WUPE7 (6U) /*!< Bit position for LLWU_PE2_WUPE7. */
screamer 0:c5e2f793b59a 398 #define BM_LLWU_PE2_WUPE7 (0xC0U) /*!< Bit mask for LLWU_PE2_WUPE7. */
screamer 0:c5e2f793b59a 399 #define BS_LLWU_PE2_WUPE7 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE7. */
screamer 0:c5e2f793b59a 400
screamer 0:c5e2f793b59a 401 /*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
screamer 0:c5e2f793b59a 402 #define BR_LLWU_PE2_WUPE7(x) (HW_LLWU_PE2(x).B.WUPE7)
screamer 0:c5e2f793b59a 403
screamer 0:c5e2f793b59a 404 /*! @brief Format value for bitfield LLWU_PE2_WUPE7. */
screamer 0:c5e2f793b59a 405 #define BF_LLWU_PE2_WUPE7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE7) & BM_LLWU_PE2_WUPE7)
screamer 0:c5e2f793b59a 406
screamer 0:c5e2f793b59a 407 /*! @brief Set the WUPE7 field to a new value. */
screamer 0:c5e2f793b59a 408 #define BW_LLWU_PE2_WUPE7(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
screamer 0:c5e2f793b59a 409 /*@}*/
screamer 0:c5e2f793b59a 410
screamer 0:c5e2f793b59a 411 /*******************************************************************************
screamer 0:c5e2f793b59a 412 * HW_LLWU_PE3 - LLWU Pin Enable 3 register
screamer 0:c5e2f793b59a 413 ******************************************************************************/
screamer 0:c5e2f793b59a 414
screamer 0:c5e2f793b59a 415 /*!
screamer 0:c5e2f793b59a 416 * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
screamer 0:c5e2f793b59a 417 *
screamer 0:c5e2f793b59a 418 * Reset value: 0x00U
screamer 0:c5e2f793b59a 419 *
screamer 0:c5e2f793b59a 420 * LLWU_PE3 contains the field to enable and select the edge detect type for the
screamer 0:c5e2f793b59a 421 * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
screamer 0:c5e2f793b59a 422 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 423 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 424 * IntroductionInformation found here describes the registers of the Reset Control Module
screamer 0:c5e2f793b59a 425 * (RCM). The RCM implements many of the reset functions for the chip. See the
screamer 0:c5e2f793b59a 426 * chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 427 */
screamer 0:c5e2f793b59a 428 typedef union _hw_llwu_pe3
screamer 0:c5e2f793b59a 429 {
screamer 0:c5e2f793b59a 430 uint8_t U;
screamer 0:c5e2f793b59a 431 struct _hw_llwu_pe3_bitfields
screamer 0:c5e2f793b59a 432 {
screamer 0:c5e2f793b59a 433 uint8_t WUPE8 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P8 */
screamer 0:c5e2f793b59a 434 uint8_t WUPE9 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P9 */
screamer 0:c5e2f793b59a 435 uint8_t WUPE10 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P10 */
screamer 0:c5e2f793b59a 436 uint8_t WUPE11 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P11 */
screamer 0:c5e2f793b59a 437 } B;
screamer 0:c5e2f793b59a 438 } hw_llwu_pe3_t;
screamer 0:c5e2f793b59a 439
screamer 0:c5e2f793b59a 440 /*!
screamer 0:c5e2f793b59a 441 * @name Constants and macros for entire LLWU_PE3 register
screamer 0:c5e2f793b59a 442 */
screamer 0:c5e2f793b59a 443 /*@{*/
screamer 0:c5e2f793b59a 444 #define HW_LLWU_PE3_ADDR(x) ((x) + 0x2U)
screamer 0:c5e2f793b59a 445
screamer 0:c5e2f793b59a 446 #define HW_LLWU_PE3(x) (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR(x))
screamer 0:c5e2f793b59a 447 #define HW_LLWU_PE3_RD(x) (HW_LLWU_PE3(x).U)
screamer 0:c5e2f793b59a 448 #define HW_LLWU_PE3_WR(x, v) (HW_LLWU_PE3(x).U = (v))
screamer 0:c5e2f793b59a 449 #define HW_LLWU_PE3_SET(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) | (v)))
screamer 0:c5e2f793b59a 450 #define HW_LLWU_PE3_CLR(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 451 #define HW_LLWU_PE3_TOG(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 452 /*@}*/
screamer 0:c5e2f793b59a 453
screamer 0:c5e2f793b59a 454 /*
screamer 0:c5e2f793b59a 455 * Constants & macros for individual LLWU_PE3 bitfields
screamer 0:c5e2f793b59a 456 */
screamer 0:c5e2f793b59a 457
screamer 0:c5e2f793b59a 458 /*!
screamer 0:c5e2f793b59a 459 * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
screamer 0:c5e2f793b59a 460 *
screamer 0:c5e2f793b59a 461 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 462 *
screamer 0:c5e2f793b59a 463 * Values:
screamer 0:c5e2f793b59a 464 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 465 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 466 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 467 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 468 */
screamer 0:c5e2f793b59a 469 /*@{*/
screamer 0:c5e2f793b59a 470 #define BP_LLWU_PE3_WUPE8 (0U) /*!< Bit position for LLWU_PE3_WUPE8. */
screamer 0:c5e2f793b59a 471 #define BM_LLWU_PE3_WUPE8 (0x03U) /*!< Bit mask for LLWU_PE3_WUPE8. */
screamer 0:c5e2f793b59a 472 #define BS_LLWU_PE3_WUPE8 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE8. */
screamer 0:c5e2f793b59a 473
screamer 0:c5e2f793b59a 474 /*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
screamer 0:c5e2f793b59a 475 #define BR_LLWU_PE3_WUPE8(x) (HW_LLWU_PE3(x).B.WUPE8)
screamer 0:c5e2f793b59a 476
screamer 0:c5e2f793b59a 477 /*! @brief Format value for bitfield LLWU_PE3_WUPE8. */
screamer 0:c5e2f793b59a 478 #define BF_LLWU_PE3_WUPE8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE8) & BM_LLWU_PE3_WUPE8)
screamer 0:c5e2f793b59a 479
screamer 0:c5e2f793b59a 480 /*! @brief Set the WUPE8 field to a new value. */
screamer 0:c5e2f793b59a 481 #define BW_LLWU_PE3_WUPE8(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
screamer 0:c5e2f793b59a 482 /*@}*/
screamer 0:c5e2f793b59a 483
screamer 0:c5e2f793b59a 484 /*!
screamer 0:c5e2f793b59a 485 * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
screamer 0:c5e2f793b59a 486 *
screamer 0:c5e2f793b59a 487 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 488 *
screamer 0:c5e2f793b59a 489 * Values:
screamer 0:c5e2f793b59a 490 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 491 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 492 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 493 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 494 */
screamer 0:c5e2f793b59a 495 /*@{*/
screamer 0:c5e2f793b59a 496 #define BP_LLWU_PE3_WUPE9 (2U) /*!< Bit position for LLWU_PE3_WUPE9. */
screamer 0:c5e2f793b59a 497 #define BM_LLWU_PE3_WUPE9 (0x0CU) /*!< Bit mask for LLWU_PE3_WUPE9. */
screamer 0:c5e2f793b59a 498 #define BS_LLWU_PE3_WUPE9 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE9. */
screamer 0:c5e2f793b59a 499
screamer 0:c5e2f793b59a 500 /*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
screamer 0:c5e2f793b59a 501 #define BR_LLWU_PE3_WUPE9(x) (HW_LLWU_PE3(x).B.WUPE9)
screamer 0:c5e2f793b59a 502
screamer 0:c5e2f793b59a 503 /*! @brief Format value for bitfield LLWU_PE3_WUPE9. */
screamer 0:c5e2f793b59a 504 #define BF_LLWU_PE3_WUPE9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE9) & BM_LLWU_PE3_WUPE9)
screamer 0:c5e2f793b59a 505
screamer 0:c5e2f793b59a 506 /*! @brief Set the WUPE9 field to a new value. */
screamer 0:c5e2f793b59a 507 #define BW_LLWU_PE3_WUPE9(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
screamer 0:c5e2f793b59a 508 /*@}*/
screamer 0:c5e2f793b59a 509
screamer 0:c5e2f793b59a 510 /*!
screamer 0:c5e2f793b59a 511 * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
screamer 0:c5e2f793b59a 512 *
screamer 0:c5e2f793b59a 513 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 514 *
screamer 0:c5e2f793b59a 515 * Values:
screamer 0:c5e2f793b59a 516 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 517 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 518 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 519 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 520 */
screamer 0:c5e2f793b59a 521 /*@{*/
screamer 0:c5e2f793b59a 522 #define BP_LLWU_PE3_WUPE10 (4U) /*!< Bit position for LLWU_PE3_WUPE10. */
screamer 0:c5e2f793b59a 523 #define BM_LLWU_PE3_WUPE10 (0x30U) /*!< Bit mask for LLWU_PE3_WUPE10. */
screamer 0:c5e2f793b59a 524 #define BS_LLWU_PE3_WUPE10 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE10. */
screamer 0:c5e2f793b59a 525
screamer 0:c5e2f793b59a 526 /*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
screamer 0:c5e2f793b59a 527 #define BR_LLWU_PE3_WUPE10(x) (HW_LLWU_PE3(x).B.WUPE10)
screamer 0:c5e2f793b59a 528
screamer 0:c5e2f793b59a 529 /*! @brief Format value for bitfield LLWU_PE3_WUPE10. */
screamer 0:c5e2f793b59a 530 #define BF_LLWU_PE3_WUPE10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE10) & BM_LLWU_PE3_WUPE10)
screamer 0:c5e2f793b59a 531
screamer 0:c5e2f793b59a 532 /*! @brief Set the WUPE10 field to a new value. */
screamer 0:c5e2f793b59a 533 #define BW_LLWU_PE3_WUPE10(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
screamer 0:c5e2f793b59a 534 /*@}*/
screamer 0:c5e2f793b59a 535
screamer 0:c5e2f793b59a 536 /*!
screamer 0:c5e2f793b59a 537 * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
screamer 0:c5e2f793b59a 538 *
screamer 0:c5e2f793b59a 539 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 540 *
screamer 0:c5e2f793b59a 541 * Values:
screamer 0:c5e2f793b59a 542 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 543 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 544 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 545 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 546 */
screamer 0:c5e2f793b59a 547 /*@{*/
screamer 0:c5e2f793b59a 548 #define BP_LLWU_PE3_WUPE11 (6U) /*!< Bit position for LLWU_PE3_WUPE11. */
screamer 0:c5e2f793b59a 549 #define BM_LLWU_PE3_WUPE11 (0xC0U) /*!< Bit mask for LLWU_PE3_WUPE11. */
screamer 0:c5e2f793b59a 550 #define BS_LLWU_PE3_WUPE11 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE11. */
screamer 0:c5e2f793b59a 551
screamer 0:c5e2f793b59a 552 /*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
screamer 0:c5e2f793b59a 553 #define BR_LLWU_PE3_WUPE11(x) (HW_LLWU_PE3(x).B.WUPE11)
screamer 0:c5e2f793b59a 554
screamer 0:c5e2f793b59a 555 /*! @brief Format value for bitfield LLWU_PE3_WUPE11. */
screamer 0:c5e2f793b59a 556 #define BF_LLWU_PE3_WUPE11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE11) & BM_LLWU_PE3_WUPE11)
screamer 0:c5e2f793b59a 557
screamer 0:c5e2f793b59a 558 /*! @brief Set the WUPE11 field to a new value. */
screamer 0:c5e2f793b59a 559 #define BW_LLWU_PE3_WUPE11(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
screamer 0:c5e2f793b59a 560 /*@}*/
screamer 0:c5e2f793b59a 561
screamer 0:c5e2f793b59a 562 /*******************************************************************************
screamer 0:c5e2f793b59a 563 * HW_LLWU_PE4 - LLWU Pin Enable 4 register
screamer 0:c5e2f793b59a 564 ******************************************************************************/
screamer 0:c5e2f793b59a 565
screamer 0:c5e2f793b59a 566 /*!
screamer 0:c5e2f793b59a 567 * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
screamer 0:c5e2f793b59a 568 *
screamer 0:c5e2f793b59a 569 * Reset value: 0x00U
screamer 0:c5e2f793b59a 570 *
screamer 0:c5e2f793b59a 571 * LLWU_PE4 contains the field to enable and select the edge detect type for the
screamer 0:c5e2f793b59a 572 * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
screamer 0:c5e2f793b59a 573 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 574 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 575 * IntroductionInformation found here describes the registers of the Reset Control
screamer 0:c5e2f793b59a 576 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
screamer 0:c5e2f793b59a 577 * chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 578 */
screamer 0:c5e2f793b59a 579 typedef union _hw_llwu_pe4
screamer 0:c5e2f793b59a 580 {
screamer 0:c5e2f793b59a 581 uint8_t U;
screamer 0:c5e2f793b59a 582 struct _hw_llwu_pe4_bitfields
screamer 0:c5e2f793b59a 583 {
screamer 0:c5e2f793b59a 584 uint8_t WUPE12 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P12 */
screamer 0:c5e2f793b59a 585 uint8_t WUPE13 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P13 */
screamer 0:c5e2f793b59a 586 uint8_t WUPE14 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P14 */
screamer 0:c5e2f793b59a 587 uint8_t WUPE15 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P15 */
screamer 0:c5e2f793b59a 588 } B;
screamer 0:c5e2f793b59a 589 } hw_llwu_pe4_t;
screamer 0:c5e2f793b59a 590
screamer 0:c5e2f793b59a 591 /*!
screamer 0:c5e2f793b59a 592 * @name Constants and macros for entire LLWU_PE4 register
screamer 0:c5e2f793b59a 593 */
screamer 0:c5e2f793b59a 594 /*@{*/
screamer 0:c5e2f793b59a 595 #define HW_LLWU_PE4_ADDR(x) ((x) + 0x3U)
screamer 0:c5e2f793b59a 596
screamer 0:c5e2f793b59a 597 #define HW_LLWU_PE4(x) (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR(x))
screamer 0:c5e2f793b59a 598 #define HW_LLWU_PE4_RD(x) (HW_LLWU_PE4(x).U)
screamer 0:c5e2f793b59a 599 #define HW_LLWU_PE4_WR(x, v) (HW_LLWU_PE4(x).U = (v))
screamer 0:c5e2f793b59a 600 #define HW_LLWU_PE4_SET(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) | (v)))
screamer 0:c5e2f793b59a 601 #define HW_LLWU_PE4_CLR(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 602 #define HW_LLWU_PE4_TOG(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 603 /*@}*/
screamer 0:c5e2f793b59a 604
screamer 0:c5e2f793b59a 605 /*
screamer 0:c5e2f793b59a 606 * Constants & macros for individual LLWU_PE4 bitfields
screamer 0:c5e2f793b59a 607 */
screamer 0:c5e2f793b59a 608
screamer 0:c5e2f793b59a 609 /*!
screamer 0:c5e2f793b59a 610 * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
screamer 0:c5e2f793b59a 611 *
screamer 0:c5e2f793b59a 612 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 613 *
screamer 0:c5e2f793b59a 614 * Values:
screamer 0:c5e2f793b59a 615 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 616 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 617 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 618 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 619 */
screamer 0:c5e2f793b59a 620 /*@{*/
screamer 0:c5e2f793b59a 621 #define BP_LLWU_PE4_WUPE12 (0U) /*!< Bit position for LLWU_PE4_WUPE12. */
screamer 0:c5e2f793b59a 622 #define BM_LLWU_PE4_WUPE12 (0x03U) /*!< Bit mask for LLWU_PE4_WUPE12. */
screamer 0:c5e2f793b59a 623 #define BS_LLWU_PE4_WUPE12 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE12. */
screamer 0:c5e2f793b59a 624
screamer 0:c5e2f793b59a 625 /*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
screamer 0:c5e2f793b59a 626 #define BR_LLWU_PE4_WUPE12(x) (HW_LLWU_PE4(x).B.WUPE12)
screamer 0:c5e2f793b59a 627
screamer 0:c5e2f793b59a 628 /*! @brief Format value for bitfield LLWU_PE4_WUPE12. */
screamer 0:c5e2f793b59a 629 #define BF_LLWU_PE4_WUPE12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE12) & BM_LLWU_PE4_WUPE12)
screamer 0:c5e2f793b59a 630
screamer 0:c5e2f793b59a 631 /*! @brief Set the WUPE12 field to a new value. */
screamer 0:c5e2f793b59a 632 #define BW_LLWU_PE4_WUPE12(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
screamer 0:c5e2f793b59a 633 /*@}*/
screamer 0:c5e2f793b59a 634
screamer 0:c5e2f793b59a 635 /*!
screamer 0:c5e2f793b59a 636 * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
screamer 0:c5e2f793b59a 637 *
screamer 0:c5e2f793b59a 638 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 639 *
screamer 0:c5e2f793b59a 640 * Values:
screamer 0:c5e2f793b59a 641 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 642 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 643 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 644 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 645 */
screamer 0:c5e2f793b59a 646 /*@{*/
screamer 0:c5e2f793b59a 647 #define BP_LLWU_PE4_WUPE13 (2U) /*!< Bit position for LLWU_PE4_WUPE13. */
screamer 0:c5e2f793b59a 648 #define BM_LLWU_PE4_WUPE13 (0x0CU) /*!< Bit mask for LLWU_PE4_WUPE13. */
screamer 0:c5e2f793b59a 649 #define BS_LLWU_PE4_WUPE13 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE13. */
screamer 0:c5e2f793b59a 650
screamer 0:c5e2f793b59a 651 /*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
screamer 0:c5e2f793b59a 652 #define BR_LLWU_PE4_WUPE13(x) (HW_LLWU_PE4(x).B.WUPE13)
screamer 0:c5e2f793b59a 653
screamer 0:c5e2f793b59a 654 /*! @brief Format value for bitfield LLWU_PE4_WUPE13. */
screamer 0:c5e2f793b59a 655 #define BF_LLWU_PE4_WUPE13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE13) & BM_LLWU_PE4_WUPE13)
screamer 0:c5e2f793b59a 656
screamer 0:c5e2f793b59a 657 /*! @brief Set the WUPE13 field to a new value. */
screamer 0:c5e2f793b59a 658 #define BW_LLWU_PE4_WUPE13(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
screamer 0:c5e2f793b59a 659 /*@}*/
screamer 0:c5e2f793b59a 660
screamer 0:c5e2f793b59a 661 /*!
screamer 0:c5e2f793b59a 662 * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
screamer 0:c5e2f793b59a 663 *
screamer 0:c5e2f793b59a 664 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 665 *
screamer 0:c5e2f793b59a 666 * Values:
screamer 0:c5e2f793b59a 667 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 668 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 669 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 670 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 671 */
screamer 0:c5e2f793b59a 672 /*@{*/
screamer 0:c5e2f793b59a 673 #define BP_LLWU_PE4_WUPE14 (4U) /*!< Bit position for LLWU_PE4_WUPE14. */
screamer 0:c5e2f793b59a 674 #define BM_LLWU_PE4_WUPE14 (0x30U) /*!< Bit mask for LLWU_PE4_WUPE14. */
screamer 0:c5e2f793b59a 675 #define BS_LLWU_PE4_WUPE14 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE14. */
screamer 0:c5e2f793b59a 676
screamer 0:c5e2f793b59a 677 /*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
screamer 0:c5e2f793b59a 678 #define BR_LLWU_PE4_WUPE14(x) (HW_LLWU_PE4(x).B.WUPE14)
screamer 0:c5e2f793b59a 679
screamer 0:c5e2f793b59a 680 /*! @brief Format value for bitfield LLWU_PE4_WUPE14. */
screamer 0:c5e2f793b59a 681 #define BF_LLWU_PE4_WUPE14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE14) & BM_LLWU_PE4_WUPE14)
screamer 0:c5e2f793b59a 682
screamer 0:c5e2f793b59a 683 /*! @brief Set the WUPE14 field to a new value. */
screamer 0:c5e2f793b59a 684 #define BW_LLWU_PE4_WUPE14(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
screamer 0:c5e2f793b59a 685 /*@}*/
screamer 0:c5e2f793b59a 686
screamer 0:c5e2f793b59a 687 /*!
screamer 0:c5e2f793b59a 688 * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
screamer 0:c5e2f793b59a 689 *
screamer 0:c5e2f793b59a 690 * Enables and configures the edge detection for the wakeup pin.
screamer 0:c5e2f793b59a 691 *
screamer 0:c5e2f793b59a 692 * Values:
screamer 0:c5e2f793b59a 693 * - 00 - External input pin disabled as wakeup input
screamer 0:c5e2f793b59a 694 * - 01 - External input pin enabled with rising edge detection
screamer 0:c5e2f793b59a 695 * - 10 - External input pin enabled with falling edge detection
screamer 0:c5e2f793b59a 696 * - 11 - External input pin enabled with any change detection
screamer 0:c5e2f793b59a 697 */
screamer 0:c5e2f793b59a 698 /*@{*/
screamer 0:c5e2f793b59a 699 #define BP_LLWU_PE4_WUPE15 (6U) /*!< Bit position for LLWU_PE4_WUPE15. */
screamer 0:c5e2f793b59a 700 #define BM_LLWU_PE4_WUPE15 (0xC0U) /*!< Bit mask for LLWU_PE4_WUPE15. */
screamer 0:c5e2f793b59a 701 #define BS_LLWU_PE4_WUPE15 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE15. */
screamer 0:c5e2f793b59a 702
screamer 0:c5e2f793b59a 703 /*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
screamer 0:c5e2f793b59a 704 #define BR_LLWU_PE4_WUPE15(x) (HW_LLWU_PE4(x).B.WUPE15)
screamer 0:c5e2f793b59a 705
screamer 0:c5e2f793b59a 706 /*! @brief Format value for bitfield LLWU_PE4_WUPE15. */
screamer 0:c5e2f793b59a 707 #define BF_LLWU_PE4_WUPE15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE15) & BM_LLWU_PE4_WUPE15)
screamer 0:c5e2f793b59a 708
screamer 0:c5e2f793b59a 709 /*! @brief Set the WUPE15 field to a new value. */
screamer 0:c5e2f793b59a 710 #define BW_LLWU_PE4_WUPE15(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
screamer 0:c5e2f793b59a 711 /*@}*/
screamer 0:c5e2f793b59a 712
screamer 0:c5e2f793b59a 713 /*******************************************************************************
screamer 0:c5e2f793b59a 714 * HW_LLWU_ME - LLWU Module Enable register
screamer 0:c5e2f793b59a 715 ******************************************************************************/
screamer 0:c5e2f793b59a 716
screamer 0:c5e2f793b59a 717 /*!
screamer 0:c5e2f793b59a 718 * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
screamer 0:c5e2f793b59a 719 *
screamer 0:c5e2f793b59a 720 * Reset value: 0x00U
screamer 0:c5e2f793b59a 721 *
screamer 0:c5e2f793b59a 722 * LLWU_ME contains the bits to enable the internal module flag as a wakeup
screamer 0:c5e2f793b59a 723 * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
screamer 0:c5e2f793b59a 724 * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
screamer 0:c5e2f793b59a 725 * reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 726 * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
screamer 0:c5e2f793b59a 727 * RCM implements many of the reset functions for the chip. See the chip's reset
screamer 0:c5e2f793b59a 728 * chapter for more information. details for more information.
screamer 0:c5e2f793b59a 729 */
screamer 0:c5e2f793b59a 730 typedef union _hw_llwu_me
screamer 0:c5e2f793b59a 731 {
screamer 0:c5e2f793b59a 732 uint8_t U;
screamer 0:c5e2f793b59a 733 struct _hw_llwu_me_bitfields
screamer 0:c5e2f793b59a 734 {
screamer 0:c5e2f793b59a 735 uint8_t WUME0 : 1; /*!< [0] Wakeup Module Enable For Module 0 */
screamer 0:c5e2f793b59a 736 uint8_t WUME1 : 1; /*!< [1] Wakeup Module Enable for Module 1 */
screamer 0:c5e2f793b59a 737 uint8_t WUME2 : 1; /*!< [2] Wakeup Module Enable For Module 2 */
screamer 0:c5e2f793b59a 738 uint8_t WUME3 : 1; /*!< [3] Wakeup Module Enable For Module 3 */
screamer 0:c5e2f793b59a 739 uint8_t WUME4 : 1; /*!< [4] Wakeup Module Enable For Module 4 */
screamer 0:c5e2f793b59a 740 uint8_t WUME5 : 1; /*!< [5] Wakeup Module Enable For Module 5 */
screamer 0:c5e2f793b59a 741 uint8_t WUME6 : 1; /*!< [6] Wakeup Module Enable For Module 6 */
screamer 0:c5e2f793b59a 742 uint8_t WUME7 : 1; /*!< [7] Wakeup Module Enable For Module 7 */
screamer 0:c5e2f793b59a 743 } B;
screamer 0:c5e2f793b59a 744 } hw_llwu_me_t;
screamer 0:c5e2f793b59a 745
screamer 0:c5e2f793b59a 746 /*!
screamer 0:c5e2f793b59a 747 * @name Constants and macros for entire LLWU_ME register
screamer 0:c5e2f793b59a 748 */
screamer 0:c5e2f793b59a 749 /*@{*/
screamer 0:c5e2f793b59a 750 #define HW_LLWU_ME_ADDR(x) ((x) + 0x4U)
screamer 0:c5e2f793b59a 751
screamer 0:c5e2f793b59a 752 #define HW_LLWU_ME(x) (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR(x))
screamer 0:c5e2f793b59a 753 #define HW_LLWU_ME_RD(x) (HW_LLWU_ME(x).U)
screamer 0:c5e2f793b59a 754 #define HW_LLWU_ME_WR(x, v) (HW_LLWU_ME(x).U = (v))
screamer 0:c5e2f793b59a 755 #define HW_LLWU_ME_SET(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) | (v)))
screamer 0:c5e2f793b59a 756 #define HW_LLWU_ME_CLR(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 757 #define HW_LLWU_ME_TOG(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 758 /*@}*/
screamer 0:c5e2f793b59a 759
screamer 0:c5e2f793b59a 760 /*
screamer 0:c5e2f793b59a 761 * Constants & macros for individual LLWU_ME bitfields
screamer 0:c5e2f793b59a 762 */
screamer 0:c5e2f793b59a 763
screamer 0:c5e2f793b59a 764 /*!
screamer 0:c5e2f793b59a 765 * @name Register LLWU_ME, field WUME0[0] (RW)
screamer 0:c5e2f793b59a 766 *
screamer 0:c5e2f793b59a 767 * Enables an internal module as a wakeup source input.
screamer 0:c5e2f793b59a 768 *
screamer 0:c5e2f793b59a 769 * Values:
screamer 0:c5e2f793b59a 770 * - 0 - Internal module flag not used as wakeup source
screamer 0:c5e2f793b59a 771 * - 1 - Internal module flag used as wakeup source
screamer 0:c5e2f793b59a 772 */
screamer 0:c5e2f793b59a 773 /*@{*/
screamer 0:c5e2f793b59a 774 #define BP_LLWU_ME_WUME0 (0U) /*!< Bit position for LLWU_ME_WUME0. */
screamer 0:c5e2f793b59a 775 #define BM_LLWU_ME_WUME0 (0x01U) /*!< Bit mask for LLWU_ME_WUME0. */
screamer 0:c5e2f793b59a 776 #define BS_LLWU_ME_WUME0 (1U) /*!< Bit field size in bits for LLWU_ME_WUME0. */
screamer 0:c5e2f793b59a 777
screamer 0:c5e2f793b59a 778 /*! @brief Read current value of the LLWU_ME_WUME0 field. */
screamer 0:c5e2f793b59a 779 #define BR_LLWU_ME_WUME0(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0))
screamer 0:c5e2f793b59a 780
screamer 0:c5e2f793b59a 781 /*! @brief Format value for bitfield LLWU_ME_WUME0. */
screamer 0:c5e2f793b59a 782 #define BF_LLWU_ME_WUME0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME0) & BM_LLWU_ME_WUME0)
screamer 0:c5e2f793b59a 783
screamer 0:c5e2f793b59a 784 /*! @brief Set the WUME0 field to a new value. */
screamer 0:c5e2f793b59a 785 #define BW_LLWU_ME_WUME0(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0) = (v))
screamer 0:c5e2f793b59a 786 /*@}*/
screamer 0:c5e2f793b59a 787
screamer 0:c5e2f793b59a 788 /*!
screamer 0:c5e2f793b59a 789 * @name Register LLWU_ME, field WUME1[1] (RW)
screamer 0:c5e2f793b59a 790 *
screamer 0:c5e2f793b59a 791 * Enables an internal module as a wakeup source input.
screamer 0:c5e2f793b59a 792 *
screamer 0:c5e2f793b59a 793 * Values:
screamer 0:c5e2f793b59a 794 * - 0 - Internal module flag not used as wakeup source
screamer 0:c5e2f793b59a 795 * - 1 - Internal module flag used as wakeup source
screamer 0:c5e2f793b59a 796 */
screamer 0:c5e2f793b59a 797 /*@{*/
screamer 0:c5e2f793b59a 798 #define BP_LLWU_ME_WUME1 (1U) /*!< Bit position for LLWU_ME_WUME1. */
screamer 0:c5e2f793b59a 799 #define BM_LLWU_ME_WUME1 (0x02U) /*!< Bit mask for LLWU_ME_WUME1. */
screamer 0:c5e2f793b59a 800 #define BS_LLWU_ME_WUME1 (1U) /*!< Bit field size in bits for LLWU_ME_WUME1. */
screamer 0:c5e2f793b59a 801
screamer 0:c5e2f793b59a 802 /*! @brief Read current value of the LLWU_ME_WUME1 field. */
screamer 0:c5e2f793b59a 803 #define BR_LLWU_ME_WUME1(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1))
screamer 0:c5e2f793b59a 804
screamer 0:c5e2f793b59a 805 /*! @brief Format value for bitfield LLWU_ME_WUME1. */
screamer 0:c5e2f793b59a 806 #define BF_LLWU_ME_WUME1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME1) & BM_LLWU_ME_WUME1)
screamer 0:c5e2f793b59a 807
screamer 0:c5e2f793b59a 808 /*! @brief Set the WUME1 field to a new value. */
screamer 0:c5e2f793b59a 809 #define BW_LLWU_ME_WUME1(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1) = (v))
screamer 0:c5e2f793b59a 810 /*@}*/
screamer 0:c5e2f793b59a 811
screamer 0:c5e2f793b59a 812 /*!
screamer 0:c5e2f793b59a 813 * @name Register LLWU_ME, field WUME2[2] (RW)
screamer 0:c5e2f793b59a 814 *
screamer 0:c5e2f793b59a 815 * Enables an internal module as a wakeup source input.
screamer 0:c5e2f793b59a 816 *
screamer 0:c5e2f793b59a 817 * Values:
screamer 0:c5e2f793b59a 818 * - 0 - Internal module flag not used as wakeup source
screamer 0:c5e2f793b59a 819 * - 1 - Internal module flag used as wakeup source
screamer 0:c5e2f793b59a 820 */
screamer 0:c5e2f793b59a 821 /*@{*/
screamer 0:c5e2f793b59a 822 #define BP_LLWU_ME_WUME2 (2U) /*!< Bit position for LLWU_ME_WUME2. */
screamer 0:c5e2f793b59a 823 #define BM_LLWU_ME_WUME2 (0x04U) /*!< Bit mask for LLWU_ME_WUME2. */
screamer 0:c5e2f793b59a 824 #define BS_LLWU_ME_WUME2 (1U) /*!< Bit field size in bits for LLWU_ME_WUME2. */
screamer 0:c5e2f793b59a 825
screamer 0:c5e2f793b59a 826 /*! @brief Read current value of the LLWU_ME_WUME2 field. */
screamer 0:c5e2f793b59a 827 #define BR_LLWU_ME_WUME2(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2))
screamer 0:c5e2f793b59a 828
screamer 0:c5e2f793b59a 829 /*! @brief Format value for bitfield LLWU_ME_WUME2. */
screamer 0:c5e2f793b59a 830 #define BF_LLWU_ME_WUME2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME2) & BM_LLWU_ME_WUME2)
screamer 0:c5e2f793b59a 831
screamer 0:c5e2f793b59a 832 /*! @brief Set the WUME2 field to a new value. */
screamer 0:c5e2f793b59a 833 #define BW_LLWU_ME_WUME2(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2) = (v))
screamer 0:c5e2f793b59a 834 /*@}*/
screamer 0:c5e2f793b59a 835
screamer 0:c5e2f793b59a 836 /*!
screamer 0:c5e2f793b59a 837 * @name Register LLWU_ME, field WUME3[3] (RW)
screamer 0:c5e2f793b59a 838 *
screamer 0:c5e2f793b59a 839 * Enables an internal module as a wakeup source input.
screamer 0:c5e2f793b59a 840 *
screamer 0:c5e2f793b59a 841 * Values:
screamer 0:c5e2f793b59a 842 * - 0 - Internal module flag not used as wakeup source
screamer 0:c5e2f793b59a 843 * - 1 - Internal module flag used as wakeup source
screamer 0:c5e2f793b59a 844 */
screamer 0:c5e2f793b59a 845 /*@{*/
screamer 0:c5e2f793b59a 846 #define BP_LLWU_ME_WUME3 (3U) /*!< Bit position for LLWU_ME_WUME3. */
screamer 0:c5e2f793b59a 847 #define BM_LLWU_ME_WUME3 (0x08U) /*!< Bit mask for LLWU_ME_WUME3. */
screamer 0:c5e2f793b59a 848 #define BS_LLWU_ME_WUME3 (1U) /*!< Bit field size in bits for LLWU_ME_WUME3. */
screamer 0:c5e2f793b59a 849
screamer 0:c5e2f793b59a 850 /*! @brief Read current value of the LLWU_ME_WUME3 field. */
screamer 0:c5e2f793b59a 851 #define BR_LLWU_ME_WUME3(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3))
screamer 0:c5e2f793b59a 852
screamer 0:c5e2f793b59a 853 /*! @brief Format value for bitfield LLWU_ME_WUME3. */
screamer 0:c5e2f793b59a 854 #define BF_LLWU_ME_WUME3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME3) & BM_LLWU_ME_WUME3)
screamer 0:c5e2f793b59a 855
screamer 0:c5e2f793b59a 856 /*! @brief Set the WUME3 field to a new value. */
screamer 0:c5e2f793b59a 857 #define BW_LLWU_ME_WUME3(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3) = (v))
screamer 0:c5e2f793b59a 858 /*@}*/
screamer 0:c5e2f793b59a 859
screamer 0:c5e2f793b59a 860 /*!
screamer 0:c5e2f793b59a 861 * @name Register LLWU_ME, field WUME4[4] (RW)
screamer 0:c5e2f793b59a 862 *
screamer 0:c5e2f793b59a 863 * Enables an internal module as a wakeup source input.
screamer 0:c5e2f793b59a 864 *
screamer 0:c5e2f793b59a 865 * Values:
screamer 0:c5e2f793b59a 866 * - 0 - Internal module flag not used as wakeup source
screamer 0:c5e2f793b59a 867 * - 1 - Internal module flag used as wakeup source
screamer 0:c5e2f793b59a 868 */
screamer 0:c5e2f793b59a 869 /*@{*/
screamer 0:c5e2f793b59a 870 #define BP_LLWU_ME_WUME4 (4U) /*!< Bit position for LLWU_ME_WUME4. */
screamer 0:c5e2f793b59a 871 #define BM_LLWU_ME_WUME4 (0x10U) /*!< Bit mask for LLWU_ME_WUME4. */
screamer 0:c5e2f793b59a 872 #define BS_LLWU_ME_WUME4 (1U) /*!< Bit field size in bits for LLWU_ME_WUME4. */
screamer 0:c5e2f793b59a 873
screamer 0:c5e2f793b59a 874 /*! @brief Read current value of the LLWU_ME_WUME4 field. */
screamer 0:c5e2f793b59a 875 #define BR_LLWU_ME_WUME4(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4))
screamer 0:c5e2f793b59a 876
screamer 0:c5e2f793b59a 877 /*! @brief Format value for bitfield LLWU_ME_WUME4. */
screamer 0:c5e2f793b59a 878 #define BF_LLWU_ME_WUME4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME4) & BM_LLWU_ME_WUME4)
screamer 0:c5e2f793b59a 879
screamer 0:c5e2f793b59a 880 /*! @brief Set the WUME4 field to a new value. */
screamer 0:c5e2f793b59a 881 #define BW_LLWU_ME_WUME4(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4) = (v))
screamer 0:c5e2f793b59a 882 /*@}*/
screamer 0:c5e2f793b59a 883
screamer 0:c5e2f793b59a 884 /*!
screamer 0:c5e2f793b59a 885 * @name Register LLWU_ME, field WUME5[5] (RW)
screamer 0:c5e2f793b59a 886 *
screamer 0:c5e2f793b59a 887 * Enables an internal module as a wakeup source input.
screamer 0:c5e2f793b59a 888 *
screamer 0:c5e2f793b59a 889 * Values:
screamer 0:c5e2f793b59a 890 * - 0 - Internal module flag not used as wakeup source
screamer 0:c5e2f793b59a 891 * - 1 - Internal module flag used as wakeup source
screamer 0:c5e2f793b59a 892 */
screamer 0:c5e2f793b59a 893 /*@{*/
screamer 0:c5e2f793b59a 894 #define BP_LLWU_ME_WUME5 (5U) /*!< Bit position for LLWU_ME_WUME5. */
screamer 0:c5e2f793b59a 895 #define BM_LLWU_ME_WUME5 (0x20U) /*!< Bit mask for LLWU_ME_WUME5. */
screamer 0:c5e2f793b59a 896 #define BS_LLWU_ME_WUME5 (1U) /*!< Bit field size in bits for LLWU_ME_WUME5. */
screamer 0:c5e2f793b59a 897
screamer 0:c5e2f793b59a 898 /*! @brief Read current value of the LLWU_ME_WUME5 field. */
screamer 0:c5e2f793b59a 899 #define BR_LLWU_ME_WUME5(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5))
screamer 0:c5e2f793b59a 900
screamer 0:c5e2f793b59a 901 /*! @brief Format value for bitfield LLWU_ME_WUME5. */
screamer 0:c5e2f793b59a 902 #define BF_LLWU_ME_WUME5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME5) & BM_LLWU_ME_WUME5)
screamer 0:c5e2f793b59a 903
screamer 0:c5e2f793b59a 904 /*! @brief Set the WUME5 field to a new value. */
screamer 0:c5e2f793b59a 905 #define BW_LLWU_ME_WUME5(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5) = (v))
screamer 0:c5e2f793b59a 906 /*@}*/
screamer 0:c5e2f793b59a 907
screamer 0:c5e2f793b59a 908 /*!
screamer 0:c5e2f793b59a 909 * @name Register LLWU_ME, field WUME6[6] (RW)
screamer 0:c5e2f793b59a 910 *
screamer 0:c5e2f793b59a 911 * Enables an internal module as a wakeup source input.
screamer 0:c5e2f793b59a 912 *
screamer 0:c5e2f793b59a 913 * Values:
screamer 0:c5e2f793b59a 914 * - 0 - Internal module flag not used as wakeup source
screamer 0:c5e2f793b59a 915 * - 1 - Internal module flag used as wakeup source
screamer 0:c5e2f793b59a 916 */
screamer 0:c5e2f793b59a 917 /*@{*/
screamer 0:c5e2f793b59a 918 #define BP_LLWU_ME_WUME6 (6U) /*!< Bit position for LLWU_ME_WUME6. */
screamer 0:c5e2f793b59a 919 #define BM_LLWU_ME_WUME6 (0x40U) /*!< Bit mask for LLWU_ME_WUME6. */
screamer 0:c5e2f793b59a 920 #define BS_LLWU_ME_WUME6 (1U) /*!< Bit field size in bits for LLWU_ME_WUME6. */
screamer 0:c5e2f793b59a 921
screamer 0:c5e2f793b59a 922 /*! @brief Read current value of the LLWU_ME_WUME6 field. */
screamer 0:c5e2f793b59a 923 #define BR_LLWU_ME_WUME6(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6))
screamer 0:c5e2f793b59a 924
screamer 0:c5e2f793b59a 925 /*! @brief Format value for bitfield LLWU_ME_WUME6. */
screamer 0:c5e2f793b59a 926 #define BF_LLWU_ME_WUME6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME6) & BM_LLWU_ME_WUME6)
screamer 0:c5e2f793b59a 927
screamer 0:c5e2f793b59a 928 /*! @brief Set the WUME6 field to a new value. */
screamer 0:c5e2f793b59a 929 #define BW_LLWU_ME_WUME6(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6) = (v))
screamer 0:c5e2f793b59a 930 /*@}*/
screamer 0:c5e2f793b59a 931
screamer 0:c5e2f793b59a 932 /*!
screamer 0:c5e2f793b59a 933 * @name Register LLWU_ME, field WUME7[7] (RW)
screamer 0:c5e2f793b59a 934 *
screamer 0:c5e2f793b59a 935 * Enables an internal module as a wakeup source input.
screamer 0:c5e2f793b59a 936 *
screamer 0:c5e2f793b59a 937 * Values:
screamer 0:c5e2f793b59a 938 * - 0 - Internal module flag not used as wakeup source
screamer 0:c5e2f793b59a 939 * - 1 - Internal module flag used as wakeup source
screamer 0:c5e2f793b59a 940 */
screamer 0:c5e2f793b59a 941 /*@{*/
screamer 0:c5e2f793b59a 942 #define BP_LLWU_ME_WUME7 (7U) /*!< Bit position for LLWU_ME_WUME7. */
screamer 0:c5e2f793b59a 943 #define BM_LLWU_ME_WUME7 (0x80U) /*!< Bit mask for LLWU_ME_WUME7. */
screamer 0:c5e2f793b59a 944 #define BS_LLWU_ME_WUME7 (1U) /*!< Bit field size in bits for LLWU_ME_WUME7. */
screamer 0:c5e2f793b59a 945
screamer 0:c5e2f793b59a 946 /*! @brief Read current value of the LLWU_ME_WUME7 field. */
screamer 0:c5e2f793b59a 947 #define BR_LLWU_ME_WUME7(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7))
screamer 0:c5e2f793b59a 948
screamer 0:c5e2f793b59a 949 /*! @brief Format value for bitfield LLWU_ME_WUME7. */
screamer 0:c5e2f793b59a 950 #define BF_LLWU_ME_WUME7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME7) & BM_LLWU_ME_WUME7)
screamer 0:c5e2f793b59a 951
screamer 0:c5e2f793b59a 952 /*! @brief Set the WUME7 field to a new value. */
screamer 0:c5e2f793b59a 953 #define BW_LLWU_ME_WUME7(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7) = (v))
screamer 0:c5e2f793b59a 954 /*@}*/
screamer 0:c5e2f793b59a 955
screamer 0:c5e2f793b59a 956 /*******************************************************************************
screamer 0:c5e2f793b59a 957 * HW_LLWU_F1 - LLWU Flag 1 register
screamer 0:c5e2f793b59a 958 ******************************************************************************/
screamer 0:c5e2f793b59a 959
screamer 0:c5e2f793b59a 960 /*!
screamer 0:c5e2f793b59a 961 * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
screamer 0:c5e2f793b59a 962 *
screamer 0:c5e2f793b59a 963 * Reset value: 0x00U
screamer 0:c5e2f793b59a 964 *
screamer 0:c5e2f793b59a 965 * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
screamer 0:c5e2f793b59a 966 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
screamer 0:c5e2f793b59a 967 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
screamer 0:c5e2f793b59a 968 * external wakeup flags are read-only and clearing a flag is accomplished by a write
screamer 0:c5e2f793b59a 969 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
screamer 0:c5e2f793b59a 970 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
screamer 0:c5e2f793b59a 971 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 972 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 973 * IntroductionInformation found here describes the registers of the Reset Control
screamer 0:c5e2f793b59a 974 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
screamer 0:c5e2f793b59a 975 * chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 976 */
screamer 0:c5e2f793b59a 977 typedef union _hw_llwu_f1
screamer 0:c5e2f793b59a 978 {
screamer 0:c5e2f793b59a 979 uint8_t U;
screamer 0:c5e2f793b59a 980 struct _hw_llwu_f1_bitfields
screamer 0:c5e2f793b59a 981 {
screamer 0:c5e2f793b59a 982 uint8_t WUF0 : 1; /*!< [0] Wakeup Flag For LLWU_P0 */
screamer 0:c5e2f793b59a 983 uint8_t WUF1 : 1; /*!< [1] Wakeup Flag For LLWU_P1 */
screamer 0:c5e2f793b59a 984 uint8_t WUF2 : 1; /*!< [2] Wakeup Flag For LLWU_P2 */
screamer 0:c5e2f793b59a 985 uint8_t WUF3 : 1; /*!< [3] Wakeup Flag For LLWU_P3 */
screamer 0:c5e2f793b59a 986 uint8_t WUF4 : 1; /*!< [4] Wakeup Flag For LLWU_P4 */
screamer 0:c5e2f793b59a 987 uint8_t WUF5 : 1; /*!< [5] Wakeup Flag For LLWU_P5 */
screamer 0:c5e2f793b59a 988 uint8_t WUF6 : 1; /*!< [6] Wakeup Flag For LLWU_P6 */
screamer 0:c5e2f793b59a 989 uint8_t WUF7 : 1; /*!< [7] Wakeup Flag For LLWU_P7 */
screamer 0:c5e2f793b59a 990 } B;
screamer 0:c5e2f793b59a 991 } hw_llwu_f1_t;
screamer 0:c5e2f793b59a 992
screamer 0:c5e2f793b59a 993 /*!
screamer 0:c5e2f793b59a 994 * @name Constants and macros for entire LLWU_F1 register
screamer 0:c5e2f793b59a 995 */
screamer 0:c5e2f793b59a 996 /*@{*/
screamer 0:c5e2f793b59a 997 #define HW_LLWU_F1_ADDR(x) ((x) + 0x5U)
screamer 0:c5e2f793b59a 998
screamer 0:c5e2f793b59a 999 #define HW_LLWU_F1(x) (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR(x))
screamer 0:c5e2f793b59a 1000 #define HW_LLWU_F1_RD(x) (HW_LLWU_F1(x).U)
screamer 0:c5e2f793b59a 1001 #define HW_LLWU_F1_WR(x, v) (HW_LLWU_F1(x).U = (v))
screamer 0:c5e2f793b59a 1002 #define HW_LLWU_F1_SET(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) | (v)))
screamer 0:c5e2f793b59a 1003 #define HW_LLWU_F1_CLR(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1004 #define HW_LLWU_F1_TOG(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1005 /*@}*/
screamer 0:c5e2f793b59a 1006
screamer 0:c5e2f793b59a 1007 /*
screamer 0:c5e2f793b59a 1008 * Constants & macros for individual LLWU_F1 bitfields
screamer 0:c5e2f793b59a 1009 */
screamer 0:c5e2f793b59a 1010
screamer 0:c5e2f793b59a 1011 /*!
screamer 0:c5e2f793b59a 1012 * @name Register LLWU_F1, field WUF0[0] (W1C)
screamer 0:c5e2f793b59a 1013 *
screamer 0:c5e2f793b59a 1014 * Indicates that an enabled external wake-up pin was a source of exiting a
screamer 0:c5e2f793b59a 1015 * low-leakage power mode. To clear the flag, write a 1 to WUF0.
screamer 0:c5e2f793b59a 1016 *
screamer 0:c5e2f793b59a 1017 * Values:
screamer 0:c5e2f793b59a 1018 * - 0 - LLWU_P0 input was not a wakeup source
screamer 0:c5e2f793b59a 1019 * - 1 - LLWU_P0 input was a wakeup source
screamer 0:c5e2f793b59a 1020 */
screamer 0:c5e2f793b59a 1021 /*@{*/
screamer 0:c5e2f793b59a 1022 #define BP_LLWU_F1_WUF0 (0U) /*!< Bit position for LLWU_F1_WUF0. */
screamer 0:c5e2f793b59a 1023 #define BM_LLWU_F1_WUF0 (0x01U) /*!< Bit mask for LLWU_F1_WUF0. */
screamer 0:c5e2f793b59a 1024 #define BS_LLWU_F1_WUF0 (1U) /*!< Bit field size in bits for LLWU_F1_WUF0. */
screamer 0:c5e2f793b59a 1025
screamer 0:c5e2f793b59a 1026 /*! @brief Read current value of the LLWU_F1_WUF0 field. */
screamer 0:c5e2f793b59a 1027 #define BR_LLWU_F1_WUF0(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0))
screamer 0:c5e2f793b59a 1028
screamer 0:c5e2f793b59a 1029 /*! @brief Format value for bitfield LLWU_F1_WUF0. */
screamer 0:c5e2f793b59a 1030 #define BF_LLWU_F1_WUF0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF0) & BM_LLWU_F1_WUF0)
screamer 0:c5e2f793b59a 1031
screamer 0:c5e2f793b59a 1032 /*! @brief Set the WUF0 field to a new value. */
screamer 0:c5e2f793b59a 1033 #define BW_LLWU_F1_WUF0(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0) = (v))
screamer 0:c5e2f793b59a 1034 /*@}*/
screamer 0:c5e2f793b59a 1035
screamer 0:c5e2f793b59a 1036 /*!
screamer 0:c5e2f793b59a 1037 * @name Register LLWU_F1, field WUF1[1] (W1C)
screamer 0:c5e2f793b59a 1038 *
screamer 0:c5e2f793b59a 1039 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1040 * low-leakage power mode. To clear the flag, write a 1 to WUF1.
screamer 0:c5e2f793b59a 1041 *
screamer 0:c5e2f793b59a 1042 * Values:
screamer 0:c5e2f793b59a 1043 * - 0 - LLWU_P1 input was not a wakeup source
screamer 0:c5e2f793b59a 1044 * - 1 - LLWU_P1 input was a wakeup source
screamer 0:c5e2f793b59a 1045 */
screamer 0:c5e2f793b59a 1046 /*@{*/
screamer 0:c5e2f793b59a 1047 #define BP_LLWU_F1_WUF1 (1U) /*!< Bit position for LLWU_F1_WUF1. */
screamer 0:c5e2f793b59a 1048 #define BM_LLWU_F1_WUF1 (0x02U) /*!< Bit mask for LLWU_F1_WUF1. */
screamer 0:c5e2f793b59a 1049 #define BS_LLWU_F1_WUF1 (1U) /*!< Bit field size in bits for LLWU_F1_WUF1. */
screamer 0:c5e2f793b59a 1050
screamer 0:c5e2f793b59a 1051 /*! @brief Read current value of the LLWU_F1_WUF1 field. */
screamer 0:c5e2f793b59a 1052 #define BR_LLWU_F1_WUF1(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1))
screamer 0:c5e2f793b59a 1053
screamer 0:c5e2f793b59a 1054 /*! @brief Format value for bitfield LLWU_F1_WUF1. */
screamer 0:c5e2f793b59a 1055 #define BF_LLWU_F1_WUF1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF1) & BM_LLWU_F1_WUF1)
screamer 0:c5e2f793b59a 1056
screamer 0:c5e2f793b59a 1057 /*! @brief Set the WUF1 field to a new value. */
screamer 0:c5e2f793b59a 1058 #define BW_LLWU_F1_WUF1(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1) = (v))
screamer 0:c5e2f793b59a 1059 /*@}*/
screamer 0:c5e2f793b59a 1060
screamer 0:c5e2f793b59a 1061 /*!
screamer 0:c5e2f793b59a 1062 * @name Register LLWU_F1, field WUF2[2] (W1C)
screamer 0:c5e2f793b59a 1063 *
screamer 0:c5e2f793b59a 1064 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1065 * low-leakage power mode. To clear the flag, write a 1 to WUF2.
screamer 0:c5e2f793b59a 1066 *
screamer 0:c5e2f793b59a 1067 * Values:
screamer 0:c5e2f793b59a 1068 * - 0 - LLWU_P2 input was not a wakeup source
screamer 0:c5e2f793b59a 1069 * - 1 - LLWU_P2 input was a wakeup source
screamer 0:c5e2f793b59a 1070 */
screamer 0:c5e2f793b59a 1071 /*@{*/
screamer 0:c5e2f793b59a 1072 #define BP_LLWU_F1_WUF2 (2U) /*!< Bit position for LLWU_F1_WUF2. */
screamer 0:c5e2f793b59a 1073 #define BM_LLWU_F1_WUF2 (0x04U) /*!< Bit mask for LLWU_F1_WUF2. */
screamer 0:c5e2f793b59a 1074 #define BS_LLWU_F1_WUF2 (1U) /*!< Bit field size in bits for LLWU_F1_WUF2. */
screamer 0:c5e2f793b59a 1075
screamer 0:c5e2f793b59a 1076 /*! @brief Read current value of the LLWU_F1_WUF2 field. */
screamer 0:c5e2f793b59a 1077 #define BR_LLWU_F1_WUF2(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2))
screamer 0:c5e2f793b59a 1078
screamer 0:c5e2f793b59a 1079 /*! @brief Format value for bitfield LLWU_F1_WUF2. */
screamer 0:c5e2f793b59a 1080 #define BF_LLWU_F1_WUF2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF2) & BM_LLWU_F1_WUF2)
screamer 0:c5e2f793b59a 1081
screamer 0:c5e2f793b59a 1082 /*! @brief Set the WUF2 field to a new value. */
screamer 0:c5e2f793b59a 1083 #define BW_LLWU_F1_WUF2(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2) = (v))
screamer 0:c5e2f793b59a 1084 /*@}*/
screamer 0:c5e2f793b59a 1085
screamer 0:c5e2f793b59a 1086 /*!
screamer 0:c5e2f793b59a 1087 * @name Register LLWU_F1, field WUF3[3] (W1C)
screamer 0:c5e2f793b59a 1088 *
screamer 0:c5e2f793b59a 1089 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1090 * low-leakage power mode. To clear the flag, write a 1 to WUF3.
screamer 0:c5e2f793b59a 1091 *
screamer 0:c5e2f793b59a 1092 * Values:
screamer 0:c5e2f793b59a 1093 * - 0 - LLWU_P3 input was not a wake-up source
screamer 0:c5e2f793b59a 1094 * - 1 - LLWU_P3 input was a wake-up source
screamer 0:c5e2f793b59a 1095 */
screamer 0:c5e2f793b59a 1096 /*@{*/
screamer 0:c5e2f793b59a 1097 #define BP_LLWU_F1_WUF3 (3U) /*!< Bit position for LLWU_F1_WUF3. */
screamer 0:c5e2f793b59a 1098 #define BM_LLWU_F1_WUF3 (0x08U) /*!< Bit mask for LLWU_F1_WUF3. */
screamer 0:c5e2f793b59a 1099 #define BS_LLWU_F1_WUF3 (1U) /*!< Bit field size in bits for LLWU_F1_WUF3. */
screamer 0:c5e2f793b59a 1100
screamer 0:c5e2f793b59a 1101 /*! @brief Read current value of the LLWU_F1_WUF3 field. */
screamer 0:c5e2f793b59a 1102 #define BR_LLWU_F1_WUF3(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3))
screamer 0:c5e2f793b59a 1103
screamer 0:c5e2f793b59a 1104 /*! @brief Format value for bitfield LLWU_F1_WUF3. */
screamer 0:c5e2f793b59a 1105 #define BF_LLWU_F1_WUF3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF3) & BM_LLWU_F1_WUF3)
screamer 0:c5e2f793b59a 1106
screamer 0:c5e2f793b59a 1107 /*! @brief Set the WUF3 field to a new value. */
screamer 0:c5e2f793b59a 1108 #define BW_LLWU_F1_WUF3(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3) = (v))
screamer 0:c5e2f793b59a 1109 /*@}*/
screamer 0:c5e2f793b59a 1110
screamer 0:c5e2f793b59a 1111 /*!
screamer 0:c5e2f793b59a 1112 * @name Register LLWU_F1, field WUF4[4] (W1C)
screamer 0:c5e2f793b59a 1113 *
screamer 0:c5e2f793b59a 1114 * Indicates that an enabled external wake-up pin was a source of exiting a
screamer 0:c5e2f793b59a 1115 * low-leakage power mode. To clear the flag, write a 1 to WUF4.
screamer 0:c5e2f793b59a 1116 *
screamer 0:c5e2f793b59a 1117 * Values:
screamer 0:c5e2f793b59a 1118 * - 0 - LLWU_P4 input was not a wakeup source
screamer 0:c5e2f793b59a 1119 * - 1 - LLWU_P4 input was a wakeup source
screamer 0:c5e2f793b59a 1120 */
screamer 0:c5e2f793b59a 1121 /*@{*/
screamer 0:c5e2f793b59a 1122 #define BP_LLWU_F1_WUF4 (4U) /*!< Bit position for LLWU_F1_WUF4. */
screamer 0:c5e2f793b59a 1123 #define BM_LLWU_F1_WUF4 (0x10U) /*!< Bit mask for LLWU_F1_WUF4. */
screamer 0:c5e2f793b59a 1124 #define BS_LLWU_F1_WUF4 (1U) /*!< Bit field size in bits for LLWU_F1_WUF4. */
screamer 0:c5e2f793b59a 1125
screamer 0:c5e2f793b59a 1126 /*! @brief Read current value of the LLWU_F1_WUF4 field. */
screamer 0:c5e2f793b59a 1127 #define BR_LLWU_F1_WUF4(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4))
screamer 0:c5e2f793b59a 1128
screamer 0:c5e2f793b59a 1129 /*! @brief Format value for bitfield LLWU_F1_WUF4. */
screamer 0:c5e2f793b59a 1130 #define BF_LLWU_F1_WUF4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF4) & BM_LLWU_F1_WUF4)
screamer 0:c5e2f793b59a 1131
screamer 0:c5e2f793b59a 1132 /*! @brief Set the WUF4 field to a new value. */
screamer 0:c5e2f793b59a 1133 #define BW_LLWU_F1_WUF4(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4) = (v))
screamer 0:c5e2f793b59a 1134 /*@}*/
screamer 0:c5e2f793b59a 1135
screamer 0:c5e2f793b59a 1136 /*!
screamer 0:c5e2f793b59a 1137 * @name Register LLWU_F1, field WUF5[5] (W1C)
screamer 0:c5e2f793b59a 1138 *
screamer 0:c5e2f793b59a 1139 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1140 * low-leakage power mode. To clear the flag, write a 1 to WUF5.
screamer 0:c5e2f793b59a 1141 *
screamer 0:c5e2f793b59a 1142 * Values:
screamer 0:c5e2f793b59a 1143 * - 0 - LLWU_P5 input was not a wakeup source
screamer 0:c5e2f793b59a 1144 * - 1 - LLWU_P5 input was a wakeup source
screamer 0:c5e2f793b59a 1145 */
screamer 0:c5e2f793b59a 1146 /*@{*/
screamer 0:c5e2f793b59a 1147 #define BP_LLWU_F1_WUF5 (5U) /*!< Bit position for LLWU_F1_WUF5. */
screamer 0:c5e2f793b59a 1148 #define BM_LLWU_F1_WUF5 (0x20U) /*!< Bit mask for LLWU_F1_WUF5. */
screamer 0:c5e2f793b59a 1149 #define BS_LLWU_F1_WUF5 (1U) /*!< Bit field size in bits for LLWU_F1_WUF5. */
screamer 0:c5e2f793b59a 1150
screamer 0:c5e2f793b59a 1151 /*! @brief Read current value of the LLWU_F1_WUF5 field. */
screamer 0:c5e2f793b59a 1152 #define BR_LLWU_F1_WUF5(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5))
screamer 0:c5e2f793b59a 1153
screamer 0:c5e2f793b59a 1154 /*! @brief Format value for bitfield LLWU_F1_WUF5. */
screamer 0:c5e2f793b59a 1155 #define BF_LLWU_F1_WUF5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF5) & BM_LLWU_F1_WUF5)
screamer 0:c5e2f793b59a 1156
screamer 0:c5e2f793b59a 1157 /*! @brief Set the WUF5 field to a new value. */
screamer 0:c5e2f793b59a 1158 #define BW_LLWU_F1_WUF5(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5) = (v))
screamer 0:c5e2f793b59a 1159 /*@}*/
screamer 0:c5e2f793b59a 1160
screamer 0:c5e2f793b59a 1161 /*!
screamer 0:c5e2f793b59a 1162 * @name Register LLWU_F1, field WUF6[6] (W1C)
screamer 0:c5e2f793b59a 1163 *
screamer 0:c5e2f793b59a 1164 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1165 * low-leakage power mode. To clear the flag, write a 1 to WUF6.
screamer 0:c5e2f793b59a 1166 *
screamer 0:c5e2f793b59a 1167 * Values:
screamer 0:c5e2f793b59a 1168 * - 0 - LLWU_P6 input was not a wakeup source
screamer 0:c5e2f793b59a 1169 * - 1 - LLWU_P6 input was a wakeup source
screamer 0:c5e2f793b59a 1170 */
screamer 0:c5e2f793b59a 1171 /*@{*/
screamer 0:c5e2f793b59a 1172 #define BP_LLWU_F1_WUF6 (6U) /*!< Bit position for LLWU_F1_WUF6. */
screamer 0:c5e2f793b59a 1173 #define BM_LLWU_F1_WUF6 (0x40U) /*!< Bit mask for LLWU_F1_WUF6. */
screamer 0:c5e2f793b59a 1174 #define BS_LLWU_F1_WUF6 (1U) /*!< Bit field size in bits for LLWU_F1_WUF6. */
screamer 0:c5e2f793b59a 1175
screamer 0:c5e2f793b59a 1176 /*! @brief Read current value of the LLWU_F1_WUF6 field. */
screamer 0:c5e2f793b59a 1177 #define BR_LLWU_F1_WUF6(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6))
screamer 0:c5e2f793b59a 1178
screamer 0:c5e2f793b59a 1179 /*! @brief Format value for bitfield LLWU_F1_WUF6. */
screamer 0:c5e2f793b59a 1180 #define BF_LLWU_F1_WUF6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF6) & BM_LLWU_F1_WUF6)
screamer 0:c5e2f793b59a 1181
screamer 0:c5e2f793b59a 1182 /*! @brief Set the WUF6 field to a new value. */
screamer 0:c5e2f793b59a 1183 #define BW_LLWU_F1_WUF6(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6) = (v))
screamer 0:c5e2f793b59a 1184 /*@}*/
screamer 0:c5e2f793b59a 1185
screamer 0:c5e2f793b59a 1186 /*!
screamer 0:c5e2f793b59a 1187 * @name Register LLWU_F1, field WUF7[7] (W1C)
screamer 0:c5e2f793b59a 1188 *
screamer 0:c5e2f793b59a 1189 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1190 * low-leakage power mode. To clear the flag, write a 1 to WUF7.
screamer 0:c5e2f793b59a 1191 *
screamer 0:c5e2f793b59a 1192 * Values:
screamer 0:c5e2f793b59a 1193 * - 0 - LLWU_P7 input was not a wakeup source
screamer 0:c5e2f793b59a 1194 * - 1 - LLWU_P7 input was a wakeup source
screamer 0:c5e2f793b59a 1195 */
screamer 0:c5e2f793b59a 1196 /*@{*/
screamer 0:c5e2f793b59a 1197 #define BP_LLWU_F1_WUF7 (7U) /*!< Bit position for LLWU_F1_WUF7. */
screamer 0:c5e2f793b59a 1198 #define BM_LLWU_F1_WUF7 (0x80U) /*!< Bit mask for LLWU_F1_WUF7. */
screamer 0:c5e2f793b59a 1199 #define BS_LLWU_F1_WUF7 (1U) /*!< Bit field size in bits for LLWU_F1_WUF7. */
screamer 0:c5e2f793b59a 1200
screamer 0:c5e2f793b59a 1201 /*! @brief Read current value of the LLWU_F1_WUF7 field. */
screamer 0:c5e2f793b59a 1202 #define BR_LLWU_F1_WUF7(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7))
screamer 0:c5e2f793b59a 1203
screamer 0:c5e2f793b59a 1204 /*! @brief Format value for bitfield LLWU_F1_WUF7. */
screamer 0:c5e2f793b59a 1205 #define BF_LLWU_F1_WUF7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF7) & BM_LLWU_F1_WUF7)
screamer 0:c5e2f793b59a 1206
screamer 0:c5e2f793b59a 1207 /*! @brief Set the WUF7 field to a new value. */
screamer 0:c5e2f793b59a 1208 #define BW_LLWU_F1_WUF7(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7) = (v))
screamer 0:c5e2f793b59a 1209 /*@}*/
screamer 0:c5e2f793b59a 1210
screamer 0:c5e2f793b59a 1211 /*******************************************************************************
screamer 0:c5e2f793b59a 1212 * HW_LLWU_F2 - LLWU Flag 2 register
screamer 0:c5e2f793b59a 1213 ******************************************************************************/
screamer 0:c5e2f793b59a 1214
screamer 0:c5e2f793b59a 1215 /*!
screamer 0:c5e2f793b59a 1216 * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
screamer 0:c5e2f793b59a 1217 *
screamer 0:c5e2f793b59a 1218 * Reset value: 0x00U
screamer 0:c5e2f793b59a 1219 *
screamer 0:c5e2f793b59a 1220 * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
screamer 0:c5e2f793b59a 1221 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
screamer 0:c5e2f793b59a 1222 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
screamer 0:c5e2f793b59a 1223 * external wakeup flags are read-only and clearing a flag is accomplished by a write
screamer 0:c5e2f793b59a 1224 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
screamer 0:c5e2f793b59a 1225 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
screamer 0:c5e2f793b59a 1226 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 1227 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 1228 * IntroductionInformation found here describes the registers of the Reset Control
screamer 0:c5e2f793b59a 1229 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
screamer 0:c5e2f793b59a 1230 * chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 1231 */
screamer 0:c5e2f793b59a 1232 typedef union _hw_llwu_f2
screamer 0:c5e2f793b59a 1233 {
screamer 0:c5e2f793b59a 1234 uint8_t U;
screamer 0:c5e2f793b59a 1235 struct _hw_llwu_f2_bitfields
screamer 0:c5e2f793b59a 1236 {
screamer 0:c5e2f793b59a 1237 uint8_t WUF8 : 1; /*!< [0] Wakeup Flag For LLWU_P8 */
screamer 0:c5e2f793b59a 1238 uint8_t WUF9 : 1; /*!< [1] Wakeup Flag For LLWU_P9 */
screamer 0:c5e2f793b59a 1239 uint8_t WUF10 : 1; /*!< [2] Wakeup Flag For LLWU_P10 */
screamer 0:c5e2f793b59a 1240 uint8_t WUF11 : 1; /*!< [3] Wakeup Flag For LLWU_P11 */
screamer 0:c5e2f793b59a 1241 uint8_t WUF12 : 1; /*!< [4] Wakeup Flag For LLWU_P12 */
screamer 0:c5e2f793b59a 1242 uint8_t WUF13 : 1; /*!< [5] Wakeup Flag For LLWU_P13 */
screamer 0:c5e2f793b59a 1243 uint8_t WUF14 : 1; /*!< [6] Wakeup Flag For LLWU_P14 */
screamer 0:c5e2f793b59a 1244 uint8_t WUF15 : 1; /*!< [7] Wakeup Flag For LLWU_P15 */
screamer 0:c5e2f793b59a 1245 } B;
screamer 0:c5e2f793b59a 1246 } hw_llwu_f2_t;
screamer 0:c5e2f793b59a 1247
screamer 0:c5e2f793b59a 1248 /*!
screamer 0:c5e2f793b59a 1249 * @name Constants and macros for entire LLWU_F2 register
screamer 0:c5e2f793b59a 1250 */
screamer 0:c5e2f793b59a 1251 /*@{*/
screamer 0:c5e2f793b59a 1252 #define HW_LLWU_F2_ADDR(x) ((x) + 0x6U)
screamer 0:c5e2f793b59a 1253
screamer 0:c5e2f793b59a 1254 #define HW_LLWU_F2(x) (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR(x))
screamer 0:c5e2f793b59a 1255 #define HW_LLWU_F2_RD(x) (HW_LLWU_F2(x).U)
screamer 0:c5e2f793b59a 1256 #define HW_LLWU_F2_WR(x, v) (HW_LLWU_F2(x).U = (v))
screamer 0:c5e2f793b59a 1257 #define HW_LLWU_F2_SET(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) | (v)))
screamer 0:c5e2f793b59a 1258 #define HW_LLWU_F2_CLR(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1259 #define HW_LLWU_F2_TOG(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1260 /*@}*/
screamer 0:c5e2f793b59a 1261
screamer 0:c5e2f793b59a 1262 /*
screamer 0:c5e2f793b59a 1263 * Constants & macros for individual LLWU_F2 bitfields
screamer 0:c5e2f793b59a 1264 */
screamer 0:c5e2f793b59a 1265
screamer 0:c5e2f793b59a 1266 /*!
screamer 0:c5e2f793b59a 1267 * @name Register LLWU_F2, field WUF8[0] (W1C)
screamer 0:c5e2f793b59a 1268 *
screamer 0:c5e2f793b59a 1269 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1270 * low-leakage power mode. To clear the flag, write a 1 to WUF8.
screamer 0:c5e2f793b59a 1271 *
screamer 0:c5e2f793b59a 1272 * Values:
screamer 0:c5e2f793b59a 1273 * - 0 - LLWU_P8 input was not a wakeup source
screamer 0:c5e2f793b59a 1274 * - 1 - LLWU_P8 input was a wakeup source
screamer 0:c5e2f793b59a 1275 */
screamer 0:c5e2f793b59a 1276 /*@{*/
screamer 0:c5e2f793b59a 1277 #define BP_LLWU_F2_WUF8 (0U) /*!< Bit position for LLWU_F2_WUF8. */
screamer 0:c5e2f793b59a 1278 #define BM_LLWU_F2_WUF8 (0x01U) /*!< Bit mask for LLWU_F2_WUF8. */
screamer 0:c5e2f793b59a 1279 #define BS_LLWU_F2_WUF8 (1U) /*!< Bit field size in bits for LLWU_F2_WUF8. */
screamer 0:c5e2f793b59a 1280
screamer 0:c5e2f793b59a 1281 /*! @brief Read current value of the LLWU_F2_WUF8 field. */
screamer 0:c5e2f793b59a 1282 #define BR_LLWU_F2_WUF8(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8))
screamer 0:c5e2f793b59a 1283
screamer 0:c5e2f793b59a 1284 /*! @brief Format value for bitfield LLWU_F2_WUF8. */
screamer 0:c5e2f793b59a 1285 #define BF_LLWU_F2_WUF8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF8) & BM_LLWU_F2_WUF8)
screamer 0:c5e2f793b59a 1286
screamer 0:c5e2f793b59a 1287 /*! @brief Set the WUF8 field to a new value. */
screamer 0:c5e2f793b59a 1288 #define BW_LLWU_F2_WUF8(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8) = (v))
screamer 0:c5e2f793b59a 1289 /*@}*/
screamer 0:c5e2f793b59a 1290
screamer 0:c5e2f793b59a 1291 /*!
screamer 0:c5e2f793b59a 1292 * @name Register LLWU_F2, field WUF9[1] (W1C)
screamer 0:c5e2f793b59a 1293 *
screamer 0:c5e2f793b59a 1294 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1295 * low-leakage power mode. To clear the flag, write a 1 to WUF9.
screamer 0:c5e2f793b59a 1296 *
screamer 0:c5e2f793b59a 1297 * Values:
screamer 0:c5e2f793b59a 1298 * - 0 - LLWU_P9 input was not a wakeup source
screamer 0:c5e2f793b59a 1299 * - 1 - LLWU_P9 input was a wakeup source
screamer 0:c5e2f793b59a 1300 */
screamer 0:c5e2f793b59a 1301 /*@{*/
screamer 0:c5e2f793b59a 1302 #define BP_LLWU_F2_WUF9 (1U) /*!< Bit position for LLWU_F2_WUF9. */
screamer 0:c5e2f793b59a 1303 #define BM_LLWU_F2_WUF9 (0x02U) /*!< Bit mask for LLWU_F2_WUF9. */
screamer 0:c5e2f793b59a 1304 #define BS_LLWU_F2_WUF9 (1U) /*!< Bit field size in bits for LLWU_F2_WUF9. */
screamer 0:c5e2f793b59a 1305
screamer 0:c5e2f793b59a 1306 /*! @brief Read current value of the LLWU_F2_WUF9 field. */
screamer 0:c5e2f793b59a 1307 #define BR_LLWU_F2_WUF9(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9))
screamer 0:c5e2f793b59a 1308
screamer 0:c5e2f793b59a 1309 /*! @brief Format value for bitfield LLWU_F2_WUF9. */
screamer 0:c5e2f793b59a 1310 #define BF_LLWU_F2_WUF9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF9) & BM_LLWU_F2_WUF9)
screamer 0:c5e2f793b59a 1311
screamer 0:c5e2f793b59a 1312 /*! @brief Set the WUF9 field to a new value. */
screamer 0:c5e2f793b59a 1313 #define BW_LLWU_F2_WUF9(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9) = (v))
screamer 0:c5e2f793b59a 1314 /*@}*/
screamer 0:c5e2f793b59a 1315
screamer 0:c5e2f793b59a 1316 /*!
screamer 0:c5e2f793b59a 1317 * @name Register LLWU_F2, field WUF10[2] (W1C)
screamer 0:c5e2f793b59a 1318 *
screamer 0:c5e2f793b59a 1319 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1320 * low-leakage power mode. To clear the flag, write a 1 to WUF10.
screamer 0:c5e2f793b59a 1321 *
screamer 0:c5e2f793b59a 1322 * Values:
screamer 0:c5e2f793b59a 1323 * - 0 - LLWU_P10 input was not a wakeup source
screamer 0:c5e2f793b59a 1324 * - 1 - LLWU_P10 input was a wakeup source
screamer 0:c5e2f793b59a 1325 */
screamer 0:c5e2f793b59a 1326 /*@{*/
screamer 0:c5e2f793b59a 1327 #define BP_LLWU_F2_WUF10 (2U) /*!< Bit position for LLWU_F2_WUF10. */
screamer 0:c5e2f793b59a 1328 #define BM_LLWU_F2_WUF10 (0x04U) /*!< Bit mask for LLWU_F2_WUF10. */
screamer 0:c5e2f793b59a 1329 #define BS_LLWU_F2_WUF10 (1U) /*!< Bit field size in bits for LLWU_F2_WUF10. */
screamer 0:c5e2f793b59a 1330
screamer 0:c5e2f793b59a 1331 /*! @brief Read current value of the LLWU_F2_WUF10 field. */
screamer 0:c5e2f793b59a 1332 #define BR_LLWU_F2_WUF10(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10))
screamer 0:c5e2f793b59a 1333
screamer 0:c5e2f793b59a 1334 /*! @brief Format value for bitfield LLWU_F2_WUF10. */
screamer 0:c5e2f793b59a 1335 #define BF_LLWU_F2_WUF10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF10) & BM_LLWU_F2_WUF10)
screamer 0:c5e2f793b59a 1336
screamer 0:c5e2f793b59a 1337 /*! @brief Set the WUF10 field to a new value. */
screamer 0:c5e2f793b59a 1338 #define BW_LLWU_F2_WUF10(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10) = (v))
screamer 0:c5e2f793b59a 1339 /*@}*/
screamer 0:c5e2f793b59a 1340
screamer 0:c5e2f793b59a 1341 /*!
screamer 0:c5e2f793b59a 1342 * @name Register LLWU_F2, field WUF11[3] (W1C)
screamer 0:c5e2f793b59a 1343 *
screamer 0:c5e2f793b59a 1344 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1345 * low-leakage power mode. To clear the flag, write a 1 to WUF11.
screamer 0:c5e2f793b59a 1346 *
screamer 0:c5e2f793b59a 1347 * Values:
screamer 0:c5e2f793b59a 1348 * - 0 - LLWU_P11 input was not a wakeup source
screamer 0:c5e2f793b59a 1349 * - 1 - LLWU_P11 input was a wakeup source
screamer 0:c5e2f793b59a 1350 */
screamer 0:c5e2f793b59a 1351 /*@{*/
screamer 0:c5e2f793b59a 1352 #define BP_LLWU_F2_WUF11 (3U) /*!< Bit position for LLWU_F2_WUF11. */
screamer 0:c5e2f793b59a 1353 #define BM_LLWU_F2_WUF11 (0x08U) /*!< Bit mask for LLWU_F2_WUF11. */
screamer 0:c5e2f793b59a 1354 #define BS_LLWU_F2_WUF11 (1U) /*!< Bit field size in bits for LLWU_F2_WUF11. */
screamer 0:c5e2f793b59a 1355
screamer 0:c5e2f793b59a 1356 /*! @brief Read current value of the LLWU_F2_WUF11 field. */
screamer 0:c5e2f793b59a 1357 #define BR_LLWU_F2_WUF11(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11))
screamer 0:c5e2f793b59a 1358
screamer 0:c5e2f793b59a 1359 /*! @brief Format value for bitfield LLWU_F2_WUF11. */
screamer 0:c5e2f793b59a 1360 #define BF_LLWU_F2_WUF11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF11) & BM_LLWU_F2_WUF11)
screamer 0:c5e2f793b59a 1361
screamer 0:c5e2f793b59a 1362 /*! @brief Set the WUF11 field to a new value. */
screamer 0:c5e2f793b59a 1363 #define BW_LLWU_F2_WUF11(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11) = (v))
screamer 0:c5e2f793b59a 1364 /*@}*/
screamer 0:c5e2f793b59a 1365
screamer 0:c5e2f793b59a 1366 /*!
screamer 0:c5e2f793b59a 1367 * @name Register LLWU_F2, field WUF12[4] (W1C)
screamer 0:c5e2f793b59a 1368 *
screamer 0:c5e2f793b59a 1369 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1370 * low-leakage power mode. To clear the flag, write a 1 to WUF12.
screamer 0:c5e2f793b59a 1371 *
screamer 0:c5e2f793b59a 1372 * Values:
screamer 0:c5e2f793b59a 1373 * - 0 - LLWU_P12 input was not a wakeup source
screamer 0:c5e2f793b59a 1374 * - 1 - LLWU_P12 input was a wakeup source
screamer 0:c5e2f793b59a 1375 */
screamer 0:c5e2f793b59a 1376 /*@{*/
screamer 0:c5e2f793b59a 1377 #define BP_LLWU_F2_WUF12 (4U) /*!< Bit position for LLWU_F2_WUF12. */
screamer 0:c5e2f793b59a 1378 #define BM_LLWU_F2_WUF12 (0x10U) /*!< Bit mask for LLWU_F2_WUF12. */
screamer 0:c5e2f793b59a 1379 #define BS_LLWU_F2_WUF12 (1U) /*!< Bit field size in bits for LLWU_F2_WUF12. */
screamer 0:c5e2f793b59a 1380
screamer 0:c5e2f793b59a 1381 /*! @brief Read current value of the LLWU_F2_WUF12 field. */
screamer 0:c5e2f793b59a 1382 #define BR_LLWU_F2_WUF12(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12))
screamer 0:c5e2f793b59a 1383
screamer 0:c5e2f793b59a 1384 /*! @brief Format value for bitfield LLWU_F2_WUF12. */
screamer 0:c5e2f793b59a 1385 #define BF_LLWU_F2_WUF12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF12) & BM_LLWU_F2_WUF12)
screamer 0:c5e2f793b59a 1386
screamer 0:c5e2f793b59a 1387 /*! @brief Set the WUF12 field to a new value. */
screamer 0:c5e2f793b59a 1388 #define BW_LLWU_F2_WUF12(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12) = (v))
screamer 0:c5e2f793b59a 1389 /*@}*/
screamer 0:c5e2f793b59a 1390
screamer 0:c5e2f793b59a 1391 /*!
screamer 0:c5e2f793b59a 1392 * @name Register LLWU_F2, field WUF13[5] (W1C)
screamer 0:c5e2f793b59a 1393 *
screamer 0:c5e2f793b59a 1394 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1395 * low-leakage power mode. To clear the flag, write a 1 to WUF13.
screamer 0:c5e2f793b59a 1396 *
screamer 0:c5e2f793b59a 1397 * Values:
screamer 0:c5e2f793b59a 1398 * - 0 - LLWU_P13 input was not a wakeup source
screamer 0:c5e2f793b59a 1399 * - 1 - LLWU_P13 input was a wakeup source
screamer 0:c5e2f793b59a 1400 */
screamer 0:c5e2f793b59a 1401 /*@{*/
screamer 0:c5e2f793b59a 1402 #define BP_LLWU_F2_WUF13 (5U) /*!< Bit position for LLWU_F2_WUF13. */
screamer 0:c5e2f793b59a 1403 #define BM_LLWU_F2_WUF13 (0x20U) /*!< Bit mask for LLWU_F2_WUF13. */
screamer 0:c5e2f793b59a 1404 #define BS_LLWU_F2_WUF13 (1U) /*!< Bit field size in bits for LLWU_F2_WUF13. */
screamer 0:c5e2f793b59a 1405
screamer 0:c5e2f793b59a 1406 /*! @brief Read current value of the LLWU_F2_WUF13 field. */
screamer 0:c5e2f793b59a 1407 #define BR_LLWU_F2_WUF13(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13))
screamer 0:c5e2f793b59a 1408
screamer 0:c5e2f793b59a 1409 /*! @brief Format value for bitfield LLWU_F2_WUF13. */
screamer 0:c5e2f793b59a 1410 #define BF_LLWU_F2_WUF13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF13) & BM_LLWU_F2_WUF13)
screamer 0:c5e2f793b59a 1411
screamer 0:c5e2f793b59a 1412 /*! @brief Set the WUF13 field to a new value. */
screamer 0:c5e2f793b59a 1413 #define BW_LLWU_F2_WUF13(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13) = (v))
screamer 0:c5e2f793b59a 1414 /*@}*/
screamer 0:c5e2f793b59a 1415
screamer 0:c5e2f793b59a 1416 /*!
screamer 0:c5e2f793b59a 1417 * @name Register LLWU_F2, field WUF14[6] (W1C)
screamer 0:c5e2f793b59a 1418 *
screamer 0:c5e2f793b59a 1419 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1420 * low-leakage power mode. To clear the flag, write a 1 to WUF14.
screamer 0:c5e2f793b59a 1421 *
screamer 0:c5e2f793b59a 1422 * Values:
screamer 0:c5e2f793b59a 1423 * - 0 - LLWU_P14 input was not a wakeup source
screamer 0:c5e2f793b59a 1424 * - 1 - LLWU_P14 input was a wakeup source
screamer 0:c5e2f793b59a 1425 */
screamer 0:c5e2f793b59a 1426 /*@{*/
screamer 0:c5e2f793b59a 1427 #define BP_LLWU_F2_WUF14 (6U) /*!< Bit position for LLWU_F2_WUF14. */
screamer 0:c5e2f793b59a 1428 #define BM_LLWU_F2_WUF14 (0x40U) /*!< Bit mask for LLWU_F2_WUF14. */
screamer 0:c5e2f793b59a 1429 #define BS_LLWU_F2_WUF14 (1U) /*!< Bit field size in bits for LLWU_F2_WUF14. */
screamer 0:c5e2f793b59a 1430
screamer 0:c5e2f793b59a 1431 /*! @brief Read current value of the LLWU_F2_WUF14 field. */
screamer 0:c5e2f793b59a 1432 #define BR_LLWU_F2_WUF14(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14))
screamer 0:c5e2f793b59a 1433
screamer 0:c5e2f793b59a 1434 /*! @brief Format value for bitfield LLWU_F2_WUF14. */
screamer 0:c5e2f793b59a 1435 #define BF_LLWU_F2_WUF14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF14) & BM_LLWU_F2_WUF14)
screamer 0:c5e2f793b59a 1436
screamer 0:c5e2f793b59a 1437 /*! @brief Set the WUF14 field to a new value. */
screamer 0:c5e2f793b59a 1438 #define BW_LLWU_F2_WUF14(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14) = (v))
screamer 0:c5e2f793b59a 1439 /*@}*/
screamer 0:c5e2f793b59a 1440
screamer 0:c5e2f793b59a 1441 /*!
screamer 0:c5e2f793b59a 1442 * @name Register LLWU_F2, field WUF15[7] (W1C)
screamer 0:c5e2f793b59a 1443 *
screamer 0:c5e2f793b59a 1444 * Indicates that an enabled external wakeup pin was a source of exiting a
screamer 0:c5e2f793b59a 1445 * low-leakage power mode. To clear the flag, write a 1 to WUF15.
screamer 0:c5e2f793b59a 1446 *
screamer 0:c5e2f793b59a 1447 * Values:
screamer 0:c5e2f793b59a 1448 * - 0 - LLWU_P15 input was not a wakeup source
screamer 0:c5e2f793b59a 1449 * - 1 - LLWU_P15 input was a wakeup source
screamer 0:c5e2f793b59a 1450 */
screamer 0:c5e2f793b59a 1451 /*@{*/
screamer 0:c5e2f793b59a 1452 #define BP_LLWU_F2_WUF15 (7U) /*!< Bit position for LLWU_F2_WUF15. */
screamer 0:c5e2f793b59a 1453 #define BM_LLWU_F2_WUF15 (0x80U) /*!< Bit mask for LLWU_F2_WUF15. */
screamer 0:c5e2f793b59a 1454 #define BS_LLWU_F2_WUF15 (1U) /*!< Bit field size in bits for LLWU_F2_WUF15. */
screamer 0:c5e2f793b59a 1455
screamer 0:c5e2f793b59a 1456 /*! @brief Read current value of the LLWU_F2_WUF15 field. */
screamer 0:c5e2f793b59a 1457 #define BR_LLWU_F2_WUF15(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15))
screamer 0:c5e2f793b59a 1458
screamer 0:c5e2f793b59a 1459 /*! @brief Format value for bitfield LLWU_F2_WUF15. */
screamer 0:c5e2f793b59a 1460 #define BF_LLWU_F2_WUF15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF15) & BM_LLWU_F2_WUF15)
screamer 0:c5e2f793b59a 1461
screamer 0:c5e2f793b59a 1462 /*! @brief Set the WUF15 field to a new value. */
screamer 0:c5e2f793b59a 1463 #define BW_LLWU_F2_WUF15(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15) = (v))
screamer 0:c5e2f793b59a 1464 /*@}*/
screamer 0:c5e2f793b59a 1465
screamer 0:c5e2f793b59a 1466 /*******************************************************************************
screamer 0:c5e2f793b59a 1467 * HW_LLWU_F3 - LLWU Flag 3 register
screamer 0:c5e2f793b59a 1468 ******************************************************************************/
screamer 0:c5e2f793b59a 1469
screamer 0:c5e2f793b59a 1470 /*!
screamer 0:c5e2f793b59a 1471 * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
screamer 0:c5e2f793b59a 1472 *
screamer 0:c5e2f793b59a 1473 * Reset value: 0x00U
screamer 0:c5e2f793b59a 1474 *
screamer 0:c5e2f793b59a 1475 * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
screamer 0:c5e2f793b59a 1476 * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
screamer 0:c5e2f793b59a 1477 * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
screamer 0:c5e2f793b59a 1478 * For internal peripherals that are capable of running in a low-leakage power
screamer 0:c5e2f793b59a 1479 * mode, such as a real time clock module or CMP module, the flag from the
screamer 0:c5e2f793b59a 1480 * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
screamer 0:c5e2f793b59a 1481 * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
screamer 0:c5e2f793b59a 1482 * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
screamer 0:c5e2f793b59a 1483 * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
screamer 0:c5e2f793b59a 1484 * the IntroductionInformation found here describes the registers of the Reset
screamer 0:c5e2f793b59a 1485 * Control Module (RCM). The RCM implements many of the reset functions for the
screamer 0:c5e2f793b59a 1486 * chip. See the chip's reset chapter for more information. details for more
screamer 0:c5e2f793b59a 1487 * information.
screamer 0:c5e2f793b59a 1488 */
screamer 0:c5e2f793b59a 1489 typedef union _hw_llwu_f3
screamer 0:c5e2f793b59a 1490 {
screamer 0:c5e2f793b59a 1491 uint8_t U;
screamer 0:c5e2f793b59a 1492 struct _hw_llwu_f3_bitfields
screamer 0:c5e2f793b59a 1493 {
screamer 0:c5e2f793b59a 1494 uint8_t MWUF0 : 1; /*!< [0] Wakeup flag For module 0 */
screamer 0:c5e2f793b59a 1495 uint8_t MWUF1 : 1; /*!< [1] Wakeup flag For module 1 */
screamer 0:c5e2f793b59a 1496 uint8_t MWUF2 : 1; /*!< [2] Wakeup flag For module 2 */
screamer 0:c5e2f793b59a 1497 uint8_t MWUF3 : 1; /*!< [3] Wakeup flag For module 3 */
screamer 0:c5e2f793b59a 1498 uint8_t MWUF4 : 1; /*!< [4] Wakeup flag For module 4 */
screamer 0:c5e2f793b59a 1499 uint8_t MWUF5 : 1; /*!< [5] Wakeup flag For module 5 */
screamer 0:c5e2f793b59a 1500 uint8_t MWUF6 : 1; /*!< [6] Wakeup flag For module 6 */
screamer 0:c5e2f793b59a 1501 uint8_t MWUF7 : 1; /*!< [7] Wakeup flag For module 7 */
screamer 0:c5e2f793b59a 1502 } B;
screamer 0:c5e2f793b59a 1503 } hw_llwu_f3_t;
screamer 0:c5e2f793b59a 1504
screamer 0:c5e2f793b59a 1505 /*!
screamer 0:c5e2f793b59a 1506 * @name Constants and macros for entire LLWU_F3 register
screamer 0:c5e2f793b59a 1507 */
screamer 0:c5e2f793b59a 1508 /*@{*/
screamer 0:c5e2f793b59a 1509 #define HW_LLWU_F3_ADDR(x) ((x) + 0x7U)
screamer 0:c5e2f793b59a 1510
screamer 0:c5e2f793b59a 1511 #define HW_LLWU_F3(x) (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR(x))
screamer 0:c5e2f793b59a 1512 #define HW_LLWU_F3_RD(x) (HW_LLWU_F3(x).U)
screamer 0:c5e2f793b59a 1513 /*@}*/
screamer 0:c5e2f793b59a 1514
screamer 0:c5e2f793b59a 1515 /*
screamer 0:c5e2f793b59a 1516 * Constants & macros for individual LLWU_F3 bitfields
screamer 0:c5e2f793b59a 1517 */
screamer 0:c5e2f793b59a 1518
screamer 0:c5e2f793b59a 1519 /*!
screamer 0:c5e2f793b59a 1520 * @name Register LLWU_F3, field MWUF0[0] (RO)
screamer 0:c5e2f793b59a 1521 *
screamer 0:c5e2f793b59a 1522 * Indicates that an enabled internal peripheral was a source of exiting a
screamer 0:c5e2f793b59a 1523 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
screamer 0:c5e2f793b59a 1524 * clearing mechanism.
screamer 0:c5e2f793b59a 1525 *
screamer 0:c5e2f793b59a 1526 * Values:
screamer 0:c5e2f793b59a 1527 * - 0 - Module 0 input was not a wakeup source
screamer 0:c5e2f793b59a 1528 * - 1 - Module 0 input was a wakeup source
screamer 0:c5e2f793b59a 1529 */
screamer 0:c5e2f793b59a 1530 /*@{*/
screamer 0:c5e2f793b59a 1531 #define BP_LLWU_F3_MWUF0 (0U) /*!< Bit position for LLWU_F3_MWUF0. */
screamer 0:c5e2f793b59a 1532 #define BM_LLWU_F3_MWUF0 (0x01U) /*!< Bit mask for LLWU_F3_MWUF0. */
screamer 0:c5e2f793b59a 1533 #define BS_LLWU_F3_MWUF0 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF0. */
screamer 0:c5e2f793b59a 1534
screamer 0:c5e2f793b59a 1535 /*! @brief Read current value of the LLWU_F3_MWUF0 field. */
screamer 0:c5e2f793b59a 1536 #define BR_LLWU_F3_MWUF0(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF0))
screamer 0:c5e2f793b59a 1537 /*@}*/
screamer 0:c5e2f793b59a 1538
screamer 0:c5e2f793b59a 1539 /*!
screamer 0:c5e2f793b59a 1540 * @name Register LLWU_F3, field MWUF1[1] (RO)
screamer 0:c5e2f793b59a 1541 *
screamer 0:c5e2f793b59a 1542 * Indicates that an enabled internal peripheral was a source of exiting a
screamer 0:c5e2f793b59a 1543 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
screamer 0:c5e2f793b59a 1544 * clearing mechanism.
screamer 0:c5e2f793b59a 1545 *
screamer 0:c5e2f793b59a 1546 * Values:
screamer 0:c5e2f793b59a 1547 * - 0 - Module 1 input was not a wakeup source
screamer 0:c5e2f793b59a 1548 * - 1 - Module 1 input was a wakeup source
screamer 0:c5e2f793b59a 1549 */
screamer 0:c5e2f793b59a 1550 /*@{*/
screamer 0:c5e2f793b59a 1551 #define BP_LLWU_F3_MWUF1 (1U) /*!< Bit position for LLWU_F3_MWUF1. */
screamer 0:c5e2f793b59a 1552 #define BM_LLWU_F3_MWUF1 (0x02U) /*!< Bit mask for LLWU_F3_MWUF1. */
screamer 0:c5e2f793b59a 1553 #define BS_LLWU_F3_MWUF1 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF1. */
screamer 0:c5e2f793b59a 1554
screamer 0:c5e2f793b59a 1555 /*! @brief Read current value of the LLWU_F3_MWUF1 field. */
screamer 0:c5e2f793b59a 1556 #define BR_LLWU_F3_MWUF1(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF1))
screamer 0:c5e2f793b59a 1557 /*@}*/
screamer 0:c5e2f793b59a 1558
screamer 0:c5e2f793b59a 1559 /*!
screamer 0:c5e2f793b59a 1560 * @name Register LLWU_F3, field MWUF2[2] (RO)
screamer 0:c5e2f793b59a 1561 *
screamer 0:c5e2f793b59a 1562 * Indicates that an enabled internal peripheral was a source of exiting a
screamer 0:c5e2f793b59a 1563 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
screamer 0:c5e2f793b59a 1564 * clearing mechanism.
screamer 0:c5e2f793b59a 1565 *
screamer 0:c5e2f793b59a 1566 * Values:
screamer 0:c5e2f793b59a 1567 * - 0 - Module 2 input was not a wakeup source
screamer 0:c5e2f793b59a 1568 * - 1 - Module 2 input was a wakeup source
screamer 0:c5e2f793b59a 1569 */
screamer 0:c5e2f793b59a 1570 /*@{*/
screamer 0:c5e2f793b59a 1571 #define BP_LLWU_F3_MWUF2 (2U) /*!< Bit position for LLWU_F3_MWUF2. */
screamer 0:c5e2f793b59a 1572 #define BM_LLWU_F3_MWUF2 (0x04U) /*!< Bit mask for LLWU_F3_MWUF2. */
screamer 0:c5e2f793b59a 1573 #define BS_LLWU_F3_MWUF2 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF2. */
screamer 0:c5e2f793b59a 1574
screamer 0:c5e2f793b59a 1575 /*! @brief Read current value of the LLWU_F3_MWUF2 field. */
screamer 0:c5e2f793b59a 1576 #define BR_LLWU_F3_MWUF2(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF2))
screamer 0:c5e2f793b59a 1577 /*@}*/
screamer 0:c5e2f793b59a 1578
screamer 0:c5e2f793b59a 1579 /*!
screamer 0:c5e2f793b59a 1580 * @name Register LLWU_F3, field MWUF3[3] (RO)
screamer 0:c5e2f793b59a 1581 *
screamer 0:c5e2f793b59a 1582 * Indicates that an enabled internal peripheral was a source of exiting a
screamer 0:c5e2f793b59a 1583 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
screamer 0:c5e2f793b59a 1584 * clearing mechanism.
screamer 0:c5e2f793b59a 1585 *
screamer 0:c5e2f793b59a 1586 * Values:
screamer 0:c5e2f793b59a 1587 * - 0 - Module 3 input was not a wakeup source
screamer 0:c5e2f793b59a 1588 * - 1 - Module 3 input was a wakeup source
screamer 0:c5e2f793b59a 1589 */
screamer 0:c5e2f793b59a 1590 /*@{*/
screamer 0:c5e2f793b59a 1591 #define BP_LLWU_F3_MWUF3 (3U) /*!< Bit position for LLWU_F3_MWUF3. */
screamer 0:c5e2f793b59a 1592 #define BM_LLWU_F3_MWUF3 (0x08U) /*!< Bit mask for LLWU_F3_MWUF3. */
screamer 0:c5e2f793b59a 1593 #define BS_LLWU_F3_MWUF3 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF3. */
screamer 0:c5e2f793b59a 1594
screamer 0:c5e2f793b59a 1595 /*! @brief Read current value of the LLWU_F3_MWUF3 field. */
screamer 0:c5e2f793b59a 1596 #define BR_LLWU_F3_MWUF3(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF3))
screamer 0:c5e2f793b59a 1597 /*@}*/
screamer 0:c5e2f793b59a 1598
screamer 0:c5e2f793b59a 1599 /*!
screamer 0:c5e2f793b59a 1600 * @name Register LLWU_F3, field MWUF4[4] (RO)
screamer 0:c5e2f793b59a 1601 *
screamer 0:c5e2f793b59a 1602 * Indicates that an enabled internal peripheral was a source of exiting a
screamer 0:c5e2f793b59a 1603 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
screamer 0:c5e2f793b59a 1604 * clearing mechanism.
screamer 0:c5e2f793b59a 1605 *
screamer 0:c5e2f793b59a 1606 * Values:
screamer 0:c5e2f793b59a 1607 * - 0 - Module 4 input was not a wakeup source
screamer 0:c5e2f793b59a 1608 * - 1 - Module 4 input was a wakeup source
screamer 0:c5e2f793b59a 1609 */
screamer 0:c5e2f793b59a 1610 /*@{*/
screamer 0:c5e2f793b59a 1611 #define BP_LLWU_F3_MWUF4 (4U) /*!< Bit position for LLWU_F3_MWUF4. */
screamer 0:c5e2f793b59a 1612 #define BM_LLWU_F3_MWUF4 (0x10U) /*!< Bit mask for LLWU_F3_MWUF4. */
screamer 0:c5e2f793b59a 1613 #define BS_LLWU_F3_MWUF4 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF4. */
screamer 0:c5e2f793b59a 1614
screamer 0:c5e2f793b59a 1615 /*! @brief Read current value of the LLWU_F3_MWUF4 field. */
screamer 0:c5e2f793b59a 1616 #define BR_LLWU_F3_MWUF4(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF4))
screamer 0:c5e2f793b59a 1617 /*@}*/
screamer 0:c5e2f793b59a 1618
screamer 0:c5e2f793b59a 1619 /*!
screamer 0:c5e2f793b59a 1620 * @name Register LLWU_F3, field MWUF5[5] (RO)
screamer 0:c5e2f793b59a 1621 *
screamer 0:c5e2f793b59a 1622 * Indicates that an enabled internal peripheral was a source of exiting a
screamer 0:c5e2f793b59a 1623 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
screamer 0:c5e2f793b59a 1624 * clearing mechanism.
screamer 0:c5e2f793b59a 1625 *
screamer 0:c5e2f793b59a 1626 * Values:
screamer 0:c5e2f793b59a 1627 * - 0 - Module 5 input was not a wakeup source
screamer 0:c5e2f793b59a 1628 * - 1 - Module 5 input was a wakeup source
screamer 0:c5e2f793b59a 1629 */
screamer 0:c5e2f793b59a 1630 /*@{*/
screamer 0:c5e2f793b59a 1631 #define BP_LLWU_F3_MWUF5 (5U) /*!< Bit position for LLWU_F3_MWUF5. */
screamer 0:c5e2f793b59a 1632 #define BM_LLWU_F3_MWUF5 (0x20U) /*!< Bit mask for LLWU_F3_MWUF5. */
screamer 0:c5e2f793b59a 1633 #define BS_LLWU_F3_MWUF5 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF5. */
screamer 0:c5e2f793b59a 1634
screamer 0:c5e2f793b59a 1635 /*! @brief Read current value of the LLWU_F3_MWUF5 field. */
screamer 0:c5e2f793b59a 1636 #define BR_LLWU_F3_MWUF5(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF5))
screamer 0:c5e2f793b59a 1637 /*@}*/
screamer 0:c5e2f793b59a 1638
screamer 0:c5e2f793b59a 1639 /*!
screamer 0:c5e2f793b59a 1640 * @name Register LLWU_F3, field MWUF6[6] (RO)
screamer 0:c5e2f793b59a 1641 *
screamer 0:c5e2f793b59a 1642 * Indicates that an enabled internal peripheral was a source of exiting a
screamer 0:c5e2f793b59a 1643 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
screamer 0:c5e2f793b59a 1644 * clearing mechanism.
screamer 0:c5e2f793b59a 1645 *
screamer 0:c5e2f793b59a 1646 * Values:
screamer 0:c5e2f793b59a 1647 * - 0 - Module 6 input was not a wakeup source
screamer 0:c5e2f793b59a 1648 * - 1 - Module 6 input was a wakeup source
screamer 0:c5e2f793b59a 1649 */
screamer 0:c5e2f793b59a 1650 /*@{*/
screamer 0:c5e2f793b59a 1651 #define BP_LLWU_F3_MWUF6 (6U) /*!< Bit position for LLWU_F3_MWUF6. */
screamer 0:c5e2f793b59a 1652 #define BM_LLWU_F3_MWUF6 (0x40U) /*!< Bit mask for LLWU_F3_MWUF6. */
screamer 0:c5e2f793b59a 1653 #define BS_LLWU_F3_MWUF6 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF6. */
screamer 0:c5e2f793b59a 1654
screamer 0:c5e2f793b59a 1655 /*! @brief Read current value of the LLWU_F3_MWUF6 field. */
screamer 0:c5e2f793b59a 1656 #define BR_LLWU_F3_MWUF6(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF6))
screamer 0:c5e2f793b59a 1657 /*@}*/
screamer 0:c5e2f793b59a 1658
screamer 0:c5e2f793b59a 1659 /*!
screamer 0:c5e2f793b59a 1660 * @name Register LLWU_F3, field MWUF7[7] (RO)
screamer 0:c5e2f793b59a 1661 *
screamer 0:c5e2f793b59a 1662 * Indicates that an enabled internal peripheral was a source of exiting a
screamer 0:c5e2f793b59a 1663 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
screamer 0:c5e2f793b59a 1664 * clearing mechanism.
screamer 0:c5e2f793b59a 1665 *
screamer 0:c5e2f793b59a 1666 * Values:
screamer 0:c5e2f793b59a 1667 * - 0 - Module 7 input was not a wakeup source
screamer 0:c5e2f793b59a 1668 * - 1 - Module 7 input was a wakeup source
screamer 0:c5e2f793b59a 1669 */
screamer 0:c5e2f793b59a 1670 /*@{*/
screamer 0:c5e2f793b59a 1671 #define BP_LLWU_F3_MWUF7 (7U) /*!< Bit position for LLWU_F3_MWUF7. */
screamer 0:c5e2f793b59a 1672 #define BM_LLWU_F3_MWUF7 (0x80U) /*!< Bit mask for LLWU_F3_MWUF7. */
screamer 0:c5e2f793b59a 1673 #define BS_LLWU_F3_MWUF7 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF7. */
screamer 0:c5e2f793b59a 1674
screamer 0:c5e2f793b59a 1675 /*! @brief Read current value of the LLWU_F3_MWUF7 field. */
screamer 0:c5e2f793b59a 1676 #define BR_LLWU_F3_MWUF7(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF7))
screamer 0:c5e2f793b59a 1677 /*@}*/
screamer 0:c5e2f793b59a 1678
screamer 0:c5e2f793b59a 1679 /*******************************************************************************
screamer 0:c5e2f793b59a 1680 * HW_LLWU_FILT1 - LLWU Pin Filter 1 register
screamer 0:c5e2f793b59a 1681 ******************************************************************************/
screamer 0:c5e2f793b59a 1682
screamer 0:c5e2f793b59a 1683 /*!
screamer 0:c5e2f793b59a 1684 * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
screamer 0:c5e2f793b59a 1685 *
screamer 0:c5e2f793b59a 1686 * Reset value: 0x00U
screamer 0:c5e2f793b59a 1687 *
screamer 0:c5e2f793b59a 1688 * LLWU_FILT1 is a control and status register that is used to enable/disable
screamer 0:c5e2f793b59a 1689 * the digital filter 1 features for an external pin. This register is reset on
screamer 0:c5e2f793b59a 1690 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 1691 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 1692 * IntroductionInformation found here describes the registers of the Reset Control
screamer 0:c5e2f793b59a 1693 * Module (RCM). The RCM implements many of the reset functions for the chip. See
screamer 0:c5e2f793b59a 1694 * the chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 1695 */
screamer 0:c5e2f793b59a 1696 typedef union _hw_llwu_filt1
screamer 0:c5e2f793b59a 1697 {
screamer 0:c5e2f793b59a 1698 uint8_t U;
screamer 0:c5e2f793b59a 1699 struct _hw_llwu_filt1_bitfields
screamer 0:c5e2f793b59a 1700 {
screamer 0:c5e2f793b59a 1701 uint8_t FILTSEL : 4; /*!< [3:0] Filter Pin Select */
screamer 0:c5e2f793b59a 1702 uint8_t RESERVED0 : 1; /*!< [4] */
screamer 0:c5e2f793b59a 1703 uint8_t FILTE : 2; /*!< [6:5] Digital Filter On External Pin */
screamer 0:c5e2f793b59a 1704 uint8_t FILTF : 1; /*!< [7] Filter Detect Flag */
screamer 0:c5e2f793b59a 1705 } B;
screamer 0:c5e2f793b59a 1706 } hw_llwu_filt1_t;
screamer 0:c5e2f793b59a 1707
screamer 0:c5e2f793b59a 1708 /*!
screamer 0:c5e2f793b59a 1709 * @name Constants and macros for entire LLWU_FILT1 register
screamer 0:c5e2f793b59a 1710 */
screamer 0:c5e2f793b59a 1711 /*@{*/
screamer 0:c5e2f793b59a 1712 #define HW_LLWU_FILT1_ADDR(x) ((x) + 0x8U)
screamer 0:c5e2f793b59a 1713
screamer 0:c5e2f793b59a 1714 #define HW_LLWU_FILT1(x) (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR(x))
screamer 0:c5e2f793b59a 1715 #define HW_LLWU_FILT1_RD(x) (HW_LLWU_FILT1(x).U)
screamer 0:c5e2f793b59a 1716 #define HW_LLWU_FILT1_WR(x, v) (HW_LLWU_FILT1(x).U = (v))
screamer 0:c5e2f793b59a 1717 #define HW_LLWU_FILT1_SET(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) | (v)))
screamer 0:c5e2f793b59a 1718 #define HW_LLWU_FILT1_CLR(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1719 #define HW_LLWU_FILT1_TOG(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1720 /*@}*/
screamer 0:c5e2f793b59a 1721
screamer 0:c5e2f793b59a 1722 /*
screamer 0:c5e2f793b59a 1723 * Constants & macros for individual LLWU_FILT1 bitfields
screamer 0:c5e2f793b59a 1724 */
screamer 0:c5e2f793b59a 1725
screamer 0:c5e2f793b59a 1726 /*!
screamer 0:c5e2f793b59a 1727 * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
screamer 0:c5e2f793b59a 1728 *
screamer 0:c5e2f793b59a 1729 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
screamer 0:c5e2f793b59a 1730 *
screamer 0:c5e2f793b59a 1731 * Values:
screamer 0:c5e2f793b59a 1732 * - 0000 - Select LLWU_P0 for filter
screamer 0:c5e2f793b59a 1733 * - 1111 - Select LLWU_P15 for filter
screamer 0:c5e2f793b59a 1734 */
screamer 0:c5e2f793b59a 1735 /*@{*/
screamer 0:c5e2f793b59a 1736 #define BP_LLWU_FILT1_FILTSEL (0U) /*!< Bit position for LLWU_FILT1_FILTSEL. */
screamer 0:c5e2f793b59a 1737 #define BM_LLWU_FILT1_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT1_FILTSEL. */
screamer 0:c5e2f793b59a 1738 #define BS_LLWU_FILT1_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT1_FILTSEL. */
screamer 0:c5e2f793b59a 1739
screamer 0:c5e2f793b59a 1740 /*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
screamer 0:c5e2f793b59a 1741 #define BR_LLWU_FILT1_FILTSEL(x) (HW_LLWU_FILT1(x).B.FILTSEL)
screamer 0:c5e2f793b59a 1742
screamer 0:c5e2f793b59a 1743 /*! @brief Format value for bitfield LLWU_FILT1_FILTSEL. */
screamer 0:c5e2f793b59a 1744 #define BF_LLWU_FILT1_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTSEL) & BM_LLWU_FILT1_FILTSEL)
screamer 0:c5e2f793b59a 1745
screamer 0:c5e2f793b59a 1746 /*! @brief Set the FILTSEL field to a new value. */
screamer 0:c5e2f793b59a 1747 #define BW_LLWU_FILT1_FILTSEL(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
screamer 0:c5e2f793b59a 1748 /*@}*/
screamer 0:c5e2f793b59a 1749
screamer 0:c5e2f793b59a 1750 /*!
screamer 0:c5e2f793b59a 1751 * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
screamer 0:c5e2f793b59a 1752 *
screamer 0:c5e2f793b59a 1753 * Controls the digital filter options for the external pin detect.
screamer 0:c5e2f793b59a 1754 *
screamer 0:c5e2f793b59a 1755 * Values:
screamer 0:c5e2f793b59a 1756 * - 00 - Filter disabled
screamer 0:c5e2f793b59a 1757 * - 01 - Filter posedge detect enabled
screamer 0:c5e2f793b59a 1758 * - 10 - Filter negedge detect enabled
screamer 0:c5e2f793b59a 1759 * - 11 - Filter any edge detect enabled
screamer 0:c5e2f793b59a 1760 */
screamer 0:c5e2f793b59a 1761 /*@{*/
screamer 0:c5e2f793b59a 1762 #define BP_LLWU_FILT1_FILTE (5U) /*!< Bit position for LLWU_FILT1_FILTE. */
screamer 0:c5e2f793b59a 1763 #define BM_LLWU_FILT1_FILTE (0x60U) /*!< Bit mask for LLWU_FILT1_FILTE. */
screamer 0:c5e2f793b59a 1764 #define BS_LLWU_FILT1_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT1_FILTE. */
screamer 0:c5e2f793b59a 1765
screamer 0:c5e2f793b59a 1766 /*! @brief Read current value of the LLWU_FILT1_FILTE field. */
screamer 0:c5e2f793b59a 1767 #define BR_LLWU_FILT1_FILTE(x) (HW_LLWU_FILT1(x).B.FILTE)
screamer 0:c5e2f793b59a 1768
screamer 0:c5e2f793b59a 1769 /*! @brief Format value for bitfield LLWU_FILT1_FILTE. */
screamer 0:c5e2f793b59a 1770 #define BF_LLWU_FILT1_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTE) & BM_LLWU_FILT1_FILTE)
screamer 0:c5e2f793b59a 1771
screamer 0:c5e2f793b59a 1772 /*! @brief Set the FILTE field to a new value. */
screamer 0:c5e2f793b59a 1773 #define BW_LLWU_FILT1_FILTE(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
screamer 0:c5e2f793b59a 1774 /*@}*/
screamer 0:c5e2f793b59a 1775
screamer 0:c5e2f793b59a 1776 /*!
screamer 0:c5e2f793b59a 1777 * @name Register LLWU_FILT1, field FILTF[7] (W1C)
screamer 0:c5e2f793b59a 1778 *
screamer 0:c5e2f793b59a 1779 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
screamer 0:c5e2f793b59a 1780 * source of exiting a low-leakage power mode. To clear the flag write a one to
screamer 0:c5e2f793b59a 1781 * FILTF.
screamer 0:c5e2f793b59a 1782 *
screamer 0:c5e2f793b59a 1783 * Values:
screamer 0:c5e2f793b59a 1784 * - 0 - Pin Filter 1 was not a wakeup source
screamer 0:c5e2f793b59a 1785 * - 1 - Pin Filter 1 was a wakeup source
screamer 0:c5e2f793b59a 1786 */
screamer 0:c5e2f793b59a 1787 /*@{*/
screamer 0:c5e2f793b59a 1788 #define BP_LLWU_FILT1_FILTF (7U) /*!< Bit position for LLWU_FILT1_FILTF. */
screamer 0:c5e2f793b59a 1789 #define BM_LLWU_FILT1_FILTF (0x80U) /*!< Bit mask for LLWU_FILT1_FILTF. */
screamer 0:c5e2f793b59a 1790 #define BS_LLWU_FILT1_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT1_FILTF. */
screamer 0:c5e2f793b59a 1791
screamer 0:c5e2f793b59a 1792 /*! @brief Read current value of the LLWU_FILT1_FILTF field. */
screamer 0:c5e2f793b59a 1793 #define BR_LLWU_FILT1_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF))
screamer 0:c5e2f793b59a 1794
screamer 0:c5e2f793b59a 1795 /*! @brief Format value for bitfield LLWU_FILT1_FILTF. */
screamer 0:c5e2f793b59a 1796 #define BF_LLWU_FILT1_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTF) & BM_LLWU_FILT1_FILTF)
screamer 0:c5e2f793b59a 1797
screamer 0:c5e2f793b59a 1798 /*! @brief Set the FILTF field to a new value. */
screamer 0:c5e2f793b59a 1799 #define BW_LLWU_FILT1_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF) = (v))
screamer 0:c5e2f793b59a 1800 /*@}*/
screamer 0:c5e2f793b59a 1801
screamer 0:c5e2f793b59a 1802 /*******************************************************************************
screamer 0:c5e2f793b59a 1803 * HW_LLWU_FILT2 - LLWU Pin Filter 2 register
screamer 0:c5e2f793b59a 1804 ******************************************************************************/
screamer 0:c5e2f793b59a 1805
screamer 0:c5e2f793b59a 1806 /*!
screamer 0:c5e2f793b59a 1807 * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
screamer 0:c5e2f793b59a 1808 *
screamer 0:c5e2f793b59a 1809 * Reset value: 0x00U
screamer 0:c5e2f793b59a 1810 *
screamer 0:c5e2f793b59a 1811 * LLWU_FILT2 is a control and status register that is used to enable/disable
screamer 0:c5e2f793b59a 1812 * the digital filter 2 features for an external pin. This register is reset on
screamer 0:c5e2f793b59a 1813 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 1814 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 1815 * IntroductionInformation found here describes the registers of the Reset Control
screamer 0:c5e2f793b59a 1816 * Module (RCM). The RCM implements many of the reset functions for the chip. See
screamer 0:c5e2f793b59a 1817 * the chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 1818 */
screamer 0:c5e2f793b59a 1819 typedef union _hw_llwu_filt2
screamer 0:c5e2f793b59a 1820 {
screamer 0:c5e2f793b59a 1821 uint8_t U;
screamer 0:c5e2f793b59a 1822 struct _hw_llwu_filt2_bitfields
screamer 0:c5e2f793b59a 1823 {
screamer 0:c5e2f793b59a 1824 uint8_t FILTSEL : 4; /*!< [3:0] Filter Pin Select */
screamer 0:c5e2f793b59a 1825 uint8_t RESERVED0 : 1; /*!< [4] */
screamer 0:c5e2f793b59a 1826 uint8_t FILTE : 2; /*!< [6:5] Digital Filter On External Pin */
screamer 0:c5e2f793b59a 1827 uint8_t FILTF : 1; /*!< [7] Filter Detect Flag */
screamer 0:c5e2f793b59a 1828 } B;
screamer 0:c5e2f793b59a 1829 } hw_llwu_filt2_t;
screamer 0:c5e2f793b59a 1830
screamer 0:c5e2f793b59a 1831 /*!
screamer 0:c5e2f793b59a 1832 * @name Constants and macros for entire LLWU_FILT2 register
screamer 0:c5e2f793b59a 1833 */
screamer 0:c5e2f793b59a 1834 /*@{*/
screamer 0:c5e2f793b59a 1835 #define HW_LLWU_FILT2_ADDR(x) ((x) + 0x9U)
screamer 0:c5e2f793b59a 1836
screamer 0:c5e2f793b59a 1837 #define HW_LLWU_FILT2(x) (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR(x))
screamer 0:c5e2f793b59a 1838 #define HW_LLWU_FILT2_RD(x) (HW_LLWU_FILT2(x).U)
screamer 0:c5e2f793b59a 1839 #define HW_LLWU_FILT2_WR(x, v) (HW_LLWU_FILT2(x).U = (v))
screamer 0:c5e2f793b59a 1840 #define HW_LLWU_FILT2_SET(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) | (v)))
screamer 0:c5e2f793b59a 1841 #define HW_LLWU_FILT2_CLR(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1842 #define HW_LLWU_FILT2_TOG(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1843 /*@}*/
screamer 0:c5e2f793b59a 1844
screamer 0:c5e2f793b59a 1845 /*
screamer 0:c5e2f793b59a 1846 * Constants & macros for individual LLWU_FILT2 bitfields
screamer 0:c5e2f793b59a 1847 */
screamer 0:c5e2f793b59a 1848
screamer 0:c5e2f793b59a 1849 /*!
screamer 0:c5e2f793b59a 1850 * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
screamer 0:c5e2f793b59a 1851 *
screamer 0:c5e2f793b59a 1852 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
screamer 0:c5e2f793b59a 1853 *
screamer 0:c5e2f793b59a 1854 * Values:
screamer 0:c5e2f793b59a 1855 * - 0000 - Select LLWU_P0 for filter
screamer 0:c5e2f793b59a 1856 * - 1111 - Select LLWU_P15 for filter
screamer 0:c5e2f793b59a 1857 */
screamer 0:c5e2f793b59a 1858 /*@{*/
screamer 0:c5e2f793b59a 1859 #define BP_LLWU_FILT2_FILTSEL (0U) /*!< Bit position for LLWU_FILT2_FILTSEL. */
screamer 0:c5e2f793b59a 1860 #define BM_LLWU_FILT2_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT2_FILTSEL. */
screamer 0:c5e2f793b59a 1861 #define BS_LLWU_FILT2_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT2_FILTSEL. */
screamer 0:c5e2f793b59a 1862
screamer 0:c5e2f793b59a 1863 /*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
screamer 0:c5e2f793b59a 1864 #define BR_LLWU_FILT2_FILTSEL(x) (HW_LLWU_FILT2(x).B.FILTSEL)
screamer 0:c5e2f793b59a 1865
screamer 0:c5e2f793b59a 1866 /*! @brief Format value for bitfield LLWU_FILT2_FILTSEL. */
screamer 0:c5e2f793b59a 1867 #define BF_LLWU_FILT2_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTSEL) & BM_LLWU_FILT2_FILTSEL)
screamer 0:c5e2f793b59a 1868
screamer 0:c5e2f793b59a 1869 /*! @brief Set the FILTSEL field to a new value. */
screamer 0:c5e2f793b59a 1870 #define BW_LLWU_FILT2_FILTSEL(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
screamer 0:c5e2f793b59a 1871 /*@}*/
screamer 0:c5e2f793b59a 1872
screamer 0:c5e2f793b59a 1873 /*!
screamer 0:c5e2f793b59a 1874 * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
screamer 0:c5e2f793b59a 1875 *
screamer 0:c5e2f793b59a 1876 * Controls the digital filter options for the external pin detect.
screamer 0:c5e2f793b59a 1877 *
screamer 0:c5e2f793b59a 1878 * Values:
screamer 0:c5e2f793b59a 1879 * - 00 - Filter disabled
screamer 0:c5e2f793b59a 1880 * - 01 - Filter posedge detect enabled
screamer 0:c5e2f793b59a 1881 * - 10 - Filter negedge detect enabled
screamer 0:c5e2f793b59a 1882 * - 11 - Filter any edge detect enabled
screamer 0:c5e2f793b59a 1883 */
screamer 0:c5e2f793b59a 1884 /*@{*/
screamer 0:c5e2f793b59a 1885 #define BP_LLWU_FILT2_FILTE (5U) /*!< Bit position for LLWU_FILT2_FILTE. */
screamer 0:c5e2f793b59a 1886 #define BM_LLWU_FILT2_FILTE (0x60U) /*!< Bit mask for LLWU_FILT2_FILTE. */
screamer 0:c5e2f793b59a 1887 #define BS_LLWU_FILT2_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT2_FILTE. */
screamer 0:c5e2f793b59a 1888
screamer 0:c5e2f793b59a 1889 /*! @brief Read current value of the LLWU_FILT2_FILTE field. */
screamer 0:c5e2f793b59a 1890 #define BR_LLWU_FILT2_FILTE(x) (HW_LLWU_FILT2(x).B.FILTE)
screamer 0:c5e2f793b59a 1891
screamer 0:c5e2f793b59a 1892 /*! @brief Format value for bitfield LLWU_FILT2_FILTE. */
screamer 0:c5e2f793b59a 1893 #define BF_LLWU_FILT2_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTE) & BM_LLWU_FILT2_FILTE)
screamer 0:c5e2f793b59a 1894
screamer 0:c5e2f793b59a 1895 /*! @brief Set the FILTE field to a new value. */
screamer 0:c5e2f793b59a 1896 #define BW_LLWU_FILT2_FILTE(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
screamer 0:c5e2f793b59a 1897 /*@}*/
screamer 0:c5e2f793b59a 1898
screamer 0:c5e2f793b59a 1899 /*!
screamer 0:c5e2f793b59a 1900 * @name Register LLWU_FILT2, field FILTF[7] (W1C)
screamer 0:c5e2f793b59a 1901 *
screamer 0:c5e2f793b59a 1902 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
screamer 0:c5e2f793b59a 1903 * source of exiting a low-leakage power mode. To clear the flag write a one to
screamer 0:c5e2f793b59a 1904 * FILTF.
screamer 0:c5e2f793b59a 1905 *
screamer 0:c5e2f793b59a 1906 * Values:
screamer 0:c5e2f793b59a 1907 * - 0 - Pin Filter 2 was not a wakeup source
screamer 0:c5e2f793b59a 1908 * - 1 - Pin Filter 2 was a wakeup source
screamer 0:c5e2f793b59a 1909 */
screamer 0:c5e2f793b59a 1910 /*@{*/
screamer 0:c5e2f793b59a 1911 #define BP_LLWU_FILT2_FILTF (7U) /*!< Bit position for LLWU_FILT2_FILTF. */
screamer 0:c5e2f793b59a 1912 #define BM_LLWU_FILT2_FILTF (0x80U) /*!< Bit mask for LLWU_FILT2_FILTF. */
screamer 0:c5e2f793b59a 1913 #define BS_LLWU_FILT2_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT2_FILTF. */
screamer 0:c5e2f793b59a 1914
screamer 0:c5e2f793b59a 1915 /*! @brief Read current value of the LLWU_FILT2_FILTF field. */
screamer 0:c5e2f793b59a 1916 #define BR_LLWU_FILT2_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF))
screamer 0:c5e2f793b59a 1917
screamer 0:c5e2f793b59a 1918 /*! @brief Format value for bitfield LLWU_FILT2_FILTF. */
screamer 0:c5e2f793b59a 1919 #define BF_LLWU_FILT2_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTF) & BM_LLWU_FILT2_FILTF)
screamer 0:c5e2f793b59a 1920
screamer 0:c5e2f793b59a 1921 /*! @brief Set the FILTF field to a new value. */
screamer 0:c5e2f793b59a 1922 #define BW_LLWU_FILT2_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF) = (v))
screamer 0:c5e2f793b59a 1923 /*@}*/
screamer 0:c5e2f793b59a 1924
screamer 0:c5e2f793b59a 1925 /*******************************************************************************
screamer 0:c5e2f793b59a 1926 * HW_LLWU_RST - LLWU Reset Enable register
screamer 0:c5e2f793b59a 1927 ******************************************************************************/
screamer 0:c5e2f793b59a 1928
screamer 0:c5e2f793b59a 1929 /*!
screamer 0:c5e2f793b59a 1930 * @brief HW_LLWU_RST - LLWU Reset Enable register (RW)
screamer 0:c5e2f793b59a 1931 *
screamer 0:c5e2f793b59a 1932 * Reset value: 0x02U
screamer 0:c5e2f793b59a 1933 *
screamer 0:c5e2f793b59a 1934 * LLWU_RST is a control register that is used to enable/disable the digital
screamer 0:c5e2f793b59a 1935 * filter for the external pin detect and RESET pin. This register is reset on Chip
screamer 0:c5e2f793b59a 1936 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
screamer 0:c5e2f793b59a 1937 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
screamer 0:c5e2f793b59a 1938 * IntroductionInformation found here describes the registers of the Reset Control
screamer 0:c5e2f793b59a 1939 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
screamer 0:c5e2f793b59a 1940 * chip's reset chapter for more information. details for more information.
screamer 0:c5e2f793b59a 1941 */
screamer 0:c5e2f793b59a 1942 typedef union _hw_llwu_rst
screamer 0:c5e2f793b59a 1943 {
screamer 0:c5e2f793b59a 1944 uint8_t U;
screamer 0:c5e2f793b59a 1945 struct _hw_llwu_rst_bitfields
screamer 0:c5e2f793b59a 1946 {
screamer 0:c5e2f793b59a 1947 uint8_t RSTFILT : 1; /*!< [0] Digital Filter On RESET Pin */
screamer 0:c5e2f793b59a 1948 uint8_t LLRSTE : 1; /*!< [1] Low-Leakage Mode RESET Enable */
screamer 0:c5e2f793b59a 1949 uint8_t RESERVED0 : 6; /*!< [7:2] */
screamer 0:c5e2f793b59a 1950 } B;
screamer 0:c5e2f793b59a 1951 } hw_llwu_rst_t;
screamer 0:c5e2f793b59a 1952
screamer 0:c5e2f793b59a 1953 /*!
screamer 0:c5e2f793b59a 1954 * @name Constants and macros for entire LLWU_RST register
screamer 0:c5e2f793b59a 1955 */
screamer 0:c5e2f793b59a 1956 /*@{*/
screamer 0:c5e2f793b59a 1957 #define HW_LLWU_RST_ADDR(x) ((x) + 0xAU)
screamer 0:c5e2f793b59a 1958
screamer 0:c5e2f793b59a 1959 #define HW_LLWU_RST(x) (*(__IO hw_llwu_rst_t *) HW_LLWU_RST_ADDR(x))
screamer 0:c5e2f793b59a 1960 #define HW_LLWU_RST_RD(x) (HW_LLWU_RST(x).U)
screamer 0:c5e2f793b59a 1961 #define HW_LLWU_RST_WR(x, v) (HW_LLWU_RST(x).U = (v))
screamer 0:c5e2f793b59a 1962 #define HW_LLWU_RST_SET(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) | (v)))
screamer 0:c5e2f793b59a 1963 #define HW_LLWU_RST_CLR(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1964 #define HW_LLWU_RST_TOG(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1965 /*@}*/
screamer 0:c5e2f793b59a 1966
screamer 0:c5e2f793b59a 1967 /*
screamer 0:c5e2f793b59a 1968 * Constants & macros for individual LLWU_RST bitfields
screamer 0:c5e2f793b59a 1969 */
screamer 0:c5e2f793b59a 1970
screamer 0:c5e2f793b59a 1971 /*!
screamer 0:c5e2f793b59a 1972 * @name Register LLWU_RST, field RSTFILT[0] (RW)
screamer 0:c5e2f793b59a 1973 *
screamer 0:c5e2f793b59a 1974 * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
screamer 0:c5e2f793b59a 1975 * VLLS1 modes.
screamer 0:c5e2f793b59a 1976 *
screamer 0:c5e2f793b59a 1977 * Values:
screamer 0:c5e2f793b59a 1978 * - 0 - Filter not enabled
screamer 0:c5e2f793b59a 1979 * - 1 - Filter enabled
screamer 0:c5e2f793b59a 1980 */
screamer 0:c5e2f793b59a 1981 /*@{*/
screamer 0:c5e2f793b59a 1982 #define BP_LLWU_RST_RSTFILT (0U) /*!< Bit position for LLWU_RST_RSTFILT. */
screamer 0:c5e2f793b59a 1983 #define BM_LLWU_RST_RSTFILT (0x01U) /*!< Bit mask for LLWU_RST_RSTFILT. */
screamer 0:c5e2f793b59a 1984 #define BS_LLWU_RST_RSTFILT (1U) /*!< Bit field size in bits for LLWU_RST_RSTFILT. */
screamer 0:c5e2f793b59a 1985
screamer 0:c5e2f793b59a 1986 /*! @brief Read current value of the LLWU_RST_RSTFILT field. */
screamer 0:c5e2f793b59a 1987 #define BR_LLWU_RST_RSTFILT(x) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT))
screamer 0:c5e2f793b59a 1988
screamer 0:c5e2f793b59a 1989 /*! @brief Format value for bitfield LLWU_RST_RSTFILT. */
screamer 0:c5e2f793b59a 1990 #define BF_LLWU_RST_RSTFILT(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_RSTFILT) & BM_LLWU_RST_RSTFILT)
screamer 0:c5e2f793b59a 1991
screamer 0:c5e2f793b59a 1992 /*! @brief Set the RSTFILT field to a new value. */
screamer 0:c5e2f793b59a 1993 #define BW_LLWU_RST_RSTFILT(x, v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT) = (v))
screamer 0:c5e2f793b59a 1994 /*@}*/
screamer 0:c5e2f793b59a 1995
screamer 0:c5e2f793b59a 1996 /*!
screamer 0:c5e2f793b59a 1997 * @name Register LLWU_RST, field LLRSTE[1] (RW)
screamer 0:c5e2f793b59a 1998 *
screamer 0:c5e2f793b59a 1999 * This bit must be set to allow the device to be reset while in a low-leakage
screamer 0:c5e2f793b59a 2000 * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
screamer 0:c5e2f793b59a 2001 * also be enabled in the explicit port mux control.
screamer 0:c5e2f793b59a 2002 *
screamer 0:c5e2f793b59a 2003 * Values:
screamer 0:c5e2f793b59a 2004 * - 0 - RESET pin not enabled as a leakage mode exit source
screamer 0:c5e2f793b59a 2005 * - 1 - RESET pin enabled as a low leakage mode exit source
screamer 0:c5e2f793b59a 2006 */
screamer 0:c5e2f793b59a 2007 /*@{*/
screamer 0:c5e2f793b59a 2008 #define BP_LLWU_RST_LLRSTE (1U) /*!< Bit position for LLWU_RST_LLRSTE. */
screamer 0:c5e2f793b59a 2009 #define BM_LLWU_RST_LLRSTE (0x02U) /*!< Bit mask for LLWU_RST_LLRSTE. */
screamer 0:c5e2f793b59a 2010 #define BS_LLWU_RST_LLRSTE (1U) /*!< Bit field size in bits for LLWU_RST_LLRSTE. */
screamer 0:c5e2f793b59a 2011
screamer 0:c5e2f793b59a 2012 /*! @brief Read current value of the LLWU_RST_LLRSTE field. */
screamer 0:c5e2f793b59a 2013 #define BR_LLWU_RST_LLRSTE(x) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE))
screamer 0:c5e2f793b59a 2014
screamer 0:c5e2f793b59a 2015 /*! @brief Format value for bitfield LLWU_RST_LLRSTE. */
screamer 0:c5e2f793b59a 2016 #define BF_LLWU_RST_LLRSTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_LLRSTE) & BM_LLWU_RST_LLRSTE)
screamer 0:c5e2f793b59a 2017
screamer 0:c5e2f793b59a 2018 /*! @brief Set the LLRSTE field to a new value. */
screamer 0:c5e2f793b59a 2019 #define BW_LLWU_RST_LLRSTE(x, v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE) = (v))
screamer 0:c5e2f793b59a 2020 /*@}*/
screamer 0:c5e2f793b59a 2021
screamer 0:c5e2f793b59a 2022 /*******************************************************************************
screamer 0:c5e2f793b59a 2023 * hw_llwu_t - module struct
screamer 0:c5e2f793b59a 2024 ******************************************************************************/
screamer 0:c5e2f793b59a 2025 /*!
screamer 0:c5e2f793b59a 2026 * @brief All LLWU module registers.
screamer 0:c5e2f793b59a 2027 */
screamer 0:c5e2f793b59a 2028 #pragma pack(1)
screamer 0:c5e2f793b59a 2029 typedef struct _hw_llwu
screamer 0:c5e2f793b59a 2030 {
screamer 0:c5e2f793b59a 2031 __IO hw_llwu_pe1_t PE1; /*!< [0x0] LLWU Pin Enable 1 register */
screamer 0:c5e2f793b59a 2032 __IO hw_llwu_pe2_t PE2; /*!< [0x1] LLWU Pin Enable 2 register */
screamer 0:c5e2f793b59a 2033 __IO hw_llwu_pe3_t PE3; /*!< [0x2] LLWU Pin Enable 3 register */
screamer 0:c5e2f793b59a 2034 __IO hw_llwu_pe4_t PE4; /*!< [0x3] LLWU Pin Enable 4 register */
screamer 0:c5e2f793b59a 2035 __IO hw_llwu_me_t ME; /*!< [0x4] LLWU Module Enable register */
screamer 0:c5e2f793b59a 2036 __IO hw_llwu_f1_t F1; /*!< [0x5] LLWU Flag 1 register */
screamer 0:c5e2f793b59a 2037 __IO hw_llwu_f2_t F2; /*!< [0x6] LLWU Flag 2 register */
screamer 0:c5e2f793b59a 2038 __I hw_llwu_f3_t F3; /*!< [0x7] LLWU Flag 3 register */
screamer 0:c5e2f793b59a 2039 __IO hw_llwu_filt1_t FILT1; /*!< [0x8] LLWU Pin Filter 1 register */
screamer 0:c5e2f793b59a 2040 __IO hw_llwu_filt2_t FILT2; /*!< [0x9] LLWU Pin Filter 2 register */
screamer 0:c5e2f793b59a 2041 __IO hw_llwu_rst_t RST; /*!< [0xA] LLWU Reset Enable register */
screamer 0:c5e2f793b59a 2042 } hw_llwu_t;
screamer 0:c5e2f793b59a 2043 #pragma pack()
screamer 0:c5e2f793b59a 2044
screamer 0:c5e2f793b59a 2045 /*! @brief Macro to access all LLWU registers. */
screamer 0:c5e2f793b59a 2046 /*! @param x LLWU module instance base address. */
screamer 0:c5e2f793b59a 2047 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
screamer 0:c5e2f793b59a 2048 * use the '&' operator, like <code>&HW_LLWU(LLWU_BASE)</code>. */
screamer 0:c5e2f793b59a 2049 #define HW_LLWU(x) (*(hw_llwu_t *)(x))
screamer 0:c5e2f793b59a 2050
screamer 0:c5e2f793b59a 2051 #endif /* __HW_LLWU_REGISTERS_H__ */
screamer 0:c5e2f793b59a 2052 /* EOF */