Morpheus / target-mcu-k64f

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hal/device/device/MK64F12/MK64F12_ftm.h@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 4 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 5 ** GNU C Compiler
screamer 0:c5e2f793b59a 6 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 9 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 10 ** Build: b140604
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Abstract:
screamer 0:c5e2f793b59a 13 ** Extension to the CMSIS register access layer header.
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 16 ** All rights reserved.
screamer 0:c5e2f793b59a 17 **
screamer 0:c5e2f793b59a 18 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 19 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 20 **
screamer 0:c5e2f793b59a 21 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 22 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 25 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 26 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 27 **
screamer 0:c5e2f793b59a 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 29 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 30 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 31 **
screamer 0:c5e2f793b59a 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 42 **
screamer 0:c5e2f793b59a 43 ** http: www.freescale.com
screamer 0:c5e2f793b59a 44 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 45 **
screamer 0:c5e2f793b59a 46 ** Revisions:
screamer 0:c5e2f793b59a 47 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 48 ** Initial version.
screamer 0:c5e2f793b59a 49 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 50 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 53 ** System initialization updated.
screamer 0:c5e2f793b59a 54 ** MCG - registers updated.
screamer 0:c5e2f793b59a 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 56 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 58 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 59 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 60 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 61 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 62 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 63 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 64 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 67 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 71 **
screamer 0:c5e2f793b59a 72 ** ###################################################################
screamer 0:c5e2f793b59a 73 */
screamer 0:c5e2f793b59a 74
screamer 0:c5e2f793b59a 75 /*
screamer 0:c5e2f793b59a 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
screamer 0:c5e2f793b59a 77 *
screamer 0:c5e2f793b59a 78 * This file was generated automatically and any changes may be lost.
screamer 0:c5e2f793b59a 79 */
screamer 0:c5e2f793b59a 80 #ifndef __HW_FTM_REGISTERS_H__
screamer 0:c5e2f793b59a 81 #define __HW_FTM_REGISTERS_H__
screamer 0:c5e2f793b59a 82
screamer 0:c5e2f793b59a 83 #include "MK64F12.h"
screamer 0:c5e2f793b59a 84 #include "fsl_bitaccess.h"
screamer 0:c5e2f793b59a 85
screamer 0:c5e2f793b59a 86 /*
screamer 0:c5e2f793b59a 87 * MK64F12 FTM
screamer 0:c5e2f793b59a 88 *
screamer 0:c5e2f793b59a 89 * FlexTimer Module
screamer 0:c5e2f793b59a 90 *
screamer 0:c5e2f793b59a 91 * Registers defined in this header file:
screamer 0:c5e2f793b59a 92 * - HW_FTM_SC - Status And Control
screamer 0:c5e2f793b59a 93 * - HW_FTM_CNT - Counter
screamer 0:c5e2f793b59a 94 * - HW_FTM_MOD - Modulo
screamer 0:c5e2f793b59a 95 * - HW_FTM_CnSC - Channel (n) Status And Control
screamer 0:c5e2f793b59a 96 * - HW_FTM_CnV - Channel (n) Value
screamer 0:c5e2f793b59a 97 * - HW_FTM_CNTIN - Counter Initial Value
screamer 0:c5e2f793b59a 98 * - HW_FTM_STATUS - Capture And Compare Status
screamer 0:c5e2f793b59a 99 * - HW_FTM_MODE - Features Mode Selection
screamer 0:c5e2f793b59a 100 * - HW_FTM_SYNC - Synchronization
screamer 0:c5e2f793b59a 101 * - HW_FTM_OUTINIT - Initial State For Channels Output
screamer 0:c5e2f793b59a 102 * - HW_FTM_OUTMASK - Output Mask
screamer 0:c5e2f793b59a 103 * - HW_FTM_COMBINE - Function For Linked Channels
screamer 0:c5e2f793b59a 104 * - HW_FTM_DEADTIME - Deadtime Insertion Control
screamer 0:c5e2f793b59a 105 * - HW_FTM_EXTTRIG - FTM External Trigger
screamer 0:c5e2f793b59a 106 * - HW_FTM_POL - Channels Polarity
screamer 0:c5e2f793b59a 107 * - HW_FTM_FMS - Fault Mode Status
screamer 0:c5e2f793b59a 108 * - HW_FTM_FILTER - Input Capture Filter Control
screamer 0:c5e2f793b59a 109 * - HW_FTM_FLTCTRL - Fault Control
screamer 0:c5e2f793b59a 110 * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
screamer 0:c5e2f793b59a 111 * - HW_FTM_CONF - Configuration
screamer 0:c5e2f793b59a 112 * - HW_FTM_FLTPOL - FTM Fault Input Polarity
screamer 0:c5e2f793b59a 113 * - HW_FTM_SYNCONF - Synchronization Configuration
screamer 0:c5e2f793b59a 114 * - HW_FTM_INVCTRL - FTM Inverting Control
screamer 0:c5e2f793b59a 115 * - HW_FTM_SWOCTRL - FTM Software Output Control
screamer 0:c5e2f793b59a 116 * - HW_FTM_PWMLOAD - FTM PWM Load
screamer 0:c5e2f793b59a 117 *
screamer 0:c5e2f793b59a 118 * - hw_ftm_t - Struct containing all module registers.
screamer 0:c5e2f793b59a 119 */
screamer 0:c5e2f793b59a 120
screamer 0:c5e2f793b59a 121 #define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
screamer 0:c5e2f793b59a 122 #define HW_FTM0 (0U) /*!< Instance number for FTM0. */
screamer 0:c5e2f793b59a 123 #define HW_FTM1 (1U) /*!< Instance number for FTM1. */
screamer 0:c5e2f793b59a 124 #define HW_FTM2 (2U) /*!< Instance number for FTM2. */
screamer 0:c5e2f793b59a 125 #define HW_FTM3 (3U) /*!< Instance number for FTM3. */
screamer 0:c5e2f793b59a 126
screamer 0:c5e2f793b59a 127 /*******************************************************************************
screamer 0:c5e2f793b59a 128 * HW_FTM_SC - Status And Control
screamer 0:c5e2f793b59a 129 ******************************************************************************/
screamer 0:c5e2f793b59a 130
screamer 0:c5e2f793b59a 131 /*!
screamer 0:c5e2f793b59a 132 * @brief HW_FTM_SC - Status And Control (RW)
screamer 0:c5e2f793b59a 133 *
screamer 0:c5e2f793b59a 134 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 135 *
screamer 0:c5e2f793b59a 136 * SC contains the overflow status flag and control bits used to configure the
screamer 0:c5e2f793b59a 137 * interrupt enable, FTM configuration, clock source, and prescaler factor. These
screamer 0:c5e2f793b59a 138 * controls relate to all channels within this module.
screamer 0:c5e2f793b59a 139 */
screamer 0:c5e2f793b59a 140 typedef union _hw_ftm_sc
screamer 0:c5e2f793b59a 141 {
screamer 0:c5e2f793b59a 142 uint32_t U;
screamer 0:c5e2f793b59a 143 struct _hw_ftm_sc_bitfields
screamer 0:c5e2f793b59a 144 {
screamer 0:c5e2f793b59a 145 uint32_t PS : 3; /*!< [2:0] Prescale Factor Selection */
screamer 0:c5e2f793b59a 146 uint32_t CLKS : 2; /*!< [4:3] Clock Source Selection */
screamer 0:c5e2f793b59a 147 uint32_t CPWMS : 1; /*!< [5] Center-Aligned PWM Select */
screamer 0:c5e2f793b59a 148 uint32_t TOIE : 1; /*!< [6] Timer Overflow Interrupt Enable */
screamer 0:c5e2f793b59a 149 uint32_t TOF : 1; /*!< [7] Timer Overflow Flag */
screamer 0:c5e2f793b59a 150 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 151 } B;
screamer 0:c5e2f793b59a 152 } hw_ftm_sc_t;
screamer 0:c5e2f793b59a 153
screamer 0:c5e2f793b59a 154 /*!
screamer 0:c5e2f793b59a 155 * @name Constants and macros for entire FTM_SC register
screamer 0:c5e2f793b59a 156 */
screamer 0:c5e2f793b59a 157 /*@{*/
screamer 0:c5e2f793b59a 158 #define HW_FTM_SC_ADDR(x) ((x) + 0x0U)
screamer 0:c5e2f793b59a 159
screamer 0:c5e2f793b59a 160 #define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
screamer 0:c5e2f793b59a 161 #define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
screamer 0:c5e2f793b59a 162 #define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
screamer 0:c5e2f793b59a 163 #define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v)))
screamer 0:c5e2f793b59a 164 #define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 165 #define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 166 /*@}*/
screamer 0:c5e2f793b59a 167
screamer 0:c5e2f793b59a 168 /*
screamer 0:c5e2f793b59a 169 * Constants & macros for individual FTM_SC bitfields
screamer 0:c5e2f793b59a 170 */
screamer 0:c5e2f793b59a 171
screamer 0:c5e2f793b59a 172 /*!
screamer 0:c5e2f793b59a 173 * @name Register FTM_SC, field PS[2:0] (RW)
screamer 0:c5e2f793b59a 174 *
screamer 0:c5e2f793b59a 175 * Selects one of 8 division factors for the clock source selected by CLKS. The
screamer 0:c5e2f793b59a 176 * new prescaler factor affects the clock source on the next system clock cycle
screamer 0:c5e2f793b59a 177 * after the new value is updated into the register bits. This field is write
screamer 0:c5e2f793b59a 178 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 179 *
screamer 0:c5e2f793b59a 180 * Values:
screamer 0:c5e2f793b59a 181 * - 000 - Divide by 1
screamer 0:c5e2f793b59a 182 * - 001 - Divide by 2
screamer 0:c5e2f793b59a 183 * - 010 - Divide by 4
screamer 0:c5e2f793b59a 184 * - 011 - Divide by 8
screamer 0:c5e2f793b59a 185 * - 100 - Divide by 16
screamer 0:c5e2f793b59a 186 * - 101 - Divide by 32
screamer 0:c5e2f793b59a 187 * - 110 - Divide by 64
screamer 0:c5e2f793b59a 188 * - 111 - Divide by 128
screamer 0:c5e2f793b59a 189 */
screamer 0:c5e2f793b59a 190 /*@{*/
screamer 0:c5e2f793b59a 191 #define BP_FTM_SC_PS (0U) /*!< Bit position for FTM_SC_PS. */
screamer 0:c5e2f793b59a 192 #define BM_FTM_SC_PS (0x00000007U) /*!< Bit mask for FTM_SC_PS. */
screamer 0:c5e2f793b59a 193 #define BS_FTM_SC_PS (3U) /*!< Bit field size in bits for FTM_SC_PS. */
screamer 0:c5e2f793b59a 194
screamer 0:c5e2f793b59a 195 /*! @brief Read current value of the FTM_SC_PS field. */
screamer 0:c5e2f793b59a 196 #define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
screamer 0:c5e2f793b59a 197
screamer 0:c5e2f793b59a 198 /*! @brief Format value for bitfield FTM_SC_PS. */
screamer 0:c5e2f793b59a 199 #define BF_FTM_SC_PS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS)
screamer 0:c5e2f793b59a 200
screamer 0:c5e2f793b59a 201 /*! @brief Set the PS field to a new value. */
screamer 0:c5e2f793b59a 202 #define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
screamer 0:c5e2f793b59a 203 /*@}*/
screamer 0:c5e2f793b59a 204
screamer 0:c5e2f793b59a 205 /*!
screamer 0:c5e2f793b59a 206 * @name Register FTM_SC, field CLKS[4:3] (RW)
screamer 0:c5e2f793b59a 207 *
screamer 0:c5e2f793b59a 208 * Selects one of the three FTM counter clock sources. This field is write
screamer 0:c5e2f793b59a 209 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 210 *
screamer 0:c5e2f793b59a 211 * Values:
screamer 0:c5e2f793b59a 212 * - 00 - No clock selected. This in effect disables the FTM counter.
screamer 0:c5e2f793b59a 213 * - 01 - System clock
screamer 0:c5e2f793b59a 214 * - 10 - Fixed frequency clock
screamer 0:c5e2f793b59a 215 * - 11 - External clock
screamer 0:c5e2f793b59a 216 */
screamer 0:c5e2f793b59a 217 /*@{*/
screamer 0:c5e2f793b59a 218 #define BP_FTM_SC_CLKS (3U) /*!< Bit position for FTM_SC_CLKS. */
screamer 0:c5e2f793b59a 219 #define BM_FTM_SC_CLKS (0x00000018U) /*!< Bit mask for FTM_SC_CLKS. */
screamer 0:c5e2f793b59a 220 #define BS_FTM_SC_CLKS (2U) /*!< Bit field size in bits for FTM_SC_CLKS. */
screamer 0:c5e2f793b59a 221
screamer 0:c5e2f793b59a 222 /*! @brief Read current value of the FTM_SC_CLKS field. */
screamer 0:c5e2f793b59a 223 #define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
screamer 0:c5e2f793b59a 224
screamer 0:c5e2f793b59a 225 /*! @brief Format value for bitfield FTM_SC_CLKS. */
screamer 0:c5e2f793b59a 226 #define BF_FTM_SC_CLKS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS)
screamer 0:c5e2f793b59a 227
screamer 0:c5e2f793b59a 228 /*! @brief Set the CLKS field to a new value. */
screamer 0:c5e2f793b59a 229 #define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
screamer 0:c5e2f793b59a 230 /*@}*/
screamer 0:c5e2f793b59a 231
screamer 0:c5e2f793b59a 232 /*!
screamer 0:c5e2f793b59a 233 * @name Register FTM_SC, field CPWMS[5] (RW)
screamer 0:c5e2f793b59a 234 *
screamer 0:c5e2f793b59a 235 * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
screamer 0:c5e2f793b59a 236 * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
screamer 0:c5e2f793b59a 237 * = 1.
screamer 0:c5e2f793b59a 238 *
screamer 0:c5e2f793b59a 239 * Values:
screamer 0:c5e2f793b59a 240 * - 0 - FTM counter operates in Up Counting mode.
screamer 0:c5e2f793b59a 241 * - 1 - FTM counter operates in Up-Down Counting mode.
screamer 0:c5e2f793b59a 242 */
screamer 0:c5e2f793b59a 243 /*@{*/
screamer 0:c5e2f793b59a 244 #define BP_FTM_SC_CPWMS (5U) /*!< Bit position for FTM_SC_CPWMS. */
screamer 0:c5e2f793b59a 245 #define BM_FTM_SC_CPWMS (0x00000020U) /*!< Bit mask for FTM_SC_CPWMS. */
screamer 0:c5e2f793b59a 246 #define BS_FTM_SC_CPWMS (1U) /*!< Bit field size in bits for FTM_SC_CPWMS. */
screamer 0:c5e2f793b59a 247
screamer 0:c5e2f793b59a 248 /*! @brief Read current value of the FTM_SC_CPWMS field. */
screamer 0:c5e2f793b59a 249 #define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
screamer 0:c5e2f793b59a 250
screamer 0:c5e2f793b59a 251 /*! @brief Format value for bitfield FTM_SC_CPWMS. */
screamer 0:c5e2f793b59a 252 #define BF_FTM_SC_CPWMS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS)
screamer 0:c5e2f793b59a 253
screamer 0:c5e2f793b59a 254 /*! @brief Set the CPWMS field to a new value. */
screamer 0:c5e2f793b59a 255 #define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
screamer 0:c5e2f793b59a 256 /*@}*/
screamer 0:c5e2f793b59a 257
screamer 0:c5e2f793b59a 258 /*!
screamer 0:c5e2f793b59a 259 * @name Register FTM_SC, field TOIE[6] (RW)
screamer 0:c5e2f793b59a 260 *
screamer 0:c5e2f793b59a 261 * Enables FTM overflow interrupts.
screamer 0:c5e2f793b59a 262 *
screamer 0:c5e2f793b59a 263 * Values:
screamer 0:c5e2f793b59a 264 * - 0 - Disable TOF interrupts. Use software polling.
screamer 0:c5e2f793b59a 265 * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
screamer 0:c5e2f793b59a 266 */
screamer 0:c5e2f793b59a 267 /*@{*/
screamer 0:c5e2f793b59a 268 #define BP_FTM_SC_TOIE (6U) /*!< Bit position for FTM_SC_TOIE. */
screamer 0:c5e2f793b59a 269 #define BM_FTM_SC_TOIE (0x00000040U) /*!< Bit mask for FTM_SC_TOIE. */
screamer 0:c5e2f793b59a 270 #define BS_FTM_SC_TOIE (1U) /*!< Bit field size in bits for FTM_SC_TOIE. */
screamer 0:c5e2f793b59a 271
screamer 0:c5e2f793b59a 272 /*! @brief Read current value of the FTM_SC_TOIE field. */
screamer 0:c5e2f793b59a 273 #define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
screamer 0:c5e2f793b59a 274
screamer 0:c5e2f793b59a 275 /*! @brief Format value for bitfield FTM_SC_TOIE. */
screamer 0:c5e2f793b59a 276 #define BF_FTM_SC_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE)
screamer 0:c5e2f793b59a 277
screamer 0:c5e2f793b59a 278 /*! @brief Set the TOIE field to a new value. */
screamer 0:c5e2f793b59a 279 #define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
screamer 0:c5e2f793b59a 280 /*@}*/
screamer 0:c5e2f793b59a 281
screamer 0:c5e2f793b59a 282 /*!
screamer 0:c5e2f793b59a 283 * @name Register FTM_SC, field TOF[7] (ROWZ)
screamer 0:c5e2f793b59a 284 *
screamer 0:c5e2f793b59a 285 * Set by hardware when the FTM counter passes the value in the MOD register.
screamer 0:c5e2f793b59a 286 * The TOF bit is cleared by reading the SC register while TOF is set and then
screamer 0:c5e2f793b59a 287 * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
screamer 0:c5e2f793b59a 288 * occurs between the read and write operations, the write operation has no
screamer 0:c5e2f793b59a 289 * effect; therefore, TOF remains set indicating an overflow has occurred. In this
screamer 0:c5e2f793b59a 290 * case, a TOF interrupt request is not lost due to the clearing sequence for a
screamer 0:c5e2f793b59a 291 * previous TOF.
screamer 0:c5e2f793b59a 292 *
screamer 0:c5e2f793b59a 293 * Values:
screamer 0:c5e2f793b59a 294 * - 0 - FTM counter has not overflowed.
screamer 0:c5e2f793b59a 295 * - 1 - FTM counter has overflowed.
screamer 0:c5e2f793b59a 296 */
screamer 0:c5e2f793b59a 297 /*@{*/
screamer 0:c5e2f793b59a 298 #define BP_FTM_SC_TOF (7U) /*!< Bit position for FTM_SC_TOF. */
screamer 0:c5e2f793b59a 299 #define BM_FTM_SC_TOF (0x00000080U) /*!< Bit mask for FTM_SC_TOF. */
screamer 0:c5e2f793b59a 300 #define BS_FTM_SC_TOF (1U) /*!< Bit field size in bits for FTM_SC_TOF. */
screamer 0:c5e2f793b59a 301
screamer 0:c5e2f793b59a 302 /*! @brief Read current value of the FTM_SC_TOF field. */
screamer 0:c5e2f793b59a 303 #define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
screamer 0:c5e2f793b59a 304
screamer 0:c5e2f793b59a 305 /*! @brief Format value for bitfield FTM_SC_TOF. */
screamer 0:c5e2f793b59a 306 #define BF_FTM_SC_TOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF)
screamer 0:c5e2f793b59a 307
screamer 0:c5e2f793b59a 308 /*! @brief Set the TOF field to a new value. */
screamer 0:c5e2f793b59a 309 #define BW_FTM_SC_TOF(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF) = (v))
screamer 0:c5e2f793b59a 310 /*@}*/
screamer 0:c5e2f793b59a 311
screamer 0:c5e2f793b59a 312 /*******************************************************************************
screamer 0:c5e2f793b59a 313 * HW_FTM_CNT - Counter
screamer 0:c5e2f793b59a 314 ******************************************************************************/
screamer 0:c5e2f793b59a 315
screamer 0:c5e2f793b59a 316 /*!
screamer 0:c5e2f793b59a 317 * @brief HW_FTM_CNT - Counter (RW)
screamer 0:c5e2f793b59a 318 *
screamer 0:c5e2f793b59a 319 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 320 *
screamer 0:c5e2f793b59a 321 * The CNT register contains the FTM counter value. Reset clears the CNT
screamer 0:c5e2f793b59a 322 * register. Writing any value to COUNT updates the counter with its initial value,
screamer 0:c5e2f793b59a 323 * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
screamer 0:c5e2f793b59a 324 * may read.
screamer 0:c5e2f793b59a 325 */
screamer 0:c5e2f793b59a 326 typedef union _hw_ftm_cnt
screamer 0:c5e2f793b59a 327 {
screamer 0:c5e2f793b59a 328 uint32_t U;
screamer 0:c5e2f793b59a 329 struct _hw_ftm_cnt_bitfields
screamer 0:c5e2f793b59a 330 {
screamer 0:c5e2f793b59a 331 uint32_t COUNT : 16; /*!< [15:0] Counter Value */
screamer 0:c5e2f793b59a 332 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 333 } B;
screamer 0:c5e2f793b59a 334 } hw_ftm_cnt_t;
screamer 0:c5e2f793b59a 335
screamer 0:c5e2f793b59a 336 /*!
screamer 0:c5e2f793b59a 337 * @name Constants and macros for entire FTM_CNT register
screamer 0:c5e2f793b59a 338 */
screamer 0:c5e2f793b59a 339 /*@{*/
screamer 0:c5e2f793b59a 340 #define HW_FTM_CNT_ADDR(x) ((x) + 0x4U)
screamer 0:c5e2f793b59a 341
screamer 0:c5e2f793b59a 342 #define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
screamer 0:c5e2f793b59a 343 #define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
screamer 0:c5e2f793b59a 344 #define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
screamer 0:c5e2f793b59a 345 #define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v)))
screamer 0:c5e2f793b59a 346 #define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 347 #define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 348 /*@}*/
screamer 0:c5e2f793b59a 349
screamer 0:c5e2f793b59a 350 /*
screamer 0:c5e2f793b59a 351 * Constants & macros for individual FTM_CNT bitfields
screamer 0:c5e2f793b59a 352 */
screamer 0:c5e2f793b59a 353
screamer 0:c5e2f793b59a 354 /*!
screamer 0:c5e2f793b59a 355 * @name Register FTM_CNT, field COUNT[15:0] (RW)
screamer 0:c5e2f793b59a 356 */
screamer 0:c5e2f793b59a 357 /*@{*/
screamer 0:c5e2f793b59a 358 #define BP_FTM_CNT_COUNT (0U) /*!< Bit position for FTM_CNT_COUNT. */
screamer 0:c5e2f793b59a 359 #define BM_FTM_CNT_COUNT (0x0000FFFFU) /*!< Bit mask for FTM_CNT_COUNT. */
screamer 0:c5e2f793b59a 360 #define BS_FTM_CNT_COUNT (16U) /*!< Bit field size in bits for FTM_CNT_COUNT. */
screamer 0:c5e2f793b59a 361
screamer 0:c5e2f793b59a 362 /*! @brief Read current value of the FTM_CNT_COUNT field. */
screamer 0:c5e2f793b59a 363 #define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
screamer 0:c5e2f793b59a 364
screamer 0:c5e2f793b59a 365 /*! @brief Format value for bitfield FTM_CNT_COUNT. */
screamer 0:c5e2f793b59a 366 #define BF_FTM_CNT_COUNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT)
screamer 0:c5e2f793b59a 367
screamer 0:c5e2f793b59a 368 /*! @brief Set the COUNT field to a new value. */
screamer 0:c5e2f793b59a 369 #define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
screamer 0:c5e2f793b59a 370 /*@}*/
screamer 0:c5e2f793b59a 371
screamer 0:c5e2f793b59a 372 /*******************************************************************************
screamer 0:c5e2f793b59a 373 * HW_FTM_MOD - Modulo
screamer 0:c5e2f793b59a 374 ******************************************************************************/
screamer 0:c5e2f793b59a 375
screamer 0:c5e2f793b59a 376 /*!
screamer 0:c5e2f793b59a 377 * @brief HW_FTM_MOD - Modulo (RW)
screamer 0:c5e2f793b59a 378 *
screamer 0:c5e2f793b59a 379 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 380 *
screamer 0:c5e2f793b59a 381 * The Modulo register contains the modulo value for the FTM counter. After the
screamer 0:c5e2f793b59a 382 * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
screamer 0:c5e2f793b59a 383 * the next clock, and the next value of FTM counter depends on the selected
screamer 0:c5e2f793b59a 384 * counting method; see Counter. Writing to the MOD register latches the value into a
screamer 0:c5e2f793b59a 385 * buffer. The MOD register is updated with the value of its write buffer
screamer 0:c5e2f793b59a 386 * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
screamer 0:c5e2f793b59a 387 * mechanism may be manually reset by writing to the SC register whether BDM is
screamer 0:c5e2f793b59a 388 * active or not. Initialize the FTM counter, by writing to CNT, before writing
screamer 0:c5e2f793b59a 389 * to the MOD register to avoid confusion about when the first counter overflow
screamer 0:c5e2f793b59a 390 * will occur.
screamer 0:c5e2f793b59a 391 */
screamer 0:c5e2f793b59a 392 typedef union _hw_ftm_mod
screamer 0:c5e2f793b59a 393 {
screamer 0:c5e2f793b59a 394 uint32_t U;
screamer 0:c5e2f793b59a 395 struct _hw_ftm_mod_bitfields
screamer 0:c5e2f793b59a 396 {
screamer 0:c5e2f793b59a 397 uint32_t MOD : 16; /*!< [15:0] */
screamer 0:c5e2f793b59a 398 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 399 } B;
screamer 0:c5e2f793b59a 400 } hw_ftm_mod_t;
screamer 0:c5e2f793b59a 401
screamer 0:c5e2f793b59a 402 /*!
screamer 0:c5e2f793b59a 403 * @name Constants and macros for entire FTM_MOD register
screamer 0:c5e2f793b59a 404 */
screamer 0:c5e2f793b59a 405 /*@{*/
screamer 0:c5e2f793b59a 406 #define HW_FTM_MOD_ADDR(x) ((x) + 0x8U)
screamer 0:c5e2f793b59a 407
screamer 0:c5e2f793b59a 408 #define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
screamer 0:c5e2f793b59a 409 #define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
screamer 0:c5e2f793b59a 410 #define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
screamer 0:c5e2f793b59a 411 #define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v)))
screamer 0:c5e2f793b59a 412 #define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 413 #define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 414 /*@}*/
screamer 0:c5e2f793b59a 415
screamer 0:c5e2f793b59a 416 /*
screamer 0:c5e2f793b59a 417 * Constants & macros for individual FTM_MOD bitfields
screamer 0:c5e2f793b59a 418 */
screamer 0:c5e2f793b59a 419
screamer 0:c5e2f793b59a 420 /*!
screamer 0:c5e2f793b59a 421 * @name Register FTM_MOD, field MOD[15:0] (RW)
screamer 0:c5e2f793b59a 422 *
screamer 0:c5e2f793b59a 423 * Modulo Value
screamer 0:c5e2f793b59a 424 */
screamer 0:c5e2f793b59a 425 /*@{*/
screamer 0:c5e2f793b59a 426 #define BP_FTM_MOD_MOD (0U) /*!< Bit position for FTM_MOD_MOD. */
screamer 0:c5e2f793b59a 427 #define BM_FTM_MOD_MOD (0x0000FFFFU) /*!< Bit mask for FTM_MOD_MOD. */
screamer 0:c5e2f793b59a 428 #define BS_FTM_MOD_MOD (16U) /*!< Bit field size in bits for FTM_MOD_MOD. */
screamer 0:c5e2f793b59a 429
screamer 0:c5e2f793b59a 430 /*! @brief Read current value of the FTM_MOD_MOD field. */
screamer 0:c5e2f793b59a 431 #define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
screamer 0:c5e2f793b59a 432
screamer 0:c5e2f793b59a 433 /*! @brief Format value for bitfield FTM_MOD_MOD. */
screamer 0:c5e2f793b59a 434 #define BF_FTM_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD)
screamer 0:c5e2f793b59a 435
screamer 0:c5e2f793b59a 436 /*! @brief Set the MOD field to a new value. */
screamer 0:c5e2f793b59a 437 #define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
screamer 0:c5e2f793b59a 438 /*@}*/
screamer 0:c5e2f793b59a 439
screamer 0:c5e2f793b59a 440 /*******************************************************************************
screamer 0:c5e2f793b59a 441 * HW_FTM_CnSC - Channel (n) Status And Control
screamer 0:c5e2f793b59a 442 ******************************************************************************/
screamer 0:c5e2f793b59a 443
screamer 0:c5e2f793b59a 444 /*!
screamer 0:c5e2f793b59a 445 * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
screamer 0:c5e2f793b59a 446 *
screamer 0:c5e2f793b59a 447 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 448 *
screamer 0:c5e2f793b59a 449 * CnSC contains the channel-interrupt-status flag and control bits used to
screamer 0:c5e2f793b59a 450 * configure the interrupt enable, channel configuration, and pin function. Mode,
screamer 0:c5e2f793b59a 451 * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
screamer 0:c5e2f793b59a 452 * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
screamer 0:c5e2f793b59a 453 * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
screamer 0:c5e2f793b59a 454 * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
screamer 0:c5e2f793b59a 455 * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
screamer 0:c5e2f793b59a 456 * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
screamer 0:c5e2f793b59a 457 * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
screamer 0:c5e2f793b59a 458 * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
screamer 0:c5e2f793b59a 459 * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
screamer 0:c5e2f793b59a 460 * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
screamer 0:c5e2f793b59a 461 * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
screamer 0:c5e2f793b59a 462 * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
screamer 0:c5e2f793b59a 463 * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
screamer 0:c5e2f793b59a 464 * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
screamer 0:c5e2f793b59a 465 * Enabled Rising and falling edges
screamer 0:c5e2f793b59a 466 */
screamer 0:c5e2f793b59a 467 typedef union _hw_ftm_cnsc
screamer 0:c5e2f793b59a 468 {
screamer 0:c5e2f793b59a 469 uint32_t U;
screamer 0:c5e2f793b59a 470 struct _hw_ftm_cnsc_bitfields
screamer 0:c5e2f793b59a 471 {
screamer 0:c5e2f793b59a 472 uint32_t DMA : 1; /*!< [0] DMA Enable */
screamer 0:c5e2f793b59a 473 uint32_t RESERVED0 : 1; /*!< [1] */
screamer 0:c5e2f793b59a 474 uint32_t ELSA : 1; /*!< [2] Edge or Level Select */
screamer 0:c5e2f793b59a 475 uint32_t ELSB : 1; /*!< [3] Edge or Level Select */
screamer 0:c5e2f793b59a 476 uint32_t MSA : 1; /*!< [4] Channel Mode Select */
screamer 0:c5e2f793b59a 477 uint32_t MSB : 1; /*!< [5] Channel Mode Select */
screamer 0:c5e2f793b59a 478 uint32_t CHIE : 1; /*!< [6] Channel Interrupt Enable */
screamer 0:c5e2f793b59a 479 uint32_t CHF : 1; /*!< [7] Channel Flag */
screamer 0:c5e2f793b59a 480 uint32_t RESERVED1 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 481 } B;
screamer 0:c5e2f793b59a 482 } hw_ftm_cnsc_t;
screamer 0:c5e2f793b59a 483
screamer 0:c5e2f793b59a 484 /*!
screamer 0:c5e2f793b59a 485 * @name Constants and macros for entire FTM_CnSC register
screamer 0:c5e2f793b59a 486 */
screamer 0:c5e2f793b59a 487 /*@{*/
screamer 0:c5e2f793b59a 488 #define HW_FTM_CnSC_COUNT (8U)
screamer 0:c5e2f793b59a 489
screamer 0:c5e2f793b59a 490 #define HW_FTM_CnSC_ADDR(x, n) ((x) + 0xCU + (0x8U * (n)))
screamer 0:c5e2f793b59a 491
screamer 0:c5e2f793b59a 492 #define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
screamer 0:c5e2f793b59a 493 #define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
screamer 0:c5e2f793b59a 494 #define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
screamer 0:c5e2f793b59a 495 #define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 496 #define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 497 #define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 498 /*@}*/
screamer 0:c5e2f793b59a 499
screamer 0:c5e2f793b59a 500 /*
screamer 0:c5e2f793b59a 501 * Constants & macros for individual FTM_CnSC bitfields
screamer 0:c5e2f793b59a 502 */
screamer 0:c5e2f793b59a 503
screamer 0:c5e2f793b59a 504 /*!
screamer 0:c5e2f793b59a 505 * @name Register FTM_CnSC, field DMA[0] (RW)
screamer 0:c5e2f793b59a 506 *
screamer 0:c5e2f793b59a 507 * Enables DMA transfers for the channel.
screamer 0:c5e2f793b59a 508 *
screamer 0:c5e2f793b59a 509 * Values:
screamer 0:c5e2f793b59a 510 * - 0 - Disable DMA transfers.
screamer 0:c5e2f793b59a 511 * - 1 - Enable DMA transfers.
screamer 0:c5e2f793b59a 512 */
screamer 0:c5e2f793b59a 513 /*@{*/
screamer 0:c5e2f793b59a 514 #define BP_FTM_CnSC_DMA (0U) /*!< Bit position for FTM_CnSC_DMA. */
screamer 0:c5e2f793b59a 515 #define BM_FTM_CnSC_DMA (0x00000001U) /*!< Bit mask for FTM_CnSC_DMA. */
screamer 0:c5e2f793b59a 516 #define BS_FTM_CnSC_DMA (1U) /*!< Bit field size in bits for FTM_CnSC_DMA. */
screamer 0:c5e2f793b59a 517
screamer 0:c5e2f793b59a 518 /*! @brief Read current value of the FTM_CnSC_DMA field. */
screamer 0:c5e2f793b59a 519 #define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
screamer 0:c5e2f793b59a 520
screamer 0:c5e2f793b59a 521 /*! @brief Format value for bitfield FTM_CnSC_DMA. */
screamer 0:c5e2f793b59a 522 #define BF_FTM_CnSC_DMA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA)
screamer 0:c5e2f793b59a 523
screamer 0:c5e2f793b59a 524 /*! @brief Set the DMA field to a new value. */
screamer 0:c5e2f793b59a 525 #define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
screamer 0:c5e2f793b59a 526 /*@}*/
screamer 0:c5e2f793b59a 527
screamer 0:c5e2f793b59a 528 /*!
screamer 0:c5e2f793b59a 529 * @name Register FTM_CnSC, field ELSA[2] (RW)
screamer 0:c5e2f793b59a 530 *
screamer 0:c5e2f793b59a 531 * The functionality of ELSB and ELSA depends on the channel mode. See
screamer 0:c5e2f793b59a 532 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
screamer 0:c5e2f793b59a 533 * = 1.
screamer 0:c5e2f793b59a 534 */
screamer 0:c5e2f793b59a 535 /*@{*/
screamer 0:c5e2f793b59a 536 #define BP_FTM_CnSC_ELSA (2U) /*!< Bit position for FTM_CnSC_ELSA. */
screamer 0:c5e2f793b59a 537 #define BM_FTM_CnSC_ELSA (0x00000004U) /*!< Bit mask for FTM_CnSC_ELSA. */
screamer 0:c5e2f793b59a 538 #define BS_FTM_CnSC_ELSA (1U) /*!< Bit field size in bits for FTM_CnSC_ELSA. */
screamer 0:c5e2f793b59a 539
screamer 0:c5e2f793b59a 540 /*! @brief Read current value of the FTM_CnSC_ELSA field. */
screamer 0:c5e2f793b59a 541 #define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
screamer 0:c5e2f793b59a 542
screamer 0:c5e2f793b59a 543 /*! @brief Format value for bitfield FTM_CnSC_ELSA. */
screamer 0:c5e2f793b59a 544 #define BF_FTM_CnSC_ELSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA)
screamer 0:c5e2f793b59a 545
screamer 0:c5e2f793b59a 546 /*! @brief Set the ELSA field to a new value. */
screamer 0:c5e2f793b59a 547 #define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
screamer 0:c5e2f793b59a 548 /*@}*/
screamer 0:c5e2f793b59a 549
screamer 0:c5e2f793b59a 550 /*!
screamer 0:c5e2f793b59a 551 * @name Register FTM_CnSC, field ELSB[3] (RW)
screamer 0:c5e2f793b59a 552 *
screamer 0:c5e2f793b59a 553 * The functionality of ELSB and ELSA depends on the channel mode. See
screamer 0:c5e2f793b59a 554 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
screamer 0:c5e2f793b59a 555 * = 1.
screamer 0:c5e2f793b59a 556 */
screamer 0:c5e2f793b59a 557 /*@{*/
screamer 0:c5e2f793b59a 558 #define BP_FTM_CnSC_ELSB (3U) /*!< Bit position for FTM_CnSC_ELSB. */
screamer 0:c5e2f793b59a 559 #define BM_FTM_CnSC_ELSB (0x00000008U) /*!< Bit mask for FTM_CnSC_ELSB. */
screamer 0:c5e2f793b59a 560 #define BS_FTM_CnSC_ELSB (1U) /*!< Bit field size in bits for FTM_CnSC_ELSB. */
screamer 0:c5e2f793b59a 561
screamer 0:c5e2f793b59a 562 /*! @brief Read current value of the FTM_CnSC_ELSB field. */
screamer 0:c5e2f793b59a 563 #define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
screamer 0:c5e2f793b59a 564
screamer 0:c5e2f793b59a 565 /*! @brief Format value for bitfield FTM_CnSC_ELSB. */
screamer 0:c5e2f793b59a 566 #define BF_FTM_CnSC_ELSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB)
screamer 0:c5e2f793b59a 567
screamer 0:c5e2f793b59a 568 /*! @brief Set the ELSB field to a new value. */
screamer 0:c5e2f793b59a 569 #define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
screamer 0:c5e2f793b59a 570 /*@}*/
screamer 0:c5e2f793b59a 571
screamer 0:c5e2f793b59a 572 /*!
screamer 0:c5e2f793b59a 573 * @name Register FTM_CnSC, field MSA[4] (RW)
screamer 0:c5e2f793b59a 574 *
screamer 0:c5e2f793b59a 575 * Used for further selections in the channel logic. Its functionality is
screamer 0:c5e2f793b59a 576 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
screamer 0:c5e2f793b59a 577 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 578 */
screamer 0:c5e2f793b59a 579 /*@{*/
screamer 0:c5e2f793b59a 580 #define BP_FTM_CnSC_MSA (4U) /*!< Bit position for FTM_CnSC_MSA. */
screamer 0:c5e2f793b59a 581 #define BM_FTM_CnSC_MSA (0x00000010U) /*!< Bit mask for FTM_CnSC_MSA. */
screamer 0:c5e2f793b59a 582 #define BS_FTM_CnSC_MSA (1U) /*!< Bit field size in bits for FTM_CnSC_MSA. */
screamer 0:c5e2f793b59a 583
screamer 0:c5e2f793b59a 584 /*! @brief Read current value of the FTM_CnSC_MSA field. */
screamer 0:c5e2f793b59a 585 #define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
screamer 0:c5e2f793b59a 586
screamer 0:c5e2f793b59a 587 /*! @brief Format value for bitfield FTM_CnSC_MSA. */
screamer 0:c5e2f793b59a 588 #define BF_FTM_CnSC_MSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA)
screamer 0:c5e2f793b59a 589
screamer 0:c5e2f793b59a 590 /*! @brief Set the MSA field to a new value. */
screamer 0:c5e2f793b59a 591 #define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
screamer 0:c5e2f793b59a 592 /*@}*/
screamer 0:c5e2f793b59a 593
screamer 0:c5e2f793b59a 594 /*!
screamer 0:c5e2f793b59a 595 * @name Register FTM_CnSC, field MSB[5] (RW)
screamer 0:c5e2f793b59a 596 *
screamer 0:c5e2f793b59a 597 * Used for further selections in the channel logic. Its functionality is
screamer 0:c5e2f793b59a 598 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
screamer 0:c5e2f793b59a 599 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 600 */
screamer 0:c5e2f793b59a 601 /*@{*/
screamer 0:c5e2f793b59a 602 #define BP_FTM_CnSC_MSB (5U) /*!< Bit position for FTM_CnSC_MSB. */
screamer 0:c5e2f793b59a 603 #define BM_FTM_CnSC_MSB (0x00000020U) /*!< Bit mask for FTM_CnSC_MSB. */
screamer 0:c5e2f793b59a 604 #define BS_FTM_CnSC_MSB (1U) /*!< Bit field size in bits for FTM_CnSC_MSB. */
screamer 0:c5e2f793b59a 605
screamer 0:c5e2f793b59a 606 /*! @brief Read current value of the FTM_CnSC_MSB field. */
screamer 0:c5e2f793b59a 607 #define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
screamer 0:c5e2f793b59a 608
screamer 0:c5e2f793b59a 609 /*! @brief Format value for bitfield FTM_CnSC_MSB. */
screamer 0:c5e2f793b59a 610 #define BF_FTM_CnSC_MSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB)
screamer 0:c5e2f793b59a 611
screamer 0:c5e2f793b59a 612 /*! @brief Set the MSB field to a new value. */
screamer 0:c5e2f793b59a 613 #define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
screamer 0:c5e2f793b59a 614 /*@}*/
screamer 0:c5e2f793b59a 615
screamer 0:c5e2f793b59a 616 /*!
screamer 0:c5e2f793b59a 617 * @name Register FTM_CnSC, field CHIE[6] (RW)
screamer 0:c5e2f793b59a 618 *
screamer 0:c5e2f793b59a 619 * Enables channel interrupts.
screamer 0:c5e2f793b59a 620 *
screamer 0:c5e2f793b59a 621 * Values:
screamer 0:c5e2f793b59a 622 * - 0 - Disable channel interrupts. Use software polling.
screamer 0:c5e2f793b59a 623 * - 1 - Enable channel interrupts.
screamer 0:c5e2f793b59a 624 */
screamer 0:c5e2f793b59a 625 /*@{*/
screamer 0:c5e2f793b59a 626 #define BP_FTM_CnSC_CHIE (6U) /*!< Bit position for FTM_CnSC_CHIE. */
screamer 0:c5e2f793b59a 627 #define BM_FTM_CnSC_CHIE (0x00000040U) /*!< Bit mask for FTM_CnSC_CHIE. */
screamer 0:c5e2f793b59a 628 #define BS_FTM_CnSC_CHIE (1U) /*!< Bit field size in bits for FTM_CnSC_CHIE. */
screamer 0:c5e2f793b59a 629
screamer 0:c5e2f793b59a 630 /*! @brief Read current value of the FTM_CnSC_CHIE field. */
screamer 0:c5e2f793b59a 631 #define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
screamer 0:c5e2f793b59a 632
screamer 0:c5e2f793b59a 633 /*! @brief Format value for bitfield FTM_CnSC_CHIE. */
screamer 0:c5e2f793b59a 634 #define BF_FTM_CnSC_CHIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE)
screamer 0:c5e2f793b59a 635
screamer 0:c5e2f793b59a 636 /*! @brief Set the CHIE field to a new value. */
screamer 0:c5e2f793b59a 637 #define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
screamer 0:c5e2f793b59a 638 /*@}*/
screamer 0:c5e2f793b59a 639
screamer 0:c5e2f793b59a 640 /*!
screamer 0:c5e2f793b59a 641 * @name Register FTM_CnSC, field CHF[7] (ROWZ)
screamer 0:c5e2f793b59a 642 *
screamer 0:c5e2f793b59a 643 * Set by hardware when an event occurs on the channel. CHF is cleared by
screamer 0:c5e2f793b59a 644 * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
screamer 0:c5e2f793b59a 645 * Writing a 1 to CHF has no effect. If another event occurs between the read and
screamer 0:c5e2f793b59a 646 * write operations, the write operation has no effect; therefore, CHF remains set
screamer 0:c5e2f793b59a 647 * indicating an event has occurred. In this case a CHF interrupt request is not
screamer 0:c5e2f793b59a 648 * lost due to the clearing sequence for a previous CHF.
screamer 0:c5e2f793b59a 649 *
screamer 0:c5e2f793b59a 650 * Values:
screamer 0:c5e2f793b59a 651 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 652 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 653 */
screamer 0:c5e2f793b59a 654 /*@{*/
screamer 0:c5e2f793b59a 655 #define BP_FTM_CnSC_CHF (7U) /*!< Bit position for FTM_CnSC_CHF. */
screamer 0:c5e2f793b59a 656 #define BM_FTM_CnSC_CHF (0x00000080U) /*!< Bit mask for FTM_CnSC_CHF. */
screamer 0:c5e2f793b59a 657 #define BS_FTM_CnSC_CHF (1U) /*!< Bit field size in bits for FTM_CnSC_CHF. */
screamer 0:c5e2f793b59a 658
screamer 0:c5e2f793b59a 659 /*! @brief Read current value of the FTM_CnSC_CHF field. */
screamer 0:c5e2f793b59a 660 #define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
screamer 0:c5e2f793b59a 661
screamer 0:c5e2f793b59a 662 /*! @brief Format value for bitfield FTM_CnSC_CHF. */
screamer 0:c5e2f793b59a 663 #define BF_FTM_CnSC_CHF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF)
screamer 0:c5e2f793b59a 664
screamer 0:c5e2f793b59a 665 /*! @brief Set the CHF field to a new value. */
screamer 0:c5e2f793b59a 666 #define BW_FTM_CnSC_CHF(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF) = (v))
screamer 0:c5e2f793b59a 667 /*@}*/
screamer 0:c5e2f793b59a 668 /*******************************************************************************
screamer 0:c5e2f793b59a 669 * HW_FTM_CnV - Channel (n) Value
screamer 0:c5e2f793b59a 670 ******************************************************************************/
screamer 0:c5e2f793b59a 671
screamer 0:c5e2f793b59a 672 /*!
screamer 0:c5e2f793b59a 673 * @brief HW_FTM_CnV - Channel (n) Value (RW)
screamer 0:c5e2f793b59a 674 *
screamer 0:c5e2f793b59a 675 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 676 *
screamer 0:c5e2f793b59a 677 * These registers contain the captured FTM counter value for the input modes or
screamer 0:c5e2f793b59a 678 * the match value for the output modes. In Input Capture, Capture Test, and
screamer 0:c5e2f793b59a 679 * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
screamer 0:c5e2f793b59a 680 * writing to a CnV register latches the value into a buffer. A CnV register is
screamer 0:c5e2f793b59a 681 * updated with the value of its write buffer according to Registers updated from
screamer 0:c5e2f793b59a 682 * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
screamer 0:c5e2f793b59a 683 * reset by writing to the CnSC register whether BDM mode is active or not.
screamer 0:c5e2f793b59a 684 */
screamer 0:c5e2f793b59a 685 typedef union _hw_ftm_cnv
screamer 0:c5e2f793b59a 686 {
screamer 0:c5e2f793b59a 687 uint32_t U;
screamer 0:c5e2f793b59a 688 struct _hw_ftm_cnv_bitfields
screamer 0:c5e2f793b59a 689 {
screamer 0:c5e2f793b59a 690 uint32_t VAL : 16; /*!< [15:0] Channel Value */
screamer 0:c5e2f793b59a 691 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 692 } B;
screamer 0:c5e2f793b59a 693 } hw_ftm_cnv_t;
screamer 0:c5e2f793b59a 694
screamer 0:c5e2f793b59a 695 /*!
screamer 0:c5e2f793b59a 696 * @name Constants and macros for entire FTM_CnV register
screamer 0:c5e2f793b59a 697 */
screamer 0:c5e2f793b59a 698 /*@{*/
screamer 0:c5e2f793b59a 699 #define HW_FTM_CnV_COUNT (8U)
screamer 0:c5e2f793b59a 700
screamer 0:c5e2f793b59a 701 #define HW_FTM_CnV_ADDR(x, n) ((x) + 0x10U + (0x8U * (n)))
screamer 0:c5e2f793b59a 702
screamer 0:c5e2f793b59a 703 #define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
screamer 0:c5e2f793b59a 704 #define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
screamer 0:c5e2f793b59a 705 #define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
screamer 0:c5e2f793b59a 706 #define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 707 #define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 708 #define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 709 /*@}*/
screamer 0:c5e2f793b59a 710
screamer 0:c5e2f793b59a 711 /*
screamer 0:c5e2f793b59a 712 * Constants & macros for individual FTM_CnV bitfields
screamer 0:c5e2f793b59a 713 */
screamer 0:c5e2f793b59a 714
screamer 0:c5e2f793b59a 715 /*!
screamer 0:c5e2f793b59a 716 * @name Register FTM_CnV, field VAL[15:0] (RW)
screamer 0:c5e2f793b59a 717 *
screamer 0:c5e2f793b59a 718 * Captured FTM counter value of the input modes or the match value for the
screamer 0:c5e2f793b59a 719 * output modes
screamer 0:c5e2f793b59a 720 */
screamer 0:c5e2f793b59a 721 /*@{*/
screamer 0:c5e2f793b59a 722 #define BP_FTM_CnV_VAL (0U) /*!< Bit position for FTM_CnV_VAL. */
screamer 0:c5e2f793b59a 723 #define BM_FTM_CnV_VAL (0x0000FFFFU) /*!< Bit mask for FTM_CnV_VAL. */
screamer 0:c5e2f793b59a 724 #define BS_FTM_CnV_VAL (16U) /*!< Bit field size in bits for FTM_CnV_VAL. */
screamer 0:c5e2f793b59a 725
screamer 0:c5e2f793b59a 726 /*! @brief Read current value of the FTM_CnV_VAL field. */
screamer 0:c5e2f793b59a 727 #define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
screamer 0:c5e2f793b59a 728
screamer 0:c5e2f793b59a 729 /*! @brief Format value for bitfield FTM_CnV_VAL. */
screamer 0:c5e2f793b59a 730 #define BF_FTM_CnV_VAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL)
screamer 0:c5e2f793b59a 731
screamer 0:c5e2f793b59a 732 /*! @brief Set the VAL field to a new value. */
screamer 0:c5e2f793b59a 733 #define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
screamer 0:c5e2f793b59a 734 /*@}*/
screamer 0:c5e2f793b59a 735
screamer 0:c5e2f793b59a 736 /*******************************************************************************
screamer 0:c5e2f793b59a 737 * HW_FTM_CNTIN - Counter Initial Value
screamer 0:c5e2f793b59a 738 ******************************************************************************/
screamer 0:c5e2f793b59a 739
screamer 0:c5e2f793b59a 740 /*!
screamer 0:c5e2f793b59a 741 * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
screamer 0:c5e2f793b59a 742 *
screamer 0:c5e2f793b59a 743 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 744 *
screamer 0:c5e2f793b59a 745 * The Counter Initial Value register contains the initial value for the FTM
screamer 0:c5e2f793b59a 746 * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
screamer 0:c5e2f793b59a 747 * register is updated with the value of its write buffer according to Registers
screamer 0:c5e2f793b59a 748 * updated from write buffers. When the FTM clock is initially selected, by
screamer 0:c5e2f793b59a 749 * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
screamer 0:c5e2f793b59a 750 * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
screamer 0:c5e2f793b59a 751 * write the new value to the the CNTIN register and then initialize the FTM
screamer 0:c5e2f793b59a 752 * counter by writing any value to the CNT register.
screamer 0:c5e2f793b59a 753 */
screamer 0:c5e2f793b59a 754 typedef union _hw_ftm_cntin
screamer 0:c5e2f793b59a 755 {
screamer 0:c5e2f793b59a 756 uint32_t U;
screamer 0:c5e2f793b59a 757 struct _hw_ftm_cntin_bitfields
screamer 0:c5e2f793b59a 758 {
screamer 0:c5e2f793b59a 759 uint32_t INIT : 16; /*!< [15:0] */
screamer 0:c5e2f793b59a 760 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 761 } B;
screamer 0:c5e2f793b59a 762 } hw_ftm_cntin_t;
screamer 0:c5e2f793b59a 763
screamer 0:c5e2f793b59a 764 /*!
screamer 0:c5e2f793b59a 765 * @name Constants and macros for entire FTM_CNTIN register
screamer 0:c5e2f793b59a 766 */
screamer 0:c5e2f793b59a 767 /*@{*/
screamer 0:c5e2f793b59a 768 #define HW_FTM_CNTIN_ADDR(x) ((x) + 0x4CU)
screamer 0:c5e2f793b59a 769
screamer 0:c5e2f793b59a 770 #define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
screamer 0:c5e2f793b59a 771 #define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
screamer 0:c5e2f793b59a 772 #define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
screamer 0:c5e2f793b59a 773 #define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v)))
screamer 0:c5e2f793b59a 774 #define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 775 #define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 776 /*@}*/
screamer 0:c5e2f793b59a 777
screamer 0:c5e2f793b59a 778 /*
screamer 0:c5e2f793b59a 779 * Constants & macros for individual FTM_CNTIN bitfields
screamer 0:c5e2f793b59a 780 */
screamer 0:c5e2f793b59a 781
screamer 0:c5e2f793b59a 782 /*!
screamer 0:c5e2f793b59a 783 * @name Register FTM_CNTIN, field INIT[15:0] (RW)
screamer 0:c5e2f793b59a 784 *
screamer 0:c5e2f793b59a 785 * Initial Value Of The FTM Counter
screamer 0:c5e2f793b59a 786 */
screamer 0:c5e2f793b59a 787 /*@{*/
screamer 0:c5e2f793b59a 788 #define BP_FTM_CNTIN_INIT (0U) /*!< Bit position for FTM_CNTIN_INIT. */
screamer 0:c5e2f793b59a 789 #define BM_FTM_CNTIN_INIT (0x0000FFFFU) /*!< Bit mask for FTM_CNTIN_INIT. */
screamer 0:c5e2f793b59a 790 #define BS_FTM_CNTIN_INIT (16U) /*!< Bit field size in bits for FTM_CNTIN_INIT. */
screamer 0:c5e2f793b59a 791
screamer 0:c5e2f793b59a 792 /*! @brief Read current value of the FTM_CNTIN_INIT field. */
screamer 0:c5e2f793b59a 793 #define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
screamer 0:c5e2f793b59a 794
screamer 0:c5e2f793b59a 795 /*! @brief Format value for bitfield FTM_CNTIN_INIT. */
screamer 0:c5e2f793b59a 796 #define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT)
screamer 0:c5e2f793b59a 797
screamer 0:c5e2f793b59a 798 /*! @brief Set the INIT field to a new value. */
screamer 0:c5e2f793b59a 799 #define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
screamer 0:c5e2f793b59a 800 /*@}*/
screamer 0:c5e2f793b59a 801
screamer 0:c5e2f793b59a 802 /*******************************************************************************
screamer 0:c5e2f793b59a 803 * HW_FTM_STATUS - Capture And Compare Status
screamer 0:c5e2f793b59a 804 ******************************************************************************/
screamer 0:c5e2f793b59a 805
screamer 0:c5e2f793b59a 806 /*!
screamer 0:c5e2f793b59a 807 * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
screamer 0:c5e2f793b59a 808 *
screamer 0:c5e2f793b59a 809 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 810 *
screamer 0:c5e2f793b59a 811 * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
screamer 0:c5e2f793b59a 812 * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
screamer 0:c5e2f793b59a 813 * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
screamer 0:c5e2f793b59a 814 * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
screamer 0:c5e2f793b59a 815 * STATUS. Hardware sets the individual channel flags when an event occurs on the
screamer 0:c5e2f793b59a 816 * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
screamer 0:c5e2f793b59a 817 * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
screamer 0:c5e2f793b59a 818 * occurs between the read and write operations, the write operation has no effect;
screamer 0:c5e2f793b59a 819 * therefore, CHnF remains set indicating an event has occurred. In this case, a
screamer 0:c5e2f793b59a 820 * CHnF interrupt request is not lost due to the clearing sequence for a previous
screamer 0:c5e2f793b59a 821 * CHnF. The STATUS register should be used only in Combine mode.
screamer 0:c5e2f793b59a 822 */
screamer 0:c5e2f793b59a 823 typedef union _hw_ftm_status
screamer 0:c5e2f793b59a 824 {
screamer 0:c5e2f793b59a 825 uint32_t U;
screamer 0:c5e2f793b59a 826 struct _hw_ftm_status_bitfields
screamer 0:c5e2f793b59a 827 {
screamer 0:c5e2f793b59a 828 uint32_t CH0F : 1; /*!< [0] Channel 0 Flag */
screamer 0:c5e2f793b59a 829 uint32_t CH1F : 1; /*!< [1] Channel 1 Flag */
screamer 0:c5e2f793b59a 830 uint32_t CH2F : 1; /*!< [2] Channel 2 Flag */
screamer 0:c5e2f793b59a 831 uint32_t CH3F : 1; /*!< [3] Channel 3 Flag */
screamer 0:c5e2f793b59a 832 uint32_t CH4F : 1; /*!< [4] Channel 4 Flag */
screamer 0:c5e2f793b59a 833 uint32_t CH5F : 1; /*!< [5] Channel 5 Flag */
screamer 0:c5e2f793b59a 834 uint32_t CH6F : 1; /*!< [6] Channel 6 Flag */
screamer 0:c5e2f793b59a 835 uint32_t CH7F : 1; /*!< [7] Channel 7 Flag */
screamer 0:c5e2f793b59a 836 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 837 } B;
screamer 0:c5e2f793b59a 838 } hw_ftm_status_t;
screamer 0:c5e2f793b59a 839
screamer 0:c5e2f793b59a 840 /*!
screamer 0:c5e2f793b59a 841 * @name Constants and macros for entire FTM_STATUS register
screamer 0:c5e2f793b59a 842 */
screamer 0:c5e2f793b59a 843 /*@{*/
screamer 0:c5e2f793b59a 844 #define HW_FTM_STATUS_ADDR(x) ((x) + 0x50U)
screamer 0:c5e2f793b59a 845
screamer 0:c5e2f793b59a 846 #define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
screamer 0:c5e2f793b59a 847 #define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
screamer 0:c5e2f793b59a 848 #define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
screamer 0:c5e2f793b59a 849 #define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v)))
screamer 0:c5e2f793b59a 850 #define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 851 #define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 852 /*@}*/
screamer 0:c5e2f793b59a 853
screamer 0:c5e2f793b59a 854 /*
screamer 0:c5e2f793b59a 855 * Constants & macros for individual FTM_STATUS bitfields
screamer 0:c5e2f793b59a 856 */
screamer 0:c5e2f793b59a 857
screamer 0:c5e2f793b59a 858 /*!
screamer 0:c5e2f793b59a 859 * @name Register FTM_STATUS, field CH0F[0] (W1C)
screamer 0:c5e2f793b59a 860 *
screamer 0:c5e2f793b59a 861 * See the register description.
screamer 0:c5e2f793b59a 862 *
screamer 0:c5e2f793b59a 863 * Values:
screamer 0:c5e2f793b59a 864 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 865 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 866 */
screamer 0:c5e2f793b59a 867 /*@{*/
screamer 0:c5e2f793b59a 868 #define BP_FTM_STATUS_CH0F (0U) /*!< Bit position for FTM_STATUS_CH0F. */
screamer 0:c5e2f793b59a 869 #define BM_FTM_STATUS_CH0F (0x00000001U) /*!< Bit mask for FTM_STATUS_CH0F. */
screamer 0:c5e2f793b59a 870 #define BS_FTM_STATUS_CH0F (1U) /*!< Bit field size in bits for FTM_STATUS_CH0F. */
screamer 0:c5e2f793b59a 871
screamer 0:c5e2f793b59a 872 /*! @brief Read current value of the FTM_STATUS_CH0F field. */
screamer 0:c5e2f793b59a 873 #define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
screamer 0:c5e2f793b59a 874
screamer 0:c5e2f793b59a 875 /*! @brief Format value for bitfield FTM_STATUS_CH0F. */
screamer 0:c5e2f793b59a 876 #define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F)
screamer 0:c5e2f793b59a 877
screamer 0:c5e2f793b59a 878 /*! @brief Set the CH0F field to a new value. */
screamer 0:c5e2f793b59a 879 #define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
screamer 0:c5e2f793b59a 880 /*@}*/
screamer 0:c5e2f793b59a 881
screamer 0:c5e2f793b59a 882 /*!
screamer 0:c5e2f793b59a 883 * @name Register FTM_STATUS, field CH1F[1] (W1C)
screamer 0:c5e2f793b59a 884 *
screamer 0:c5e2f793b59a 885 * See the register description.
screamer 0:c5e2f793b59a 886 *
screamer 0:c5e2f793b59a 887 * Values:
screamer 0:c5e2f793b59a 888 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 889 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 890 */
screamer 0:c5e2f793b59a 891 /*@{*/
screamer 0:c5e2f793b59a 892 #define BP_FTM_STATUS_CH1F (1U) /*!< Bit position for FTM_STATUS_CH1F. */
screamer 0:c5e2f793b59a 893 #define BM_FTM_STATUS_CH1F (0x00000002U) /*!< Bit mask for FTM_STATUS_CH1F. */
screamer 0:c5e2f793b59a 894 #define BS_FTM_STATUS_CH1F (1U) /*!< Bit field size in bits for FTM_STATUS_CH1F. */
screamer 0:c5e2f793b59a 895
screamer 0:c5e2f793b59a 896 /*! @brief Read current value of the FTM_STATUS_CH1F field. */
screamer 0:c5e2f793b59a 897 #define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
screamer 0:c5e2f793b59a 898
screamer 0:c5e2f793b59a 899 /*! @brief Format value for bitfield FTM_STATUS_CH1F. */
screamer 0:c5e2f793b59a 900 #define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F)
screamer 0:c5e2f793b59a 901
screamer 0:c5e2f793b59a 902 /*! @brief Set the CH1F field to a new value. */
screamer 0:c5e2f793b59a 903 #define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
screamer 0:c5e2f793b59a 904 /*@}*/
screamer 0:c5e2f793b59a 905
screamer 0:c5e2f793b59a 906 /*!
screamer 0:c5e2f793b59a 907 * @name Register FTM_STATUS, field CH2F[2] (W1C)
screamer 0:c5e2f793b59a 908 *
screamer 0:c5e2f793b59a 909 * See the register description.
screamer 0:c5e2f793b59a 910 *
screamer 0:c5e2f793b59a 911 * Values:
screamer 0:c5e2f793b59a 912 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 913 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 914 */
screamer 0:c5e2f793b59a 915 /*@{*/
screamer 0:c5e2f793b59a 916 #define BP_FTM_STATUS_CH2F (2U) /*!< Bit position for FTM_STATUS_CH2F. */
screamer 0:c5e2f793b59a 917 #define BM_FTM_STATUS_CH2F (0x00000004U) /*!< Bit mask for FTM_STATUS_CH2F. */
screamer 0:c5e2f793b59a 918 #define BS_FTM_STATUS_CH2F (1U) /*!< Bit field size in bits for FTM_STATUS_CH2F. */
screamer 0:c5e2f793b59a 919
screamer 0:c5e2f793b59a 920 /*! @brief Read current value of the FTM_STATUS_CH2F field. */
screamer 0:c5e2f793b59a 921 #define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
screamer 0:c5e2f793b59a 922
screamer 0:c5e2f793b59a 923 /*! @brief Format value for bitfield FTM_STATUS_CH2F. */
screamer 0:c5e2f793b59a 924 #define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F)
screamer 0:c5e2f793b59a 925
screamer 0:c5e2f793b59a 926 /*! @brief Set the CH2F field to a new value. */
screamer 0:c5e2f793b59a 927 #define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
screamer 0:c5e2f793b59a 928 /*@}*/
screamer 0:c5e2f793b59a 929
screamer 0:c5e2f793b59a 930 /*!
screamer 0:c5e2f793b59a 931 * @name Register FTM_STATUS, field CH3F[3] (W1C)
screamer 0:c5e2f793b59a 932 *
screamer 0:c5e2f793b59a 933 * See the register description.
screamer 0:c5e2f793b59a 934 *
screamer 0:c5e2f793b59a 935 * Values:
screamer 0:c5e2f793b59a 936 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 937 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 938 */
screamer 0:c5e2f793b59a 939 /*@{*/
screamer 0:c5e2f793b59a 940 #define BP_FTM_STATUS_CH3F (3U) /*!< Bit position for FTM_STATUS_CH3F. */
screamer 0:c5e2f793b59a 941 #define BM_FTM_STATUS_CH3F (0x00000008U) /*!< Bit mask for FTM_STATUS_CH3F. */
screamer 0:c5e2f793b59a 942 #define BS_FTM_STATUS_CH3F (1U) /*!< Bit field size in bits for FTM_STATUS_CH3F. */
screamer 0:c5e2f793b59a 943
screamer 0:c5e2f793b59a 944 /*! @brief Read current value of the FTM_STATUS_CH3F field. */
screamer 0:c5e2f793b59a 945 #define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
screamer 0:c5e2f793b59a 946
screamer 0:c5e2f793b59a 947 /*! @brief Format value for bitfield FTM_STATUS_CH3F. */
screamer 0:c5e2f793b59a 948 #define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F)
screamer 0:c5e2f793b59a 949
screamer 0:c5e2f793b59a 950 /*! @brief Set the CH3F field to a new value. */
screamer 0:c5e2f793b59a 951 #define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
screamer 0:c5e2f793b59a 952 /*@}*/
screamer 0:c5e2f793b59a 953
screamer 0:c5e2f793b59a 954 /*!
screamer 0:c5e2f793b59a 955 * @name Register FTM_STATUS, field CH4F[4] (W1C)
screamer 0:c5e2f793b59a 956 *
screamer 0:c5e2f793b59a 957 * See the register description.
screamer 0:c5e2f793b59a 958 *
screamer 0:c5e2f793b59a 959 * Values:
screamer 0:c5e2f793b59a 960 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 961 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 962 */
screamer 0:c5e2f793b59a 963 /*@{*/
screamer 0:c5e2f793b59a 964 #define BP_FTM_STATUS_CH4F (4U) /*!< Bit position for FTM_STATUS_CH4F. */
screamer 0:c5e2f793b59a 965 #define BM_FTM_STATUS_CH4F (0x00000010U) /*!< Bit mask for FTM_STATUS_CH4F. */
screamer 0:c5e2f793b59a 966 #define BS_FTM_STATUS_CH4F (1U) /*!< Bit field size in bits for FTM_STATUS_CH4F. */
screamer 0:c5e2f793b59a 967
screamer 0:c5e2f793b59a 968 /*! @brief Read current value of the FTM_STATUS_CH4F field. */
screamer 0:c5e2f793b59a 969 #define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
screamer 0:c5e2f793b59a 970
screamer 0:c5e2f793b59a 971 /*! @brief Format value for bitfield FTM_STATUS_CH4F. */
screamer 0:c5e2f793b59a 972 #define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F)
screamer 0:c5e2f793b59a 973
screamer 0:c5e2f793b59a 974 /*! @brief Set the CH4F field to a new value. */
screamer 0:c5e2f793b59a 975 #define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
screamer 0:c5e2f793b59a 976 /*@}*/
screamer 0:c5e2f793b59a 977
screamer 0:c5e2f793b59a 978 /*!
screamer 0:c5e2f793b59a 979 * @name Register FTM_STATUS, field CH5F[5] (W1C)
screamer 0:c5e2f793b59a 980 *
screamer 0:c5e2f793b59a 981 * See the register description.
screamer 0:c5e2f793b59a 982 *
screamer 0:c5e2f793b59a 983 * Values:
screamer 0:c5e2f793b59a 984 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 985 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 986 */
screamer 0:c5e2f793b59a 987 /*@{*/
screamer 0:c5e2f793b59a 988 #define BP_FTM_STATUS_CH5F (5U) /*!< Bit position for FTM_STATUS_CH5F. */
screamer 0:c5e2f793b59a 989 #define BM_FTM_STATUS_CH5F (0x00000020U) /*!< Bit mask for FTM_STATUS_CH5F. */
screamer 0:c5e2f793b59a 990 #define BS_FTM_STATUS_CH5F (1U) /*!< Bit field size in bits for FTM_STATUS_CH5F. */
screamer 0:c5e2f793b59a 991
screamer 0:c5e2f793b59a 992 /*! @brief Read current value of the FTM_STATUS_CH5F field. */
screamer 0:c5e2f793b59a 993 #define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
screamer 0:c5e2f793b59a 994
screamer 0:c5e2f793b59a 995 /*! @brief Format value for bitfield FTM_STATUS_CH5F. */
screamer 0:c5e2f793b59a 996 #define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F)
screamer 0:c5e2f793b59a 997
screamer 0:c5e2f793b59a 998 /*! @brief Set the CH5F field to a new value. */
screamer 0:c5e2f793b59a 999 #define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
screamer 0:c5e2f793b59a 1000 /*@}*/
screamer 0:c5e2f793b59a 1001
screamer 0:c5e2f793b59a 1002 /*!
screamer 0:c5e2f793b59a 1003 * @name Register FTM_STATUS, field CH6F[6] (W1C)
screamer 0:c5e2f793b59a 1004 *
screamer 0:c5e2f793b59a 1005 * See the register description.
screamer 0:c5e2f793b59a 1006 *
screamer 0:c5e2f793b59a 1007 * Values:
screamer 0:c5e2f793b59a 1008 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 1009 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 1010 */
screamer 0:c5e2f793b59a 1011 /*@{*/
screamer 0:c5e2f793b59a 1012 #define BP_FTM_STATUS_CH6F (6U) /*!< Bit position for FTM_STATUS_CH6F. */
screamer 0:c5e2f793b59a 1013 #define BM_FTM_STATUS_CH6F (0x00000040U) /*!< Bit mask for FTM_STATUS_CH6F. */
screamer 0:c5e2f793b59a 1014 #define BS_FTM_STATUS_CH6F (1U) /*!< Bit field size in bits for FTM_STATUS_CH6F. */
screamer 0:c5e2f793b59a 1015
screamer 0:c5e2f793b59a 1016 /*! @brief Read current value of the FTM_STATUS_CH6F field. */
screamer 0:c5e2f793b59a 1017 #define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
screamer 0:c5e2f793b59a 1018
screamer 0:c5e2f793b59a 1019 /*! @brief Format value for bitfield FTM_STATUS_CH6F. */
screamer 0:c5e2f793b59a 1020 #define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F)
screamer 0:c5e2f793b59a 1021
screamer 0:c5e2f793b59a 1022 /*! @brief Set the CH6F field to a new value. */
screamer 0:c5e2f793b59a 1023 #define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
screamer 0:c5e2f793b59a 1024 /*@}*/
screamer 0:c5e2f793b59a 1025
screamer 0:c5e2f793b59a 1026 /*!
screamer 0:c5e2f793b59a 1027 * @name Register FTM_STATUS, field CH7F[7] (W1C)
screamer 0:c5e2f793b59a 1028 *
screamer 0:c5e2f793b59a 1029 * See the register description.
screamer 0:c5e2f793b59a 1030 *
screamer 0:c5e2f793b59a 1031 * Values:
screamer 0:c5e2f793b59a 1032 * - 0 - No channel event has occurred.
screamer 0:c5e2f793b59a 1033 * - 1 - A channel event has occurred.
screamer 0:c5e2f793b59a 1034 */
screamer 0:c5e2f793b59a 1035 /*@{*/
screamer 0:c5e2f793b59a 1036 #define BP_FTM_STATUS_CH7F (7U) /*!< Bit position for FTM_STATUS_CH7F. */
screamer 0:c5e2f793b59a 1037 #define BM_FTM_STATUS_CH7F (0x00000080U) /*!< Bit mask for FTM_STATUS_CH7F. */
screamer 0:c5e2f793b59a 1038 #define BS_FTM_STATUS_CH7F (1U) /*!< Bit field size in bits for FTM_STATUS_CH7F. */
screamer 0:c5e2f793b59a 1039
screamer 0:c5e2f793b59a 1040 /*! @brief Read current value of the FTM_STATUS_CH7F field. */
screamer 0:c5e2f793b59a 1041 #define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
screamer 0:c5e2f793b59a 1042
screamer 0:c5e2f793b59a 1043 /*! @brief Format value for bitfield FTM_STATUS_CH7F. */
screamer 0:c5e2f793b59a 1044 #define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F)
screamer 0:c5e2f793b59a 1045
screamer 0:c5e2f793b59a 1046 /*! @brief Set the CH7F field to a new value. */
screamer 0:c5e2f793b59a 1047 #define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
screamer 0:c5e2f793b59a 1048 /*@}*/
screamer 0:c5e2f793b59a 1049
screamer 0:c5e2f793b59a 1050 /*******************************************************************************
screamer 0:c5e2f793b59a 1051 * HW_FTM_MODE - Features Mode Selection
screamer 0:c5e2f793b59a 1052 ******************************************************************************/
screamer 0:c5e2f793b59a 1053
screamer 0:c5e2f793b59a 1054 /*!
screamer 0:c5e2f793b59a 1055 * @brief HW_FTM_MODE - Features Mode Selection (RW)
screamer 0:c5e2f793b59a 1056 *
screamer 0:c5e2f793b59a 1057 * Reset value: 0x00000004U
screamer 0:c5e2f793b59a 1058 *
screamer 0:c5e2f793b59a 1059 * This register contains the global enable bit for FTM-specific features and
screamer 0:c5e2f793b59a 1060 * the control bits used to configure: Fault control mode and interrupt Capture
screamer 0:c5e2f793b59a 1061 * Test mode PWM synchronization Write protection Channel output initialization
screamer 0:c5e2f793b59a 1062 * These controls relate to all channels within this module.
screamer 0:c5e2f793b59a 1063 */
screamer 0:c5e2f793b59a 1064 typedef union _hw_ftm_mode
screamer 0:c5e2f793b59a 1065 {
screamer 0:c5e2f793b59a 1066 uint32_t U;
screamer 0:c5e2f793b59a 1067 struct _hw_ftm_mode_bitfields
screamer 0:c5e2f793b59a 1068 {
screamer 0:c5e2f793b59a 1069 uint32_t FTMEN : 1; /*!< [0] FTM Enable */
screamer 0:c5e2f793b59a 1070 uint32_t INIT : 1; /*!< [1] Initialize The Channels Output */
screamer 0:c5e2f793b59a 1071 uint32_t WPDIS : 1; /*!< [2] Write Protection Disable */
screamer 0:c5e2f793b59a 1072 uint32_t PWMSYNC : 1; /*!< [3] PWM Synchronization Mode */
screamer 0:c5e2f793b59a 1073 uint32_t CAPTEST : 1; /*!< [4] Capture Test Mode Enable */
screamer 0:c5e2f793b59a 1074 uint32_t FAULTM : 2; /*!< [6:5] Fault Control Mode */
screamer 0:c5e2f793b59a 1075 uint32_t FAULTIE : 1; /*!< [7] Fault Interrupt Enable */
screamer 0:c5e2f793b59a 1076 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 1077 } B;
screamer 0:c5e2f793b59a 1078 } hw_ftm_mode_t;
screamer 0:c5e2f793b59a 1079
screamer 0:c5e2f793b59a 1080 /*!
screamer 0:c5e2f793b59a 1081 * @name Constants and macros for entire FTM_MODE register
screamer 0:c5e2f793b59a 1082 */
screamer 0:c5e2f793b59a 1083 /*@{*/
screamer 0:c5e2f793b59a 1084 #define HW_FTM_MODE_ADDR(x) ((x) + 0x54U)
screamer 0:c5e2f793b59a 1085
screamer 0:c5e2f793b59a 1086 #define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
screamer 0:c5e2f793b59a 1087 #define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
screamer 0:c5e2f793b59a 1088 #define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
screamer 0:c5e2f793b59a 1089 #define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v)))
screamer 0:c5e2f793b59a 1090 #define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1091 #define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1092 /*@}*/
screamer 0:c5e2f793b59a 1093
screamer 0:c5e2f793b59a 1094 /*
screamer 0:c5e2f793b59a 1095 * Constants & macros for individual FTM_MODE bitfields
screamer 0:c5e2f793b59a 1096 */
screamer 0:c5e2f793b59a 1097
screamer 0:c5e2f793b59a 1098 /*!
screamer 0:c5e2f793b59a 1099 * @name Register FTM_MODE, field FTMEN[0] (RW)
screamer 0:c5e2f793b59a 1100 *
screamer 0:c5e2f793b59a 1101 * This field is write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 1102 *
screamer 0:c5e2f793b59a 1103 * Values:
screamer 0:c5e2f793b59a 1104 * - 0 - Only the TPM-compatible registers (first set of registers) can be used
screamer 0:c5e2f793b59a 1105 * without any restriction. Do not use the FTM-specific registers.
screamer 0:c5e2f793b59a 1106 * - 1 - All registers including the FTM-specific registers (second set of
screamer 0:c5e2f793b59a 1107 * registers) are available for use with no restrictions.
screamer 0:c5e2f793b59a 1108 */
screamer 0:c5e2f793b59a 1109 /*@{*/
screamer 0:c5e2f793b59a 1110 #define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */
screamer 0:c5e2f793b59a 1111 #define BM_FTM_MODE_FTMEN (0x00000001U) /*!< Bit mask for FTM_MODE_FTMEN. */
screamer 0:c5e2f793b59a 1112 #define BS_FTM_MODE_FTMEN (1U) /*!< Bit field size in bits for FTM_MODE_FTMEN. */
screamer 0:c5e2f793b59a 1113
screamer 0:c5e2f793b59a 1114 /*! @brief Read current value of the FTM_MODE_FTMEN field. */
screamer 0:c5e2f793b59a 1115 #define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
screamer 0:c5e2f793b59a 1116
screamer 0:c5e2f793b59a 1117 /*! @brief Format value for bitfield FTM_MODE_FTMEN. */
screamer 0:c5e2f793b59a 1118 #define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN)
screamer 0:c5e2f793b59a 1119
screamer 0:c5e2f793b59a 1120 /*! @brief Set the FTMEN field to a new value. */
screamer 0:c5e2f793b59a 1121 #define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
screamer 0:c5e2f793b59a 1122 /*@}*/
screamer 0:c5e2f793b59a 1123
screamer 0:c5e2f793b59a 1124 /*!
screamer 0:c5e2f793b59a 1125 * @name Register FTM_MODE, field INIT[1] (RW)
screamer 0:c5e2f793b59a 1126 *
screamer 0:c5e2f793b59a 1127 * When a 1 is written to INIT bit the channels output is initialized according
screamer 0:c5e2f793b59a 1128 * to the state of their corresponding bit in the OUTINIT register. Writing a 0
screamer 0:c5e2f793b59a 1129 * to INIT bit has no effect. The INIT bit is always read as 0.
screamer 0:c5e2f793b59a 1130 */
screamer 0:c5e2f793b59a 1131 /*@{*/
screamer 0:c5e2f793b59a 1132 #define BP_FTM_MODE_INIT (1U) /*!< Bit position for FTM_MODE_INIT. */
screamer 0:c5e2f793b59a 1133 #define BM_FTM_MODE_INIT (0x00000002U) /*!< Bit mask for FTM_MODE_INIT. */
screamer 0:c5e2f793b59a 1134 #define BS_FTM_MODE_INIT (1U) /*!< Bit field size in bits for FTM_MODE_INIT. */
screamer 0:c5e2f793b59a 1135
screamer 0:c5e2f793b59a 1136 /*! @brief Read current value of the FTM_MODE_INIT field. */
screamer 0:c5e2f793b59a 1137 #define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
screamer 0:c5e2f793b59a 1138
screamer 0:c5e2f793b59a 1139 /*! @brief Format value for bitfield FTM_MODE_INIT. */
screamer 0:c5e2f793b59a 1140 #define BF_FTM_MODE_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT)
screamer 0:c5e2f793b59a 1141
screamer 0:c5e2f793b59a 1142 /*! @brief Set the INIT field to a new value. */
screamer 0:c5e2f793b59a 1143 #define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
screamer 0:c5e2f793b59a 1144 /*@}*/
screamer 0:c5e2f793b59a 1145
screamer 0:c5e2f793b59a 1146 /*!
screamer 0:c5e2f793b59a 1147 * @name Register FTM_MODE, field WPDIS[2] (RW)
screamer 0:c5e2f793b59a 1148 *
screamer 0:c5e2f793b59a 1149 * When write protection is enabled (WPDIS = 0), write protected bits cannot be
screamer 0:c5e2f793b59a 1150 * written. When write protection is disabled (WPDIS = 1), write protected bits
screamer 0:c5e2f793b59a 1151 * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
screamer 0:c5e2f793b59a 1152 * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
screamer 0:c5e2f793b59a 1153 * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
screamer 0:c5e2f793b59a 1154 *
screamer 0:c5e2f793b59a 1155 * Values:
screamer 0:c5e2f793b59a 1156 * - 0 - Write protection is enabled.
screamer 0:c5e2f793b59a 1157 * - 1 - Write protection is disabled.
screamer 0:c5e2f793b59a 1158 */
screamer 0:c5e2f793b59a 1159 /*@{*/
screamer 0:c5e2f793b59a 1160 #define BP_FTM_MODE_WPDIS (2U) /*!< Bit position for FTM_MODE_WPDIS. */
screamer 0:c5e2f793b59a 1161 #define BM_FTM_MODE_WPDIS (0x00000004U) /*!< Bit mask for FTM_MODE_WPDIS. */
screamer 0:c5e2f793b59a 1162 #define BS_FTM_MODE_WPDIS (1U) /*!< Bit field size in bits for FTM_MODE_WPDIS. */
screamer 0:c5e2f793b59a 1163
screamer 0:c5e2f793b59a 1164 /*! @brief Read current value of the FTM_MODE_WPDIS field. */
screamer 0:c5e2f793b59a 1165 #define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
screamer 0:c5e2f793b59a 1166
screamer 0:c5e2f793b59a 1167 /*! @brief Format value for bitfield FTM_MODE_WPDIS. */
screamer 0:c5e2f793b59a 1168 #define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS)
screamer 0:c5e2f793b59a 1169
screamer 0:c5e2f793b59a 1170 /*! @brief Set the WPDIS field to a new value. */
screamer 0:c5e2f793b59a 1171 #define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
screamer 0:c5e2f793b59a 1172 /*@}*/
screamer 0:c5e2f793b59a 1173
screamer 0:c5e2f793b59a 1174 /*!
screamer 0:c5e2f793b59a 1175 * @name Register FTM_MODE, field PWMSYNC[3] (RW)
screamer 0:c5e2f793b59a 1176 *
screamer 0:c5e2f793b59a 1177 * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
screamer 0:c5e2f793b59a 1178 * synchronization. See PWM synchronization. The PWMSYNC bit configures the
screamer 0:c5e2f793b59a 1179 * synchronization when SYNCMODE is 0.
screamer 0:c5e2f793b59a 1180 *
screamer 0:c5e2f793b59a 1181 * Values:
screamer 0:c5e2f793b59a 1182 * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
screamer 0:c5e2f793b59a 1183 * CnV, OUTMASK, and FTM counter synchronization.
screamer 0:c5e2f793b59a 1184 * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
screamer 0:c5e2f793b59a 1185 * hardware triggers can only be used by OUTMASK and FTM counter
screamer 0:c5e2f793b59a 1186 * synchronization.
screamer 0:c5e2f793b59a 1187 */
screamer 0:c5e2f793b59a 1188 /*@{*/
screamer 0:c5e2f793b59a 1189 #define BP_FTM_MODE_PWMSYNC (3U) /*!< Bit position for FTM_MODE_PWMSYNC. */
screamer 0:c5e2f793b59a 1190 #define BM_FTM_MODE_PWMSYNC (0x00000008U) /*!< Bit mask for FTM_MODE_PWMSYNC. */
screamer 0:c5e2f793b59a 1191 #define BS_FTM_MODE_PWMSYNC (1U) /*!< Bit field size in bits for FTM_MODE_PWMSYNC. */
screamer 0:c5e2f793b59a 1192
screamer 0:c5e2f793b59a 1193 /*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
screamer 0:c5e2f793b59a 1194 #define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
screamer 0:c5e2f793b59a 1195
screamer 0:c5e2f793b59a 1196 /*! @brief Format value for bitfield FTM_MODE_PWMSYNC. */
screamer 0:c5e2f793b59a 1197 #define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC)
screamer 0:c5e2f793b59a 1198
screamer 0:c5e2f793b59a 1199 /*! @brief Set the PWMSYNC field to a new value. */
screamer 0:c5e2f793b59a 1200 #define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
screamer 0:c5e2f793b59a 1201 /*@}*/
screamer 0:c5e2f793b59a 1202
screamer 0:c5e2f793b59a 1203 /*!
screamer 0:c5e2f793b59a 1204 * @name Register FTM_MODE, field CAPTEST[4] (RW)
screamer 0:c5e2f793b59a 1205 *
screamer 0:c5e2f793b59a 1206 * Enables the capture test mode. This field is write protected. It can be
screamer 0:c5e2f793b59a 1207 * written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 1208 *
screamer 0:c5e2f793b59a 1209 * Values:
screamer 0:c5e2f793b59a 1210 * - 0 - Capture test mode is disabled.
screamer 0:c5e2f793b59a 1211 * - 1 - Capture test mode is enabled.
screamer 0:c5e2f793b59a 1212 */
screamer 0:c5e2f793b59a 1213 /*@{*/
screamer 0:c5e2f793b59a 1214 #define BP_FTM_MODE_CAPTEST (4U) /*!< Bit position for FTM_MODE_CAPTEST. */
screamer 0:c5e2f793b59a 1215 #define BM_FTM_MODE_CAPTEST (0x00000010U) /*!< Bit mask for FTM_MODE_CAPTEST. */
screamer 0:c5e2f793b59a 1216 #define BS_FTM_MODE_CAPTEST (1U) /*!< Bit field size in bits for FTM_MODE_CAPTEST. */
screamer 0:c5e2f793b59a 1217
screamer 0:c5e2f793b59a 1218 /*! @brief Read current value of the FTM_MODE_CAPTEST field. */
screamer 0:c5e2f793b59a 1219 #define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
screamer 0:c5e2f793b59a 1220
screamer 0:c5e2f793b59a 1221 /*! @brief Format value for bitfield FTM_MODE_CAPTEST. */
screamer 0:c5e2f793b59a 1222 #define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST)
screamer 0:c5e2f793b59a 1223
screamer 0:c5e2f793b59a 1224 /*! @brief Set the CAPTEST field to a new value. */
screamer 0:c5e2f793b59a 1225 #define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
screamer 0:c5e2f793b59a 1226 /*@}*/
screamer 0:c5e2f793b59a 1227
screamer 0:c5e2f793b59a 1228 /*!
screamer 0:c5e2f793b59a 1229 * @name Register FTM_MODE, field FAULTM[6:5] (RW)
screamer 0:c5e2f793b59a 1230 *
screamer 0:c5e2f793b59a 1231 * Defines the FTM fault control mode. This field is write protected. It can be
screamer 0:c5e2f793b59a 1232 * written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 1233 *
screamer 0:c5e2f793b59a 1234 * Values:
screamer 0:c5e2f793b59a 1235 * - 00 - Fault control is disabled for all channels.
screamer 0:c5e2f793b59a 1236 * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
screamer 0:c5e2f793b59a 1237 * 6), and the selected mode is the manual fault clearing.
screamer 0:c5e2f793b59a 1238 * - 10 - Fault control is enabled for all channels, and the selected mode is
screamer 0:c5e2f793b59a 1239 * the manual fault clearing.
screamer 0:c5e2f793b59a 1240 * - 11 - Fault control is enabled for all channels, and the selected mode is
screamer 0:c5e2f793b59a 1241 * the automatic fault clearing.
screamer 0:c5e2f793b59a 1242 */
screamer 0:c5e2f793b59a 1243 /*@{*/
screamer 0:c5e2f793b59a 1244 #define BP_FTM_MODE_FAULTM (5U) /*!< Bit position for FTM_MODE_FAULTM. */
screamer 0:c5e2f793b59a 1245 #define BM_FTM_MODE_FAULTM (0x00000060U) /*!< Bit mask for FTM_MODE_FAULTM. */
screamer 0:c5e2f793b59a 1246 #define BS_FTM_MODE_FAULTM (2U) /*!< Bit field size in bits for FTM_MODE_FAULTM. */
screamer 0:c5e2f793b59a 1247
screamer 0:c5e2f793b59a 1248 /*! @brief Read current value of the FTM_MODE_FAULTM field. */
screamer 0:c5e2f793b59a 1249 #define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
screamer 0:c5e2f793b59a 1250
screamer 0:c5e2f793b59a 1251 /*! @brief Format value for bitfield FTM_MODE_FAULTM. */
screamer 0:c5e2f793b59a 1252 #define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM)
screamer 0:c5e2f793b59a 1253
screamer 0:c5e2f793b59a 1254 /*! @brief Set the FAULTM field to a new value. */
screamer 0:c5e2f793b59a 1255 #define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
screamer 0:c5e2f793b59a 1256 /*@}*/
screamer 0:c5e2f793b59a 1257
screamer 0:c5e2f793b59a 1258 /*!
screamer 0:c5e2f793b59a 1259 * @name Register FTM_MODE, field FAULTIE[7] (RW)
screamer 0:c5e2f793b59a 1260 *
screamer 0:c5e2f793b59a 1261 * Enables the generation of an interrupt when a fault is detected by FTM and
screamer 0:c5e2f793b59a 1262 * the FTM fault control is enabled.
screamer 0:c5e2f793b59a 1263 *
screamer 0:c5e2f793b59a 1264 * Values:
screamer 0:c5e2f793b59a 1265 * - 0 - Fault control interrupt is disabled.
screamer 0:c5e2f793b59a 1266 * - 1 - Fault control interrupt is enabled.
screamer 0:c5e2f793b59a 1267 */
screamer 0:c5e2f793b59a 1268 /*@{*/
screamer 0:c5e2f793b59a 1269 #define BP_FTM_MODE_FAULTIE (7U) /*!< Bit position for FTM_MODE_FAULTIE. */
screamer 0:c5e2f793b59a 1270 #define BM_FTM_MODE_FAULTIE (0x00000080U) /*!< Bit mask for FTM_MODE_FAULTIE. */
screamer 0:c5e2f793b59a 1271 #define BS_FTM_MODE_FAULTIE (1U) /*!< Bit field size in bits for FTM_MODE_FAULTIE. */
screamer 0:c5e2f793b59a 1272
screamer 0:c5e2f793b59a 1273 /*! @brief Read current value of the FTM_MODE_FAULTIE field. */
screamer 0:c5e2f793b59a 1274 #define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
screamer 0:c5e2f793b59a 1275
screamer 0:c5e2f793b59a 1276 /*! @brief Format value for bitfield FTM_MODE_FAULTIE. */
screamer 0:c5e2f793b59a 1277 #define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE)
screamer 0:c5e2f793b59a 1278
screamer 0:c5e2f793b59a 1279 /*! @brief Set the FAULTIE field to a new value. */
screamer 0:c5e2f793b59a 1280 #define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
screamer 0:c5e2f793b59a 1281 /*@}*/
screamer 0:c5e2f793b59a 1282
screamer 0:c5e2f793b59a 1283 /*******************************************************************************
screamer 0:c5e2f793b59a 1284 * HW_FTM_SYNC - Synchronization
screamer 0:c5e2f793b59a 1285 ******************************************************************************/
screamer 0:c5e2f793b59a 1286
screamer 0:c5e2f793b59a 1287 /*!
screamer 0:c5e2f793b59a 1288 * @brief HW_FTM_SYNC - Synchronization (RW)
screamer 0:c5e2f793b59a 1289 *
screamer 0:c5e2f793b59a 1290 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 1291 *
screamer 0:c5e2f793b59a 1292 * This register configures the PWM synchronization. A synchronization event can
screamer 0:c5e2f793b59a 1293 * perform the synchronized update of MOD, CV, and OUTMASK registers with the
screamer 0:c5e2f793b59a 1294 * value of their write buffer and the FTM counter initialization. The software
screamer 0:c5e2f793b59a 1295 * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
screamer 0:c5e2f793b59a 1296 * potential conflict if used together when SYNCMODE = 0. Use only hardware or
screamer 0:c5e2f793b59a 1297 * software triggers but not both at the same time, otherwise unpredictable behavior
screamer 0:c5e2f793b59a 1298 * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
screamer 0:c5e2f793b59a 1299 * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
screamer 0:c5e2f793b59a 1300 * all enabled channels simultaneously. The use of the loading point selection
screamer 0:c5e2f793b59a 1301 * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
screamer 0:c5e2f793b59a 1302 * bits, is likely to result in unpredictable behavior. The synchronization
screamer 0:c5e2f793b59a 1303 * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
screamer 0:c5e2f793b59a 1304 * register) bits. See PWM synchronization.
screamer 0:c5e2f793b59a 1305 */
screamer 0:c5e2f793b59a 1306 typedef union _hw_ftm_sync
screamer 0:c5e2f793b59a 1307 {
screamer 0:c5e2f793b59a 1308 uint32_t U;
screamer 0:c5e2f793b59a 1309 struct _hw_ftm_sync_bitfields
screamer 0:c5e2f793b59a 1310 {
screamer 0:c5e2f793b59a 1311 uint32_t CNTMIN : 1; /*!< [0] Minimum Loading Point Enable */
screamer 0:c5e2f793b59a 1312 uint32_t CNTMAX : 1; /*!< [1] Maximum Loading Point Enable */
screamer 0:c5e2f793b59a 1313 uint32_t REINIT : 1; /*!< [2] FTM Counter Reinitialization By
screamer 0:c5e2f793b59a 1314 * Synchronization (FTM counter synchronization) */
screamer 0:c5e2f793b59a 1315 uint32_t SYNCHOM : 1; /*!< [3] Output Mask Synchronization */
screamer 0:c5e2f793b59a 1316 uint32_t TRIG0 : 1; /*!< [4] PWM Synchronization Hardware Trigger 0 */
screamer 0:c5e2f793b59a 1317 uint32_t TRIG1 : 1; /*!< [5] PWM Synchronization Hardware Trigger 1 */
screamer 0:c5e2f793b59a 1318 uint32_t TRIG2 : 1; /*!< [6] PWM Synchronization Hardware Trigger 2 */
screamer 0:c5e2f793b59a 1319 uint32_t SWSYNC : 1; /*!< [7] PWM Synchronization Software Trigger */
screamer 0:c5e2f793b59a 1320 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 1321 } B;
screamer 0:c5e2f793b59a 1322 } hw_ftm_sync_t;
screamer 0:c5e2f793b59a 1323
screamer 0:c5e2f793b59a 1324 /*!
screamer 0:c5e2f793b59a 1325 * @name Constants and macros for entire FTM_SYNC register
screamer 0:c5e2f793b59a 1326 */
screamer 0:c5e2f793b59a 1327 /*@{*/
screamer 0:c5e2f793b59a 1328 #define HW_FTM_SYNC_ADDR(x) ((x) + 0x58U)
screamer 0:c5e2f793b59a 1329
screamer 0:c5e2f793b59a 1330 #define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
screamer 0:c5e2f793b59a 1331 #define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
screamer 0:c5e2f793b59a 1332 #define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
screamer 0:c5e2f793b59a 1333 #define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v)))
screamer 0:c5e2f793b59a 1334 #define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1335 #define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1336 /*@}*/
screamer 0:c5e2f793b59a 1337
screamer 0:c5e2f793b59a 1338 /*
screamer 0:c5e2f793b59a 1339 * Constants & macros for individual FTM_SYNC bitfields
screamer 0:c5e2f793b59a 1340 */
screamer 0:c5e2f793b59a 1341
screamer 0:c5e2f793b59a 1342 /*!
screamer 0:c5e2f793b59a 1343 * @name Register FTM_SYNC, field CNTMIN[0] (RW)
screamer 0:c5e2f793b59a 1344 *
screamer 0:c5e2f793b59a 1345 * Selects the minimum loading point to PWM synchronization. See Boundary cycle
screamer 0:c5e2f793b59a 1346 * and loading points. If CNTMIN is one, the selected loading point is when the
screamer 0:c5e2f793b59a 1347 * FTM counter reaches its minimum value (CNTIN register).
screamer 0:c5e2f793b59a 1348 *
screamer 0:c5e2f793b59a 1349 * Values:
screamer 0:c5e2f793b59a 1350 * - 0 - The minimum loading point is disabled.
screamer 0:c5e2f793b59a 1351 * - 1 - The minimum loading point is enabled.
screamer 0:c5e2f793b59a 1352 */
screamer 0:c5e2f793b59a 1353 /*@{*/
screamer 0:c5e2f793b59a 1354 #define BP_FTM_SYNC_CNTMIN (0U) /*!< Bit position for FTM_SYNC_CNTMIN. */
screamer 0:c5e2f793b59a 1355 #define BM_FTM_SYNC_CNTMIN (0x00000001U) /*!< Bit mask for FTM_SYNC_CNTMIN. */
screamer 0:c5e2f793b59a 1356 #define BS_FTM_SYNC_CNTMIN (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMIN. */
screamer 0:c5e2f793b59a 1357
screamer 0:c5e2f793b59a 1358 /*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
screamer 0:c5e2f793b59a 1359 #define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
screamer 0:c5e2f793b59a 1360
screamer 0:c5e2f793b59a 1361 /*! @brief Format value for bitfield FTM_SYNC_CNTMIN. */
screamer 0:c5e2f793b59a 1362 #define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN)
screamer 0:c5e2f793b59a 1363
screamer 0:c5e2f793b59a 1364 /*! @brief Set the CNTMIN field to a new value. */
screamer 0:c5e2f793b59a 1365 #define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
screamer 0:c5e2f793b59a 1366 /*@}*/
screamer 0:c5e2f793b59a 1367
screamer 0:c5e2f793b59a 1368 /*!
screamer 0:c5e2f793b59a 1369 * @name Register FTM_SYNC, field CNTMAX[1] (RW)
screamer 0:c5e2f793b59a 1370 *
screamer 0:c5e2f793b59a 1371 * Selects the maximum loading point to PWM synchronization. See Boundary cycle
screamer 0:c5e2f793b59a 1372 * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
screamer 0:c5e2f793b59a 1373 * counter reaches its maximum value (MOD register).
screamer 0:c5e2f793b59a 1374 *
screamer 0:c5e2f793b59a 1375 * Values:
screamer 0:c5e2f793b59a 1376 * - 0 - The maximum loading point is disabled.
screamer 0:c5e2f793b59a 1377 * - 1 - The maximum loading point is enabled.
screamer 0:c5e2f793b59a 1378 */
screamer 0:c5e2f793b59a 1379 /*@{*/
screamer 0:c5e2f793b59a 1380 #define BP_FTM_SYNC_CNTMAX (1U) /*!< Bit position for FTM_SYNC_CNTMAX. */
screamer 0:c5e2f793b59a 1381 #define BM_FTM_SYNC_CNTMAX (0x00000002U) /*!< Bit mask for FTM_SYNC_CNTMAX. */
screamer 0:c5e2f793b59a 1382 #define BS_FTM_SYNC_CNTMAX (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMAX. */
screamer 0:c5e2f793b59a 1383
screamer 0:c5e2f793b59a 1384 /*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
screamer 0:c5e2f793b59a 1385 #define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
screamer 0:c5e2f793b59a 1386
screamer 0:c5e2f793b59a 1387 /*! @brief Format value for bitfield FTM_SYNC_CNTMAX. */
screamer 0:c5e2f793b59a 1388 #define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX)
screamer 0:c5e2f793b59a 1389
screamer 0:c5e2f793b59a 1390 /*! @brief Set the CNTMAX field to a new value. */
screamer 0:c5e2f793b59a 1391 #define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
screamer 0:c5e2f793b59a 1392 /*@}*/
screamer 0:c5e2f793b59a 1393
screamer 0:c5e2f793b59a 1394 /*!
screamer 0:c5e2f793b59a 1395 * @name Register FTM_SYNC, field REINIT[2] (RW)
screamer 0:c5e2f793b59a 1396 *
screamer 0:c5e2f793b59a 1397 * Determines if the FTM counter is reinitialized when the selected trigger for
screamer 0:c5e2f793b59a 1398 * the synchronization is detected. The REINIT bit configures the synchronization
screamer 0:c5e2f793b59a 1399 * when SYNCMODE is zero.
screamer 0:c5e2f793b59a 1400 *
screamer 0:c5e2f793b59a 1401 * Values:
screamer 0:c5e2f793b59a 1402 * - 0 - FTM counter continues to count normally.
screamer 0:c5e2f793b59a 1403 * - 1 - FTM counter is updated with its initial value when the selected trigger
screamer 0:c5e2f793b59a 1404 * is detected.
screamer 0:c5e2f793b59a 1405 */
screamer 0:c5e2f793b59a 1406 /*@{*/
screamer 0:c5e2f793b59a 1407 #define BP_FTM_SYNC_REINIT (2U) /*!< Bit position for FTM_SYNC_REINIT. */
screamer 0:c5e2f793b59a 1408 #define BM_FTM_SYNC_REINIT (0x00000004U) /*!< Bit mask for FTM_SYNC_REINIT. */
screamer 0:c5e2f793b59a 1409 #define BS_FTM_SYNC_REINIT (1U) /*!< Bit field size in bits for FTM_SYNC_REINIT. */
screamer 0:c5e2f793b59a 1410
screamer 0:c5e2f793b59a 1411 /*! @brief Read current value of the FTM_SYNC_REINIT field. */
screamer 0:c5e2f793b59a 1412 #define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
screamer 0:c5e2f793b59a 1413
screamer 0:c5e2f793b59a 1414 /*! @brief Format value for bitfield FTM_SYNC_REINIT. */
screamer 0:c5e2f793b59a 1415 #define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT)
screamer 0:c5e2f793b59a 1416
screamer 0:c5e2f793b59a 1417 /*! @brief Set the REINIT field to a new value. */
screamer 0:c5e2f793b59a 1418 #define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
screamer 0:c5e2f793b59a 1419 /*@}*/
screamer 0:c5e2f793b59a 1420
screamer 0:c5e2f793b59a 1421 /*!
screamer 0:c5e2f793b59a 1422 * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
screamer 0:c5e2f793b59a 1423 *
screamer 0:c5e2f793b59a 1424 * Selects when the OUTMASK register is updated with the value of its buffer.
screamer 0:c5e2f793b59a 1425 *
screamer 0:c5e2f793b59a 1426 * Values:
screamer 0:c5e2f793b59a 1427 * - 0 - OUTMASK register is updated with the value of its buffer in all rising
screamer 0:c5e2f793b59a 1428 * edges of the system clock.
screamer 0:c5e2f793b59a 1429 * - 1 - OUTMASK register is updated with the value of its buffer only by the
screamer 0:c5e2f793b59a 1430 * PWM synchronization.
screamer 0:c5e2f793b59a 1431 */
screamer 0:c5e2f793b59a 1432 /*@{*/
screamer 0:c5e2f793b59a 1433 #define BP_FTM_SYNC_SYNCHOM (3U) /*!< Bit position for FTM_SYNC_SYNCHOM. */
screamer 0:c5e2f793b59a 1434 #define BM_FTM_SYNC_SYNCHOM (0x00000008U) /*!< Bit mask for FTM_SYNC_SYNCHOM. */
screamer 0:c5e2f793b59a 1435 #define BS_FTM_SYNC_SYNCHOM (1U) /*!< Bit field size in bits for FTM_SYNC_SYNCHOM. */
screamer 0:c5e2f793b59a 1436
screamer 0:c5e2f793b59a 1437 /*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
screamer 0:c5e2f793b59a 1438 #define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
screamer 0:c5e2f793b59a 1439
screamer 0:c5e2f793b59a 1440 /*! @brief Format value for bitfield FTM_SYNC_SYNCHOM. */
screamer 0:c5e2f793b59a 1441 #define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM)
screamer 0:c5e2f793b59a 1442
screamer 0:c5e2f793b59a 1443 /*! @brief Set the SYNCHOM field to a new value. */
screamer 0:c5e2f793b59a 1444 #define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
screamer 0:c5e2f793b59a 1445 /*@}*/
screamer 0:c5e2f793b59a 1446
screamer 0:c5e2f793b59a 1447 /*!
screamer 0:c5e2f793b59a 1448 * @name Register FTM_SYNC, field TRIG0[4] (RW)
screamer 0:c5e2f793b59a 1449 *
screamer 0:c5e2f793b59a 1450 * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
screamer 0:c5e2f793b59a 1451 * occurs when a rising edge is detected at the trigger 0 input signal.
screamer 0:c5e2f793b59a 1452 *
screamer 0:c5e2f793b59a 1453 * Values:
screamer 0:c5e2f793b59a 1454 * - 0 - Trigger is disabled.
screamer 0:c5e2f793b59a 1455 * - 1 - Trigger is enabled.
screamer 0:c5e2f793b59a 1456 */
screamer 0:c5e2f793b59a 1457 /*@{*/
screamer 0:c5e2f793b59a 1458 #define BP_FTM_SYNC_TRIG0 (4U) /*!< Bit position for FTM_SYNC_TRIG0. */
screamer 0:c5e2f793b59a 1459 #define BM_FTM_SYNC_TRIG0 (0x00000010U) /*!< Bit mask for FTM_SYNC_TRIG0. */
screamer 0:c5e2f793b59a 1460 #define BS_FTM_SYNC_TRIG0 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG0. */
screamer 0:c5e2f793b59a 1461
screamer 0:c5e2f793b59a 1462 /*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
screamer 0:c5e2f793b59a 1463 #define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
screamer 0:c5e2f793b59a 1464
screamer 0:c5e2f793b59a 1465 /*! @brief Format value for bitfield FTM_SYNC_TRIG0. */
screamer 0:c5e2f793b59a 1466 #define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0)
screamer 0:c5e2f793b59a 1467
screamer 0:c5e2f793b59a 1468 /*! @brief Set the TRIG0 field to a new value. */
screamer 0:c5e2f793b59a 1469 #define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
screamer 0:c5e2f793b59a 1470 /*@}*/
screamer 0:c5e2f793b59a 1471
screamer 0:c5e2f793b59a 1472 /*!
screamer 0:c5e2f793b59a 1473 * @name Register FTM_SYNC, field TRIG1[5] (RW)
screamer 0:c5e2f793b59a 1474 *
screamer 0:c5e2f793b59a 1475 * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
screamer 0:c5e2f793b59a 1476 * happens when a rising edge is detected at the trigger 1 input signal.
screamer 0:c5e2f793b59a 1477 *
screamer 0:c5e2f793b59a 1478 * Values:
screamer 0:c5e2f793b59a 1479 * - 0 - Trigger is disabled.
screamer 0:c5e2f793b59a 1480 * - 1 - Trigger is enabled.
screamer 0:c5e2f793b59a 1481 */
screamer 0:c5e2f793b59a 1482 /*@{*/
screamer 0:c5e2f793b59a 1483 #define BP_FTM_SYNC_TRIG1 (5U) /*!< Bit position for FTM_SYNC_TRIG1. */
screamer 0:c5e2f793b59a 1484 #define BM_FTM_SYNC_TRIG1 (0x00000020U) /*!< Bit mask for FTM_SYNC_TRIG1. */
screamer 0:c5e2f793b59a 1485 #define BS_FTM_SYNC_TRIG1 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG1. */
screamer 0:c5e2f793b59a 1486
screamer 0:c5e2f793b59a 1487 /*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
screamer 0:c5e2f793b59a 1488 #define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
screamer 0:c5e2f793b59a 1489
screamer 0:c5e2f793b59a 1490 /*! @brief Format value for bitfield FTM_SYNC_TRIG1. */
screamer 0:c5e2f793b59a 1491 #define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1)
screamer 0:c5e2f793b59a 1492
screamer 0:c5e2f793b59a 1493 /*! @brief Set the TRIG1 field to a new value. */
screamer 0:c5e2f793b59a 1494 #define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
screamer 0:c5e2f793b59a 1495 /*@}*/
screamer 0:c5e2f793b59a 1496
screamer 0:c5e2f793b59a 1497 /*!
screamer 0:c5e2f793b59a 1498 * @name Register FTM_SYNC, field TRIG2[6] (RW)
screamer 0:c5e2f793b59a 1499 *
screamer 0:c5e2f793b59a 1500 * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
screamer 0:c5e2f793b59a 1501 * happens when a rising edge is detected at the trigger 2 input signal.
screamer 0:c5e2f793b59a 1502 *
screamer 0:c5e2f793b59a 1503 * Values:
screamer 0:c5e2f793b59a 1504 * - 0 - Trigger is disabled.
screamer 0:c5e2f793b59a 1505 * - 1 - Trigger is enabled.
screamer 0:c5e2f793b59a 1506 */
screamer 0:c5e2f793b59a 1507 /*@{*/
screamer 0:c5e2f793b59a 1508 #define BP_FTM_SYNC_TRIG2 (6U) /*!< Bit position for FTM_SYNC_TRIG2. */
screamer 0:c5e2f793b59a 1509 #define BM_FTM_SYNC_TRIG2 (0x00000040U) /*!< Bit mask for FTM_SYNC_TRIG2. */
screamer 0:c5e2f793b59a 1510 #define BS_FTM_SYNC_TRIG2 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG2. */
screamer 0:c5e2f793b59a 1511
screamer 0:c5e2f793b59a 1512 /*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
screamer 0:c5e2f793b59a 1513 #define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
screamer 0:c5e2f793b59a 1514
screamer 0:c5e2f793b59a 1515 /*! @brief Format value for bitfield FTM_SYNC_TRIG2. */
screamer 0:c5e2f793b59a 1516 #define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2)
screamer 0:c5e2f793b59a 1517
screamer 0:c5e2f793b59a 1518 /*! @brief Set the TRIG2 field to a new value. */
screamer 0:c5e2f793b59a 1519 #define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
screamer 0:c5e2f793b59a 1520 /*@}*/
screamer 0:c5e2f793b59a 1521
screamer 0:c5e2f793b59a 1522 /*!
screamer 0:c5e2f793b59a 1523 * @name Register FTM_SYNC, field SWSYNC[7] (RW)
screamer 0:c5e2f793b59a 1524 *
screamer 0:c5e2f793b59a 1525 * Selects the software trigger as the PWM synchronization trigger. The software
screamer 0:c5e2f793b59a 1526 * trigger happens when a 1 is written to SWSYNC bit.
screamer 0:c5e2f793b59a 1527 *
screamer 0:c5e2f793b59a 1528 * Values:
screamer 0:c5e2f793b59a 1529 * - 0 - Software trigger is not selected.
screamer 0:c5e2f793b59a 1530 * - 1 - Software trigger is selected.
screamer 0:c5e2f793b59a 1531 */
screamer 0:c5e2f793b59a 1532 /*@{*/
screamer 0:c5e2f793b59a 1533 #define BP_FTM_SYNC_SWSYNC (7U) /*!< Bit position for FTM_SYNC_SWSYNC. */
screamer 0:c5e2f793b59a 1534 #define BM_FTM_SYNC_SWSYNC (0x00000080U) /*!< Bit mask for FTM_SYNC_SWSYNC. */
screamer 0:c5e2f793b59a 1535 #define BS_FTM_SYNC_SWSYNC (1U) /*!< Bit field size in bits for FTM_SYNC_SWSYNC. */
screamer 0:c5e2f793b59a 1536
screamer 0:c5e2f793b59a 1537 /*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
screamer 0:c5e2f793b59a 1538 #define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
screamer 0:c5e2f793b59a 1539
screamer 0:c5e2f793b59a 1540 /*! @brief Format value for bitfield FTM_SYNC_SWSYNC. */
screamer 0:c5e2f793b59a 1541 #define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC)
screamer 0:c5e2f793b59a 1542
screamer 0:c5e2f793b59a 1543 /*! @brief Set the SWSYNC field to a new value. */
screamer 0:c5e2f793b59a 1544 #define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
screamer 0:c5e2f793b59a 1545 /*@}*/
screamer 0:c5e2f793b59a 1546
screamer 0:c5e2f793b59a 1547 /*******************************************************************************
screamer 0:c5e2f793b59a 1548 * HW_FTM_OUTINIT - Initial State For Channels Output
screamer 0:c5e2f793b59a 1549 ******************************************************************************/
screamer 0:c5e2f793b59a 1550
screamer 0:c5e2f793b59a 1551 /*!
screamer 0:c5e2f793b59a 1552 * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
screamer 0:c5e2f793b59a 1553 *
screamer 0:c5e2f793b59a 1554 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 1555 */
screamer 0:c5e2f793b59a 1556 typedef union _hw_ftm_outinit
screamer 0:c5e2f793b59a 1557 {
screamer 0:c5e2f793b59a 1558 uint32_t U;
screamer 0:c5e2f793b59a 1559 struct _hw_ftm_outinit_bitfields
screamer 0:c5e2f793b59a 1560 {
screamer 0:c5e2f793b59a 1561 uint32_t CH0OI : 1; /*!< [0] Channel 0 Output Initialization Value */
screamer 0:c5e2f793b59a 1562 uint32_t CH1OI : 1; /*!< [1] Channel 1 Output Initialization Value */
screamer 0:c5e2f793b59a 1563 uint32_t CH2OI : 1; /*!< [2] Channel 2 Output Initialization Value */
screamer 0:c5e2f793b59a 1564 uint32_t CH3OI : 1; /*!< [3] Channel 3 Output Initialization Value */
screamer 0:c5e2f793b59a 1565 uint32_t CH4OI : 1; /*!< [4] Channel 4 Output Initialization Value */
screamer 0:c5e2f793b59a 1566 uint32_t CH5OI : 1; /*!< [5] Channel 5 Output Initialization Value */
screamer 0:c5e2f793b59a 1567 uint32_t CH6OI : 1; /*!< [6] Channel 6 Output Initialization Value */
screamer 0:c5e2f793b59a 1568 uint32_t CH7OI : 1; /*!< [7] Channel 7 Output Initialization Value */
screamer 0:c5e2f793b59a 1569 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 1570 } B;
screamer 0:c5e2f793b59a 1571 } hw_ftm_outinit_t;
screamer 0:c5e2f793b59a 1572
screamer 0:c5e2f793b59a 1573 /*!
screamer 0:c5e2f793b59a 1574 * @name Constants and macros for entire FTM_OUTINIT register
screamer 0:c5e2f793b59a 1575 */
screamer 0:c5e2f793b59a 1576 /*@{*/
screamer 0:c5e2f793b59a 1577 #define HW_FTM_OUTINIT_ADDR(x) ((x) + 0x5CU)
screamer 0:c5e2f793b59a 1578
screamer 0:c5e2f793b59a 1579 #define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
screamer 0:c5e2f793b59a 1580 #define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
screamer 0:c5e2f793b59a 1581 #define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
screamer 0:c5e2f793b59a 1582 #define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v)))
screamer 0:c5e2f793b59a 1583 #define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1584 #define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1585 /*@}*/
screamer 0:c5e2f793b59a 1586
screamer 0:c5e2f793b59a 1587 /*
screamer 0:c5e2f793b59a 1588 * Constants & macros for individual FTM_OUTINIT bitfields
screamer 0:c5e2f793b59a 1589 */
screamer 0:c5e2f793b59a 1590
screamer 0:c5e2f793b59a 1591 /*!
screamer 0:c5e2f793b59a 1592 * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
screamer 0:c5e2f793b59a 1593 *
screamer 0:c5e2f793b59a 1594 * Selects the value that is forced into the channel output when the
screamer 0:c5e2f793b59a 1595 * initialization occurs.
screamer 0:c5e2f793b59a 1596 *
screamer 0:c5e2f793b59a 1597 * Values:
screamer 0:c5e2f793b59a 1598 * - 0 - The initialization value is 0.
screamer 0:c5e2f793b59a 1599 * - 1 - The initialization value is 1.
screamer 0:c5e2f793b59a 1600 */
screamer 0:c5e2f793b59a 1601 /*@{*/
screamer 0:c5e2f793b59a 1602 #define BP_FTM_OUTINIT_CH0OI (0U) /*!< Bit position for FTM_OUTINIT_CH0OI. */
screamer 0:c5e2f793b59a 1603 #define BM_FTM_OUTINIT_CH0OI (0x00000001U) /*!< Bit mask for FTM_OUTINIT_CH0OI. */
screamer 0:c5e2f793b59a 1604 #define BS_FTM_OUTINIT_CH0OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH0OI. */
screamer 0:c5e2f793b59a 1605
screamer 0:c5e2f793b59a 1606 /*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
screamer 0:c5e2f793b59a 1607 #define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
screamer 0:c5e2f793b59a 1608
screamer 0:c5e2f793b59a 1609 /*! @brief Format value for bitfield FTM_OUTINIT_CH0OI. */
screamer 0:c5e2f793b59a 1610 #define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI)
screamer 0:c5e2f793b59a 1611
screamer 0:c5e2f793b59a 1612 /*! @brief Set the CH0OI field to a new value. */
screamer 0:c5e2f793b59a 1613 #define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
screamer 0:c5e2f793b59a 1614 /*@}*/
screamer 0:c5e2f793b59a 1615
screamer 0:c5e2f793b59a 1616 /*!
screamer 0:c5e2f793b59a 1617 * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
screamer 0:c5e2f793b59a 1618 *
screamer 0:c5e2f793b59a 1619 * Selects the value that is forced into the channel output when the
screamer 0:c5e2f793b59a 1620 * initialization occurs.
screamer 0:c5e2f793b59a 1621 *
screamer 0:c5e2f793b59a 1622 * Values:
screamer 0:c5e2f793b59a 1623 * - 0 - The initialization value is 0.
screamer 0:c5e2f793b59a 1624 * - 1 - The initialization value is 1.
screamer 0:c5e2f793b59a 1625 */
screamer 0:c5e2f793b59a 1626 /*@{*/
screamer 0:c5e2f793b59a 1627 #define BP_FTM_OUTINIT_CH1OI (1U) /*!< Bit position for FTM_OUTINIT_CH1OI. */
screamer 0:c5e2f793b59a 1628 #define BM_FTM_OUTINIT_CH1OI (0x00000002U) /*!< Bit mask for FTM_OUTINIT_CH1OI. */
screamer 0:c5e2f793b59a 1629 #define BS_FTM_OUTINIT_CH1OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH1OI. */
screamer 0:c5e2f793b59a 1630
screamer 0:c5e2f793b59a 1631 /*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
screamer 0:c5e2f793b59a 1632 #define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
screamer 0:c5e2f793b59a 1633
screamer 0:c5e2f793b59a 1634 /*! @brief Format value for bitfield FTM_OUTINIT_CH1OI. */
screamer 0:c5e2f793b59a 1635 #define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI)
screamer 0:c5e2f793b59a 1636
screamer 0:c5e2f793b59a 1637 /*! @brief Set the CH1OI field to a new value. */
screamer 0:c5e2f793b59a 1638 #define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
screamer 0:c5e2f793b59a 1639 /*@}*/
screamer 0:c5e2f793b59a 1640
screamer 0:c5e2f793b59a 1641 /*!
screamer 0:c5e2f793b59a 1642 * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
screamer 0:c5e2f793b59a 1643 *
screamer 0:c5e2f793b59a 1644 * Selects the value that is forced into the channel output when the
screamer 0:c5e2f793b59a 1645 * initialization occurs.
screamer 0:c5e2f793b59a 1646 *
screamer 0:c5e2f793b59a 1647 * Values:
screamer 0:c5e2f793b59a 1648 * - 0 - The initialization value is 0.
screamer 0:c5e2f793b59a 1649 * - 1 - The initialization value is 1.
screamer 0:c5e2f793b59a 1650 */
screamer 0:c5e2f793b59a 1651 /*@{*/
screamer 0:c5e2f793b59a 1652 #define BP_FTM_OUTINIT_CH2OI (2U) /*!< Bit position for FTM_OUTINIT_CH2OI. */
screamer 0:c5e2f793b59a 1653 #define BM_FTM_OUTINIT_CH2OI (0x00000004U) /*!< Bit mask for FTM_OUTINIT_CH2OI. */
screamer 0:c5e2f793b59a 1654 #define BS_FTM_OUTINIT_CH2OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH2OI. */
screamer 0:c5e2f793b59a 1655
screamer 0:c5e2f793b59a 1656 /*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
screamer 0:c5e2f793b59a 1657 #define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
screamer 0:c5e2f793b59a 1658
screamer 0:c5e2f793b59a 1659 /*! @brief Format value for bitfield FTM_OUTINIT_CH2OI. */
screamer 0:c5e2f793b59a 1660 #define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI)
screamer 0:c5e2f793b59a 1661
screamer 0:c5e2f793b59a 1662 /*! @brief Set the CH2OI field to a new value. */
screamer 0:c5e2f793b59a 1663 #define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
screamer 0:c5e2f793b59a 1664 /*@}*/
screamer 0:c5e2f793b59a 1665
screamer 0:c5e2f793b59a 1666 /*!
screamer 0:c5e2f793b59a 1667 * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
screamer 0:c5e2f793b59a 1668 *
screamer 0:c5e2f793b59a 1669 * Selects the value that is forced into the channel output when the
screamer 0:c5e2f793b59a 1670 * initialization occurs.
screamer 0:c5e2f793b59a 1671 *
screamer 0:c5e2f793b59a 1672 * Values:
screamer 0:c5e2f793b59a 1673 * - 0 - The initialization value is 0.
screamer 0:c5e2f793b59a 1674 * - 1 - The initialization value is 1.
screamer 0:c5e2f793b59a 1675 */
screamer 0:c5e2f793b59a 1676 /*@{*/
screamer 0:c5e2f793b59a 1677 #define BP_FTM_OUTINIT_CH3OI (3U) /*!< Bit position for FTM_OUTINIT_CH3OI. */
screamer 0:c5e2f793b59a 1678 #define BM_FTM_OUTINIT_CH3OI (0x00000008U) /*!< Bit mask for FTM_OUTINIT_CH3OI. */
screamer 0:c5e2f793b59a 1679 #define BS_FTM_OUTINIT_CH3OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH3OI. */
screamer 0:c5e2f793b59a 1680
screamer 0:c5e2f793b59a 1681 /*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
screamer 0:c5e2f793b59a 1682 #define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
screamer 0:c5e2f793b59a 1683
screamer 0:c5e2f793b59a 1684 /*! @brief Format value for bitfield FTM_OUTINIT_CH3OI. */
screamer 0:c5e2f793b59a 1685 #define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI)
screamer 0:c5e2f793b59a 1686
screamer 0:c5e2f793b59a 1687 /*! @brief Set the CH3OI field to a new value. */
screamer 0:c5e2f793b59a 1688 #define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
screamer 0:c5e2f793b59a 1689 /*@}*/
screamer 0:c5e2f793b59a 1690
screamer 0:c5e2f793b59a 1691 /*!
screamer 0:c5e2f793b59a 1692 * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
screamer 0:c5e2f793b59a 1693 *
screamer 0:c5e2f793b59a 1694 * Selects the value that is forced into the channel output when the
screamer 0:c5e2f793b59a 1695 * initialization occurs.
screamer 0:c5e2f793b59a 1696 *
screamer 0:c5e2f793b59a 1697 * Values:
screamer 0:c5e2f793b59a 1698 * - 0 - The initialization value is 0.
screamer 0:c5e2f793b59a 1699 * - 1 - The initialization value is 1.
screamer 0:c5e2f793b59a 1700 */
screamer 0:c5e2f793b59a 1701 /*@{*/
screamer 0:c5e2f793b59a 1702 #define BP_FTM_OUTINIT_CH4OI (4U) /*!< Bit position for FTM_OUTINIT_CH4OI. */
screamer 0:c5e2f793b59a 1703 #define BM_FTM_OUTINIT_CH4OI (0x00000010U) /*!< Bit mask for FTM_OUTINIT_CH4OI. */
screamer 0:c5e2f793b59a 1704 #define BS_FTM_OUTINIT_CH4OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH4OI. */
screamer 0:c5e2f793b59a 1705
screamer 0:c5e2f793b59a 1706 /*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
screamer 0:c5e2f793b59a 1707 #define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
screamer 0:c5e2f793b59a 1708
screamer 0:c5e2f793b59a 1709 /*! @brief Format value for bitfield FTM_OUTINIT_CH4OI. */
screamer 0:c5e2f793b59a 1710 #define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI)
screamer 0:c5e2f793b59a 1711
screamer 0:c5e2f793b59a 1712 /*! @brief Set the CH4OI field to a new value. */
screamer 0:c5e2f793b59a 1713 #define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
screamer 0:c5e2f793b59a 1714 /*@}*/
screamer 0:c5e2f793b59a 1715
screamer 0:c5e2f793b59a 1716 /*!
screamer 0:c5e2f793b59a 1717 * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
screamer 0:c5e2f793b59a 1718 *
screamer 0:c5e2f793b59a 1719 * Selects the value that is forced into the channel output when the
screamer 0:c5e2f793b59a 1720 * initialization occurs.
screamer 0:c5e2f793b59a 1721 *
screamer 0:c5e2f793b59a 1722 * Values:
screamer 0:c5e2f793b59a 1723 * - 0 - The initialization value is 0.
screamer 0:c5e2f793b59a 1724 * - 1 - The initialization value is 1.
screamer 0:c5e2f793b59a 1725 */
screamer 0:c5e2f793b59a 1726 /*@{*/
screamer 0:c5e2f793b59a 1727 #define BP_FTM_OUTINIT_CH5OI (5U) /*!< Bit position for FTM_OUTINIT_CH5OI. */
screamer 0:c5e2f793b59a 1728 #define BM_FTM_OUTINIT_CH5OI (0x00000020U) /*!< Bit mask for FTM_OUTINIT_CH5OI. */
screamer 0:c5e2f793b59a 1729 #define BS_FTM_OUTINIT_CH5OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH5OI. */
screamer 0:c5e2f793b59a 1730
screamer 0:c5e2f793b59a 1731 /*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
screamer 0:c5e2f793b59a 1732 #define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
screamer 0:c5e2f793b59a 1733
screamer 0:c5e2f793b59a 1734 /*! @brief Format value for bitfield FTM_OUTINIT_CH5OI. */
screamer 0:c5e2f793b59a 1735 #define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI)
screamer 0:c5e2f793b59a 1736
screamer 0:c5e2f793b59a 1737 /*! @brief Set the CH5OI field to a new value. */
screamer 0:c5e2f793b59a 1738 #define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
screamer 0:c5e2f793b59a 1739 /*@}*/
screamer 0:c5e2f793b59a 1740
screamer 0:c5e2f793b59a 1741 /*!
screamer 0:c5e2f793b59a 1742 * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
screamer 0:c5e2f793b59a 1743 *
screamer 0:c5e2f793b59a 1744 * Selects the value that is forced into the channel output when the
screamer 0:c5e2f793b59a 1745 * initialization occurs.
screamer 0:c5e2f793b59a 1746 *
screamer 0:c5e2f793b59a 1747 * Values:
screamer 0:c5e2f793b59a 1748 * - 0 - The initialization value is 0.
screamer 0:c5e2f793b59a 1749 * - 1 - The initialization value is 1.
screamer 0:c5e2f793b59a 1750 */
screamer 0:c5e2f793b59a 1751 /*@{*/
screamer 0:c5e2f793b59a 1752 #define BP_FTM_OUTINIT_CH6OI (6U) /*!< Bit position for FTM_OUTINIT_CH6OI. */
screamer 0:c5e2f793b59a 1753 #define BM_FTM_OUTINIT_CH6OI (0x00000040U) /*!< Bit mask for FTM_OUTINIT_CH6OI. */
screamer 0:c5e2f793b59a 1754 #define BS_FTM_OUTINIT_CH6OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH6OI. */
screamer 0:c5e2f793b59a 1755
screamer 0:c5e2f793b59a 1756 /*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
screamer 0:c5e2f793b59a 1757 #define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
screamer 0:c5e2f793b59a 1758
screamer 0:c5e2f793b59a 1759 /*! @brief Format value for bitfield FTM_OUTINIT_CH6OI. */
screamer 0:c5e2f793b59a 1760 #define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI)
screamer 0:c5e2f793b59a 1761
screamer 0:c5e2f793b59a 1762 /*! @brief Set the CH6OI field to a new value. */
screamer 0:c5e2f793b59a 1763 #define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
screamer 0:c5e2f793b59a 1764 /*@}*/
screamer 0:c5e2f793b59a 1765
screamer 0:c5e2f793b59a 1766 /*!
screamer 0:c5e2f793b59a 1767 * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
screamer 0:c5e2f793b59a 1768 *
screamer 0:c5e2f793b59a 1769 * Selects the value that is forced into the channel output when the
screamer 0:c5e2f793b59a 1770 * initialization occurs.
screamer 0:c5e2f793b59a 1771 *
screamer 0:c5e2f793b59a 1772 * Values:
screamer 0:c5e2f793b59a 1773 * - 0 - The initialization value is 0.
screamer 0:c5e2f793b59a 1774 * - 1 - The initialization value is 1.
screamer 0:c5e2f793b59a 1775 */
screamer 0:c5e2f793b59a 1776 /*@{*/
screamer 0:c5e2f793b59a 1777 #define BP_FTM_OUTINIT_CH7OI (7U) /*!< Bit position for FTM_OUTINIT_CH7OI. */
screamer 0:c5e2f793b59a 1778 #define BM_FTM_OUTINIT_CH7OI (0x00000080U) /*!< Bit mask for FTM_OUTINIT_CH7OI. */
screamer 0:c5e2f793b59a 1779 #define BS_FTM_OUTINIT_CH7OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH7OI. */
screamer 0:c5e2f793b59a 1780
screamer 0:c5e2f793b59a 1781 /*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
screamer 0:c5e2f793b59a 1782 #define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
screamer 0:c5e2f793b59a 1783
screamer 0:c5e2f793b59a 1784 /*! @brief Format value for bitfield FTM_OUTINIT_CH7OI. */
screamer 0:c5e2f793b59a 1785 #define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI)
screamer 0:c5e2f793b59a 1786
screamer 0:c5e2f793b59a 1787 /*! @brief Set the CH7OI field to a new value. */
screamer 0:c5e2f793b59a 1788 #define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
screamer 0:c5e2f793b59a 1789 /*@}*/
screamer 0:c5e2f793b59a 1790
screamer 0:c5e2f793b59a 1791 /*******************************************************************************
screamer 0:c5e2f793b59a 1792 * HW_FTM_OUTMASK - Output Mask
screamer 0:c5e2f793b59a 1793 ******************************************************************************/
screamer 0:c5e2f793b59a 1794
screamer 0:c5e2f793b59a 1795 /*!
screamer 0:c5e2f793b59a 1796 * @brief HW_FTM_OUTMASK - Output Mask (RW)
screamer 0:c5e2f793b59a 1797 *
screamer 0:c5e2f793b59a 1798 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 1799 *
screamer 0:c5e2f793b59a 1800 * This register provides a mask for each FTM channel. The mask of a channel
screamer 0:c5e2f793b59a 1801 * determines if its output responds, that is, it is masked or not, when a match
screamer 0:c5e2f793b59a 1802 * occurs. This feature is used for BLDC control where the PWM signal is presented
screamer 0:c5e2f793b59a 1803 * to an electric motor at specific times to provide electronic commutation. Any
screamer 0:c5e2f793b59a 1804 * write to the OUTMASK register, stores the value in its write buffer. The
screamer 0:c5e2f793b59a 1805 * register is updated with the value of its write buffer according to PWM
screamer 0:c5e2f793b59a 1806 * synchronization.
screamer 0:c5e2f793b59a 1807 */
screamer 0:c5e2f793b59a 1808 typedef union _hw_ftm_outmask
screamer 0:c5e2f793b59a 1809 {
screamer 0:c5e2f793b59a 1810 uint32_t U;
screamer 0:c5e2f793b59a 1811 struct _hw_ftm_outmask_bitfields
screamer 0:c5e2f793b59a 1812 {
screamer 0:c5e2f793b59a 1813 uint32_t CH0OM : 1; /*!< [0] Channel 0 Output Mask */
screamer 0:c5e2f793b59a 1814 uint32_t CH1OM : 1; /*!< [1] Channel 1 Output Mask */
screamer 0:c5e2f793b59a 1815 uint32_t CH2OM : 1; /*!< [2] Channel 2 Output Mask */
screamer 0:c5e2f793b59a 1816 uint32_t CH3OM : 1; /*!< [3] Channel 3 Output Mask */
screamer 0:c5e2f793b59a 1817 uint32_t CH4OM : 1; /*!< [4] Channel 4 Output Mask */
screamer 0:c5e2f793b59a 1818 uint32_t CH5OM : 1; /*!< [5] Channel 5 Output Mask */
screamer 0:c5e2f793b59a 1819 uint32_t CH6OM : 1; /*!< [6] Channel 6 Output Mask */
screamer 0:c5e2f793b59a 1820 uint32_t CH7OM : 1; /*!< [7] Channel 7 Output Mask */
screamer 0:c5e2f793b59a 1821 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 1822 } B;
screamer 0:c5e2f793b59a 1823 } hw_ftm_outmask_t;
screamer 0:c5e2f793b59a 1824
screamer 0:c5e2f793b59a 1825 /*!
screamer 0:c5e2f793b59a 1826 * @name Constants and macros for entire FTM_OUTMASK register
screamer 0:c5e2f793b59a 1827 */
screamer 0:c5e2f793b59a 1828 /*@{*/
screamer 0:c5e2f793b59a 1829 #define HW_FTM_OUTMASK_ADDR(x) ((x) + 0x60U)
screamer 0:c5e2f793b59a 1830
screamer 0:c5e2f793b59a 1831 #define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
screamer 0:c5e2f793b59a 1832 #define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
screamer 0:c5e2f793b59a 1833 #define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
screamer 0:c5e2f793b59a 1834 #define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v)))
screamer 0:c5e2f793b59a 1835 #define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1836 #define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1837 /*@}*/
screamer 0:c5e2f793b59a 1838
screamer 0:c5e2f793b59a 1839 /*
screamer 0:c5e2f793b59a 1840 * Constants & macros for individual FTM_OUTMASK bitfields
screamer 0:c5e2f793b59a 1841 */
screamer 0:c5e2f793b59a 1842
screamer 0:c5e2f793b59a 1843 /*!
screamer 0:c5e2f793b59a 1844 * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
screamer 0:c5e2f793b59a 1845 *
screamer 0:c5e2f793b59a 1846 * Defines if the channel output is masked or unmasked.
screamer 0:c5e2f793b59a 1847 *
screamer 0:c5e2f793b59a 1848 * Values:
screamer 0:c5e2f793b59a 1849 * - 0 - Channel output is not masked. It continues to operate normally.
screamer 0:c5e2f793b59a 1850 * - 1 - Channel output is masked. It is forced to its inactive state.
screamer 0:c5e2f793b59a 1851 */
screamer 0:c5e2f793b59a 1852 /*@{*/
screamer 0:c5e2f793b59a 1853 #define BP_FTM_OUTMASK_CH0OM (0U) /*!< Bit position for FTM_OUTMASK_CH0OM. */
screamer 0:c5e2f793b59a 1854 #define BM_FTM_OUTMASK_CH0OM (0x00000001U) /*!< Bit mask for FTM_OUTMASK_CH0OM. */
screamer 0:c5e2f793b59a 1855 #define BS_FTM_OUTMASK_CH0OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH0OM. */
screamer 0:c5e2f793b59a 1856
screamer 0:c5e2f793b59a 1857 /*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
screamer 0:c5e2f793b59a 1858 #define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
screamer 0:c5e2f793b59a 1859
screamer 0:c5e2f793b59a 1860 /*! @brief Format value for bitfield FTM_OUTMASK_CH0OM. */
screamer 0:c5e2f793b59a 1861 #define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM)
screamer 0:c5e2f793b59a 1862
screamer 0:c5e2f793b59a 1863 /*! @brief Set the CH0OM field to a new value. */
screamer 0:c5e2f793b59a 1864 #define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
screamer 0:c5e2f793b59a 1865 /*@}*/
screamer 0:c5e2f793b59a 1866
screamer 0:c5e2f793b59a 1867 /*!
screamer 0:c5e2f793b59a 1868 * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
screamer 0:c5e2f793b59a 1869 *
screamer 0:c5e2f793b59a 1870 * Defines if the channel output is masked or unmasked.
screamer 0:c5e2f793b59a 1871 *
screamer 0:c5e2f793b59a 1872 * Values:
screamer 0:c5e2f793b59a 1873 * - 0 - Channel output is not masked. It continues to operate normally.
screamer 0:c5e2f793b59a 1874 * - 1 - Channel output is masked. It is forced to its inactive state.
screamer 0:c5e2f793b59a 1875 */
screamer 0:c5e2f793b59a 1876 /*@{*/
screamer 0:c5e2f793b59a 1877 #define BP_FTM_OUTMASK_CH1OM (1U) /*!< Bit position for FTM_OUTMASK_CH1OM. */
screamer 0:c5e2f793b59a 1878 #define BM_FTM_OUTMASK_CH1OM (0x00000002U) /*!< Bit mask for FTM_OUTMASK_CH1OM. */
screamer 0:c5e2f793b59a 1879 #define BS_FTM_OUTMASK_CH1OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH1OM. */
screamer 0:c5e2f793b59a 1880
screamer 0:c5e2f793b59a 1881 /*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
screamer 0:c5e2f793b59a 1882 #define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
screamer 0:c5e2f793b59a 1883
screamer 0:c5e2f793b59a 1884 /*! @brief Format value for bitfield FTM_OUTMASK_CH1OM. */
screamer 0:c5e2f793b59a 1885 #define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM)
screamer 0:c5e2f793b59a 1886
screamer 0:c5e2f793b59a 1887 /*! @brief Set the CH1OM field to a new value. */
screamer 0:c5e2f793b59a 1888 #define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
screamer 0:c5e2f793b59a 1889 /*@}*/
screamer 0:c5e2f793b59a 1890
screamer 0:c5e2f793b59a 1891 /*!
screamer 0:c5e2f793b59a 1892 * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
screamer 0:c5e2f793b59a 1893 *
screamer 0:c5e2f793b59a 1894 * Defines if the channel output is masked or unmasked.
screamer 0:c5e2f793b59a 1895 *
screamer 0:c5e2f793b59a 1896 * Values:
screamer 0:c5e2f793b59a 1897 * - 0 - Channel output is not masked. It continues to operate normally.
screamer 0:c5e2f793b59a 1898 * - 1 - Channel output is masked. It is forced to its inactive state.
screamer 0:c5e2f793b59a 1899 */
screamer 0:c5e2f793b59a 1900 /*@{*/
screamer 0:c5e2f793b59a 1901 #define BP_FTM_OUTMASK_CH2OM (2U) /*!< Bit position for FTM_OUTMASK_CH2OM. */
screamer 0:c5e2f793b59a 1902 #define BM_FTM_OUTMASK_CH2OM (0x00000004U) /*!< Bit mask for FTM_OUTMASK_CH2OM. */
screamer 0:c5e2f793b59a 1903 #define BS_FTM_OUTMASK_CH2OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH2OM. */
screamer 0:c5e2f793b59a 1904
screamer 0:c5e2f793b59a 1905 /*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
screamer 0:c5e2f793b59a 1906 #define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
screamer 0:c5e2f793b59a 1907
screamer 0:c5e2f793b59a 1908 /*! @brief Format value for bitfield FTM_OUTMASK_CH2OM. */
screamer 0:c5e2f793b59a 1909 #define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM)
screamer 0:c5e2f793b59a 1910
screamer 0:c5e2f793b59a 1911 /*! @brief Set the CH2OM field to a new value. */
screamer 0:c5e2f793b59a 1912 #define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
screamer 0:c5e2f793b59a 1913 /*@}*/
screamer 0:c5e2f793b59a 1914
screamer 0:c5e2f793b59a 1915 /*!
screamer 0:c5e2f793b59a 1916 * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
screamer 0:c5e2f793b59a 1917 *
screamer 0:c5e2f793b59a 1918 * Defines if the channel output is masked or unmasked.
screamer 0:c5e2f793b59a 1919 *
screamer 0:c5e2f793b59a 1920 * Values:
screamer 0:c5e2f793b59a 1921 * - 0 - Channel output is not masked. It continues to operate normally.
screamer 0:c5e2f793b59a 1922 * - 1 - Channel output is masked. It is forced to its inactive state.
screamer 0:c5e2f793b59a 1923 */
screamer 0:c5e2f793b59a 1924 /*@{*/
screamer 0:c5e2f793b59a 1925 #define BP_FTM_OUTMASK_CH3OM (3U) /*!< Bit position for FTM_OUTMASK_CH3OM. */
screamer 0:c5e2f793b59a 1926 #define BM_FTM_OUTMASK_CH3OM (0x00000008U) /*!< Bit mask for FTM_OUTMASK_CH3OM. */
screamer 0:c5e2f793b59a 1927 #define BS_FTM_OUTMASK_CH3OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH3OM. */
screamer 0:c5e2f793b59a 1928
screamer 0:c5e2f793b59a 1929 /*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
screamer 0:c5e2f793b59a 1930 #define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
screamer 0:c5e2f793b59a 1931
screamer 0:c5e2f793b59a 1932 /*! @brief Format value for bitfield FTM_OUTMASK_CH3OM. */
screamer 0:c5e2f793b59a 1933 #define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM)
screamer 0:c5e2f793b59a 1934
screamer 0:c5e2f793b59a 1935 /*! @brief Set the CH3OM field to a new value. */
screamer 0:c5e2f793b59a 1936 #define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
screamer 0:c5e2f793b59a 1937 /*@}*/
screamer 0:c5e2f793b59a 1938
screamer 0:c5e2f793b59a 1939 /*!
screamer 0:c5e2f793b59a 1940 * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
screamer 0:c5e2f793b59a 1941 *
screamer 0:c5e2f793b59a 1942 * Defines if the channel output is masked or unmasked.
screamer 0:c5e2f793b59a 1943 *
screamer 0:c5e2f793b59a 1944 * Values:
screamer 0:c5e2f793b59a 1945 * - 0 - Channel output is not masked. It continues to operate normally.
screamer 0:c5e2f793b59a 1946 * - 1 - Channel output is masked. It is forced to its inactive state.
screamer 0:c5e2f793b59a 1947 */
screamer 0:c5e2f793b59a 1948 /*@{*/
screamer 0:c5e2f793b59a 1949 #define BP_FTM_OUTMASK_CH4OM (4U) /*!< Bit position for FTM_OUTMASK_CH4OM. */
screamer 0:c5e2f793b59a 1950 #define BM_FTM_OUTMASK_CH4OM (0x00000010U) /*!< Bit mask for FTM_OUTMASK_CH4OM. */
screamer 0:c5e2f793b59a 1951 #define BS_FTM_OUTMASK_CH4OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH4OM. */
screamer 0:c5e2f793b59a 1952
screamer 0:c5e2f793b59a 1953 /*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
screamer 0:c5e2f793b59a 1954 #define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
screamer 0:c5e2f793b59a 1955
screamer 0:c5e2f793b59a 1956 /*! @brief Format value for bitfield FTM_OUTMASK_CH4OM. */
screamer 0:c5e2f793b59a 1957 #define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM)
screamer 0:c5e2f793b59a 1958
screamer 0:c5e2f793b59a 1959 /*! @brief Set the CH4OM field to a new value. */
screamer 0:c5e2f793b59a 1960 #define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
screamer 0:c5e2f793b59a 1961 /*@}*/
screamer 0:c5e2f793b59a 1962
screamer 0:c5e2f793b59a 1963 /*!
screamer 0:c5e2f793b59a 1964 * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
screamer 0:c5e2f793b59a 1965 *
screamer 0:c5e2f793b59a 1966 * Defines if the channel output is masked or unmasked.
screamer 0:c5e2f793b59a 1967 *
screamer 0:c5e2f793b59a 1968 * Values:
screamer 0:c5e2f793b59a 1969 * - 0 - Channel output is not masked. It continues to operate normally.
screamer 0:c5e2f793b59a 1970 * - 1 - Channel output is masked. It is forced to its inactive state.
screamer 0:c5e2f793b59a 1971 */
screamer 0:c5e2f793b59a 1972 /*@{*/
screamer 0:c5e2f793b59a 1973 #define BP_FTM_OUTMASK_CH5OM (5U) /*!< Bit position for FTM_OUTMASK_CH5OM. */
screamer 0:c5e2f793b59a 1974 #define BM_FTM_OUTMASK_CH5OM (0x00000020U) /*!< Bit mask for FTM_OUTMASK_CH5OM. */
screamer 0:c5e2f793b59a 1975 #define BS_FTM_OUTMASK_CH5OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH5OM. */
screamer 0:c5e2f793b59a 1976
screamer 0:c5e2f793b59a 1977 /*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
screamer 0:c5e2f793b59a 1978 #define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
screamer 0:c5e2f793b59a 1979
screamer 0:c5e2f793b59a 1980 /*! @brief Format value for bitfield FTM_OUTMASK_CH5OM. */
screamer 0:c5e2f793b59a 1981 #define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM)
screamer 0:c5e2f793b59a 1982
screamer 0:c5e2f793b59a 1983 /*! @brief Set the CH5OM field to a new value. */
screamer 0:c5e2f793b59a 1984 #define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
screamer 0:c5e2f793b59a 1985 /*@}*/
screamer 0:c5e2f793b59a 1986
screamer 0:c5e2f793b59a 1987 /*!
screamer 0:c5e2f793b59a 1988 * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
screamer 0:c5e2f793b59a 1989 *
screamer 0:c5e2f793b59a 1990 * Defines if the channel output is masked or unmasked.
screamer 0:c5e2f793b59a 1991 *
screamer 0:c5e2f793b59a 1992 * Values:
screamer 0:c5e2f793b59a 1993 * - 0 - Channel output is not masked. It continues to operate normally.
screamer 0:c5e2f793b59a 1994 * - 1 - Channel output is masked. It is forced to its inactive state.
screamer 0:c5e2f793b59a 1995 */
screamer 0:c5e2f793b59a 1996 /*@{*/
screamer 0:c5e2f793b59a 1997 #define BP_FTM_OUTMASK_CH6OM (6U) /*!< Bit position for FTM_OUTMASK_CH6OM. */
screamer 0:c5e2f793b59a 1998 #define BM_FTM_OUTMASK_CH6OM (0x00000040U) /*!< Bit mask for FTM_OUTMASK_CH6OM. */
screamer 0:c5e2f793b59a 1999 #define BS_FTM_OUTMASK_CH6OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH6OM. */
screamer 0:c5e2f793b59a 2000
screamer 0:c5e2f793b59a 2001 /*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
screamer 0:c5e2f793b59a 2002 #define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
screamer 0:c5e2f793b59a 2003
screamer 0:c5e2f793b59a 2004 /*! @brief Format value for bitfield FTM_OUTMASK_CH6OM. */
screamer 0:c5e2f793b59a 2005 #define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM)
screamer 0:c5e2f793b59a 2006
screamer 0:c5e2f793b59a 2007 /*! @brief Set the CH6OM field to a new value. */
screamer 0:c5e2f793b59a 2008 #define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
screamer 0:c5e2f793b59a 2009 /*@}*/
screamer 0:c5e2f793b59a 2010
screamer 0:c5e2f793b59a 2011 /*!
screamer 0:c5e2f793b59a 2012 * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
screamer 0:c5e2f793b59a 2013 *
screamer 0:c5e2f793b59a 2014 * Defines if the channel output is masked or unmasked.
screamer 0:c5e2f793b59a 2015 *
screamer 0:c5e2f793b59a 2016 * Values:
screamer 0:c5e2f793b59a 2017 * - 0 - Channel output is not masked. It continues to operate normally.
screamer 0:c5e2f793b59a 2018 * - 1 - Channel output is masked. It is forced to its inactive state.
screamer 0:c5e2f793b59a 2019 */
screamer 0:c5e2f793b59a 2020 /*@{*/
screamer 0:c5e2f793b59a 2021 #define BP_FTM_OUTMASK_CH7OM (7U) /*!< Bit position for FTM_OUTMASK_CH7OM. */
screamer 0:c5e2f793b59a 2022 #define BM_FTM_OUTMASK_CH7OM (0x00000080U) /*!< Bit mask for FTM_OUTMASK_CH7OM. */
screamer 0:c5e2f793b59a 2023 #define BS_FTM_OUTMASK_CH7OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH7OM. */
screamer 0:c5e2f793b59a 2024
screamer 0:c5e2f793b59a 2025 /*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
screamer 0:c5e2f793b59a 2026 #define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
screamer 0:c5e2f793b59a 2027
screamer 0:c5e2f793b59a 2028 /*! @brief Format value for bitfield FTM_OUTMASK_CH7OM. */
screamer 0:c5e2f793b59a 2029 #define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM)
screamer 0:c5e2f793b59a 2030
screamer 0:c5e2f793b59a 2031 /*! @brief Set the CH7OM field to a new value. */
screamer 0:c5e2f793b59a 2032 #define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
screamer 0:c5e2f793b59a 2033 /*@}*/
screamer 0:c5e2f793b59a 2034
screamer 0:c5e2f793b59a 2035 /*******************************************************************************
screamer 0:c5e2f793b59a 2036 * HW_FTM_COMBINE - Function For Linked Channels
screamer 0:c5e2f793b59a 2037 ******************************************************************************/
screamer 0:c5e2f793b59a 2038
screamer 0:c5e2f793b59a 2039 /*!
screamer 0:c5e2f793b59a 2040 * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
screamer 0:c5e2f793b59a 2041 *
screamer 0:c5e2f793b59a 2042 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 2043 *
screamer 0:c5e2f793b59a 2044 * This register contains the control bits used to configure the fault control,
screamer 0:c5e2f793b59a 2045 * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
screamer 0:c5e2f793b59a 2046 * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
screamer 0:c5e2f793b59a 2047 * 4, and 6.
screamer 0:c5e2f793b59a 2048 */
screamer 0:c5e2f793b59a 2049 typedef union _hw_ftm_combine
screamer 0:c5e2f793b59a 2050 {
screamer 0:c5e2f793b59a 2051 uint32_t U;
screamer 0:c5e2f793b59a 2052 struct _hw_ftm_combine_bitfields
screamer 0:c5e2f793b59a 2053 {
screamer 0:c5e2f793b59a 2054 uint32_t COMBINE0 : 1; /*!< [0] Combine Channels For n = 0 */
screamer 0:c5e2f793b59a 2055 uint32_t COMP0 : 1; /*!< [1] Complement Of Channel (n) For n = 0 */
screamer 0:c5e2f793b59a 2056 uint32_t DECAPEN0 : 1; /*!< [2] Dual Edge Capture Mode Enable For n =
screamer 0:c5e2f793b59a 2057 * 0 */
screamer 0:c5e2f793b59a 2058 uint32_t DECAP0 : 1; /*!< [3] Dual Edge Capture Mode Captures For n =
screamer 0:c5e2f793b59a 2059 * 0 */
screamer 0:c5e2f793b59a 2060 uint32_t DTEN0 : 1; /*!< [4] Deadtime Enable For n = 0 */
screamer 0:c5e2f793b59a 2061 uint32_t SYNCEN0 : 1; /*!< [5] Synchronization Enable For n = 0 */
screamer 0:c5e2f793b59a 2062 uint32_t FAULTEN0 : 1; /*!< [6] Fault Control Enable For n = 0 */
screamer 0:c5e2f793b59a 2063 uint32_t RESERVED0 : 1; /*!< [7] */
screamer 0:c5e2f793b59a 2064 uint32_t COMBINE1 : 1; /*!< [8] Combine Channels For n = 2 */
screamer 0:c5e2f793b59a 2065 uint32_t COMP1 : 1; /*!< [9] Complement Of Channel (n) For n = 2 */
screamer 0:c5e2f793b59a 2066 uint32_t DECAPEN1 : 1; /*!< [10] Dual Edge Capture Mode Enable For n
screamer 0:c5e2f793b59a 2067 * = 2 */
screamer 0:c5e2f793b59a 2068 uint32_t DECAP1 : 1; /*!< [11] Dual Edge Capture Mode Captures For n
screamer 0:c5e2f793b59a 2069 * = 2 */
screamer 0:c5e2f793b59a 2070 uint32_t DTEN1 : 1; /*!< [12] Deadtime Enable For n = 2 */
screamer 0:c5e2f793b59a 2071 uint32_t SYNCEN1 : 1; /*!< [13] Synchronization Enable For n = 2 */
screamer 0:c5e2f793b59a 2072 uint32_t FAULTEN1 : 1; /*!< [14] Fault Control Enable For n = 2 */
screamer 0:c5e2f793b59a 2073 uint32_t RESERVED1 : 1; /*!< [15] */
screamer 0:c5e2f793b59a 2074 uint32_t COMBINE2 : 1; /*!< [16] Combine Channels For n = 4 */
screamer 0:c5e2f793b59a 2075 uint32_t COMP2 : 1; /*!< [17] Complement Of Channel (n) For n = 4 */
screamer 0:c5e2f793b59a 2076 uint32_t DECAPEN2 : 1; /*!< [18] Dual Edge Capture Mode Enable For n
screamer 0:c5e2f793b59a 2077 * = 4 */
screamer 0:c5e2f793b59a 2078 uint32_t DECAP2 : 1; /*!< [19] Dual Edge Capture Mode Captures For n
screamer 0:c5e2f793b59a 2079 * = 4 */
screamer 0:c5e2f793b59a 2080 uint32_t DTEN2 : 1; /*!< [20] Deadtime Enable For n = 4 */
screamer 0:c5e2f793b59a 2081 uint32_t SYNCEN2 : 1; /*!< [21] Synchronization Enable For n = 4 */
screamer 0:c5e2f793b59a 2082 uint32_t FAULTEN2 : 1; /*!< [22] Fault Control Enable For n = 4 */
screamer 0:c5e2f793b59a 2083 uint32_t RESERVED2 : 1; /*!< [23] */
screamer 0:c5e2f793b59a 2084 uint32_t COMBINE3 : 1; /*!< [24] Combine Channels For n = 6 */
screamer 0:c5e2f793b59a 2085 uint32_t COMP3 : 1; /*!< [25] Complement Of Channel (n) for n = 6 */
screamer 0:c5e2f793b59a 2086 uint32_t DECAPEN3 : 1; /*!< [26] Dual Edge Capture Mode Enable For n
screamer 0:c5e2f793b59a 2087 * = 6 */
screamer 0:c5e2f793b59a 2088 uint32_t DECAP3 : 1; /*!< [27] Dual Edge Capture Mode Captures For n
screamer 0:c5e2f793b59a 2089 * = 6 */
screamer 0:c5e2f793b59a 2090 uint32_t DTEN3 : 1; /*!< [28] Deadtime Enable For n = 6 */
screamer 0:c5e2f793b59a 2091 uint32_t SYNCEN3 : 1; /*!< [29] Synchronization Enable For n = 6 */
screamer 0:c5e2f793b59a 2092 uint32_t FAULTEN3 : 1; /*!< [30] Fault Control Enable For n = 6 */
screamer 0:c5e2f793b59a 2093 uint32_t RESERVED3 : 1; /*!< [31] */
screamer 0:c5e2f793b59a 2094 } B;
screamer 0:c5e2f793b59a 2095 } hw_ftm_combine_t;
screamer 0:c5e2f793b59a 2096
screamer 0:c5e2f793b59a 2097 /*!
screamer 0:c5e2f793b59a 2098 * @name Constants and macros for entire FTM_COMBINE register
screamer 0:c5e2f793b59a 2099 */
screamer 0:c5e2f793b59a 2100 /*@{*/
screamer 0:c5e2f793b59a 2101 #define HW_FTM_COMBINE_ADDR(x) ((x) + 0x64U)
screamer 0:c5e2f793b59a 2102
screamer 0:c5e2f793b59a 2103 #define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
screamer 0:c5e2f793b59a 2104 #define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
screamer 0:c5e2f793b59a 2105 #define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
screamer 0:c5e2f793b59a 2106 #define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v)))
screamer 0:c5e2f793b59a 2107 #define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 2108 #define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 2109 /*@}*/
screamer 0:c5e2f793b59a 2110
screamer 0:c5e2f793b59a 2111 /*
screamer 0:c5e2f793b59a 2112 * Constants & macros for individual FTM_COMBINE bitfields
screamer 0:c5e2f793b59a 2113 */
screamer 0:c5e2f793b59a 2114
screamer 0:c5e2f793b59a 2115 /*!
screamer 0:c5e2f793b59a 2116 * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
screamer 0:c5e2f793b59a 2117 *
screamer 0:c5e2f793b59a 2118 * Enables the combine feature for channels (n) and (n+1). This field is write
screamer 0:c5e2f793b59a 2119 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2120 *
screamer 0:c5e2f793b59a 2121 * Values:
screamer 0:c5e2f793b59a 2122 * - 0 - Channels (n) and (n+1) are independent.
screamer 0:c5e2f793b59a 2123 * - 1 - Channels (n) and (n+1) are combined.
screamer 0:c5e2f793b59a 2124 */
screamer 0:c5e2f793b59a 2125 /*@{*/
screamer 0:c5e2f793b59a 2126 #define BP_FTM_COMBINE_COMBINE0 (0U) /*!< Bit position for FTM_COMBINE_COMBINE0. */
screamer 0:c5e2f793b59a 2127 #define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /*!< Bit mask for FTM_COMBINE_COMBINE0. */
screamer 0:c5e2f793b59a 2128 #define BS_FTM_COMBINE_COMBINE0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE0. */
screamer 0:c5e2f793b59a 2129
screamer 0:c5e2f793b59a 2130 /*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
screamer 0:c5e2f793b59a 2131 #define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
screamer 0:c5e2f793b59a 2132
screamer 0:c5e2f793b59a 2133 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE0. */
screamer 0:c5e2f793b59a 2134 #define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0)
screamer 0:c5e2f793b59a 2135
screamer 0:c5e2f793b59a 2136 /*! @brief Set the COMBINE0 field to a new value. */
screamer 0:c5e2f793b59a 2137 #define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
screamer 0:c5e2f793b59a 2138 /*@}*/
screamer 0:c5e2f793b59a 2139
screamer 0:c5e2f793b59a 2140 /*!
screamer 0:c5e2f793b59a 2141 * @name Register FTM_COMBINE, field COMP0[1] (RW)
screamer 0:c5e2f793b59a 2142 *
screamer 0:c5e2f793b59a 2143 * Enables Complementary mode for the combined channels. In Complementary mode
screamer 0:c5e2f793b59a 2144 * the channel (n+1) output is the inverse of the channel (n) output. This field
screamer 0:c5e2f793b59a 2145 * is write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2146 *
screamer 0:c5e2f793b59a 2147 * Values:
screamer 0:c5e2f793b59a 2148 * - 0 - The channel (n+1) output is the same as the channel (n) output.
screamer 0:c5e2f793b59a 2149 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
screamer 0:c5e2f793b59a 2150 */
screamer 0:c5e2f793b59a 2151 /*@{*/
screamer 0:c5e2f793b59a 2152 #define BP_FTM_COMBINE_COMP0 (1U) /*!< Bit position for FTM_COMBINE_COMP0. */
screamer 0:c5e2f793b59a 2153 #define BM_FTM_COMBINE_COMP0 (0x00000002U) /*!< Bit mask for FTM_COMBINE_COMP0. */
screamer 0:c5e2f793b59a 2154 #define BS_FTM_COMBINE_COMP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP0. */
screamer 0:c5e2f793b59a 2155
screamer 0:c5e2f793b59a 2156 /*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
screamer 0:c5e2f793b59a 2157 #define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
screamer 0:c5e2f793b59a 2158
screamer 0:c5e2f793b59a 2159 /*! @brief Format value for bitfield FTM_COMBINE_COMP0. */
screamer 0:c5e2f793b59a 2160 #define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0)
screamer 0:c5e2f793b59a 2161
screamer 0:c5e2f793b59a 2162 /*! @brief Set the COMP0 field to a new value. */
screamer 0:c5e2f793b59a 2163 #define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
screamer 0:c5e2f793b59a 2164 /*@}*/
screamer 0:c5e2f793b59a 2165
screamer 0:c5e2f793b59a 2166 /*!
screamer 0:c5e2f793b59a 2167 * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
screamer 0:c5e2f793b59a 2168 *
screamer 0:c5e2f793b59a 2169 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
screamer 0:c5e2f793b59a 2170 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
screamer 0:c5e2f793b59a 2171 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
screamer 0:c5e2f793b59a 2172 * when FTMEN = 1. This field is write protected. It can be written only when
screamer 0:c5e2f793b59a 2173 * MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2174 *
screamer 0:c5e2f793b59a 2175 * Values:
screamer 0:c5e2f793b59a 2176 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2177 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2178 */
screamer 0:c5e2f793b59a 2179 /*@{*/
screamer 0:c5e2f793b59a 2180 #define BP_FTM_COMBINE_DECAPEN0 (2U) /*!< Bit position for FTM_COMBINE_DECAPEN0. */
screamer 0:c5e2f793b59a 2181 #define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /*!< Bit mask for FTM_COMBINE_DECAPEN0. */
screamer 0:c5e2f793b59a 2182 #define BS_FTM_COMBINE_DECAPEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN0. */
screamer 0:c5e2f793b59a 2183
screamer 0:c5e2f793b59a 2184 /*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
screamer 0:c5e2f793b59a 2185 #define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
screamer 0:c5e2f793b59a 2186
screamer 0:c5e2f793b59a 2187 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. */
screamer 0:c5e2f793b59a 2188 #define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0)
screamer 0:c5e2f793b59a 2189
screamer 0:c5e2f793b59a 2190 /*! @brief Set the DECAPEN0 field to a new value. */
screamer 0:c5e2f793b59a 2191 #define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
screamer 0:c5e2f793b59a 2192 /*@}*/
screamer 0:c5e2f793b59a 2193
screamer 0:c5e2f793b59a 2194 /*!
screamer 0:c5e2f793b59a 2195 * @name Register FTM_COMBINE, field DECAP0[3] (RW)
screamer 0:c5e2f793b59a 2196 *
screamer 0:c5e2f793b59a 2197 * Enables the capture of the FTM counter value according to the channel (n)
screamer 0:c5e2f793b59a 2198 * input event and the configuration of the dual edge capture bits. This field
screamer 0:c5e2f793b59a 2199 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
screamer 0:c5e2f793b59a 2200 * hardware if dual edge capture - one-shot mode is selected and when the capture
screamer 0:c5e2f793b59a 2201 * of channel (n+1) event is made.
screamer 0:c5e2f793b59a 2202 *
screamer 0:c5e2f793b59a 2203 * Values:
screamer 0:c5e2f793b59a 2204 * - 0 - The dual edge captures are inactive.
screamer 0:c5e2f793b59a 2205 * - 1 - The dual edge captures are active.
screamer 0:c5e2f793b59a 2206 */
screamer 0:c5e2f793b59a 2207 /*@{*/
screamer 0:c5e2f793b59a 2208 #define BP_FTM_COMBINE_DECAP0 (3U) /*!< Bit position for FTM_COMBINE_DECAP0. */
screamer 0:c5e2f793b59a 2209 #define BM_FTM_COMBINE_DECAP0 (0x00000008U) /*!< Bit mask for FTM_COMBINE_DECAP0. */
screamer 0:c5e2f793b59a 2210 #define BS_FTM_COMBINE_DECAP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP0. */
screamer 0:c5e2f793b59a 2211
screamer 0:c5e2f793b59a 2212 /*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
screamer 0:c5e2f793b59a 2213 #define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
screamer 0:c5e2f793b59a 2214
screamer 0:c5e2f793b59a 2215 /*! @brief Format value for bitfield FTM_COMBINE_DECAP0. */
screamer 0:c5e2f793b59a 2216 #define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0)
screamer 0:c5e2f793b59a 2217
screamer 0:c5e2f793b59a 2218 /*! @brief Set the DECAP0 field to a new value. */
screamer 0:c5e2f793b59a 2219 #define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
screamer 0:c5e2f793b59a 2220 /*@}*/
screamer 0:c5e2f793b59a 2221
screamer 0:c5e2f793b59a 2222 /*!
screamer 0:c5e2f793b59a 2223 * @name Register FTM_COMBINE, field DTEN0[4] (RW)
screamer 0:c5e2f793b59a 2224 *
screamer 0:c5e2f793b59a 2225 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
screamer 0:c5e2f793b59a 2226 * write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2227 *
screamer 0:c5e2f793b59a 2228 * Values:
screamer 0:c5e2f793b59a 2229 * - 0 - The deadtime insertion in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2230 * - 1 - The deadtime insertion in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2231 */
screamer 0:c5e2f793b59a 2232 /*@{*/
screamer 0:c5e2f793b59a 2233 #define BP_FTM_COMBINE_DTEN0 (4U) /*!< Bit position for FTM_COMBINE_DTEN0. */
screamer 0:c5e2f793b59a 2234 #define BM_FTM_COMBINE_DTEN0 (0x00000010U) /*!< Bit mask for FTM_COMBINE_DTEN0. */
screamer 0:c5e2f793b59a 2235 #define BS_FTM_COMBINE_DTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN0. */
screamer 0:c5e2f793b59a 2236
screamer 0:c5e2f793b59a 2237 /*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
screamer 0:c5e2f793b59a 2238 #define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
screamer 0:c5e2f793b59a 2239
screamer 0:c5e2f793b59a 2240 /*! @brief Format value for bitfield FTM_COMBINE_DTEN0. */
screamer 0:c5e2f793b59a 2241 #define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0)
screamer 0:c5e2f793b59a 2242
screamer 0:c5e2f793b59a 2243 /*! @brief Set the DTEN0 field to a new value. */
screamer 0:c5e2f793b59a 2244 #define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
screamer 0:c5e2f793b59a 2245 /*@}*/
screamer 0:c5e2f793b59a 2246
screamer 0:c5e2f793b59a 2247 /*!
screamer 0:c5e2f793b59a 2248 * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
screamer 0:c5e2f793b59a 2249 *
screamer 0:c5e2f793b59a 2250 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
screamer 0:c5e2f793b59a 2251 *
screamer 0:c5e2f793b59a 2252 * Values:
screamer 0:c5e2f793b59a 2253 * - 0 - The PWM synchronization in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2254 * - 1 - The PWM synchronization in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2255 */
screamer 0:c5e2f793b59a 2256 /*@{*/
screamer 0:c5e2f793b59a 2257 #define BP_FTM_COMBINE_SYNCEN0 (5U) /*!< Bit position for FTM_COMBINE_SYNCEN0. */
screamer 0:c5e2f793b59a 2258 #define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /*!< Bit mask for FTM_COMBINE_SYNCEN0. */
screamer 0:c5e2f793b59a 2259 #define BS_FTM_COMBINE_SYNCEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN0. */
screamer 0:c5e2f793b59a 2260
screamer 0:c5e2f793b59a 2261 /*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
screamer 0:c5e2f793b59a 2262 #define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
screamer 0:c5e2f793b59a 2263
screamer 0:c5e2f793b59a 2264 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. */
screamer 0:c5e2f793b59a 2265 #define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0)
screamer 0:c5e2f793b59a 2266
screamer 0:c5e2f793b59a 2267 /*! @brief Set the SYNCEN0 field to a new value. */
screamer 0:c5e2f793b59a 2268 #define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
screamer 0:c5e2f793b59a 2269 /*@}*/
screamer 0:c5e2f793b59a 2270
screamer 0:c5e2f793b59a 2271 /*!
screamer 0:c5e2f793b59a 2272 * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
screamer 0:c5e2f793b59a 2273 *
screamer 0:c5e2f793b59a 2274 * Enables the fault control in channels (n) and (n+1). This field is write
screamer 0:c5e2f793b59a 2275 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2276 *
screamer 0:c5e2f793b59a 2277 * Values:
screamer 0:c5e2f793b59a 2278 * - 0 - The fault control in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2279 * - 1 - The fault control in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2280 */
screamer 0:c5e2f793b59a 2281 /*@{*/
screamer 0:c5e2f793b59a 2282 #define BP_FTM_COMBINE_FAULTEN0 (6U) /*!< Bit position for FTM_COMBINE_FAULTEN0. */
screamer 0:c5e2f793b59a 2283 #define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /*!< Bit mask for FTM_COMBINE_FAULTEN0. */
screamer 0:c5e2f793b59a 2284 #define BS_FTM_COMBINE_FAULTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN0. */
screamer 0:c5e2f793b59a 2285
screamer 0:c5e2f793b59a 2286 /*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
screamer 0:c5e2f793b59a 2287 #define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
screamer 0:c5e2f793b59a 2288
screamer 0:c5e2f793b59a 2289 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. */
screamer 0:c5e2f793b59a 2290 #define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0)
screamer 0:c5e2f793b59a 2291
screamer 0:c5e2f793b59a 2292 /*! @brief Set the FAULTEN0 field to a new value. */
screamer 0:c5e2f793b59a 2293 #define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
screamer 0:c5e2f793b59a 2294 /*@}*/
screamer 0:c5e2f793b59a 2295
screamer 0:c5e2f793b59a 2296 /*!
screamer 0:c5e2f793b59a 2297 * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
screamer 0:c5e2f793b59a 2298 *
screamer 0:c5e2f793b59a 2299 * Enables the combine feature for channels (n) and (n+1). This field is write
screamer 0:c5e2f793b59a 2300 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2301 *
screamer 0:c5e2f793b59a 2302 * Values:
screamer 0:c5e2f793b59a 2303 * - 0 - Channels (n) and (n+1) are independent.
screamer 0:c5e2f793b59a 2304 * - 1 - Channels (n) and (n+1) are combined.
screamer 0:c5e2f793b59a 2305 */
screamer 0:c5e2f793b59a 2306 /*@{*/
screamer 0:c5e2f793b59a 2307 #define BP_FTM_COMBINE_COMBINE1 (8U) /*!< Bit position for FTM_COMBINE_COMBINE1. */
screamer 0:c5e2f793b59a 2308 #define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /*!< Bit mask for FTM_COMBINE_COMBINE1. */
screamer 0:c5e2f793b59a 2309 #define BS_FTM_COMBINE_COMBINE1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE1. */
screamer 0:c5e2f793b59a 2310
screamer 0:c5e2f793b59a 2311 /*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
screamer 0:c5e2f793b59a 2312 #define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
screamer 0:c5e2f793b59a 2313
screamer 0:c5e2f793b59a 2314 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE1. */
screamer 0:c5e2f793b59a 2315 #define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1)
screamer 0:c5e2f793b59a 2316
screamer 0:c5e2f793b59a 2317 /*! @brief Set the COMBINE1 field to a new value. */
screamer 0:c5e2f793b59a 2318 #define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
screamer 0:c5e2f793b59a 2319 /*@}*/
screamer 0:c5e2f793b59a 2320
screamer 0:c5e2f793b59a 2321 /*!
screamer 0:c5e2f793b59a 2322 * @name Register FTM_COMBINE, field COMP1[9] (RW)
screamer 0:c5e2f793b59a 2323 *
screamer 0:c5e2f793b59a 2324 * Enables Complementary mode for the combined channels. In Complementary mode
screamer 0:c5e2f793b59a 2325 * the channel (n+1) output is the inverse of the channel (n) output. This field
screamer 0:c5e2f793b59a 2326 * is write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2327 *
screamer 0:c5e2f793b59a 2328 * Values:
screamer 0:c5e2f793b59a 2329 * - 0 - The channel (n+1) output is the same as the channel (n) output.
screamer 0:c5e2f793b59a 2330 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
screamer 0:c5e2f793b59a 2331 */
screamer 0:c5e2f793b59a 2332 /*@{*/
screamer 0:c5e2f793b59a 2333 #define BP_FTM_COMBINE_COMP1 (9U) /*!< Bit position for FTM_COMBINE_COMP1. */
screamer 0:c5e2f793b59a 2334 #define BM_FTM_COMBINE_COMP1 (0x00000200U) /*!< Bit mask for FTM_COMBINE_COMP1. */
screamer 0:c5e2f793b59a 2335 #define BS_FTM_COMBINE_COMP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP1. */
screamer 0:c5e2f793b59a 2336
screamer 0:c5e2f793b59a 2337 /*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
screamer 0:c5e2f793b59a 2338 #define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
screamer 0:c5e2f793b59a 2339
screamer 0:c5e2f793b59a 2340 /*! @brief Format value for bitfield FTM_COMBINE_COMP1. */
screamer 0:c5e2f793b59a 2341 #define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1)
screamer 0:c5e2f793b59a 2342
screamer 0:c5e2f793b59a 2343 /*! @brief Set the COMP1 field to a new value. */
screamer 0:c5e2f793b59a 2344 #define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
screamer 0:c5e2f793b59a 2345 /*@}*/
screamer 0:c5e2f793b59a 2346
screamer 0:c5e2f793b59a 2347 /*!
screamer 0:c5e2f793b59a 2348 * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
screamer 0:c5e2f793b59a 2349 *
screamer 0:c5e2f793b59a 2350 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
screamer 0:c5e2f793b59a 2351 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
screamer 0:c5e2f793b59a 2352 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
screamer 0:c5e2f793b59a 2353 * when FTMEN = 1. This field is write protected. It can be written only when
screamer 0:c5e2f793b59a 2354 * MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2355 *
screamer 0:c5e2f793b59a 2356 * Values:
screamer 0:c5e2f793b59a 2357 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2358 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2359 */
screamer 0:c5e2f793b59a 2360 /*@{*/
screamer 0:c5e2f793b59a 2361 #define BP_FTM_COMBINE_DECAPEN1 (10U) /*!< Bit position for FTM_COMBINE_DECAPEN1. */
screamer 0:c5e2f793b59a 2362 #define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /*!< Bit mask for FTM_COMBINE_DECAPEN1. */
screamer 0:c5e2f793b59a 2363 #define BS_FTM_COMBINE_DECAPEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN1. */
screamer 0:c5e2f793b59a 2364
screamer 0:c5e2f793b59a 2365 /*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
screamer 0:c5e2f793b59a 2366 #define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
screamer 0:c5e2f793b59a 2367
screamer 0:c5e2f793b59a 2368 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. */
screamer 0:c5e2f793b59a 2369 #define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1)
screamer 0:c5e2f793b59a 2370
screamer 0:c5e2f793b59a 2371 /*! @brief Set the DECAPEN1 field to a new value. */
screamer 0:c5e2f793b59a 2372 #define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
screamer 0:c5e2f793b59a 2373 /*@}*/
screamer 0:c5e2f793b59a 2374
screamer 0:c5e2f793b59a 2375 /*!
screamer 0:c5e2f793b59a 2376 * @name Register FTM_COMBINE, field DECAP1[11] (RW)
screamer 0:c5e2f793b59a 2377 *
screamer 0:c5e2f793b59a 2378 * Enables the capture of the FTM counter value according to the channel (n)
screamer 0:c5e2f793b59a 2379 * input event and the configuration of the dual edge capture bits. This field
screamer 0:c5e2f793b59a 2380 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
screamer 0:c5e2f793b59a 2381 * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
screamer 0:c5e2f793b59a 2382 * of channel (n+1) event is made.
screamer 0:c5e2f793b59a 2383 *
screamer 0:c5e2f793b59a 2384 * Values:
screamer 0:c5e2f793b59a 2385 * - 0 - The dual edge captures are inactive.
screamer 0:c5e2f793b59a 2386 * - 1 - The dual edge captures are active.
screamer 0:c5e2f793b59a 2387 */
screamer 0:c5e2f793b59a 2388 /*@{*/
screamer 0:c5e2f793b59a 2389 #define BP_FTM_COMBINE_DECAP1 (11U) /*!< Bit position for FTM_COMBINE_DECAP1. */
screamer 0:c5e2f793b59a 2390 #define BM_FTM_COMBINE_DECAP1 (0x00000800U) /*!< Bit mask for FTM_COMBINE_DECAP1. */
screamer 0:c5e2f793b59a 2391 #define BS_FTM_COMBINE_DECAP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP1. */
screamer 0:c5e2f793b59a 2392
screamer 0:c5e2f793b59a 2393 /*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
screamer 0:c5e2f793b59a 2394 #define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
screamer 0:c5e2f793b59a 2395
screamer 0:c5e2f793b59a 2396 /*! @brief Format value for bitfield FTM_COMBINE_DECAP1. */
screamer 0:c5e2f793b59a 2397 #define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1)
screamer 0:c5e2f793b59a 2398
screamer 0:c5e2f793b59a 2399 /*! @brief Set the DECAP1 field to a new value. */
screamer 0:c5e2f793b59a 2400 #define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
screamer 0:c5e2f793b59a 2401 /*@}*/
screamer 0:c5e2f793b59a 2402
screamer 0:c5e2f793b59a 2403 /*!
screamer 0:c5e2f793b59a 2404 * @name Register FTM_COMBINE, field DTEN1[12] (RW)
screamer 0:c5e2f793b59a 2405 *
screamer 0:c5e2f793b59a 2406 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
screamer 0:c5e2f793b59a 2407 * write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2408 *
screamer 0:c5e2f793b59a 2409 * Values:
screamer 0:c5e2f793b59a 2410 * - 0 - The deadtime insertion in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2411 * - 1 - The deadtime insertion in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2412 */
screamer 0:c5e2f793b59a 2413 /*@{*/
screamer 0:c5e2f793b59a 2414 #define BP_FTM_COMBINE_DTEN1 (12U) /*!< Bit position for FTM_COMBINE_DTEN1. */
screamer 0:c5e2f793b59a 2415 #define BM_FTM_COMBINE_DTEN1 (0x00001000U) /*!< Bit mask for FTM_COMBINE_DTEN1. */
screamer 0:c5e2f793b59a 2416 #define BS_FTM_COMBINE_DTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN1. */
screamer 0:c5e2f793b59a 2417
screamer 0:c5e2f793b59a 2418 /*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
screamer 0:c5e2f793b59a 2419 #define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
screamer 0:c5e2f793b59a 2420
screamer 0:c5e2f793b59a 2421 /*! @brief Format value for bitfield FTM_COMBINE_DTEN1. */
screamer 0:c5e2f793b59a 2422 #define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1)
screamer 0:c5e2f793b59a 2423
screamer 0:c5e2f793b59a 2424 /*! @brief Set the DTEN1 field to a new value. */
screamer 0:c5e2f793b59a 2425 #define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
screamer 0:c5e2f793b59a 2426 /*@}*/
screamer 0:c5e2f793b59a 2427
screamer 0:c5e2f793b59a 2428 /*!
screamer 0:c5e2f793b59a 2429 * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
screamer 0:c5e2f793b59a 2430 *
screamer 0:c5e2f793b59a 2431 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
screamer 0:c5e2f793b59a 2432 *
screamer 0:c5e2f793b59a 2433 * Values:
screamer 0:c5e2f793b59a 2434 * - 0 - The PWM synchronization in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2435 * - 1 - The PWM synchronization in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2436 */
screamer 0:c5e2f793b59a 2437 /*@{*/
screamer 0:c5e2f793b59a 2438 #define BP_FTM_COMBINE_SYNCEN1 (13U) /*!< Bit position for FTM_COMBINE_SYNCEN1. */
screamer 0:c5e2f793b59a 2439 #define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /*!< Bit mask for FTM_COMBINE_SYNCEN1. */
screamer 0:c5e2f793b59a 2440 #define BS_FTM_COMBINE_SYNCEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN1. */
screamer 0:c5e2f793b59a 2441
screamer 0:c5e2f793b59a 2442 /*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
screamer 0:c5e2f793b59a 2443 #define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
screamer 0:c5e2f793b59a 2444
screamer 0:c5e2f793b59a 2445 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. */
screamer 0:c5e2f793b59a 2446 #define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1)
screamer 0:c5e2f793b59a 2447
screamer 0:c5e2f793b59a 2448 /*! @brief Set the SYNCEN1 field to a new value. */
screamer 0:c5e2f793b59a 2449 #define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
screamer 0:c5e2f793b59a 2450 /*@}*/
screamer 0:c5e2f793b59a 2451
screamer 0:c5e2f793b59a 2452 /*!
screamer 0:c5e2f793b59a 2453 * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
screamer 0:c5e2f793b59a 2454 *
screamer 0:c5e2f793b59a 2455 * Enables the fault control in channels (n) and (n+1). This field is write
screamer 0:c5e2f793b59a 2456 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2457 *
screamer 0:c5e2f793b59a 2458 * Values:
screamer 0:c5e2f793b59a 2459 * - 0 - The fault control in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2460 * - 1 - The fault control in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2461 */
screamer 0:c5e2f793b59a 2462 /*@{*/
screamer 0:c5e2f793b59a 2463 #define BP_FTM_COMBINE_FAULTEN1 (14U) /*!< Bit position for FTM_COMBINE_FAULTEN1. */
screamer 0:c5e2f793b59a 2464 #define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /*!< Bit mask for FTM_COMBINE_FAULTEN1. */
screamer 0:c5e2f793b59a 2465 #define BS_FTM_COMBINE_FAULTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN1. */
screamer 0:c5e2f793b59a 2466
screamer 0:c5e2f793b59a 2467 /*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
screamer 0:c5e2f793b59a 2468 #define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
screamer 0:c5e2f793b59a 2469
screamer 0:c5e2f793b59a 2470 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. */
screamer 0:c5e2f793b59a 2471 #define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1)
screamer 0:c5e2f793b59a 2472
screamer 0:c5e2f793b59a 2473 /*! @brief Set the FAULTEN1 field to a new value. */
screamer 0:c5e2f793b59a 2474 #define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
screamer 0:c5e2f793b59a 2475 /*@}*/
screamer 0:c5e2f793b59a 2476
screamer 0:c5e2f793b59a 2477 /*!
screamer 0:c5e2f793b59a 2478 * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
screamer 0:c5e2f793b59a 2479 *
screamer 0:c5e2f793b59a 2480 * Enables the combine feature for channels (n) and (n+1). This field is write
screamer 0:c5e2f793b59a 2481 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2482 *
screamer 0:c5e2f793b59a 2483 * Values:
screamer 0:c5e2f793b59a 2484 * - 0 - Channels (n) and (n+1) are independent.
screamer 0:c5e2f793b59a 2485 * - 1 - Channels (n) and (n+1) are combined.
screamer 0:c5e2f793b59a 2486 */
screamer 0:c5e2f793b59a 2487 /*@{*/
screamer 0:c5e2f793b59a 2488 #define BP_FTM_COMBINE_COMBINE2 (16U) /*!< Bit position for FTM_COMBINE_COMBINE2. */
screamer 0:c5e2f793b59a 2489 #define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /*!< Bit mask for FTM_COMBINE_COMBINE2. */
screamer 0:c5e2f793b59a 2490 #define BS_FTM_COMBINE_COMBINE2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE2. */
screamer 0:c5e2f793b59a 2491
screamer 0:c5e2f793b59a 2492 /*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
screamer 0:c5e2f793b59a 2493 #define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
screamer 0:c5e2f793b59a 2494
screamer 0:c5e2f793b59a 2495 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE2. */
screamer 0:c5e2f793b59a 2496 #define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2)
screamer 0:c5e2f793b59a 2497
screamer 0:c5e2f793b59a 2498 /*! @brief Set the COMBINE2 field to a new value. */
screamer 0:c5e2f793b59a 2499 #define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
screamer 0:c5e2f793b59a 2500 /*@}*/
screamer 0:c5e2f793b59a 2501
screamer 0:c5e2f793b59a 2502 /*!
screamer 0:c5e2f793b59a 2503 * @name Register FTM_COMBINE, field COMP2[17] (RW)
screamer 0:c5e2f793b59a 2504 *
screamer 0:c5e2f793b59a 2505 * Enables Complementary mode for the combined channels. In Complementary mode
screamer 0:c5e2f793b59a 2506 * the channel (n+1) output is the inverse of the channel (n) output. This field
screamer 0:c5e2f793b59a 2507 * is write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2508 *
screamer 0:c5e2f793b59a 2509 * Values:
screamer 0:c5e2f793b59a 2510 * - 0 - The channel (n+1) output is the same as the channel (n) output.
screamer 0:c5e2f793b59a 2511 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
screamer 0:c5e2f793b59a 2512 */
screamer 0:c5e2f793b59a 2513 /*@{*/
screamer 0:c5e2f793b59a 2514 #define BP_FTM_COMBINE_COMP2 (17U) /*!< Bit position for FTM_COMBINE_COMP2. */
screamer 0:c5e2f793b59a 2515 #define BM_FTM_COMBINE_COMP2 (0x00020000U) /*!< Bit mask for FTM_COMBINE_COMP2. */
screamer 0:c5e2f793b59a 2516 #define BS_FTM_COMBINE_COMP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP2. */
screamer 0:c5e2f793b59a 2517
screamer 0:c5e2f793b59a 2518 /*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
screamer 0:c5e2f793b59a 2519 #define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
screamer 0:c5e2f793b59a 2520
screamer 0:c5e2f793b59a 2521 /*! @brief Format value for bitfield FTM_COMBINE_COMP2. */
screamer 0:c5e2f793b59a 2522 #define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2)
screamer 0:c5e2f793b59a 2523
screamer 0:c5e2f793b59a 2524 /*! @brief Set the COMP2 field to a new value. */
screamer 0:c5e2f793b59a 2525 #define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
screamer 0:c5e2f793b59a 2526 /*@}*/
screamer 0:c5e2f793b59a 2527
screamer 0:c5e2f793b59a 2528 /*!
screamer 0:c5e2f793b59a 2529 * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
screamer 0:c5e2f793b59a 2530 *
screamer 0:c5e2f793b59a 2531 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
screamer 0:c5e2f793b59a 2532 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
screamer 0:c5e2f793b59a 2533 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
screamer 0:c5e2f793b59a 2534 * when FTMEN = 1. This field is write protected. It can be written only when
screamer 0:c5e2f793b59a 2535 * MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2536 *
screamer 0:c5e2f793b59a 2537 * Values:
screamer 0:c5e2f793b59a 2538 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2539 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2540 */
screamer 0:c5e2f793b59a 2541 /*@{*/
screamer 0:c5e2f793b59a 2542 #define BP_FTM_COMBINE_DECAPEN2 (18U) /*!< Bit position for FTM_COMBINE_DECAPEN2. */
screamer 0:c5e2f793b59a 2543 #define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /*!< Bit mask for FTM_COMBINE_DECAPEN2. */
screamer 0:c5e2f793b59a 2544 #define BS_FTM_COMBINE_DECAPEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN2. */
screamer 0:c5e2f793b59a 2545
screamer 0:c5e2f793b59a 2546 /*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
screamer 0:c5e2f793b59a 2547 #define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
screamer 0:c5e2f793b59a 2548
screamer 0:c5e2f793b59a 2549 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. */
screamer 0:c5e2f793b59a 2550 #define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2)
screamer 0:c5e2f793b59a 2551
screamer 0:c5e2f793b59a 2552 /*! @brief Set the DECAPEN2 field to a new value. */
screamer 0:c5e2f793b59a 2553 #define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
screamer 0:c5e2f793b59a 2554 /*@}*/
screamer 0:c5e2f793b59a 2555
screamer 0:c5e2f793b59a 2556 /*!
screamer 0:c5e2f793b59a 2557 * @name Register FTM_COMBINE, field DECAP2[19] (RW)
screamer 0:c5e2f793b59a 2558 *
screamer 0:c5e2f793b59a 2559 * Enables the capture of the FTM counter value according to the channel (n)
screamer 0:c5e2f793b59a 2560 * input event and the configuration of the dual edge capture bits. This field
screamer 0:c5e2f793b59a 2561 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
screamer 0:c5e2f793b59a 2562 * hardware if dual edge capture - one-shot mode is selected and when the capture
screamer 0:c5e2f793b59a 2563 * of channel (n+1) event is made.
screamer 0:c5e2f793b59a 2564 *
screamer 0:c5e2f793b59a 2565 * Values:
screamer 0:c5e2f793b59a 2566 * - 0 - The dual edge captures are inactive.
screamer 0:c5e2f793b59a 2567 * - 1 - The dual edge captures are active.
screamer 0:c5e2f793b59a 2568 */
screamer 0:c5e2f793b59a 2569 /*@{*/
screamer 0:c5e2f793b59a 2570 #define BP_FTM_COMBINE_DECAP2 (19U) /*!< Bit position for FTM_COMBINE_DECAP2. */
screamer 0:c5e2f793b59a 2571 #define BM_FTM_COMBINE_DECAP2 (0x00080000U) /*!< Bit mask for FTM_COMBINE_DECAP2. */
screamer 0:c5e2f793b59a 2572 #define BS_FTM_COMBINE_DECAP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP2. */
screamer 0:c5e2f793b59a 2573
screamer 0:c5e2f793b59a 2574 /*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
screamer 0:c5e2f793b59a 2575 #define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
screamer 0:c5e2f793b59a 2576
screamer 0:c5e2f793b59a 2577 /*! @brief Format value for bitfield FTM_COMBINE_DECAP2. */
screamer 0:c5e2f793b59a 2578 #define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2)
screamer 0:c5e2f793b59a 2579
screamer 0:c5e2f793b59a 2580 /*! @brief Set the DECAP2 field to a new value. */
screamer 0:c5e2f793b59a 2581 #define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
screamer 0:c5e2f793b59a 2582 /*@}*/
screamer 0:c5e2f793b59a 2583
screamer 0:c5e2f793b59a 2584 /*!
screamer 0:c5e2f793b59a 2585 * @name Register FTM_COMBINE, field DTEN2[20] (RW)
screamer 0:c5e2f793b59a 2586 *
screamer 0:c5e2f793b59a 2587 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
screamer 0:c5e2f793b59a 2588 * write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2589 *
screamer 0:c5e2f793b59a 2590 * Values:
screamer 0:c5e2f793b59a 2591 * - 0 - The deadtime insertion in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2592 * - 1 - The deadtime insertion in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2593 */
screamer 0:c5e2f793b59a 2594 /*@{*/
screamer 0:c5e2f793b59a 2595 #define BP_FTM_COMBINE_DTEN2 (20U) /*!< Bit position for FTM_COMBINE_DTEN2. */
screamer 0:c5e2f793b59a 2596 #define BM_FTM_COMBINE_DTEN2 (0x00100000U) /*!< Bit mask for FTM_COMBINE_DTEN2. */
screamer 0:c5e2f793b59a 2597 #define BS_FTM_COMBINE_DTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN2. */
screamer 0:c5e2f793b59a 2598
screamer 0:c5e2f793b59a 2599 /*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
screamer 0:c5e2f793b59a 2600 #define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
screamer 0:c5e2f793b59a 2601
screamer 0:c5e2f793b59a 2602 /*! @brief Format value for bitfield FTM_COMBINE_DTEN2. */
screamer 0:c5e2f793b59a 2603 #define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2)
screamer 0:c5e2f793b59a 2604
screamer 0:c5e2f793b59a 2605 /*! @brief Set the DTEN2 field to a new value. */
screamer 0:c5e2f793b59a 2606 #define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
screamer 0:c5e2f793b59a 2607 /*@}*/
screamer 0:c5e2f793b59a 2608
screamer 0:c5e2f793b59a 2609 /*!
screamer 0:c5e2f793b59a 2610 * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
screamer 0:c5e2f793b59a 2611 *
screamer 0:c5e2f793b59a 2612 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
screamer 0:c5e2f793b59a 2613 *
screamer 0:c5e2f793b59a 2614 * Values:
screamer 0:c5e2f793b59a 2615 * - 0 - The PWM synchronization in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2616 * - 1 - The PWM synchronization in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2617 */
screamer 0:c5e2f793b59a 2618 /*@{*/
screamer 0:c5e2f793b59a 2619 #define BP_FTM_COMBINE_SYNCEN2 (21U) /*!< Bit position for FTM_COMBINE_SYNCEN2. */
screamer 0:c5e2f793b59a 2620 #define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /*!< Bit mask for FTM_COMBINE_SYNCEN2. */
screamer 0:c5e2f793b59a 2621 #define BS_FTM_COMBINE_SYNCEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN2. */
screamer 0:c5e2f793b59a 2622
screamer 0:c5e2f793b59a 2623 /*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
screamer 0:c5e2f793b59a 2624 #define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
screamer 0:c5e2f793b59a 2625
screamer 0:c5e2f793b59a 2626 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. */
screamer 0:c5e2f793b59a 2627 #define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2)
screamer 0:c5e2f793b59a 2628
screamer 0:c5e2f793b59a 2629 /*! @brief Set the SYNCEN2 field to a new value. */
screamer 0:c5e2f793b59a 2630 #define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
screamer 0:c5e2f793b59a 2631 /*@}*/
screamer 0:c5e2f793b59a 2632
screamer 0:c5e2f793b59a 2633 /*!
screamer 0:c5e2f793b59a 2634 * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
screamer 0:c5e2f793b59a 2635 *
screamer 0:c5e2f793b59a 2636 * Enables the fault control in channels (n) and (n+1). This field is write
screamer 0:c5e2f793b59a 2637 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2638 *
screamer 0:c5e2f793b59a 2639 * Values:
screamer 0:c5e2f793b59a 2640 * - 0 - The fault control in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2641 * - 1 - The fault control in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2642 */
screamer 0:c5e2f793b59a 2643 /*@{*/
screamer 0:c5e2f793b59a 2644 #define BP_FTM_COMBINE_FAULTEN2 (22U) /*!< Bit position for FTM_COMBINE_FAULTEN2. */
screamer 0:c5e2f793b59a 2645 #define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /*!< Bit mask for FTM_COMBINE_FAULTEN2. */
screamer 0:c5e2f793b59a 2646 #define BS_FTM_COMBINE_FAULTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN2. */
screamer 0:c5e2f793b59a 2647
screamer 0:c5e2f793b59a 2648 /*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
screamer 0:c5e2f793b59a 2649 #define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
screamer 0:c5e2f793b59a 2650
screamer 0:c5e2f793b59a 2651 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. */
screamer 0:c5e2f793b59a 2652 #define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2)
screamer 0:c5e2f793b59a 2653
screamer 0:c5e2f793b59a 2654 /*! @brief Set the FAULTEN2 field to a new value. */
screamer 0:c5e2f793b59a 2655 #define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
screamer 0:c5e2f793b59a 2656 /*@}*/
screamer 0:c5e2f793b59a 2657
screamer 0:c5e2f793b59a 2658 /*!
screamer 0:c5e2f793b59a 2659 * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
screamer 0:c5e2f793b59a 2660 *
screamer 0:c5e2f793b59a 2661 * Enables the combine feature for channels (n) and (n+1). This field is write
screamer 0:c5e2f793b59a 2662 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2663 *
screamer 0:c5e2f793b59a 2664 * Values:
screamer 0:c5e2f793b59a 2665 * - 0 - Channels (n) and (n+1) are independent.
screamer 0:c5e2f793b59a 2666 * - 1 - Channels (n) and (n+1) are combined.
screamer 0:c5e2f793b59a 2667 */
screamer 0:c5e2f793b59a 2668 /*@{*/
screamer 0:c5e2f793b59a 2669 #define BP_FTM_COMBINE_COMBINE3 (24U) /*!< Bit position for FTM_COMBINE_COMBINE3. */
screamer 0:c5e2f793b59a 2670 #define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /*!< Bit mask for FTM_COMBINE_COMBINE3. */
screamer 0:c5e2f793b59a 2671 #define BS_FTM_COMBINE_COMBINE3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE3. */
screamer 0:c5e2f793b59a 2672
screamer 0:c5e2f793b59a 2673 /*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
screamer 0:c5e2f793b59a 2674 #define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
screamer 0:c5e2f793b59a 2675
screamer 0:c5e2f793b59a 2676 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE3. */
screamer 0:c5e2f793b59a 2677 #define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3)
screamer 0:c5e2f793b59a 2678
screamer 0:c5e2f793b59a 2679 /*! @brief Set the COMBINE3 field to a new value. */
screamer 0:c5e2f793b59a 2680 #define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
screamer 0:c5e2f793b59a 2681 /*@}*/
screamer 0:c5e2f793b59a 2682
screamer 0:c5e2f793b59a 2683 /*!
screamer 0:c5e2f793b59a 2684 * @name Register FTM_COMBINE, field COMP3[25] (RW)
screamer 0:c5e2f793b59a 2685 *
screamer 0:c5e2f793b59a 2686 * Enables Complementary mode for the combined channels. In Complementary mode
screamer 0:c5e2f793b59a 2687 * the channel (n+1) output is the inverse of the channel (n) output. This field
screamer 0:c5e2f793b59a 2688 * is write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2689 *
screamer 0:c5e2f793b59a 2690 * Values:
screamer 0:c5e2f793b59a 2691 * - 0 - The channel (n+1) output is the same as the channel (n) output.
screamer 0:c5e2f793b59a 2692 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
screamer 0:c5e2f793b59a 2693 */
screamer 0:c5e2f793b59a 2694 /*@{*/
screamer 0:c5e2f793b59a 2695 #define BP_FTM_COMBINE_COMP3 (25U) /*!< Bit position for FTM_COMBINE_COMP3. */
screamer 0:c5e2f793b59a 2696 #define BM_FTM_COMBINE_COMP3 (0x02000000U) /*!< Bit mask for FTM_COMBINE_COMP3. */
screamer 0:c5e2f793b59a 2697 #define BS_FTM_COMBINE_COMP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP3. */
screamer 0:c5e2f793b59a 2698
screamer 0:c5e2f793b59a 2699 /*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
screamer 0:c5e2f793b59a 2700 #define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
screamer 0:c5e2f793b59a 2701
screamer 0:c5e2f793b59a 2702 /*! @brief Format value for bitfield FTM_COMBINE_COMP3. */
screamer 0:c5e2f793b59a 2703 #define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3)
screamer 0:c5e2f793b59a 2704
screamer 0:c5e2f793b59a 2705 /*! @brief Set the COMP3 field to a new value. */
screamer 0:c5e2f793b59a 2706 #define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
screamer 0:c5e2f793b59a 2707 /*@}*/
screamer 0:c5e2f793b59a 2708
screamer 0:c5e2f793b59a 2709 /*!
screamer 0:c5e2f793b59a 2710 * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
screamer 0:c5e2f793b59a 2711 *
screamer 0:c5e2f793b59a 2712 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
screamer 0:c5e2f793b59a 2713 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
screamer 0:c5e2f793b59a 2714 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
screamer 0:c5e2f793b59a 2715 * when FTMEN = 1. This field is write protected. It can be written only when
screamer 0:c5e2f793b59a 2716 * MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2717 *
screamer 0:c5e2f793b59a 2718 * Values:
screamer 0:c5e2f793b59a 2719 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2720 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2721 */
screamer 0:c5e2f793b59a 2722 /*@{*/
screamer 0:c5e2f793b59a 2723 #define BP_FTM_COMBINE_DECAPEN3 (26U) /*!< Bit position for FTM_COMBINE_DECAPEN3. */
screamer 0:c5e2f793b59a 2724 #define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /*!< Bit mask for FTM_COMBINE_DECAPEN3. */
screamer 0:c5e2f793b59a 2725 #define BS_FTM_COMBINE_DECAPEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN3. */
screamer 0:c5e2f793b59a 2726
screamer 0:c5e2f793b59a 2727 /*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
screamer 0:c5e2f793b59a 2728 #define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
screamer 0:c5e2f793b59a 2729
screamer 0:c5e2f793b59a 2730 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. */
screamer 0:c5e2f793b59a 2731 #define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3)
screamer 0:c5e2f793b59a 2732
screamer 0:c5e2f793b59a 2733 /*! @brief Set the DECAPEN3 field to a new value. */
screamer 0:c5e2f793b59a 2734 #define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
screamer 0:c5e2f793b59a 2735 /*@}*/
screamer 0:c5e2f793b59a 2736
screamer 0:c5e2f793b59a 2737 /*!
screamer 0:c5e2f793b59a 2738 * @name Register FTM_COMBINE, field DECAP3[27] (RW)
screamer 0:c5e2f793b59a 2739 *
screamer 0:c5e2f793b59a 2740 * Enables the capture of the FTM counter value according to the channel (n)
screamer 0:c5e2f793b59a 2741 * input event and the configuration of the dual edge capture bits. This field
screamer 0:c5e2f793b59a 2742 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
screamer 0:c5e2f793b59a 2743 * hardware if dual edge capture - one-shot mode is selected and when the capture
screamer 0:c5e2f793b59a 2744 * of channel (n+1) event is made.
screamer 0:c5e2f793b59a 2745 *
screamer 0:c5e2f793b59a 2746 * Values:
screamer 0:c5e2f793b59a 2747 * - 0 - The dual edge captures are inactive.
screamer 0:c5e2f793b59a 2748 * - 1 - The dual edge captures are active.
screamer 0:c5e2f793b59a 2749 */
screamer 0:c5e2f793b59a 2750 /*@{*/
screamer 0:c5e2f793b59a 2751 #define BP_FTM_COMBINE_DECAP3 (27U) /*!< Bit position for FTM_COMBINE_DECAP3. */
screamer 0:c5e2f793b59a 2752 #define BM_FTM_COMBINE_DECAP3 (0x08000000U) /*!< Bit mask for FTM_COMBINE_DECAP3. */
screamer 0:c5e2f793b59a 2753 #define BS_FTM_COMBINE_DECAP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP3. */
screamer 0:c5e2f793b59a 2754
screamer 0:c5e2f793b59a 2755 /*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
screamer 0:c5e2f793b59a 2756 #define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
screamer 0:c5e2f793b59a 2757
screamer 0:c5e2f793b59a 2758 /*! @brief Format value for bitfield FTM_COMBINE_DECAP3. */
screamer 0:c5e2f793b59a 2759 #define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3)
screamer 0:c5e2f793b59a 2760
screamer 0:c5e2f793b59a 2761 /*! @brief Set the DECAP3 field to a new value. */
screamer 0:c5e2f793b59a 2762 #define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
screamer 0:c5e2f793b59a 2763 /*@}*/
screamer 0:c5e2f793b59a 2764
screamer 0:c5e2f793b59a 2765 /*!
screamer 0:c5e2f793b59a 2766 * @name Register FTM_COMBINE, field DTEN3[28] (RW)
screamer 0:c5e2f793b59a 2767 *
screamer 0:c5e2f793b59a 2768 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
screamer 0:c5e2f793b59a 2769 * write protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2770 *
screamer 0:c5e2f793b59a 2771 * Values:
screamer 0:c5e2f793b59a 2772 * - 0 - The deadtime insertion in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2773 * - 1 - The deadtime insertion in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2774 */
screamer 0:c5e2f793b59a 2775 /*@{*/
screamer 0:c5e2f793b59a 2776 #define BP_FTM_COMBINE_DTEN3 (28U) /*!< Bit position for FTM_COMBINE_DTEN3. */
screamer 0:c5e2f793b59a 2777 #define BM_FTM_COMBINE_DTEN3 (0x10000000U) /*!< Bit mask for FTM_COMBINE_DTEN3. */
screamer 0:c5e2f793b59a 2778 #define BS_FTM_COMBINE_DTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN3. */
screamer 0:c5e2f793b59a 2779
screamer 0:c5e2f793b59a 2780 /*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
screamer 0:c5e2f793b59a 2781 #define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
screamer 0:c5e2f793b59a 2782
screamer 0:c5e2f793b59a 2783 /*! @brief Format value for bitfield FTM_COMBINE_DTEN3. */
screamer 0:c5e2f793b59a 2784 #define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3)
screamer 0:c5e2f793b59a 2785
screamer 0:c5e2f793b59a 2786 /*! @brief Set the DTEN3 field to a new value. */
screamer 0:c5e2f793b59a 2787 #define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
screamer 0:c5e2f793b59a 2788 /*@}*/
screamer 0:c5e2f793b59a 2789
screamer 0:c5e2f793b59a 2790 /*!
screamer 0:c5e2f793b59a 2791 * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
screamer 0:c5e2f793b59a 2792 *
screamer 0:c5e2f793b59a 2793 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
screamer 0:c5e2f793b59a 2794 *
screamer 0:c5e2f793b59a 2795 * Values:
screamer 0:c5e2f793b59a 2796 * - 0 - The PWM synchronization in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2797 * - 1 - The PWM synchronization in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2798 */
screamer 0:c5e2f793b59a 2799 /*@{*/
screamer 0:c5e2f793b59a 2800 #define BP_FTM_COMBINE_SYNCEN3 (29U) /*!< Bit position for FTM_COMBINE_SYNCEN3. */
screamer 0:c5e2f793b59a 2801 #define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /*!< Bit mask for FTM_COMBINE_SYNCEN3. */
screamer 0:c5e2f793b59a 2802 #define BS_FTM_COMBINE_SYNCEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN3. */
screamer 0:c5e2f793b59a 2803
screamer 0:c5e2f793b59a 2804 /*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
screamer 0:c5e2f793b59a 2805 #define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
screamer 0:c5e2f793b59a 2806
screamer 0:c5e2f793b59a 2807 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. */
screamer 0:c5e2f793b59a 2808 #define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3)
screamer 0:c5e2f793b59a 2809
screamer 0:c5e2f793b59a 2810 /*! @brief Set the SYNCEN3 field to a new value. */
screamer 0:c5e2f793b59a 2811 #define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
screamer 0:c5e2f793b59a 2812 /*@}*/
screamer 0:c5e2f793b59a 2813
screamer 0:c5e2f793b59a 2814 /*!
screamer 0:c5e2f793b59a 2815 * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
screamer 0:c5e2f793b59a 2816 *
screamer 0:c5e2f793b59a 2817 * Enables the fault control in channels (n) and (n+1). This field is write
screamer 0:c5e2f793b59a 2818 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2819 *
screamer 0:c5e2f793b59a 2820 * Values:
screamer 0:c5e2f793b59a 2821 * - 0 - The fault control in this pair of channels is disabled.
screamer 0:c5e2f793b59a 2822 * - 1 - The fault control in this pair of channels is enabled.
screamer 0:c5e2f793b59a 2823 */
screamer 0:c5e2f793b59a 2824 /*@{*/
screamer 0:c5e2f793b59a 2825 #define BP_FTM_COMBINE_FAULTEN3 (30U) /*!< Bit position for FTM_COMBINE_FAULTEN3. */
screamer 0:c5e2f793b59a 2826 #define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /*!< Bit mask for FTM_COMBINE_FAULTEN3. */
screamer 0:c5e2f793b59a 2827 #define BS_FTM_COMBINE_FAULTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN3. */
screamer 0:c5e2f793b59a 2828
screamer 0:c5e2f793b59a 2829 /*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
screamer 0:c5e2f793b59a 2830 #define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
screamer 0:c5e2f793b59a 2831
screamer 0:c5e2f793b59a 2832 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. */
screamer 0:c5e2f793b59a 2833 #define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3)
screamer 0:c5e2f793b59a 2834
screamer 0:c5e2f793b59a 2835 /*! @brief Set the FAULTEN3 field to a new value. */
screamer 0:c5e2f793b59a 2836 #define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
screamer 0:c5e2f793b59a 2837 /*@}*/
screamer 0:c5e2f793b59a 2838
screamer 0:c5e2f793b59a 2839 /*******************************************************************************
screamer 0:c5e2f793b59a 2840 * HW_FTM_DEADTIME - Deadtime Insertion Control
screamer 0:c5e2f793b59a 2841 ******************************************************************************/
screamer 0:c5e2f793b59a 2842
screamer 0:c5e2f793b59a 2843 /*!
screamer 0:c5e2f793b59a 2844 * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
screamer 0:c5e2f793b59a 2845 *
screamer 0:c5e2f793b59a 2846 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 2847 *
screamer 0:c5e2f793b59a 2848 * This register selects the deadtime prescaler factor and deadtime value. All
screamer 0:c5e2f793b59a 2849 * FTM channels use this clock prescaler and this deadtime value for the deadtime
screamer 0:c5e2f793b59a 2850 * insertion.
screamer 0:c5e2f793b59a 2851 */
screamer 0:c5e2f793b59a 2852 typedef union _hw_ftm_deadtime
screamer 0:c5e2f793b59a 2853 {
screamer 0:c5e2f793b59a 2854 uint32_t U;
screamer 0:c5e2f793b59a 2855 struct _hw_ftm_deadtime_bitfields
screamer 0:c5e2f793b59a 2856 {
screamer 0:c5e2f793b59a 2857 uint32_t DTVAL : 6; /*!< [5:0] Deadtime Value */
screamer 0:c5e2f793b59a 2858 uint32_t DTPS : 2; /*!< [7:6] Deadtime Prescaler Value */
screamer 0:c5e2f793b59a 2859 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 2860 } B;
screamer 0:c5e2f793b59a 2861 } hw_ftm_deadtime_t;
screamer 0:c5e2f793b59a 2862
screamer 0:c5e2f793b59a 2863 /*!
screamer 0:c5e2f793b59a 2864 * @name Constants and macros for entire FTM_DEADTIME register
screamer 0:c5e2f793b59a 2865 */
screamer 0:c5e2f793b59a 2866 /*@{*/
screamer 0:c5e2f793b59a 2867 #define HW_FTM_DEADTIME_ADDR(x) ((x) + 0x68U)
screamer 0:c5e2f793b59a 2868
screamer 0:c5e2f793b59a 2869 #define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
screamer 0:c5e2f793b59a 2870 #define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
screamer 0:c5e2f793b59a 2871 #define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
screamer 0:c5e2f793b59a 2872 #define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v)))
screamer 0:c5e2f793b59a 2873 #define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 2874 #define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 2875 /*@}*/
screamer 0:c5e2f793b59a 2876
screamer 0:c5e2f793b59a 2877 /*
screamer 0:c5e2f793b59a 2878 * Constants & macros for individual FTM_DEADTIME bitfields
screamer 0:c5e2f793b59a 2879 */
screamer 0:c5e2f793b59a 2880
screamer 0:c5e2f793b59a 2881 /*!
screamer 0:c5e2f793b59a 2882 * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
screamer 0:c5e2f793b59a 2883 *
screamer 0:c5e2f793b59a 2884 * Selects the deadtime insertion value for the deadtime counter. The deadtime
screamer 0:c5e2f793b59a 2885 * counter is clocked by a scaled version of the system clock. See the description
screamer 0:c5e2f793b59a 2886 * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
screamer 0:c5e2f793b59a 2887 * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
screamer 0:c5e2f793b59a 2888 * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
screamer 0:c5e2f793b59a 2889 * This pattern continues up to a possible 63 counts. This field is write
screamer 0:c5e2f793b59a 2890 * protected. It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2891 */
screamer 0:c5e2f793b59a 2892 /*@{*/
screamer 0:c5e2f793b59a 2893 #define BP_FTM_DEADTIME_DTVAL (0U) /*!< Bit position for FTM_DEADTIME_DTVAL. */
screamer 0:c5e2f793b59a 2894 #define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /*!< Bit mask for FTM_DEADTIME_DTVAL. */
screamer 0:c5e2f793b59a 2895 #define BS_FTM_DEADTIME_DTVAL (6U) /*!< Bit field size in bits for FTM_DEADTIME_DTVAL. */
screamer 0:c5e2f793b59a 2896
screamer 0:c5e2f793b59a 2897 /*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
screamer 0:c5e2f793b59a 2898 #define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
screamer 0:c5e2f793b59a 2899
screamer 0:c5e2f793b59a 2900 /*! @brief Format value for bitfield FTM_DEADTIME_DTVAL. */
screamer 0:c5e2f793b59a 2901 #define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL)
screamer 0:c5e2f793b59a 2902
screamer 0:c5e2f793b59a 2903 /*! @brief Set the DTVAL field to a new value. */
screamer 0:c5e2f793b59a 2904 #define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
screamer 0:c5e2f793b59a 2905 /*@}*/
screamer 0:c5e2f793b59a 2906
screamer 0:c5e2f793b59a 2907 /*!
screamer 0:c5e2f793b59a 2908 * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
screamer 0:c5e2f793b59a 2909 *
screamer 0:c5e2f793b59a 2910 * Selects the division factor of the system clock. This prescaled clock is used
screamer 0:c5e2f793b59a 2911 * by the deadtime counter. This field is write protected. It can be written
screamer 0:c5e2f793b59a 2912 * only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 2913 *
screamer 0:c5e2f793b59a 2914 * Values:
screamer 0:c5e2f793b59a 2915 * - 0x - Divide the system clock by 1.
screamer 0:c5e2f793b59a 2916 * - 10 - Divide the system clock by 4.
screamer 0:c5e2f793b59a 2917 * - 11 - Divide the system clock by 16.
screamer 0:c5e2f793b59a 2918 */
screamer 0:c5e2f793b59a 2919 /*@{*/
screamer 0:c5e2f793b59a 2920 #define BP_FTM_DEADTIME_DTPS (6U) /*!< Bit position for FTM_DEADTIME_DTPS. */
screamer 0:c5e2f793b59a 2921 #define BM_FTM_DEADTIME_DTPS (0x000000C0U) /*!< Bit mask for FTM_DEADTIME_DTPS. */
screamer 0:c5e2f793b59a 2922 #define BS_FTM_DEADTIME_DTPS (2U) /*!< Bit field size in bits for FTM_DEADTIME_DTPS. */
screamer 0:c5e2f793b59a 2923
screamer 0:c5e2f793b59a 2924 /*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
screamer 0:c5e2f793b59a 2925 #define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
screamer 0:c5e2f793b59a 2926
screamer 0:c5e2f793b59a 2927 /*! @brief Format value for bitfield FTM_DEADTIME_DTPS. */
screamer 0:c5e2f793b59a 2928 #define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS)
screamer 0:c5e2f793b59a 2929
screamer 0:c5e2f793b59a 2930 /*! @brief Set the DTPS field to a new value. */
screamer 0:c5e2f793b59a 2931 #define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
screamer 0:c5e2f793b59a 2932 /*@}*/
screamer 0:c5e2f793b59a 2933
screamer 0:c5e2f793b59a 2934 /*******************************************************************************
screamer 0:c5e2f793b59a 2935 * HW_FTM_EXTTRIG - FTM External Trigger
screamer 0:c5e2f793b59a 2936 ******************************************************************************/
screamer 0:c5e2f793b59a 2937
screamer 0:c5e2f793b59a 2938 /*!
screamer 0:c5e2f793b59a 2939 * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
screamer 0:c5e2f793b59a 2940 *
screamer 0:c5e2f793b59a 2941 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 2942 *
screamer 0:c5e2f793b59a 2943 * This register: Indicates when a channel trigger was generated Enables the
screamer 0:c5e2f793b59a 2944 * generation of a trigger when the FTM counter is equal to its initial value
screamer 0:c5e2f793b59a 2945 * Selects which channels are used in the generation of the channel triggers Several
screamer 0:c5e2f793b59a 2946 * channels can be selected to generate multiple triggers in one PWM period.
screamer 0:c5e2f793b59a 2947 * Channels 6 and 7 are not used to generate channel triggers.
screamer 0:c5e2f793b59a 2948 */
screamer 0:c5e2f793b59a 2949 typedef union _hw_ftm_exttrig
screamer 0:c5e2f793b59a 2950 {
screamer 0:c5e2f793b59a 2951 uint32_t U;
screamer 0:c5e2f793b59a 2952 struct _hw_ftm_exttrig_bitfields
screamer 0:c5e2f793b59a 2953 {
screamer 0:c5e2f793b59a 2954 uint32_t CH2TRIG : 1; /*!< [0] Channel 2 Trigger Enable */
screamer 0:c5e2f793b59a 2955 uint32_t CH3TRIG : 1; /*!< [1] Channel 3 Trigger Enable */
screamer 0:c5e2f793b59a 2956 uint32_t CH4TRIG : 1; /*!< [2] Channel 4 Trigger Enable */
screamer 0:c5e2f793b59a 2957 uint32_t CH5TRIG : 1; /*!< [3] Channel 5 Trigger Enable */
screamer 0:c5e2f793b59a 2958 uint32_t CH0TRIG : 1; /*!< [4] Channel 0 Trigger Enable */
screamer 0:c5e2f793b59a 2959 uint32_t CH1TRIG : 1; /*!< [5] Channel 1 Trigger Enable */
screamer 0:c5e2f793b59a 2960 uint32_t INITTRIGEN : 1; /*!< [6] Initialization Trigger Enable */
screamer 0:c5e2f793b59a 2961 uint32_t TRIGF : 1; /*!< [7] Channel Trigger Flag */
screamer 0:c5e2f793b59a 2962 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 2963 } B;
screamer 0:c5e2f793b59a 2964 } hw_ftm_exttrig_t;
screamer 0:c5e2f793b59a 2965
screamer 0:c5e2f793b59a 2966 /*!
screamer 0:c5e2f793b59a 2967 * @name Constants and macros for entire FTM_EXTTRIG register
screamer 0:c5e2f793b59a 2968 */
screamer 0:c5e2f793b59a 2969 /*@{*/
screamer 0:c5e2f793b59a 2970 #define HW_FTM_EXTTRIG_ADDR(x) ((x) + 0x6CU)
screamer 0:c5e2f793b59a 2971
screamer 0:c5e2f793b59a 2972 #define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
screamer 0:c5e2f793b59a 2973 #define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
screamer 0:c5e2f793b59a 2974 #define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
screamer 0:c5e2f793b59a 2975 #define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v)))
screamer 0:c5e2f793b59a 2976 #define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 2977 #define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 2978 /*@}*/
screamer 0:c5e2f793b59a 2979
screamer 0:c5e2f793b59a 2980 /*
screamer 0:c5e2f793b59a 2981 * Constants & macros for individual FTM_EXTTRIG bitfields
screamer 0:c5e2f793b59a 2982 */
screamer 0:c5e2f793b59a 2983
screamer 0:c5e2f793b59a 2984 /*!
screamer 0:c5e2f793b59a 2985 * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
screamer 0:c5e2f793b59a 2986 *
screamer 0:c5e2f793b59a 2987 * Enables the generation of the channel trigger when the FTM counter is equal
screamer 0:c5e2f793b59a 2988 * to the CnV register.
screamer 0:c5e2f793b59a 2989 *
screamer 0:c5e2f793b59a 2990 * Values:
screamer 0:c5e2f793b59a 2991 * - 0 - The generation of the channel trigger is disabled.
screamer 0:c5e2f793b59a 2992 * - 1 - The generation of the channel trigger is enabled.
screamer 0:c5e2f793b59a 2993 */
screamer 0:c5e2f793b59a 2994 /*@{*/
screamer 0:c5e2f793b59a 2995 #define BP_FTM_EXTTRIG_CH2TRIG (0U) /*!< Bit position for FTM_EXTTRIG_CH2TRIG. */
screamer 0:c5e2f793b59a 2996 #define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /*!< Bit mask for FTM_EXTTRIG_CH2TRIG. */
screamer 0:c5e2f793b59a 2997 #define BS_FTM_EXTTRIG_CH2TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. */
screamer 0:c5e2f793b59a 2998
screamer 0:c5e2f793b59a 2999 /*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
screamer 0:c5e2f793b59a 3000 #define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
screamer 0:c5e2f793b59a 3001
screamer 0:c5e2f793b59a 3002 /*! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. */
screamer 0:c5e2f793b59a 3003 #define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG)
screamer 0:c5e2f793b59a 3004
screamer 0:c5e2f793b59a 3005 /*! @brief Set the CH2TRIG field to a new value. */
screamer 0:c5e2f793b59a 3006 #define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
screamer 0:c5e2f793b59a 3007 /*@}*/
screamer 0:c5e2f793b59a 3008
screamer 0:c5e2f793b59a 3009 /*!
screamer 0:c5e2f793b59a 3010 * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
screamer 0:c5e2f793b59a 3011 *
screamer 0:c5e2f793b59a 3012 * Enables the generation of the channel trigger when the FTM counter is equal
screamer 0:c5e2f793b59a 3013 * to the CnV register.
screamer 0:c5e2f793b59a 3014 *
screamer 0:c5e2f793b59a 3015 * Values:
screamer 0:c5e2f793b59a 3016 * - 0 - The generation of the channel trigger is disabled.
screamer 0:c5e2f793b59a 3017 * - 1 - The generation of the channel trigger is enabled.
screamer 0:c5e2f793b59a 3018 */
screamer 0:c5e2f793b59a 3019 /*@{*/
screamer 0:c5e2f793b59a 3020 #define BP_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit position for FTM_EXTTRIG_CH3TRIG. */
screamer 0:c5e2f793b59a 3021 #define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /*!< Bit mask for FTM_EXTTRIG_CH3TRIG. */
screamer 0:c5e2f793b59a 3022 #define BS_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. */
screamer 0:c5e2f793b59a 3023
screamer 0:c5e2f793b59a 3024 /*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
screamer 0:c5e2f793b59a 3025 #define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
screamer 0:c5e2f793b59a 3026
screamer 0:c5e2f793b59a 3027 /*! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. */
screamer 0:c5e2f793b59a 3028 #define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG)
screamer 0:c5e2f793b59a 3029
screamer 0:c5e2f793b59a 3030 /*! @brief Set the CH3TRIG field to a new value. */
screamer 0:c5e2f793b59a 3031 #define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
screamer 0:c5e2f793b59a 3032 /*@}*/
screamer 0:c5e2f793b59a 3033
screamer 0:c5e2f793b59a 3034 /*!
screamer 0:c5e2f793b59a 3035 * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
screamer 0:c5e2f793b59a 3036 *
screamer 0:c5e2f793b59a 3037 * Enables the generation of the channel trigger when the FTM counter is equal
screamer 0:c5e2f793b59a 3038 * to the CnV register.
screamer 0:c5e2f793b59a 3039 *
screamer 0:c5e2f793b59a 3040 * Values:
screamer 0:c5e2f793b59a 3041 * - 0 - The generation of the channel trigger is disabled.
screamer 0:c5e2f793b59a 3042 * - 1 - The generation of the channel trigger is enabled.
screamer 0:c5e2f793b59a 3043 */
screamer 0:c5e2f793b59a 3044 /*@{*/
screamer 0:c5e2f793b59a 3045 #define BP_FTM_EXTTRIG_CH4TRIG (2U) /*!< Bit position for FTM_EXTTRIG_CH4TRIG. */
screamer 0:c5e2f793b59a 3046 #define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /*!< Bit mask for FTM_EXTTRIG_CH4TRIG. */
screamer 0:c5e2f793b59a 3047 #define BS_FTM_EXTTRIG_CH4TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. */
screamer 0:c5e2f793b59a 3048
screamer 0:c5e2f793b59a 3049 /*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
screamer 0:c5e2f793b59a 3050 #define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
screamer 0:c5e2f793b59a 3051
screamer 0:c5e2f793b59a 3052 /*! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. */
screamer 0:c5e2f793b59a 3053 #define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG)
screamer 0:c5e2f793b59a 3054
screamer 0:c5e2f793b59a 3055 /*! @brief Set the CH4TRIG field to a new value. */
screamer 0:c5e2f793b59a 3056 #define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
screamer 0:c5e2f793b59a 3057 /*@}*/
screamer 0:c5e2f793b59a 3058
screamer 0:c5e2f793b59a 3059 /*!
screamer 0:c5e2f793b59a 3060 * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
screamer 0:c5e2f793b59a 3061 *
screamer 0:c5e2f793b59a 3062 * Enables the generation of the channel trigger when the FTM counter is equal
screamer 0:c5e2f793b59a 3063 * to the CnV register.
screamer 0:c5e2f793b59a 3064 *
screamer 0:c5e2f793b59a 3065 * Values:
screamer 0:c5e2f793b59a 3066 * - 0 - The generation of the channel trigger is disabled.
screamer 0:c5e2f793b59a 3067 * - 1 - The generation of the channel trigger is enabled.
screamer 0:c5e2f793b59a 3068 */
screamer 0:c5e2f793b59a 3069 /*@{*/
screamer 0:c5e2f793b59a 3070 #define BP_FTM_EXTTRIG_CH5TRIG (3U) /*!< Bit position for FTM_EXTTRIG_CH5TRIG. */
screamer 0:c5e2f793b59a 3071 #define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /*!< Bit mask for FTM_EXTTRIG_CH5TRIG. */
screamer 0:c5e2f793b59a 3072 #define BS_FTM_EXTTRIG_CH5TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. */
screamer 0:c5e2f793b59a 3073
screamer 0:c5e2f793b59a 3074 /*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
screamer 0:c5e2f793b59a 3075 #define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
screamer 0:c5e2f793b59a 3076
screamer 0:c5e2f793b59a 3077 /*! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. */
screamer 0:c5e2f793b59a 3078 #define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG)
screamer 0:c5e2f793b59a 3079
screamer 0:c5e2f793b59a 3080 /*! @brief Set the CH5TRIG field to a new value. */
screamer 0:c5e2f793b59a 3081 #define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
screamer 0:c5e2f793b59a 3082 /*@}*/
screamer 0:c5e2f793b59a 3083
screamer 0:c5e2f793b59a 3084 /*!
screamer 0:c5e2f793b59a 3085 * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
screamer 0:c5e2f793b59a 3086 *
screamer 0:c5e2f793b59a 3087 * Enables the generation of the channel trigger when the FTM counter is equal
screamer 0:c5e2f793b59a 3088 * to the CnV register.
screamer 0:c5e2f793b59a 3089 *
screamer 0:c5e2f793b59a 3090 * Values:
screamer 0:c5e2f793b59a 3091 * - 0 - The generation of the channel trigger is disabled.
screamer 0:c5e2f793b59a 3092 * - 1 - The generation of the channel trigger is enabled.
screamer 0:c5e2f793b59a 3093 */
screamer 0:c5e2f793b59a 3094 /*@{*/
screamer 0:c5e2f793b59a 3095 #define BP_FTM_EXTTRIG_CH0TRIG (4U) /*!< Bit position for FTM_EXTTRIG_CH0TRIG. */
screamer 0:c5e2f793b59a 3096 #define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /*!< Bit mask for FTM_EXTTRIG_CH0TRIG. */
screamer 0:c5e2f793b59a 3097 #define BS_FTM_EXTTRIG_CH0TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. */
screamer 0:c5e2f793b59a 3098
screamer 0:c5e2f793b59a 3099 /*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
screamer 0:c5e2f793b59a 3100 #define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
screamer 0:c5e2f793b59a 3101
screamer 0:c5e2f793b59a 3102 /*! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. */
screamer 0:c5e2f793b59a 3103 #define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG)
screamer 0:c5e2f793b59a 3104
screamer 0:c5e2f793b59a 3105 /*! @brief Set the CH0TRIG field to a new value. */
screamer 0:c5e2f793b59a 3106 #define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
screamer 0:c5e2f793b59a 3107 /*@}*/
screamer 0:c5e2f793b59a 3108
screamer 0:c5e2f793b59a 3109 /*!
screamer 0:c5e2f793b59a 3110 * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
screamer 0:c5e2f793b59a 3111 *
screamer 0:c5e2f793b59a 3112 * Enables the generation of the channel trigger when the FTM counter is equal
screamer 0:c5e2f793b59a 3113 * to the CnV register.
screamer 0:c5e2f793b59a 3114 *
screamer 0:c5e2f793b59a 3115 * Values:
screamer 0:c5e2f793b59a 3116 * - 0 - The generation of the channel trigger is disabled.
screamer 0:c5e2f793b59a 3117 * - 1 - The generation of the channel trigger is enabled.
screamer 0:c5e2f793b59a 3118 */
screamer 0:c5e2f793b59a 3119 /*@{*/
screamer 0:c5e2f793b59a 3120 #define BP_FTM_EXTTRIG_CH1TRIG (5U) /*!< Bit position for FTM_EXTTRIG_CH1TRIG. */
screamer 0:c5e2f793b59a 3121 #define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /*!< Bit mask for FTM_EXTTRIG_CH1TRIG. */
screamer 0:c5e2f793b59a 3122 #define BS_FTM_EXTTRIG_CH1TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. */
screamer 0:c5e2f793b59a 3123
screamer 0:c5e2f793b59a 3124 /*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
screamer 0:c5e2f793b59a 3125 #define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
screamer 0:c5e2f793b59a 3126
screamer 0:c5e2f793b59a 3127 /*! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. */
screamer 0:c5e2f793b59a 3128 #define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG)
screamer 0:c5e2f793b59a 3129
screamer 0:c5e2f793b59a 3130 /*! @brief Set the CH1TRIG field to a new value. */
screamer 0:c5e2f793b59a 3131 #define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
screamer 0:c5e2f793b59a 3132 /*@}*/
screamer 0:c5e2f793b59a 3133
screamer 0:c5e2f793b59a 3134 /*!
screamer 0:c5e2f793b59a 3135 * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
screamer 0:c5e2f793b59a 3136 *
screamer 0:c5e2f793b59a 3137 * Enables the generation of the trigger when the FTM counter is equal to the
screamer 0:c5e2f793b59a 3138 * CNTIN register.
screamer 0:c5e2f793b59a 3139 *
screamer 0:c5e2f793b59a 3140 * Values:
screamer 0:c5e2f793b59a 3141 * - 0 - The generation of initialization trigger is disabled.
screamer 0:c5e2f793b59a 3142 * - 1 - The generation of initialization trigger is enabled.
screamer 0:c5e2f793b59a 3143 */
screamer 0:c5e2f793b59a 3144 /*@{*/
screamer 0:c5e2f793b59a 3145 #define BP_FTM_EXTTRIG_INITTRIGEN (6U) /*!< Bit position for FTM_EXTTRIG_INITTRIGEN. */
screamer 0:c5e2f793b59a 3146 #define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /*!< Bit mask for FTM_EXTTRIG_INITTRIGEN. */
screamer 0:c5e2f793b59a 3147 #define BS_FTM_EXTTRIG_INITTRIGEN (1U) /*!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. */
screamer 0:c5e2f793b59a 3148
screamer 0:c5e2f793b59a 3149 /*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
screamer 0:c5e2f793b59a 3150 #define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
screamer 0:c5e2f793b59a 3151
screamer 0:c5e2f793b59a 3152 /*! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. */
screamer 0:c5e2f793b59a 3153 #define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN)
screamer 0:c5e2f793b59a 3154
screamer 0:c5e2f793b59a 3155 /*! @brief Set the INITTRIGEN field to a new value. */
screamer 0:c5e2f793b59a 3156 #define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
screamer 0:c5e2f793b59a 3157 /*@}*/
screamer 0:c5e2f793b59a 3158
screamer 0:c5e2f793b59a 3159 /*!
screamer 0:c5e2f793b59a 3160 * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
screamer 0:c5e2f793b59a 3161 *
screamer 0:c5e2f793b59a 3162 * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
screamer 0:c5e2f793b59a 3163 * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
screamer 0:c5e2f793b59a 3164 * has no effect. If another channel trigger is generated before the clearing
screamer 0:c5e2f793b59a 3165 * sequence is completed, the sequence is reset so TRIGF remains set after the clear
screamer 0:c5e2f793b59a 3166 * sequence is completed for the earlier TRIGF.
screamer 0:c5e2f793b59a 3167 *
screamer 0:c5e2f793b59a 3168 * Values:
screamer 0:c5e2f793b59a 3169 * - 0 - No channel trigger was generated.
screamer 0:c5e2f793b59a 3170 * - 1 - A channel trigger was generated.
screamer 0:c5e2f793b59a 3171 */
screamer 0:c5e2f793b59a 3172 /*@{*/
screamer 0:c5e2f793b59a 3173 #define BP_FTM_EXTTRIG_TRIGF (7U) /*!< Bit position for FTM_EXTTRIG_TRIGF. */
screamer 0:c5e2f793b59a 3174 #define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /*!< Bit mask for FTM_EXTTRIG_TRIGF. */
screamer 0:c5e2f793b59a 3175 #define BS_FTM_EXTTRIG_TRIGF (1U) /*!< Bit field size in bits for FTM_EXTTRIG_TRIGF. */
screamer 0:c5e2f793b59a 3176
screamer 0:c5e2f793b59a 3177 /*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
screamer 0:c5e2f793b59a 3178 #define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
screamer 0:c5e2f793b59a 3179
screamer 0:c5e2f793b59a 3180 /*! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. */
screamer 0:c5e2f793b59a 3181 #define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF)
screamer 0:c5e2f793b59a 3182
screamer 0:c5e2f793b59a 3183 /*! @brief Set the TRIGF field to a new value. */
screamer 0:c5e2f793b59a 3184 #define BW_FTM_EXTTRIG_TRIGF(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF) = (v))
screamer 0:c5e2f793b59a 3185 /*@}*/
screamer 0:c5e2f793b59a 3186
screamer 0:c5e2f793b59a 3187 /*******************************************************************************
screamer 0:c5e2f793b59a 3188 * HW_FTM_POL - Channels Polarity
screamer 0:c5e2f793b59a 3189 ******************************************************************************/
screamer 0:c5e2f793b59a 3190
screamer 0:c5e2f793b59a 3191 /*!
screamer 0:c5e2f793b59a 3192 * @brief HW_FTM_POL - Channels Polarity (RW)
screamer 0:c5e2f793b59a 3193 *
screamer 0:c5e2f793b59a 3194 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 3195 *
screamer 0:c5e2f793b59a 3196 * This register defines the output polarity of the FTM channels. The safe value
screamer 0:c5e2f793b59a 3197 * that is driven in a channel output when the fault control is enabled and a
screamer 0:c5e2f793b59a 3198 * fault condition is detected is the inactive state of the channel. That is, the
screamer 0:c5e2f793b59a 3199 * safe value of a channel is the value of its POL bit.
screamer 0:c5e2f793b59a 3200 */
screamer 0:c5e2f793b59a 3201 typedef union _hw_ftm_pol
screamer 0:c5e2f793b59a 3202 {
screamer 0:c5e2f793b59a 3203 uint32_t U;
screamer 0:c5e2f793b59a 3204 struct _hw_ftm_pol_bitfields
screamer 0:c5e2f793b59a 3205 {
screamer 0:c5e2f793b59a 3206 uint32_t POL0 : 1; /*!< [0] Channel 0 Polarity */
screamer 0:c5e2f793b59a 3207 uint32_t POL1 : 1; /*!< [1] Channel 1 Polarity */
screamer 0:c5e2f793b59a 3208 uint32_t POL2 : 1; /*!< [2] Channel 2 Polarity */
screamer 0:c5e2f793b59a 3209 uint32_t POL3 : 1; /*!< [3] Channel 3 Polarity */
screamer 0:c5e2f793b59a 3210 uint32_t POL4 : 1; /*!< [4] Channel 4 Polarity */
screamer 0:c5e2f793b59a 3211 uint32_t POL5 : 1; /*!< [5] Channel 5 Polarity */
screamer 0:c5e2f793b59a 3212 uint32_t POL6 : 1; /*!< [6] Channel 6 Polarity */
screamer 0:c5e2f793b59a 3213 uint32_t POL7 : 1; /*!< [7] Channel 7 Polarity */
screamer 0:c5e2f793b59a 3214 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 3215 } B;
screamer 0:c5e2f793b59a 3216 } hw_ftm_pol_t;
screamer 0:c5e2f793b59a 3217
screamer 0:c5e2f793b59a 3218 /*!
screamer 0:c5e2f793b59a 3219 * @name Constants and macros for entire FTM_POL register
screamer 0:c5e2f793b59a 3220 */
screamer 0:c5e2f793b59a 3221 /*@{*/
screamer 0:c5e2f793b59a 3222 #define HW_FTM_POL_ADDR(x) ((x) + 0x70U)
screamer 0:c5e2f793b59a 3223
screamer 0:c5e2f793b59a 3224 #define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
screamer 0:c5e2f793b59a 3225 #define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
screamer 0:c5e2f793b59a 3226 #define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
screamer 0:c5e2f793b59a 3227 #define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v)))
screamer 0:c5e2f793b59a 3228 #define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 3229 #define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 3230 /*@}*/
screamer 0:c5e2f793b59a 3231
screamer 0:c5e2f793b59a 3232 /*
screamer 0:c5e2f793b59a 3233 * Constants & macros for individual FTM_POL bitfields
screamer 0:c5e2f793b59a 3234 */
screamer 0:c5e2f793b59a 3235
screamer 0:c5e2f793b59a 3236 /*!
screamer 0:c5e2f793b59a 3237 * @name Register FTM_POL, field POL0[0] (RW)
screamer 0:c5e2f793b59a 3238 *
screamer 0:c5e2f793b59a 3239 * Defines the polarity of the channel output. This field is write protected. It
screamer 0:c5e2f793b59a 3240 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3241 *
screamer 0:c5e2f793b59a 3242 * Values:
screamer 0:c5e2f793b59a 3243 * - 0 - The channel polarity is active high.
screamer 0:c5e2f793b59a 3244 * - 1 - The channel polarity is active low.
screamer 0:c5e2f793b59a 3245 */
screamer 0:c5e2f793b59a 3246 /*@{*/
screamer 0:c5e2f793b59a 3247 #define BP_FTM_POL_POL0 (0U) /*!< Bit position for FTM_POL_POL0. */
screamer 0:c5e2f793b59a 3248 #define BM_FTM_POL_POL0 (0x00000001U) /*!< Bit mask for FTM_POL_POL0. */
screamer 0:c5e2f793b59a 3249 #define BS_FTM_POL_POL0 (1U) /*!< Bit field size in bits for FTM_POL_POL0. */
screamer 0:c5e2f793b59a 3250
screamer 0:c5e2f793b59a 3251 /*! @brief Read current value of the FTM_POL_POL0 field. */
screamer 0:c5e2f793b59a 3252 #define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
screamer 0:c5e2f793b59a 3253
screamer 0:c5e2f793b59a 3254 /*! @brief Format value for bitfield FTM_POL_POL0. */
screamer 0:c5e2f793b59a 3255 #define BF_FTM_POL_POL0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0)
screamer 0:c5e2f793b59a 3256
screamer 0:c5e2f793b59a 3257 /*! @brief Set the POL0 field to a new value. */
screamer 0:c5e2f793b59a 3258 #define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
screamer 0:c5e2f793b59a 3259 /*@}*/
screamer 0:c5e2f793b59a 3260
screamer 0:c5e2f793b59a 3261 /*!
screamer 0:c5e2f793b59a 3262 * @name Register FTM_POL, field POL1[1] (RW)
screamer 0:c5e2f793b59a 3263 *
screamer 0:c5e2f793b59a 3264 * Defines the polarity of the channel output. This field is write protected. It
screamer 0:c5e2f793b59a 3265 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3266 *
screamer 0:c5e2f793b59a 3267 * Values:
screamer 0:c5e2f793b59a 3268 * - 0 - The channel polarity is active high.
screamer 0:c5e2f793b59a 3269 * - 1 - The channel polarity is active low.
screamer 0:c5e2f793b59a 3270 */
screamer 0:c5e2f793b59a 3271 /*@{*/
screamer 0:c5e2f793b59a 3272 #define BP_FTM_POL_POL1 (1U) /*!< Bit position for FTM_POL_POL1. */
screamer 0:c5e2f793b59a 3273 #define BM_FTM_POL_POL1 (0x00000002U) /*!< Bit mask for FTM_POL_POL1. */
screamer 0:c5e2f793b59a 3274 #define BS_FTM_POL_POL1 (1U) /*!< Bit field size in bits for FTM_POL_POL1. */
screamer 0:c5e2f793b59a 3275
screamer 0:c5e2f793b59a 3276 /*! @brief Read current value of the FTM_POL_POL1 field. */
screamer 0:c5e2f793b59a 3277 #define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
screamer 0:c5e2f793b59a 3278
screamer 0:c5e2f793b59a 3279 /*! @brief Format value for bitfield FTM_POL_POL1. */
screamer 0:c5e2f793b59a 3280 #define BF_FTM_POL_POL1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1)
screamer 0:c5e2f793b59a 3281
screamer 0:c5e2f793b59a 3282 /*! @brief Set the POL1 field to a new value. */
screamer 0:c5e2f793b59a 3283 #define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
screamer 0:c5e2f793b59a 3284 /*@}*/
screamer 0:c5e2f793b59a 3285
screamer 0:c5e2f793b59a 3286 /*!
screamer 0:c5e2f793b59a 3287 * @name Register FTM_POL, field POL2[2] (RW)
screamer 0:c5e2f793b59a 3288 *
screamer 0:c5e2f793b59a 3289 * Defines the polarity of the channel output. This field is write protected. It
screamer 0:c5e2f793b59a 3290 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3291 *
screamer 0:c5e2f793b59a 3292 * Values:
screamer 0:c5e2f793b59a 3293 * - 0 - The channel polarity is active high.
screamer 0:c5e2f793b59a 3294 * - 1 - The channel polarity is active low.
screamer 0:c5e2f793b59a 3295 */
screamer 0:c5e2f793b59a 3296 /*@{*/
screamer 0:c5e2f793b59a 3297 #define BP_FTM_POL_POL2 (2U) /*!< Bit position for FTM_POL_POL2. */
screamer 0:c5e2f793b59a 3298 #define BM_FTM_POL_POL2 (0x00000004U) /*!< Bit mask for FTM_POL_POL2. */
screamer 0:c5e2f793b59a 3299 #define BS_FTM_POL_POL2 (1U) /*!< Bit field size in bits for FTM_POL_POL2. */
screamer 0:c5e2f793b59a 3300
screamer 0:c5e2f793b59a 3301 /*! @brief Read current value of the FTM_POL_POL2 field. */
screamer 0:c5e2f793b59a 3302 #define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
screamer 0:c5e2f793b59a 3303
screamer 0:c5e2f793b59a 3304 /*! @brief Format value for bitfield FTM_POL_POL2. */
screamer 0:c5e2f793b59a 3305 #define BF_FTM_POL_POL2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2)
screamer 0:c5e2f793b59a 3306
screamer 0:c5e2f793b59a 3307 /*! @brief Set the POL2 field to a new value. */
screamer 0:c5e2f793b59a 3308 #define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
screamer 0:c5e2f793b59a 3309 /*@}*/
screamer 0:c5e2f793b59a 3310
screamer 0:c5e2f793b59a 3311 /*!
screamer 0:c5e2f793b59a 3312 * @name Register FTM_POL, field POL3[3] (RW)
screamer 0:c5e2f793b59a 3313 *
screamer 0:c5e2f793b59a 3314 * Defines the polarity of the channel output. This field is write protected. It
screamer 0:c5e2f793b59a 3315 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3316 *
screamer 0:c5e2f793b59a 3317 * Values:
screamer 0:c5e2f793b59a 3318 * - 0 - The channel polarity is active high.
screamer 0:c5e2f793b59a 3319 * - 1 - The channel polarity is active low.
screamer 0:c5e2f793b59a 3320 */
screamer 0:c5e2f793b59a 3321 /*@{*/
screamer 0:c5e2f793b59a 3322 #define BP_FTM_POL_POL3 (3U) /*!< Bit position for FTM_POL_POL3. */
screamer 0:c5e2f793b59a 3323 #define BM_FTM_POL_POL3 (0x00000008U) /*!< Bit mask for FTM_POL_POL3. */
screamer 0:c5e2f793b59a 3324 #define BS_FTM_POL_POL3 (1U) /*!< Bit field size in bits for FTM_POL_POL3. */
screamer 0:c5e2f793b59a 3325
screamer 0:c5e2f793b59a 3326 /*! @brief Read current value of the FTM_POL_POL3 field. */
screamer 0:c5e2f793b59a 3327 #define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
screamer 0:c5e2f793b59a 3328
screamer 0:c5e2f793b59a 3329 /*! @brief Format value for bitfield FTM_POL_POL3. */
screamer 0:c5e2f793b59a 3330 #define BF_FTM_POL_POL3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3)
screamer 0:c5e2f793b59a 3331
screamer 0:c5e2f793b59a 3332 /*! @brief Set the POL3 field to a new value. */
screamer 0:c5e2f793b59a 3333 #define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
screamer 0:c5e2f793b59a 3334 /*@}*/
screamer 0:c5e2f793b59a 3335
screamer 0:c5e2f793b59a 3336 /*!
screamer 0:c5e2f793b59a 3337 * @name Register FTM_POL, field POL4[4] (RW)
screamer 0:c5e2f793b59a 3338 *
screamer 0:c5e2f793b59a 3339 * Defines the polarity of the channel output. This field is write protected. It
screamer 0:c5e2f793b59a 3340 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3341 *
screamer 0:c5e2f793b59a 3342 * Values:
screamer 0:c5e2f793b59a 3343 * - 0 - The channel polarity is active high.
screamer 0:c5e2f793b59a 3344 * - 1 - The channel polarity is active low.
screamer 0:c5e2f793b59a 3345 */
screamer 0:c5e2f793b59a 3346 /*@{*/
screamer 0:c5e2f793b59a 3347 #define BP_FTM_POL_POL4 (4U) /*!< Bit position for FTM_POL_POL4. */
screamer 0:c5e2f793b59a 3348 #define BM_FTM_POL_POL4 (0x00000010U) /*!< Bit mask for FTM_POL_POL4. */
screamer 0:c5e2f793b59a 3349 #define BS_FTM_POL_POL4 (1U) /*!< Bit field size in bits for FTM_POL_POL4. */
screamer 0:c5e2f793b59a 3350
screamer 0:c5e2f793b59a 3351 /*! @brief Read current value of the FTM_POL_POL4 field. */
screamer 0:c5e2f793b59a 3352 #define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
screamer 0:c5e2f793b59a 3353
screamer 0:c5e2f793b59a 3354 /*! @brief Format value for bitfield FTM_POL_POL4. */
screamer 0:c5e2f793b59a 3355 #define BF_FTM_POL_POL4(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4)
screamer 0:c5e2f793b59a 3356
screamer 0:c5e2f793b59a 3357 /*! @brief Set the POL4 field to a new value. */
screamer 0:c5e2f793b59a 3358 #define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
screamer 0:c5e2f793b59a 3359 /*@}*/
screamer 0:c5e2f793b59a 3360
screamer 0:c5e2f793b59a 3361 /*!
screamer 0:c5e2f793b59a 3362 * @name Register FTM_POL, field POL5[5] (RW)
screamer 0:c5e2f793b59a 3363 *
screamer 0:c5e2f793b59a 3364 * Defines the polarity of the channel output. This field is write protected. It
screamer 0:c5e2f793b59a 3365 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3366 *
screamer 0:c5e2f793b59a 3367 * Values:
screamer 0:c5e2f793b59a 3368 * - 0 - The channel polarity is active high.
screamer 0:c5e2f793b59a 3369 * - 1 - The channel polarity is active low.
screamer 0:c5e2f793b59a 3370 */
screamer 0:c5e2f793b59a 3371 /*@{*/
screamer 0:c5e2f793b59a 3372 #define BP_FTM_POL_POL5 (5U) /*!< Bit position for FTM_POL_POL5. */
screamer 0:c5e2f793b59a 3373 #define BM_FTM_POL_POL5 (0x00000020U) /*!< Bit mask for FTM_POL_POL5. */
screamer 0:c5e2f793b59a 3374 #define BS_FTM_POL_POL5 (1U) /*!< Bit field size in bits for FTM_POL_POL5. */
screamer 0:c5e2f793b59a 3375
screamer 0:c5e2f793b59a 3376 /*! @brief Read current value of the FTM_POL_POL5 field. */
screamer 0:c5e2f793b59a 3377 #define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
screamer 0:c5e2f793b59a 3378
screamer 0:c5e2f793b59a 3379 /*! @brief Format value for bitfield FTM_POL_POL5. */
screamer 0:c5e2f793b59a 3380 #define BF_FTM_POL_POL5(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5)
screamer 0:c5e2f793b59a 3381
screamer 0:c5e2f793b59a 3382 /*! @brief Set the POL5 field to a new value. */
screamer 0:c5e2f793b59a 3383 #define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
screamer 0:c5e2f793b59a 3384 /*@}*/
screamer 0:c5e2f793b59a 3385
screamer 0:c5e2f793b59a 3386 /*!
screamer 0:c5e2f793b59a 3387 * @name Register FTM_POL, field POL6[6] (RW)
screamer 0:c5e2f793b59a 3388 *
screamer 0:c5e2f793b59a 3389 * Defines the polarity of the channel output. This field is write protected. It
screamer 0:c5e2f793b59a 3390 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3391 *
screamer 0:c5e2f793b59a 3392 * Values:
screamer 0:c5e2f793b59a 3393 * - 0 - The channel polarity is active high.
screamer 0:c5e2f793b59a 3394 * - 1 - The channel polarity is active low.
screamer 0:c5e2f793b59a 3395 */
screamer 0:c5e2f793b59a 3396 /*@{*/
screamer 0:c5e2f793b59a 3397 #define BP_FTM_POL_POL6 (6U) /*!< Bit position for FTM_POL_POL6. */
screamer 0:c5e2f793b59a 3398 #define BM_FTM_POL_POL6 (0x00000040U) /*!< Bit mask for FTM_POL_POL6. */
screamer 0:c5e2f793b59a 3399 #define BS_FTM_POL_POL6 (1U) /*!< Bit field size in bits for FTM_POL_POL6. */
screamer 0:c5e2f793b59a 3400
screamer 0:c5e2f793b59a 3401 /*! @brief Read current value of the FTM_POL_POL6 field. */
screamer 0:c5e2f793b59a 3402 #define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
screamer 0:c5e2f793b59a 3403
screamer 0:c5e2f793b59a 3404 /*! @brief Format value for bitfield FTM_POL_POL6. */
screamer 0:c5e2f793b59a 3405 #define BF_FTM_POL_POL6(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6)
screamer 0:c5e2f793b59a 3406
screamer 0:c5e2f793b59a 3407 /*! @brief Set the POL6 field to a new value. */
screamer 0:c5e2f793b59a 3408 #define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
screamer 0:c5e2f793b59a 3409 /*@}*/
screamer 0:c5e2f793b59a 3410
screamer 0:c5e2f793b59a 3411 /*!
screamer 0:c5e2f793b59a 3412 * @name Register FTM_POL, field POL7[7] (RW)
screamer 0:c5e2f793b59a 3413 *
screamer 0:c5e2f793b59a 3414 * Defines the polarity of the channel output. This field is write protected. It
screamer 0:c5e2f793b59a 3415 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3416 *
screamer 0:c5e2f793b59a 3417 * Values:
screamer 0:c5e2f793b59a 3418 * - 0 - The channel polarity is active high.
screamer 0:c5e2f793b59a 3419 * - 1 - The channel polarity is active low.
screamer 0:c5e2f793b59a 3420 */
screamer 0:c5e2f793b59a 3421 /*@{*/
screamer 0:c5e2f793b59a 3422 #define BP_FTM_POL_POL7 (7U) /*!< Bit position for FTM_POL_POL7. */
screamer 0:c5e2f793b59a 3423 #define BM_FTM_POL_POL7 (0x00000080U) /*!< Bit mask for FTM_POL_POL7. */
screamer 0:c5e2f793b59a 3424 #define BS_FTM_POL_POL7 (1U) /*!< Bit field size in bits for FTM_POL_POL7. */
screamer 0:c5e2f793b59a 3425
screamer 0:c5e2f793b59a 3426 /*! @brief Read current value of the FTM_POL_POL7 field. */
screamer 0:c5e2f793b59a 3427 #define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
screamer 0:c5e2f793b59a 3428
screamer 0:c5e2f793b59a 3429 /*! @brief Format value for bitfield FTM_POL_POL7. */
screamer 0:c5e2f793b59a 3430 #define BF_FTM_POL_POL7(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7)
screamer 0:c5e2f793b59a 3431
screamer 0:c5e2f793b59a 3432 /*! @brief Set the POL7 field to a new value. */
screamer 0:c5e2f793b59a 3433 #define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
screamer 0:c5e2f793b59a 3434 /*@}*/
screamer 0:c5e2f793b59a 3435
screamer 0:c5e2f793b59a 3436 /*******************************************************************************
screamer 0:c5e2f793b59a 3437 * HW_FTM_FMS - Fault Mode Status
screamer 0:c5e2f793b59a 3438 ******************************************************************************/
screamer 0:c5e2f793b59a 3439
screamer 0:c5e2f793b59a 3440 /*!
screamer 0:c5e2f793b59a 3441 * @brief HW_FTM_FMS - Fault Mode Status (RW)
screamer 0:c5e2f793b59a 3442 *
screamer 0:c5e2f793b59a 3443 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 3444 *
screamer 0:c5e2f793b59a 3445 * This register contains the fault detection flags, write protection enable
screamer 0:c5e2f793b59a 3446 * bit, and the logic OR of the enabled fault inputs.
screamer 0:c5e2f793b59a 3447 */
screamer 0:c5e2f793b59a 3448 typedef union _hw_ftm_fms
screamer 0:c5e2f793b59a 3449 {
screamer 0:c5e2f793b59a 3450 uint32_t U;
screamer 0:c5e2f793b59a 3451 struct _hw_ftm_fms_bitfields
screamer 0:c5e2f793b59a 3452 {
screamer 0:c5e2f793b59a 3453 uint32_t FAULTF0 : 1; /*!< [0] Fault Detection Flag 0 */
screamer 0:c5e2f793b59a 3454 uint32_t FAULTF1 : 1; /*!< [1] Fault Detection Flag 1 */
screamer 0:c5e2f793b59a 3455 uint32_t FAULTF2 : 1; /*!< [2] Fault Detection Flag 2 */
screamer 0:c5e2f793b59a 3456 uint32_t FAULTF3 : 1; /*!< [3] Fault Detection Flag 3 */
screamer 0:c5e2f793b59a 3457 uint32_t RESERVED0 : 1; /*!< [4] */
screamer 0:c5e2f793b59a 3458 uint32_t FAULTIN : 1; /*!< [5] Fault Inputs */
screamer 0:c5e2f793b59a 3459 uint32_t WPEN : 1; /*!< [6] Write Protection Enable */
screamer 0:c5e2f793b59a 3460 uint32_t FAULTF : 1; /*!< [7] Fault Detection Flag */
screamer 0:c5e2f793b59a 3461 uint32_t RESERVED1 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 3462 } B;
screamer 0:c5e2f793b59a 3463 } hw_ftm_fms_t;
screamer 0:c5e2f793b59a 3464
screamer 0:c5e2f793b59a 3465 /*!
screamer 0:c5e2f793b59a 3466 * @name Constants and macros for entire FTM_FMS register
screamer 0:c5e2f793b59a 3467 */
screamer 0:c5e2f793b59a 3468 /*@{*/
screamer 0:c5e2f793b59a 3469 #define HW_FTM_FMS_ADDR(x) ((x) + 0x74U)
screamer 0:c5e2f793b59a 3470
screamer 0:c5e2f793b59a 3471 #define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
screamer 0:c5e2f793b59a 3472 #define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
screamer 0:c5e2f793b59a 3473 #define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
screamer 0:c5e2f793b59a 3474 #define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v)))
screamer 0:c5e2f793b59a 3475 #define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 3476 #define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 3477 /*@}*/
screamer 0:c5e2f793b59a 3478
screamer 0:c5e2f793b59a 3479 /*
screamer 0:c5e2f793b59a 3480 * Constants & macros for individual FTM_FMS bitfields
screamer 0:c5e2f793b59a 3481 */
screamer 0:c5e2f793b59a 3482
screamer 0:c5e2f793b59a 3483 /*!
screamer 0:c5e2f793b59a 3484 * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
screamer 0:c5e2f793b59a 3485 *
screamer 0:c5e2f793b59a 3486 * Set by hardware when fault control is enabled, the corresponding fault input
screamer 0:c5e2f793b59a 3487 * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
screamer 0:c5e2f793b59a 3488 * by reading the FMS register while FAULTF0 is set and then writing a 0 to
screamer 0:c5e2f793b59a 3489 * FAULTF0 while there is no existing fault condition at the corresponding fault
screamer 0:c5e2f793b59a 3490 * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
screamer 0:c5e2f793b59a 3491 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
screamer 0:c5e2f793b59a 3492 * fault input before the clearing sequence is completed, the sequence is reset
screamer 0:c5e2f793b59a 3493 * so FAULTF0 remains set after the clearing sequence is completed for the
screamer 0:c5e2f793b59a 3494 * earlier fault condition.
screamer 0:c5e2f793b59a 3495 *
screamer 0:c5e2f793b59a 3496 * Values:
screamer 0:c5e2f793b59a 3497 * - 0 - No fault condition was detected at the fault input.
screamer 0:c5e2f793b59a 3498 * - 1 - A fault condition was detected at the fault input.
screamer 0:c5e2f793b59a 3499 */
screamer 0:c5e2f793b59a 3500 /*@{*/
screamer 0:c5e2f793b59a 3501 #define BP_FTM_FMS_FAULTF0 (0U) /*!< Bit position for FTM_FMS_FAULTF0. */
screamer 0:c5e2f793b59a 3502 #define BM_FTM_FMS_FAULTF0 (0x00000001U) /*!< Bit mask for FTM_FMS_FAULTF0. */
screamer 0:c5e2f793b59a 3503 #define BS_FTM_FMS_FAULTF0 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF0. */
screamer 0:c5e2f793b59a 3504
screamer 0:c5e2f793b59a 3505 /*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
screamer 0:c5e2f793b59a 3506 #define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
screamer 0:c5e2f793b59a 3507
screamer 0:c5e2f793b59a 3508 /*! @brief Format value for bitfield FTM_FMS_FAULTF0. */
screamer 0:c5e2f793b59a 3509 #define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0)
screamer 0:c5e2f793b59a 3510
screamer 0:c5e2f793b59a 3511 /*! @brief Set the FAULTF0 field to a new value. */
screamer 0:c5e2f793b59a 3512 #define BW_FTM_FMS_FAULTF0(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0) = (v))
screamer 0:c5e2f793b59a 3513 /*@}*/
screamer 0:c5e2f793b59a 3514
screamer 0:c5e2f793b59a 3515 /*!
screamer 0:c5e2f793b59a 3516 * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
screamer 0:c5e2f793b59a 3517 *
screamer 0:c5e2f793b59a 3518 * Set by hardware when fault control is enabled, the corresponding fault input
screamer 0:c5e2f793b59a 3519 * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
screamer 0:c5e2f793b59a 3520 * by reading the FMS register while FAULTF1 is set and then writing a 0 to
screamer 0:c5e2f793b59a 3521 * FAULTF1 while there is no existing fault condition at the corresponding fault
screamer 0:c5e2f793b59a 3522 * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
screamer 0:c5e2f793b59a 3523 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
screamer 0:c5e2f793b59a 3524 * fault input before the clearing sequence is completed, the sequence is reset
screamer 0:c5e2f793b59a 3525 * so FAULTF1 remains set after the clearing sequence is completed for the
screamer 0:c5e2f793b59a 3526 * earlier fault condition.
screamer 0:c5e2f793b59a 3527 *
screamer 0:c5e2f793b59a 3528 * Values:
screamer 0:c5e2f793b59a 3529 * - 0 - No fault condition was detected at the fault input.
screamer 0:c5e2f793b59a 3530 * - 1 - A fault condition was detected at the fault input.
screamer 0:c5e2f793b59a 3531 */
screamer 0:c5e2f793b59a 3532 /*@{*/
screamer 0:c5e2f793b59a 3533 #define BP_FTM_FMS_FAULTF1 (1U) /*!< Bit position for FTM_FMS_FAULTF1. */
screamer 0:c5e2f793b59a 3534 #define BM_FTM_FMS_FAULTF1 (0x00000002U) /*!< Bit mask for FTM_FMS_FAULTF1. */
screamer 0:c5e2f793b59a 3535 #define BS_FTM_FMS_FAULTF1 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF1. */
screamer 0:c5e2f793b59a 3536
screamer 0:c5e2f793b59a 3537 /*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
screamer 0:c5e2f793b59a 3538 #define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
screamer 0:c5e2f793b59a 3539
screamer 0:c5e2f793b59a 3540 /*! @brief Format value for bitfield FTM_FMS_FAULTF1. */
screamer 0:c5e2f793b59a 3541 #define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1)
screamer 0:c5e2f793b59a 3542
screamer 0:c5e2f793b59a 3543 /*! @brief Set the FAULTF1 field to a new value. */
screamer 0:c5e2f793b59a 3544 #define BW_FTM_FMS_FAULTF1(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1) = (v))
screamer 0:c5e2f793b59a 3545 /*@}*/
screamer 0:c5e2f793b59a 3546
screamer 0:c5e2f793b59a 3547 /*!
screamer 0:c5e2f793b59a 3548 * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
screamer 0:c5e2f793b59a 3549 *
screamer 0:c5e2f793b59a 3550 * Set by hardware when fault control is enabled, the corresponding fault input
screamer 0:c5e2f793b59a 3551 * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
screamer 0:c5e2f793b59a 3552 * by reading the FMS register while FAULTF2 is set and then writing a 0 to
screamer 0:c5e2f793b59a 3553 * FAULTF2 while there is no existing fault condition at the corresponding fault
screamer 0:c5e2f793b59a 3554 * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
screamer 0:c5e2f793b59a 3555 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
screamer 0:c5e2f793b59a 3556 * fault input before the clearing sequence is completed, the sequence is reset
screamer 0:c5e2f793b59a 3557 * so FAULTF2 remains set after the clearing sequence is completed for the
screamer 0:c5e2f793b59a 3558 * earlier fault condition.
screamer 0:c5e2f793b59a 3559 *
screamer 0:c5e2f793b59a 3560 * Values:
screamer 0:c5e2f793b59a 3561 * - 0 - No fault condition was detected at the fault input.
screamer 0:c5e2f793b59a 3562 * - 1 - A fault condition was detected at the fault input.
screamer 0:c5e2f793b59a 3563 */
screamer 0:c5e2f793b59a 3564 /*@{*/
screamer 0:c5e2f793b59a 3565 #define BP_FTM_FMS_FAULTF2 (2U) /*!< Bit position for FTM_FMS_FAULTF2. */
screamer 0:c5e2f793b59a 3566 #define BM_FTM_FMS_FAULTF2 (0x00000004U) /*!< Bit mask for FTM_FMS_FAULTF2. */
screamer 0:c5e2f793b59a 3567 #define BS_FTM_FMS_FAULTF2 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF2. */
screamer 0:c5e2f793b59a 3568
screamer 0:c5e2f793b59a 3569 /*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
screamer 0:c5e2f793b59a 3570 #define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
screamer 0:c5e2f793b59a 3571
screamer 0:c5e2f793b59a 3572 /*! @brief Format value for bitfield FTM_FMS_FAULTF2. */
screamer 0:c5e2f793b59a 3573 #define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2)
screamer 0:c5e2f793b59a 3574
screamer 0:c5e2f793b59a 3575 /*! @brief Set the FAULTF2 field to a new value. */
screamer 0:c5e2f793b59a 3576 #define BW_FTM_FMS_FAULTF2(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2) = (v))
screamer 0:c5e2f793b59a 3577 /*@}*/
screamer 0:c5e2f793b59a 3578
screamer 0:c5e2f793b59a 3579 /*!
screamer 0:c5e2f793b59a 3580 * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
screamer 0:c5e2f793b59a 3581 *
screamer 0:c5e2f793b59a 3582 * Set by hardware when fault control is enabled, the corresponding fault input
screamer 0:c5e2f793b59a 3583 * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
screamer 0:c5e2f793b59a 3584 * by reading the FMS register while FAULTF3 is set and then writing a 0 to
screamer 0:c5e2f793b59a 3585 * FAULTF3 while there is no existing fault condition at the corresponding fault
screamer 0:c5e2f793b59a 3586 * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
screamer 0:c5e2f793b59a 3587 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
screamer 0:c5e2f793b59a 3588 * fault input before the clearing sequence is completed, the sequence is reset
screamer 0:c5e2f793b59a 3589 * so FAULTF3 remains set after the clearing sequence is completed for the
screamer 0:c5e2f793b59a 3590 * earlier fault condition.
screamer 0:c5e2f793b59a 3591 *
screamer 0:c5e2f793b59a 3592 * Values:
screamer 0:c5e2f793b59a 3593 * - 0 - No fault condition was detected at the fault input.
screamer 0:c5e2f793b59a 3594 * - 1 - A fault condition was detected at the fault input.
screamer 0:c5e2f793b59a 3595 */
screamer 0:c5e2f793b59a 3596 /*@{*/
screamer 0:c5e2f793b59a 3597 #define BP_FTM_FMS_FAULTF3 (3U) /*!< Bit position for FTM_FMS_FAULTF3. */
screamer 0:c5e2f793b59a 3598 #define BM_FTM_FMS_FAULTF3 (0x00000008U) /*!< Bit mask for FTM_FMS_FAULTF3. */
screamer 0:c5e2f793b59a 3599 #define BS_FTM_FMS_FAULTF3 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF3. */
screamer 0:c5e2f793b59a 3600
screamer 0:c5e2f793b59a 3601 /*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
screamer 0:c5e2f793b59a 3602 #define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
screamer 0:c5e2f793b59a 3603
screamer 0:c5e2f793b59a 3604 /*! @brief Format value for bitfield FTM_FMS_FAULTF3. */
screamer 0:c5e2f793b59a 3605 #define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3)
screamer 0:c5e2f793b59a 3606
screamer 0:c5e2f793b59a 3607 /*! @brief Set the FAULTF3 field to a new value. */
screamer 0:c5e2f793b59a 3608 #define BW_FTM_FMS_FAULTF3(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3) = (v))
screamer 0:c5e2f793b59a 3609 /*@}*/
screamer 0:c5e2f793b59a 3610
screamer 0:c5e2f793b59a 3611 /*!
screamer 0:c5e2f793b59a 3612 * @name Register FTM_FMS, field FAULTIN[5] (RO)
screamer 0:c5e2f793b59a 3613 *
screamer 0:c5e2f793b59a 3614 * Represents the logic OR of the enabled fault inputs after their filter (if
screamer 0:c5e2f793b59a 3615 * their filter is enabled) when fault control is enabled.
screamer 0:c5e2f793b59a 3616 *
screamer 0:c5e2f793b59a 3617 * Values:
screamer 0:c5e2f793b59a 3618 * - 0 - The logic OR of the enabled fault inputs is 0.
screamer 0:c5e2f793b59a 3619 * - 1 - The logic OR of the enabled fault inputs is 1.
screamer 0:c5e2f793b59a 3620 */
screamer 0:c5e2f793b59a 3621 /*@{*/
screamer 0:c5e2f793b59a 3622 #define BP_FTM_FMS_FAULTIN (5U) /*!< Bit position for FTM_FMS_FAULTIN. */
screamer 0:c5e2f793b59a 3623 #define BM_FTM_FMS_FAULTIN (0x00000020U) /*!< Bit mask for FTM_FMS_FAULTIN. */
screamer 0:c5e2f793b59a 3624 #define BS_FTM_FMS_FAULTIN (1U) /*!< Bit field size in bits for FTM_FMS_FAULTIN. */
screamer 0:c5e2f793b59a 3625
screamer 0:c5e2f793b59a 3626 /*! @brief Read current value of the FTM_FMS_FAULTIN field. */
screamer 0:c5e2f793b59a 3627 #define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
screamer 0:c5e2f793b59a 3628 /*@}*/
screamer 0:c5e2f793b59a 3629
screamer 0:c5e2f793b59a 3630 /*!
screamer 0:c5e2f793b59a 3631 * @name Register FTM_FMS, field WPEN[6] (RW)
screamer 0:c5e2f793b59a 3632 *
screamer 0:c5e2f793b59a 3633 * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
screamer 0:c5e2f793b59a 3634 * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
screamer 0:c5e2f793b59a 3635 * WPDIS. Writing 0 to WPEN has no effect.
screamer 0:c5e2f793b59a 3636 *
screamer 0:c5e2f793b59a 3637 * Values:
screamer 0:c5e2f793b59a 3638 * - 0 - Write protection is disabled. Write protected bits can be written.
screamer 0:c5e2f793b59a 3639 * - 1 - Write protection is enabled. Write protected bits cannot be written.
screamer 0:c5e2f793b59a 3640 */
screamer 0:c5e2f793b59a 3641 /*@{*/
screamer 0:c5e2f793b59a 3642 #define BP_FTM_FMS_WPEN (6U) /*!< Bit position for FTM_FMS_WPEN. */
screamer 0:c5e2f793b59a 3643 #define BM_FTM_FMS_WPEN (0x00000040U) /*!< Bit mask for FTM_FMS_WPEN. */
screamer 0:c5e2f793b59a 3644 #define BS_FTM_FMS_WPEN (1U) /*!< Bit field size in bits for FTM_FMS_WPEN. */
screamer 0:c5e2f793b59a 3645
screamer 0:c5e2f793b59a 3646 /*! @brief Read current value of the FTM_FMS_WPEN field. */
screamer 0:c5e2f793b59a 3647 #define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
screamer 0:c5e2f793b59a 3648
screamer 0:c5e2f793b59a 3649 /*! @brief Format value for bitfield FTM_FMS_WPEN. */
screamer 0:c5e2f793b59a 3650 #define BF_FTM_FMS_WPEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN)
screamer 0:c5e2f793b59a 3651
screamer 0:c5e2f793b59a 3652 /*! @brief Set the WPEN field to a new value. */
screamer 0:c5e2f793b59a 3653 #define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
screamer 0:c5e2f793b59a 3654 /*@}*/
screamer 0:c5e2f793b59a 3655
screamer 0:c5e2f793b59a 3656 /*!
screamer 0:c5e2f793b59a 3657 * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
screamer 0:c5e2f793b59a 3658 *
screamer 0:c5e2f793b59a 3659 * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
screamer 0:c5e2f793b59a 3660 * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
screamer 0:c5e2f793b59a 3661 * a 0 to FAULTF while there is no existing fault condition at the enabled fault
screamer 0:c5e2f793b59a 3662 * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
screamer 0:c5e2f793b59a 3663 * detected in an enabled fault input before the clearing sequence is completed, the
screamer 0:c5e2f793b59a 3664 * sequence is reset so FAULTF remains set after the clearing sequence is
screamer 0:c5e2f793b59a 3665 * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
screamer 0:c5e2f793b59a 3666 * are cleared individually.
screamer 0:c5e2f793b59a 3667 *
screamer 0:c5e2f793b59a 3668 * Values:
screamer 0:c5e2f793b59a 3669 * - 0 - No fault condition was detected.
screamer 0:c5e2f793b59a 3670 * - 1 - A fault condition was detected.
screamer 0:c5e2f793b59a 3671 */
screamer 0:c5e2f793b59a 3672 /*@{*/
screamer 0:c5e2f793b59a 3673 #define BP_FTM_FMS_FAULTF (7U) /*!< Bit position for FTM_FMS_FAULTF. */
screamer 0:c5e2f793b59a 3674 #define BM_FTM_FMS_FAULTF (0x00000080U) /*!< Bit mask for FTM_FMS_FAULTF. */
screamer 0:c5e2f793b59a 3675 #define BS_FTM_FMS_FAULTF (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF. */
screamer 0:c5e2f793b59a 3676
screamer 0:c5e2f793b59a 3677 /*! @brief Read current value of the FTM_FMS_FAULTF field. */
screamer 0:c5e2f793b59a 3678 #define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
screamer 0:c5e2f793b59a 3679
screamer 0:c5e2f793b59a 3680 /*! @brief Format value for bitfield FTM_FMS_FAULTF. */
screamer 0:c5e2f793b59a 3681 #define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF)
screamer 0:c5e2f793b59a 3682
screamer 0:c5e2f793b59a 3683 /*! @brief Set the FAULTF field to a new value. */
screamer 0:c5e2f793b59a 3684 #define BW_FTM_FMS_FAULTF(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF) = (v))
screamer 0:c5e2f793b59a 3685 /*@}*/
screamer 0:c5e2f793b59a 3686
screamer 0:c5e2f793b59a 3687 /*******************************************************************************
screamer 0:c5e2f793b59a 3688 * HW_FTM_FILTER - Input Capture Filter Control
screamer 0:c5e2f793b59a 3689 ******************************************************************************/
screamer 0:c5e2f793b59a 3690
screamer 0:c5e2f793b59a 3691 /*!
screamer 0:c5e2f793b59a 3692 * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
screamer 0:c5e2f793b59a 3693 *
screamer 0:c5e2f793b59a 3694 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 3695 *
screamer 0:c5e2f793b59a 3696 * This register selects the filter value for the inputs of channels. Channels
screamer 0:c5e2f793b59a 3697 * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
screamer 0:c5e2f793b59a 3698 * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
screamer 0:c5e2f793b59a 3699 * in input modes. Failure to do this could result in a missing valid signal.
screamer 0:c5e2f793b59a 3700 */
screamer 0:c5e2f793b59a 3701 typedef union _hw_ftm_filter
screamer 0:c5e2f793b59a 3702 {
screamer 0:c5e2f793b59a 3703 uint32_t U;
screamer 0:c5e2f793b59a 3704 struct _hw_ftm_filter_bitfields
screamer 0:c5e2f793b59a 3705 {
screamer 0:c5e2f793b59a 3706 uint32_t CH0FVAL : 4; /*!< [3:0] Channel 0 Input Filter */
screamer 0:c5e2f793b59a 3707 uint32_t CH1FVAL : 4; /*!< [7:4] Channel 1 Input Filter */
screamer 0:c5e2f793b59a 3708 uint32_t CH2FVAL : 4; /*!< [11:8] Channel 2 Input Filter */
screamer 0:c5e2f793b59a 3709 uint32_t CH3FVAL : 4; /*!< [15:12] Channel 3 Input Filter */
screamer 0:c5e2f793b59a 3710 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 3711 } B;
screamer 0:c5e2f793b59a 3712 } hw_ftm_filter_t;
screamer 0:c5e2f793b59a 3713
screamer 0:c5e2f793b59a 3714 /*!
screamer 0:c5e2f793b59a 3715 * @name Constants and macros for entire FTM_FILTER register
screamer 0:c5e2f793b59a 3716 */
screamer 0:c5e2f793b59a 3717 /*@{*/
screamer 0:c5e2f793b59a 3718 #define HW_FTM_FILTER_ADDR(x) ((x) + 0x78U)
screamer 0:c5e2f793b59a 3719
screamer 0:c5e2f793b59a 3720 #define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
screamer 0:c5e2f793b59a 3721 #define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
screamer 0:c5e2f793b59a 3722 #define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
screamer 0:c5e2f793b59a 3723 #define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v)))
screamer 0:c5e2f793b59a 3724 #define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 3725 #define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 3726 /*@}*/
screamer 0:c5e2f793b59a 3727
screamer 0:c5e2f793b59a 3728 /*
screamer 0:c5e2f793b59a 3729 * Constants & macros for individual FTM_FILTER bitfields
screamer 0:c5e2f793b59a 3730 */
screamer 0:c5e2f793b59a 3731
screamer 0:c5e2f793b59a 3732 /*!
screamer 0:c5e2f793b59a 3733 * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
screamer 0:c5e2f793b59a 3734 *
screamer 0:c5e2f793b59a 3735 * Selects the filter value for the channel input. The filter is disabled when
screamer 0:c5e2f793b59a 3736 * the value is zero.
screamer 0:c5e2f793b59a 3737 */
screamer 0:c5e2f793b59a 3738 /*@{*/
screamer 0:c5e2f793b59a 3739 #define BP_FTM_FILTER_CH0FVAL (0U) /*!< Bit position for FTM_FILTER_CH0FVAL. */
screamer 0:c5e2f793b59a 3740 #define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /*!< Bit mask for FTM_FILTER_CH0FVAL. */
screamer 0:c5e2f793b59a 3741 #define BS_FTM_FILTER_CH0FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH0FVAL. */
screamer 0:c5e2f793b59a 3742
screamer 0:c5e2f793b59a 3743 /*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
screamer 0:c5e2f793b59a 3744 #define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
screamer 0:c5e2f793b59a 3745
screamer 0:c5e2f793b59a 3746 /*! @brief Format value for bitfield FTM_FILTER_CH0FVAL. */
screamer 0:c5e2f793b59a 3747 #define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL)
screamer 0:c5e2f793b59a 3748
screamer 0:c5e2f793b59a 3749 /*! @brief Set the CH0FVAL field to a new value. */
screamer 0:c5e2f793b59a 3750 #define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
screamer 0:c5e2f793b59a 3751 /*@}*/
screamer 0:c5e2f793b59a 3752
screamer 0:c5e2f793b59a 3753 /*!
screamer 0:c5e2f793b59a 3754 * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
screamer 0:c5e2f793b59a 3755 *
screamer 0:c5e2f793b59a 3756 * Selects the filter value for the channel input. The filter is disabled when
screamer 0:c5e2f793b59a 3757 * the value is zero.
screamer 0:c5e2f793b59a 3758 */
screamer 0:c5e2f793b59a 3759 /*@{*/
screamer 0:c5e2f793b59a 3760 #define BP_FTM_FILTER_CH1FVAL (4U) /*!< Bit position for FTM_FILTER_CH1FVAL. */
screamer 0:c5e2f793b59a 3761 #define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /*!< Bit mask for FTM_FILTER_CH1FVAL. */
screamer 0:c5e2f793b59a 3762 #define BS_FTM_FILTER_CH1FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH1FVAL. */
screamer 0:c5e2f793b59a 3763
screamer 0:c5e2f793b59a 3764 /*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
screamer 0:c5e2f793b59a 3765 #define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
screamer 0:c5e2f793b59a 3766
screamer 0:c5e2f793b59a 3767 /*! @brief Format value for bitfield FTM_FILTER_CH1FVAL. */
screamer 0:c5e2f793b59a 3768 #define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL)
screamer 0:c5e2f793b59a 3769
screamer 0:c5e2f793b59a 3770 /*! @brief Set the CH1FVAL field to a new value. */
screamer 0:c5e2f793b59a 3771 #define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
screamer 0:c5e2f793b59a 3772 /*@}*/
screamer 0:c5e2f793b59a 3773
screamer 0:c5e2f793b59a 3774 /*!
screamer 0:c5e2f793b59a 3775 * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
screamer 0:c5e2f793b59a 3776 *
screamer 0:c5e2f793b59a 3777 * Selects the filter value for the channel input. The filter is disabled when
screamer 0:c5e2f793b59a 3778 * the value is zero.
screamer 0:c5e2f793b59a 3779 */
screamer 0:c5e2f793b59a 3780 /*@{*/
screamer 0:c5e2f793b59a 3781 #define BP_FTM_FILTER_CH2FVAL (8U) /*!< Bit position for FTM_FILTER_CH2FVAL. */
screamer 0:c5e2f793b59a 3782 #define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /*!< Bit mask for FTM_FILTER_CH2FVAL. */
screamer 0:c5e2f793b59a 3783 #define BS_FTM_FILTER_CH2FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH2FVAL. */
screamer 0:c5e2f793b59a 3784
screamer 0:c5e2f793b59a 3785 /*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
screamer 0:c5e2f793b59a 3786 #define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
screamer 0:c5e2f793b59a 3787
screamer 0:c5e2f793b59a 3788 /*! @brief Format value for bitfield FTM_FILTER_CH2FVAL. */
screamer 0:c5e2f793b59a 3789 #define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL)
screamer 0:c5e2f793b59a 3790
screamer 0:c5e2f793b59a 3791 /*! @brief Set the CH2FVAL field to a new value. */
screamer 0:c5e2f793b59a 3792 #define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
screamer 0:c5e2f793b59a 3793 /*@}*/
screamer 0:c5e2f793b59a 3794
screamer 0:c5e2f793b59a 3795 /*!
screamer 0:c5e2f793b59a 3796 * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
screamer 0:c5e2f793b59a 3797 *
screamer 0:c5e2f793b59a 3798 * Selects the filter value for the channel input. The filter is disabled when
screamer 0:c5e2f793b59a 3799 * the value is zero.
screamer 0:c5e2f793b59a 3800 */
screamer 0:c5e2f793b59a 3801 /*@{*/
screamer 0:c5e2f793b59a 3802 #define BP_FTM_FILTER_CH3FVAL (12U) /*!< Bit position for FTM_FILTER_CH3FVAL. */
screamer 0:c5e2f793b59a 3803 #define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /*!< Bit mask for FTM_FILTER_CH3FVAL. */
screamer 0:c5e2f793b59a 3804 #define BS_FTM_FILTER_CH3FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH3FVAL. */
screamer 0:c5e2f793b59a 3805
screamer 0:c5e2f793b59a 3806 /*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
screamer 0:c5e2f793b59a 3807 #define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
screamer 0:c5e2f793b59a 3808
screamer 0:c5e2f793b59a 3809 /*! @brief Format value for bitfield FTM_FILTER_CH3FVAL. */
screamer 0:c5e2f793b59a 3810 #define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL)
screamer 0:c5e2f793b59a 3811
screamer 0:c5e2f793b59a 3812 /*! @brief Set the CH3FVAL field to a new value. */
screamer 0:c5e2f793b59a 3813 #define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
screamer 0:c5e2f793b59a 3814 /*@}*/
screamer 0:c5e2f793b59a 3815
screamer 0:c5e2f793b59a 3816 /*******************************************************************************
screamer 0:c5e2f793b59a 3817 * HW_FTM_FLTCTRL - Fault Control
screamer 0:c5e2f793b59a 3818 ******************************************************************************/
screamer 0:c5e2f793b59a 3819
screamer 0:c5e2f793b59a 3820 /*!
screamer 0:c5e2f793b59a 3821 * @brief HW_FTM_FLTCTRL - Fault Control (RW)
screamer 0:c5e2f793b59a 3822 *
screamer 0:c5e2f793b59a 3823 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 3824 *
screamer 0:c5e2f793b59a 3825 * This register selects the filter value for the fault inputs, enables the
screamer 0:c5e2f793b59a 3826 * fault inputs and the fault inputs filter.
screamer 0:c5e2f793b59a 3827 */
screamer 0:c5e2f793b59a 3828 typedef union _hw_ftm_fltctrl
screamer 0:c5e2f793b59a 3829 {
screamer 0:c5e2f793b59a 3830 uint32_t U;
screamer 0:c5e2f793b59a 3831 struct _hw_ftm_fltctrl_bitfields
screamer 0:c5e2f793b59a 3832 {
screamer 0:c5e2f793b59a 3833 uint32_t FAULT0EN : 1; /*!< [0] Fault Input 0 Enable */
screamer 0:c5e2f793b59a 3834 uint32_t FAULT1EN : 1; /*!< [1] Fault Input 1 Enable */
screamer 0:c5e2f793b59a 3835 uint32_t FAULT2EN : 1; /*!< [2] Fault Input 2 Enable */
screamer 0:c5e2f793b59a 3836 uint32_t FAULT3EN : 1; /*!< [3] Fault Input 3 Enable */
screamer 0:c5e2f793b59a 3837 uint32_t FFLTR0EN : 1; /*!< [4] Fault Input 0 Filter Enable */
screamer 0:c5e2f793b59a 3838 uint32_t FFLTR1EN : 1; /*!< [5] Fault Input 1 Filter Enable */
screamer 0:c5e2f793b59a 3839 uint32_t FFLTR2EN : 1; /*!< [6] Fault Input 2 Filter Enable */
screamer 0:c5e2f793b59a 3840 uint32_t FFLTR3EN : 1; /*!< [7] Fault Input 3 Filter Enable */
screamer 0:c5e2f793b59a 3841 uint32_t FFVAL : 4; /*!< [11:8] Fault Input Filter */
screamer 0:c5e2f793b59a 3842 uint32_t RESERVED0 : 20; /*!< [31:12] */
screamer 0:c5e2f793b59a 3843 } B;
screamer 0:c5e2f793b59a 3844 } hw_ftm_fltctrl_t;
screamer 0:c5e2f793b59a 3845
screamer 0:c5e2f793b59a 3846 /*!
screamer 0:c5e2f793b59a 3847 * @name Constants and macros for entire FTM_FLTCTRL register
screamer 0:c5e2f793b59a 3848 */
screamer 0:c5e2f793b59a 3849 /*@{*/
screamer 0:c5e2f793b59a 3850 #define HW_FTM_FLTCTRL_ADDR(x) ((x) + 0x7CU)
screamer 0:c5e2f793b59a 3851
screamer 0:c5e2f793b59a 3852 #define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
screamer 0:c5e2f793b59a 3853 #define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
screamer 0:c5e2f793b59a 3854 #define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
screamer 0:c5e2f793b59a 3855 #define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v)))
screamer 0:c5e2f793b59a 3856 #define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 3857 #define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 3858 /*@}*/
screamer 0:c5e2f793b59a 3859
screamer 0:c5e2f793b59a 3860 /*
screamer 0:c5e2f793b59a 3861 * Constants & macros for individual FTM_FLTCTRL bitfields
screamer 0:c5e2f793b59a 3862 */
screamer 0:c5e2f793b59a 3863
screamer 0:c5e2f793b59a 3864 /*!
screamer 0:c5e2f793b59a 3865 * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
screamer 0:c5e2f793b59a 3866 *
screamer 0:c5e2f793b59a 3867 * Enables the fault input. This field is write protected. It can be written
screamer 0:c5e2f793b59a 3868 * only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3869 *
screamer 0:c5e2f793b59a 3870 * Values:
screamer 0:c5e2f793b59a 3871 * - 0 - Fault input is disabled.
screamer 0:c5e2f793b59a 3872 * - 1 - Fault input is enabled.
screamer 0:c5e2f793b59a 3873 */
screamer 0:c5e2f793b59a 3874 /*@{*/
screamer 0:c5e2f793b59a 3875 #define BP_FTM_FLTCTRL_FAULT0EN (0U) /*!< Bit position for FTM_FLTCTRL_FAULT0EN. */
screamer 0:c5e2f793b59a 3876 #define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /*!< Bit mask for FTM_FLTCTRL_FAULT0EN. */
screamer 0:c5e2f793b59a 3877 #define BS_FTM_FLTCTRL_FAULT0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. */
screamer 0:c5e2f793b59a 3878
screamer 0:c5e2f793b59a 3879 /*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
screamer 0:c5e2f793b59a 3880 #define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
screamer 0:c5e2f793b59a 3881
screamer 0:c5e2f793b59a 3882 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. */
screamer 0:c5e2f793b59a 3883 #define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN)
screamer 0:c5e2f793b59a 3884
screamer 0:c5e2f793b59a 3885 /*! @brief Set the FAULT0EN field to a new value. */
screamer 0:c5e2f793b59a 3886 #define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
screamer 0:c5e2f793b59a 3887 /*@}*/
screamer 0:c5e2f793b59a 3888
screamer 0:c5e2f793b59a 3889 /*!
screamer 0:c5e2f793b59a 3890 * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
screamer 0:c5e2f793b59a 3891 *
screamer 0:c5e2f793b59a 3892 * Enables the fault input. This field is write protected. It can be written
screamer 0:c5e2f793b59a 3893 * only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3894 *
screamer 0:c5e2f793b59a 3895 * Values:
screamer 0:c5e2f793b59a 3896 * - 0 - Fault input is disabled.
screamer 0:c5e2f793b59a 3897 * - 1 - Fault input is enabled.
screamer 0:c5e2f793b59a 3898 */
screamer 0:c5e2f793b59a 3899 /*@{*/
screamer 0:c5e2f793b59a 3900 #define BP_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit position for FTM_FLTCTRL_FAULT1EN. */
screamer 0:c5e2f793b59a 3901 #define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /*!< Bit mask for FTM_FLTCTRL_FAULT1EN. */
screamer 0:c5e2f793b59a 3902 #define BS_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. */
screamer 0:c5e2f793b59a 3903
screamer 0:c5e2f793b59a 3904 /*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
screamer 0:c5e2f793b59a 3905 #define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
screamer 0:c5e2f793b59a 3906
screamer 0:c5e2f793b59a 3907 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. */
screamer 0:c5e2f793b59a 3908 #define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN)
screamer 0:c5e2f793b59a 3909
screamer 0:c5e2f793b59a 3910 /*! @brief Set the FAULT1EN field to a new value. */
screamer 0:c5e2f793b59a 3911 #define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
screamer 0:c5e2f793b59a 3912 /*@}*/
screamer 0:c5e2f793b59a 3913
screamer 0:c5e2f793b59a 3914 /*!
screamer 0:c5e2f793b59a 3915 * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
screamer 0:c5e2f793b59a 3916 *
screamer 0:c5e2f793b59a 3917 * Enables the fault input. This field is write protected. It can be written
screamer 0:c5e2f793b59a 3918 * only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3919 *
screamer 0:c5e2f793b59a 3920 * Values:
screamer 0:c5e2f793b59a 3921 * - 0 - Fault input is disabled.
screamer 0:c5e2f793b59a 3922 * - 1 - Fault input is enabled.
screamer 0:c5e2f793b59a 3923 */
screamer 0:c5e2f793b59a 3924 /*@{*/
screamer 0:c5e2f793b59a 3925 #define BP_FTM_FLTCTRL_FAULT2EN (2U) /*!< Bit position for FTM_FLTCTRL_FAULT2EN. */
screamer 0:c5e2f793b59a 3926 #define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /*!< Bit mask for FTM_FLTCTRL_FAULT2EN. */
screamer 0:c5e2f793b59a 3927 #define BS_FTM_FLTCTRL_FAULT2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. */
screamer 0:c5e2f793b59a 3928
screamer 0:c5e2f793b59a 3929 /*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
screamer 0:c5e2f793b59a 3930 #define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
screamer 0:c5e2f793b59a 3931
screamer 0:c5e2f793b59a 3932 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. */
screamer 0:c5e2f793b59a 3933 #define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN)
screamer 0:c5e2f793b59a 3934
screamer 0:c5e2f793b59a 3935 /*! @brief Set the FAULT2EN field to a new value. */
screamer 0:c5e2f793b59a 3936 #define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
screamer 0:c5e2f793b59a 3937 /*@}*/
screamer 0:c5e2f793b59a 3938
screamer 0:c5e2f793b59a 3939 /*!
screamer 0:c5e2f793b59a 3940 * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
screamer 0:c5e2f793b59a 3941 *
screamer 0:c5e2f793b59a 3942 * Enables the fault input. This field is write protected. It can be written
screamer 0:c5e2f793b59a 3943 * only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3944 *
screamer 0:c5e2f793b59a 3945 * Values:
screamer 0:c5e2f793b59a 3946 * - 0 - Fault input is disabled.
screamer 0:c5e2f793b59a 3947 * - 1 - Fault input is enabled.
screamer 0:c5e2f793b59a 3948 */
screamer 0:c5e2f793b59a 3949 /*@{*/
screamer 0:c5e2f793b59a 3950 #define BP_FTM_FLTCTRL_FAULT3EN (3U) /*!< Bit position for FTM_FLTCTRL_FAULT3EN. */
screamer 0:c5e2f793b59a 3951 #define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /*!< Bit mask for FTM_FLTCTRL_FAULT3EN. */
screamer 0:c5e2f793b59a 3952 #define BS_FTM_FLTCTRL_FAULT3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. */
screamer 0:c5e2f793b59a 3953
screamer 0:c5e2f793b59a 3954 /*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
screamer 0:c5e2f793b59a 3955 #define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
screamer 0:c5e2f793b59a 3956
screamer 0:c5e2f793b59a 3957 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. */
screamer 0:c5e2f793b59a 3958 #define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN)
screamer 0:c5e2f793b59a 3959
screamer 0:c5e2f793b59a 3960 /*! @brief Set the FAULT3EN field to a new value. */
screamer 0:c5e2f793b59a 3961 #define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
screamer 0:c5e2f793b59a 3962 /*@}*/
screamer 0:c5e2f793b59a 3963
screamer 0:c5e2f793b59a 3964 /*!
screamer 0:c5e2f793b59a 3965 * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
screamer 0:c5e2f793b59a 3966 *
screamer 0:c5e2f793b59a 3967 * Enables the filter for the fault input. This field is write protected. It can
screamer 0:c5e2f793b59a 3968 * be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3969 *
screamer 0:c5e2f793b59a 3970 * Values:
screamer 0:c5e2f793b59a 3971 * - 0 - Fault input filter is disabled.
screamer 0:c5e2f793b59a 3972 * - 1 - Fault input filter is enabled.
screamer 0:c5e2f793b59a 3973 */
screamer 0:c5e2f793b59a 3974 /*@{*/
screamer 0:c5e2f793b59a 3975 #define BP_FTM_FLTCTRL_FFLTR0EN (4U) /*!< Bit position for FTM_FLTCTRL_FFLTR0EN. */
screamer 0:c5e2f793b59a 3976 #define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /*!< Bit mask for FTM_FLTCTRL_FFLTR0EN. */
screamer 0:c5e2f793b59a 3977 #define BS_FTM_FLTCTRL_FFLTR0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. */
screamer 0:c5e2f793b59a 3978
screamer 0:c5e2f793b59a 3979 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
screamer 0:c5e2f793b59a 3980 #define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
screamer 0:c5e2f793b59a 3981
screamer 0:c5e2f793b59a 3982 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. */
screamer 0:c5e2f793b59a 3983 #define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN)
screamer 0:c5e2f793b59a 3984
screamer 0:c5e2f793b59a 3985 /*! @brief Set the FFLTR0EN field to a new value. */
screamer 0:c5e2f793b59a 3986 #define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
screamer 0:c5e2f793b59a 3987 /*@}*/
screamer 0:c5e2f793b59a 3988
screamer 0:c5e2f793b59a 3989 /*!
screamer 0:c5e2f793b59a 3990 * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
screamer 0:c5e2f793b59a 3991 *
screamer 0:c5e2f793b59a 3992 * Enables the filter for the fault input. This field is write protected. It can
screamer 0:c5e2f793b59a 3993 * be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 3994 *
screamer 0:c5e2f793b59a 3995 * Values:
screamer 0:c5e2f793b59a 3996 * - 0 - Fault input filter is disabled.
screamer 0:c5e2f793b59a 3997 * - 1 - Fault input filter is enabled.
screamer 0:c5e2f793b59a 3998 */
screamer 0:c5e2f793b59a 3999 /*@{*/
screamer 0:c5e2f793b59a 4000 #define BP_FTM_FLTCTRL_FFLTR1EN (5U) /*!< Bit position for FTM_FLTCTRL_FFLTR1EN. */
screamer 0:c5e2f793b59a 4001 #define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /*!< Bit mask for FTM_FLTCTRL_FFLTR1EN. */
screamer 0:c5e2f793b59a 4002 #define BS_FTM_FLTCTRL_FFLTR1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. */
screamer 0:c5e2f793b59a 4003
screamer 0:c5e2f793b59a 4004 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
screamer 0:c5e2f793b59a 4005 #define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
screamer 0:c5e2f793b59a 4006
screamer 0:c5e2f793b59a 4007 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. */
screamer 0:c5e2f793b59a 4008 #define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN)
screamer 0:c5e2f793b59a 4009
screamer 0:c5e2f793b59a 4010 /*! @brief Set the FFLTR1EN field to a new value. */
screamer 0:c5e2f793b59a 4011 #define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
screamer 0:c5e2f793b59a 4012 /*@}*/
screamer 0:c5e2f793b59a 4013
screamer 0:c5e2f793b59a 4014 /*!
screamer 0:c5e2f793b59a 4015 * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
screamer 0:c5e2f793b59a 4016 *
screamer 0:c5e2f793b59a 4017 * Enables the filter for the fault input. This field is write protected. It can
screamer 0:c5e2f793b59a 4018 * be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 4019 *
screamer 0:c5e2f793b59a 4020 * Values:
screamer 0:c5e2f793b59a 4021 * - 0 - Fault input filter is disabled.
screamer 0:c5e2f793b59a 4022 * - 1 - Fault input filter is enabled.
screamer 0:c5e2f793b59a 4023 */
screamer 0:c5e2f793b59a 4024 /*@{*/
screamer 0:c5e2f793b59a 4025 #define BP_FTM_FLTCTRL_FFLTR2EN (6U) /*!< Bit position for FTM_FLTCTRL_FFLTR2EN. */
screamer 0:c5e2f793b59a 4026 #define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /*!< Bit mask for FTM_FLTCTRL_FFLTR2EN. */
screamer 0:c5e2f793b59a 4027 #define BS_FTM_FLTCTRL_FFLTR2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. */
screamer 0:c5e2f793b59a 4028
screamer 0:c5e2f793b59a 4029 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
screamer 0:c5e2f793b59a 4030 #define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
screamer 0:c5e2f793b59a 4031
screamer 0:c5e2f793b59a 4032 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. */
screamer 0:c5e2f793b59a 4033 #define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN)
screamer 0:c5e2f793b59a 4034
screamer 0:c5e2f793b59a 4035 /*! @brief Set the FFLTR2EN field to a new value. */
screamer 0:c5e2f793b59a 4036 #define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
screamer 0:c5e2f793b59a 4037 /*@}*/
screamer 0:c5e2f793b59a 4038
screamer 0:c5e2f793b59a 4039 /*!
screamer 0:c5e2f793b59a 4040 * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
screamer 0:c5e2f793b59a 4041 *
screamer 0:c5e2f793b59a 4042 * Enables the filter for the fault input. This field is write protected. It can
screamer 0:c5e2f793b59a 4043 * be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 4044 *
screamer 0:c5e2f793b59a 4045 * Values:
screamer 0:c5e2f793b59a 4046 * - 0 - Fault input filter is disabled.
screamer 0:c5e2f793b59a 4047 * - 1 - Fault input filter is enabled.
screamer 0:c5e2f793b59a 4048 */
screamer 0:c5e2f793b59a 4049 /*@{*/
screamer 0:c5e2f793b59a 4050 #define BP_FTM_FLTCTRL_FFLTR3EN (7U) /*!< Bit position for FTM_FLTCTRL_FFLTR3EN. */
screamer 0:c5e2f793b59a 4051 #define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /*!< Bit mask for FTM_FLTCTRL_FFLTR3EN. */
screamer 0:c5e2f793b59a 4052 #define BS_FTM_FLTCTRL_FFLTR3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. */
screamer 0:c5e2f793b59a 4053
screamer 0:c5e2f793b59a 4054 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
screamer 0:c5e2f793b59a 4055 #define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
screamer 0:c5e2f793b59a 4056
screamer 0:c5e2f793b59a 4057 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. */
screamer 0:c5e2f793b59a 4058 #define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN)
screamer 0:c5e2f793b59a 4059
screamer 0:c5e2f793b59a 4060 /*! @brief Set the FFLTR3EN field to a new value. */
screamer 0:c5e2f793b59a 4061 #define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
screamer 0:c5e2f793b59a 4062 /*@}*/
screamer 0:c5e2f793b59a 4063
screamer 0:c5e2f793b59a 4064 /*!
screamer 0:c5e2f793b59a 4065 * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
screamer 0:c5e2f793b59a 4066 *
screamer 0:c5e2f793b59a 4067 * Selects the filter value for the fault inputs. The fault filter is disabled
screamer 0:c5e2f793b59a 4068 * when the value is zero. Writing to this field has immediate effect and must be
screamer 0:c5e2f793b59a 4069 * done only when the fault control or all fault inputs are disabled. Failure to
screamer 0:c5e2f793b59a 4070 * do this could result in a missing fault detection.
screamer 0:c5e2f793b59a 4071 */
screamer 0:c5e2f793b59a 4072 /*@{*/
screamer 0:c5e2f793b59a 4073 #define BP_FTM_FLTCTRL_FFVAL (8U) /*!< Bit position for FTM_FLTCTRL_FFVAL. */
screamer 0:c5e2f793b59a 4074 #define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /*!< Bit mask for FTM_FLTCTRL_FFVAL. */
screamer 0:c5e2f793b59a 4075 #define BS_FTM_FLTCTRL_FFVAL (4U) /*!< Bit field size in bits for FTM_FLTCTRL_FFVAL. */
screamer 0:c5e2f793b59a 4076
screamer 0:c5e2f793b59a 4077 /*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
screamer 0:c5e2f793b59a 4078 #define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
screamer 0:c5e2f793b59a 4079
screamer 0:c5e2f793b59a 4080 /*! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. */
screamer 0:c5e2f793b59a 4081 #define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL)
screamer 0:c5e2f793b59a 4082
screamer 0:c5e2f793b59a 4083 /*! @brief Set the FFVAL field to a new value. */
screamer 0:c5e2f793b59a 4084 #define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
screamer 0:c5e2f793b59a 4085 /*@}*/
screamer 0:c5e2f793b59a 4086
screamer 0:c5e2f793b59a 4087 /*******************************************************************************
screamer 0:c5e2f793b59a 4088 * HW_FTM_QDCTRL - Quadrature Decoder Control And Status
screamer 0:c5e2f793b59a 4089 ******************************************************************************/
screamer 0:c5e2f793b59a 4090
screamer 0:c5e2f793b59a 4091 /*!
screamer 0:c5e2f793b59a 4092 * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
screamer 0:c5e2f793b59a 4093 *
screamer 0:c5e2f793b59a 4094 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 4095 *
screamer 0:c5e2f793b59a 4096 * This register has the control and status bits for the Quadrature Decoder mode.
screamer 0:c5e2f793b59a 4097 */
screamer 0:c5e2f793b59a 4098 typedef union _hw_ftm_qdctrl
screamer 0:c5e2f793b59a 4099 {
screamer 0:c5e2f793b59a 4100 uint32_t U;
screamer 0:c5e2f793b59a 4101 struct _hw_ftm_qdctrl_bitfields
screamer 0:c5e2f793b59a 4102 {
screamer 0:c5e2f793b59a 4103 uint32_t QUADEN : 1; /*!< [0] Quadrature Decoder Mode Enable */
screamer 0:c5e2f793b59a 4104 uint32_t TOFDIR : 1; /*!< [1] Timer Overflow Direction In Quadrature
screamer 0:c5e2f793b59a 4105 * Decoder Mode */
screamer 0:c5e2f793b59a 4106 uint32_t QUADIR : 1; /*!< [2] FTM Counter Direction In Quadrature
screamer 0:c5e2f793b59a 4107 * Decoder Mode */
screamer 0:c5e2f793b59a 4108 uint32_t QUADMODE : 1; /*!< [3] Quadrature Decoder Mode */
screamer 0:c5e2f793b59a 4109 uint32_t PHBPOL : 1; /*!< [4] Phase B Input Polarity */
screamer 0:c5e2f793b59a 4110 uint32_t PHAPOL : 1; /*!< [5] Phase A Input Polarity */
screamer 0:c5e2f793b59a 4111 uint32_t PHBFLTREN : 1; /*!< [6] Phase B Input Filter Enable */
screamer 0:c5e2f793b59a 4112 uint32_t PHAFLTREN : 1; /*!< [7] Phase A Input Filter Enable */
screamer 0:c5e2f793b59a 4113 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 4114 } B;
screamer 0:c5e2f793b59a 4115 } hw_ftm_qdctrl_t;
screamer 0:c5e2f793b59a 4116
screamer 0:c5e2f793b59a 4117 /*!
screamer 0:c5e2f793b59a 4118 * @name Constants and macros for entire FTM_QDCTRL register
screamer 0:c5e2f793b59a 4119 */
screamer 0:c5e2f793b59a 4120 /*@{*/
screamer 0:c5e2f793b59a 4121 #define HW_FTM_QDCTRL_ADDR(x) ((x) + 0x80U)
screamer 0:c5e2f793b59a 4122
screamer 0:c5e2f793b59a 4123 #define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
screamer 0:c5e2f793b59a 4124 #define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
screamer 0:c5e2f793b59a 4125 #define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
screamer 0:c5e2f793b59a 4126 #define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v)))
screamer 0:c5e2f793b59a 4127 #define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 4128 #define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 4129 /*@}*/
screamer 0:c5e2f793b59a 4130
screamer 0:c5e2f793b59a 4131 /*
screamer 0:c5e2f793b59a 4132 * Constants & macros for individual FTM_QDCTRL bitfields
screamer 0:c5e2f793b59a 4133 */
screamer 0:c5e2f793b59a 4134
screamer 0:c5e2f793b59a 4135 /*!
screamer 0:c5e2f793b59a 4136 * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
screamer 0:c5e2f793b59a 4137 *
screamer 0:c5e2f793b59a 4138 * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
screamer 0:c5e2f793b59a 4139 * signals control the FTM counter direction. The Quadrature Decoder mode has
screamer 0:c5e2f793b59a 4140 * precedence over the other modes. See #ModeSel1Table. This field is write protected.
screamer 0:c5e2f793b59a 4141 * It can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 4142 *
screamer 0:c5e2f793b59a 4143 * Values:
screamer 0:c5e2f793b59a 4144 * - 0 - Quadrature Decoder mode is disabled.
screamer 0:c5e2f793b59a 4145 * - 1 - Quadrature Decoder mode is enabled.
screamer 0:c5e2f793b59a 4146 */
screamer 0:c5e2f793b59a 4147 /*@{*/
screamer 0:c5e2f793b59a 4148 #define BP_FTM_QDCTRL_QUADEN (0U) /*!< Bit position for FTM_QDCTRL_QUADEN. */
screamer 0:c5e2f793b59a 4149 #define BM_FTM_QDCTRL_QUADEN (0x00000001U) /*!< Bit mask for FTM_QDCTRL_QUADEN. */
screamer 0:c5e2f793b59a 4150 #define BS_FTM_QDCTRL_QUADEN (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADEN. */
screamer 0:c5e2f793b59a 4151
screamer 0:c5e2f793b59a 4152 /*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
screamer 0:c5e2f793b59a 4153 #define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
screamer 0:c5e2f793b59a 4154
screamer 0:c5e2f793b59a 4155 /*! @brief Format value for bitfield FTM_QDCTRL_QUADEN. */
screamer 0:c5e2f793b59a 4156 #define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN)
screamer 0:c5e2f793b59a 4157
screamer 0:c5e2f793b59a 4158 /*! @brief Set the QUADEN field to a new value. */
screamer 0:c5e2f793b59a 4159 #define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
screamer 0:c5e2f793b59a 4160 /*@}*/
screamer 0:c5e2f793b59a 4161
screamer 0:c5e2f793b59a 4162 /*!
screamer 0:c5e2f793b59a 4163 * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
screamer 0:c5e2f793b59a 4164 *
screamer 0:c5e2f793b59a 4165 * Indicates if the TOF bit was set on the top or the bottom of counting.
screamer 0:c5e2f793b59a 4166 *
screamer 0:c5e2f793b59a 4167 * Values:
screamer 0:c5e2f793b59a 4168 * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
screamer 0:c5e2f793b59a 4169 * decrement and FTM counter changes from its minimum value (CNTIN register) to
screamer 0:c5e2f793b59a 4170 * its maximum value (MOD register).
screamer 0:c5e2f793b59a 4171 * - 1 - TOF bit was set on the top of counting. There was an FTM counter
screamer 0:c5e2f793b59a 4172 * increment and FTM counter changes from its maximum value (MOD register) to its
screamer 0:c5e2f793b59a 4173 * minimum value (CNTIN register).
screamer 0:c5e2f793b59a 4174 */
screamer 0:c5e2f793b59a 4175 /*@{*/
screamer 0:c5e2f793b59a 4176 #define BP_FTM_QDCTRL_TOFDIR (1U) /*!< Bit position for FTM_QDCTRL_TOFDIR. */
screamer 0:c5e2f793b59a 4177 #define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /*!< Bit mask for FTM_QDCTRL_TOFDIR. */
screamer 0:c5e2f793b59a 4178 #define BS_FTM_QDCTRL_TOFDIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_TOFDIR. */
screamer 0:c5e2f793b59a 4179
screamer 0:c5e2f793b59a 4180 /*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
screamer 0:c5e2f793b59a 4181 #define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
screamer 0:c5e2f793b59a 4182 /*@}*/
screamer 0:c5e2f793b59a 4183
screamer 0:c5e2f793b59a 4184 /*!
screamer 0:c5e2f793b59a 4185 * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
screamer 0:c5e2f793b59a 4186 *
screamer 0:c5e2f793b59a 4187 * Indicates the counting direction.
screamer 0:c5e2f793b59a 4188 *
screamer 0:c5e2f793b59a 4189 * Values:
screamer 0:c5e2f793b59a 4190 * - 0 - Counting direction is decreasing (FTM counter decrement).
screamer 0:c5e2f793b59a 4191 * - 1 - Counting direction is increasing (FTM counter increment).
screamer 0:c5e2f793b59a 4192 */
screamer 0:c5e2f793b59a 4193 /*@{*/
screamer 0:c5e2f793b59a 4194 #define BP_FTM_QDCTRL_QUADIR (2U) /*!< Bit position for FTM_QDCTRL_QUADIR. */
screamer 0:c5e2f793b59a 4195 #define BM_FTM_QDCTRL_QUADIR (0x00000004U) /*!< Bit mask for FTM_QDCTRL_QUADIR. */
screamer 0:c5e2f793b59a 4196 #define BS_FTM_QDCTRL_QUADIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADIR. */
screamer 0:c5e2f793b59a 4197
screamer 0:c5e2f793b59a 4198 /*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
screamer 0:c5e2f793b59a 4199 #define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
screamer 0:c5e2f793b59a 4200 /*@}*/
screamer 0:c5e2f793b59a 4201
screamer 0:c5e2f793b59a 4202 /*!
screamer 0:c5e2f793b59a 4203 * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
screamer 0:c5e2f793b59a 4204 *
screamer 0:c5e2f793b59a 4205 * Selects the encoding mode used in the Quadrature Decoder mode.
screamer 0:c5e2f793b59a 4206 *
screamer 0:c5e2f793b59a 4207 * Values:
screamer 0:c5e2f793b59a 4208 * - 0 - Phase A and phase B encoding mode.
screamer 0:c5e2f793b59a 4209 * - 1 - Count and direction encoding mode.
screamer 0:c5e2f793b59a 4210 */
screamer 0:c5e2f793b59a 4211 /*@{*/
screamer 0:c5e2f793b59a 4212 #define BP_FTM_QDCTRL_QUADMODE (3U) /*!< Bit position for FTM_QDCTRL_QUADMODE. */
screamer 0:c5e2f793b59a 4213 #define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /*!< Bit mask for FTM_QDCTRL_QUADMODE. */
screamer 0:c5e2f793b59a 4214 #define BS_FTM_QDCTRL_QUADMODE (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADMODE. */
screamer 0:c5e2f793b59a 4215
screamer 0:c5e2f793b59a 4216 /*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
screamer 0:c5e2f793b59a 4217 #define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
screamer 0:c5e2f793b59a 4218
screamer 0:c5e2f793b59a 4219 /*! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. */
screamer 0:c5e2f793b59a 4220 #define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE)
screamer 0:c5e2f793b59a 4221
screamer 0:c5e2f793b59a 4222 /*! @brief Set the QUADMODE field to a new value. */
screamer 0:c5e2f793b59a 4223 #define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
screamer 0:c5e2f793b59a 4224 /*@}*/
screamer 0:c5e2f793b59a 4225
screamer 0:c5e2f793b59a 4226 /*!
screamer 0:c5e2f793b59a 4227 * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
screamer 0:c5e2f793b59a 4228 *
screamer 0:c5e2f793b59a 4229 * Selects the polarity for the quadrature decoder phase B input.
screamer 0:c5e2f793b59a 4230 *
screamer 0:c5e2f793b59a 4231 * Values:
screamer 0:c5e2f793b59a 4232 * - 0 - Normal polarity. Phase B input signal is not inverted before
screamer 0:c5e2f793b59a 4233 * identifying the rising and falling edges of this signal.
screamer 0:c5e2f793b59a 4234 * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
screamer 0:c5e2f793b59a 4235 * the rising and falling edges of this signal.
screamer 0:c5e2f793b59a 4236 */
screamer 0:c5e2f793b59a 4237 /*@{*/
screamer 0:c5e2f793b59a 4238 #define BP_FTM_QDCTRL_PHBPOL (4U) /*!< Bit position for FTM_QDCTRL_PHBPOL. */
screamer 0:c5e2f793b59a 4239 #define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /*!< Bit mask for FTM_QDCTRL_PHBPOL. */
screamer 0:c5e2f793b59a 4240 #define BS_FTM_QDCTRL_PHBPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBPOL. */
screamer 0:c5e2f793b59a 4241
screamer 0:c5e2f793b59a 4242 /*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
screamer 0:c5e2f793b59a 4243 #define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
screamer 0:c5e2f793b59a 4244
screamer 0:c5e2f793b59a 4245 /*! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. */
screamer 0:c5e2f793b59a 4246 #define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL)
screamer 0:c5e2f793b59a 4247
screamer 0:c5e2f793b59a 4248 /*! @brief Set the PHBPOL field to a new value. */
screamer 0:c5e2f793b59a 4249 #define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
screamer 0:c5e2f793b59a 4250 /*@}*/
screamer 0:c5e2f793b59a 4251
screamer 0:c5e2f793b59a 4252 /*!
screamer 0:c5e2f793b59a 4253 * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
screamer 0:c5e2f793b59a 4254 *
screamer 0:c5e2f793b59a 4255 * Selects the polarity for the quadrature decoder phase A input.
screamer 0:c5e2f793b59a 4256 *
screamer 0:c5e2f793b59a 4257 * Values:
screamer 0:c5e2f793b59a 4258 * - 0 - Normal polarity. Phase A input signal is not inverted before
screamer 0:c5e2f793b59a 4259 * identifying the rising and falling edges of this signal.
screamer 0:c5e2f793b59a 4260 * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
screamer 0:c5e2f793b59a 4261 * the rising and falling edges of this signal.
screamer 0:c5e2f793b59a 4262 */
screamer 0:c5e2f793b59a 4263 /*@{*/
screamer 0:c5e2f793b59a 4264 #define BP_FTM_QDCTRL_PHAPOL (5U) /*!< Bit position for FTM_QDCTRL_PHAPOL. */
screamer 0:c5e2f793b59a 4265 #define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /*!< Bit mask for FTM_QDCTRL_PHAPOL. */
screamer 0:c5e2f793b59a 4266 #define BS_FTM_QDCTRL_PHAPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAPOL. */
screamer 0:c5e2f793b59a 4267
screamer 0:c5e2f793b59a 4268 /*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
screamer 0:c5e2f793b59a 4269 #define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
screamer 0:c5e2f793b59a 4270
screamer 0:c5e2f793b59a 4271 /*! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. */
screamer 0:c5e2f793b59a 4272 #define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL)
screamer 0:c5e2f793b59a 4273
screamer 0:c5e2f793b59a 4274 /*! @brief Set the PHAPOL field to a new value. */
screamer 0:c5e2f793b59a 4275 #define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
screamer 0:c5e2f793b59a 4276 /*@}*/
screamer 0:c5e2f793b59a 4277
screamer 0:c5e2f793b59a 4278 /*!
screamer 0:c5e2f793b59a 4279 * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
screamer 0:c5e2f793b59a 4280 *
screamer 0:c5e2f793b59a 4281 * Enables the filter for the quadrature decoder phase B input. The filter value
screamer 0:c5e2f793b59a 4282 * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
screamer 0:c5e2f793b59a 4283 * filter is also disabled when CH1FVAL is zero.
screamer 0:c5e2f793b59a 4284 *
screamer 0:c5e2f793b59a 4285 * Values:
screamer 0:c5e2f793b59a 4286 * - 0 - Phase B input filter is disabled.
screamer 0:c5e2f793b59a 4287 * - 1 - Phase B input filter is enabled.
screamer 0:c5e2f793b59a 4288 */
screamer 0:c5e2f793b59a 4289 /*@{*/
screamer 0:c5e2f793b59a 4290 #define BP_FTM_QDCTRL_PHBFLTREN (6U) /*!< Bit position for FTM_QDCTRL_PHBFLTREN. */
screamer 0:c5e2f793b59a 4291 #define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /*!< Bit mask for FTM_QDCTRL_PHBFLTREN. */
screamer 0:c5e2f793b59a 4292 #define BS_FTM_QDCTRL_PHBFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. */
screamer 0:c5e2f793b59a 4293
screamer 0:c5e2f793b59a 4294 /*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
screamer 0:c5e2f793b59a 4295 #define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
screamer 0:c5e2f793b59a 4296
screamer 0:c5e2f793b59a 4297 /*! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. */
screamer 0:c5e2f793b59a 4298 #define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN)
screamer 0:c5e2f793b59a 4299
screamer 0:c5e2f793b59a 4300 /*! @brief Set the PHBFLTREN field to a new value. */
screamer 0:c5e2f793b59a 4301 #define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
screamer 0:c5e2f793b59a 4302 /*@}*/
screamer 0:c5e2f793b59a 4303
screamer 0:c5e2f793b59a 4304 /*!
screamer 0:c5e2f793b59a 4305 * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
screamer 0:c5e2f793b59a 4306 *
screamer 0:c5e2f793b59a 4307 * Enables the filter for the quadrature decoder phase A input. The filter value
screamer 0:c5e2f793b59a 4308 * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
screamer 0:c5e2f793b59a 4309 * filter is also disabled when CH0FVAL is zero.
screamer 0:c5e2f793b59a 4310 *
screamer 0:c5e2f793b59a 4311 * Values:
screamer 0:c5e2f793b59a 4312 * - 0 - Phase A input filter is disabled.
screamer 0:c5e2f793b59a 4313 * - 1 - Phase A input filter is enabled.
screamer 0:c5e2f793b59a 4314 */
screamer 0:c5e2f793b59a 4315 /*@{*/
screamer 0:c5e2f793b59a 4316 #define BP_FTM_QDCTRL_PHAFLTREN (7U) /*!< Bit position for FTM_QDCTRL_PHAFLTREN. */
screamer 0:c5e2f793b59a 4317 #define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /*!< Bit mask for FTM_QDCTRL_PHAFLTREN. */
screamer 0:c5e2f793b59a 4318 #define BS_FTM_QDCTRL_PHAFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. */
screamer 0:c5e2f793b59a 4319
screamer 0:c5e2f793b59a 4320 /*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
screamer 0:c5e2f793b59a 4321 #define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
screamer 0:c5e2f793b59a 4322
screamer 0:c5e2f793b59a 4323 /*! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. */
screamer 0:c5e2f793b59a 4324 #define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN)
screamer 0:c5e2f793b59a 4325
screamer 0:c5e2f793b59a 4326 /*! @brief Set the PHAFLTREN field to a new value. */
screamer 0:c5e2f793b59a 4327 #define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
screamer 0:c5e2f793b59a 4328 /*@}*/
screamer 0:c5e2f793b59a 4329
screamer 0:c5e2f793b59a 4330 /*******************************************************************************
screamer 0:c5e2f793b59a 4331 * HW_FTM_CONF - Configuration
screamer 0:c5e2f793b59a 4332 ******************************************************************************/
screamer 0:c5e2f793b59a 4333
screamer 0:c5e2f793b59a 4334 /*!
screamer 0:c5e2f793b59a 4335 * @brief HW_FTM_CONF - Configuration (RW)
screamer 0:c5e2f793b59a 4336 *
screamer 0:c5e2f793b59a 4337 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 4338 *
screamer 0:c5e2f793b59a 4339 * This register selects the number of times that the FTM counter overflow
screamer 0:c5e2f793b59a 4340 * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
screamer 0:c5e2f793b59a 4341 * of an external global time base, and the global time base signal generation.
screamer 0:c5e2f793b59a 4342 */
screamer 0:c5e2f793b59a 4343 typedef union _hw_ftm_conf
screamer 0:c5e2f793b59a 4344 {
screamer 0:c5e2f793b59a 4345 uint32_t U;
screamer 0:c5e2f793b59a 4346 struct _hw_ftm_conf_bitfields
screamer 0:c5e2f793b59a 4347 {
screamer 0:c5e2f793b59a 4348 uint32_t NUMTOF : 5; /*!< [4:0] TOF Frequency */
screamer 0:c5e2f793b59a 4349 uint32_t RESERVED0 : 1; /*!< [5] */
screamer 0:c5e2f793b59a 4350 uint32_t BDMMODE : 2; /*!< [7:6] BDM Mode */
screamer 0:c5e2f793b59a 4351 uint32_t RESERVED1 : 1; /*!< [8] */
screamer 0:c5e2f793b59a 4352 uint32_t GTBEEN : 1; /*!< [9] Global Time Base Enable */
screamer 0:c5e2f793b59a 4353 uint32_t GTBEOUT : 1; /*!< [10] Global Time Base Output */
screamer 0:c5e2f793b59a 4354 uint32_t RESERVED2 : 21; /*!< [31:11] */
screamer 0:c5e2f793b59a 4355 } B;
screamer 0:c5e2f793b59a 4356 } hw_ftm_conf_t;
screamer 0:c5e2f793b59a 4357
screamer 0:c5e2f793b59a 4358 /*!
screamer 0:c5e2f793b59a 4359 * @name Constants and macros for entire FTM_CONF register
screamer 0:c5e2f793b59a 4360 */
screamer 0:c5e2f793b59a 4361 /*@{*/
screamer 0:c5e2f793b59a 4362 #define HW_FTM_CONF_ADDR(x) ((x) + 0x84U)
screamer 0:c5e2f793b59a 4363
screamer 0:c5e2f793b59a 4364 #define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
screamer 0:c5e2f793b59a 4365 #define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
screamer 0:c5e2f793b59a 4366 #define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
screamer 0:c5e2f793b59a 4367 #define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v)))
screamer 0:c5e2f793b59a 4368 #define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 4369 #define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 4370 /*@}*/
screamer 0:c5e2f793b59a 4371
screamer 0:c5e2f793b59a 4372 /*
screamer 0:c5e2f793b59a 4373 * Constants & macros for individual FTM_CONF bitfields
screamer 0:c5e2f793b59a 4374 */
screamer 0:c5e2f793b59a 4375
screamer 0:c5e2f793b59a 4376 /*!
screamer 0:c5e2f793b59a 4377 * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
screamer 0:c5e2f793b59a 4378 *
screamer 0:c5e2f793b59a 4379 * Selects the ratio between the number of counter overflows to the number of
screamer 0:c5e2f793b59a 4380 * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
screamer 0:c5e2f793b59a 4381 * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
screamer 0:c5e2f793b59a 4382 * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
screamer 0:c5e2f793b59a 4383 * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
screamer 0:c5e2f793b59a 4384 * first counter overflow but not for the next 3 overflows. This pattern continues
screamer 0:c5e2f793b59a 4385 * up to a maximum of 31.
screamer 0:c5e2f793b59a 4386 */
screamer 0:c5e2f793b59a 4387 /*@{*/
screamer 0:c5e2f793b59a 4388 #define BP_FTM_CONF_NUMTOF (0U) /*!< Bit position for FTM_CONF_NUMTOF. */
screamer 0:c5e2f793b59a 4389 #define BM_FTM_CONF_NUMTOF (0x0000001FU) /*!< Bit mask for FTM_CONF_NUMTOF. */
screamer 0:c5e2f793b59a 4390 #define BS_FTM_CONF_NUMTOF (5U) /*!< Bit field size in bits for FTM_CONF_NUMTOF. */
screamer 0:c5e2f793b59a 4391
screamer 0:c5e2f793b59a 4392 /*! @brief Read current value of the FTM_CONF_NUMTOF field. */
screamer 0:c5e2f793b59a 4393 #define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
screamer 0:c5e2f793b59a 4394
screamer 0:c5e2f793b59a 4395 /*! @brief Format value for bitfield FTM_CONF_NUMTOF. */
screamer 0:c5e2f793b59a 4396 #define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF)
screamer 0:c5e2f793b59a 4397
screamer 0:c5e2f793b59a 4398 /*! @brief Set the NUMTOF field to a new value. */
screamer 0:c5e2f793b59a 4399 #define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
screamer 0:c5e2f793b59a 4400 /*@}*/
screamer 0:c5e2f793b59a 4401
screamer 0:c5e2f793b59a 4402 /*!
screamer 0:c5e2f793b59a 4403 * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
screamer 0:c5e2f793b59a 4404 *
screamer 0:c5e2f793b59a 4405 * Selects the FTM behavior in BDM mode. See BDM mode.
screamer 0:c5e2f793b59a 4406 */
screamer 0:c5e2f793b59a 4407 /*@{*/
screamer 0:c5e2f793b59a 4408 #define BP_FTM_CONF_BDMMODE (6U) /*!< Bit position for FTM_CONF_BDMMODE. */
screamer 0:c5e2f793b59a 4409 #define BM_FTM_CONF_BDMMODE (0x000000C0U) /*!< Bit mask for FTM_CONF_BDMMODE. */
screamer 0:c5e2f793b59a 4410 #define BS_FTM_CONF_BDMMODE (2U) /*!< Bit field size in bits for FTM_CONF_BDMMODE. */
screamer 0:c5e2f793b59a 4411
screamer 0:c5e2f793b59a 4412 /*! @brief Read current value of the FTM_CONF_BDMMODE field. */
screamer 0:c5e2f793b59a 4413 #define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
screamer 0:c5e2f793b59a 4414
screamer 0:c5e2f793b59a 4415 /*! @brief Format value for bitfield FTM_CONF_BDMMODE. */
screamer 0:c5e2f793b59a 4416 #define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE)
screamer 0:c5e2f793b59a 4417
screamer 0:c5e2f793b59a 4418 /*! @brief Set the BDMMODE field to a new value. */
screamer 0:c5e2f793b59a 4419 #define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
screamer 0:c5e2f793b59a 4420 /*@}*/
screamer 0:c5e2f793b59a 4421
screamer 0:c5e2f793b59a 4422 /*!
screamer 0:c5e2f793b59a 4423 * @name Register FTM_CONF, field GTBEEN[9] (RW)
screamer 0:c5e2f793b59a 4424 *
screamer 0:c5e2f793b59a 4425 * Configures the FTM to use an external global time base signal that is
screamer 0:c5e2f793b59a 4426 * generated by another FTM.
screamer 0:c5e2f793b59a 4427 *
screamer 0:c5e2f793b59a 4428 * Values:
screamer 0:c5e2f793b59a 4429 * - 0 - Use of an external global time base is disabled.
screamer 0:c5e2f793b59a 4430 * - 1 - Use of an external global time base is enabled.
screamer 0:c5e2f793b59a 4431 */
screamer 0:c5e2f793b59a 4432 /*@{*/
screamer 0:c5e2f793b59a 4433 #define BP_FTM_CONF_GTBEEN (9U) /*!< Bit position for FTM_CONF_GTBEEN. */
screamer 0:c5e2f793b59a 4434 #define BM_FTM_CONF_GTBEEN (0x00000200U) /*!< Bit mask for FTM_CONF_GTBEEN. */
screamer 0:c5e2f793b59a 4435 #define BS_FTM_CONF_GTBEEN (1U) /*!< Bit field size in bits for FTM_CONF_GTBEEN. */
screamer 0:c5e2f793b59a 4436
screamer 0:c5e2f793b59a 4437 /*! @brief Read current value of the FTM_CONF_GTBEEN field. */
screamer 0:c5e2f793b59a 4438 #define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
screamer 0:c5e2f793b59a 4439
screamer 0:c5e2f793b59a 4440 /*! @brief Format value for bitfield FTM_CONF_GTBEEN. */
screamer 0:c5e2f793b59a 4441 #define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN)
screamer 0:c5e2f793b59a 4442
screamer 0:c5e2f793b59a 4443 /*! @brief Set the GTBEEN field to a new value. */
screamer 0:c5e2f793b59a 4444 #define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
screamer 0:c5e2f793b59a 4445 /*@}*/
screamer 0:c5e2f793b59a 4446
screamer 0:c5e2f793b59a 4447 /*!
screamer 0:c5e2f793b59a 4448 * @name Register FTM_CONF, field GTBEOUT[10] (RW)
screamer 0:c5e2f793b59a 4449 *
screamer 0:c5e2f793b59a 4450 * Enables the global time base signal generation to other FTMs.
screamer 0:c5e2f793b59a 4451 *
screamer 0:c5e2f793b59a 4452 * Values:
screamer 0:c5e2f793b59a 4453 * - 0 - A global time base signal generation is disabled.
screamer 0:c5e2f793b59a 4454 * - 1 - A global time base signal generation is enabled.
screamer 0:c5e2f793b59a 4455 */
screamer 0:c5e2f793b59a 4456 /*@{*/
screamer 0:c5e2f793b59a 4457 #define BP_FTM_CONF_GTBEOUT (10U) /*!< Bit position for FTM_CONF_GTBEOUT. */
screamer 0:c5e2f793b59a 4458 #define BM_FTM_CONF_GTBEOUT (0x00000400U) /*!< Bit mask for FTM_CONF_GTBEOUT. */
screamer 0:c5e2f793b59a 4459 #define BS_FTM_CONF_GTBEOUT (1U) /*!< Bit field size in bits for FTM_CONF_GTBEOUT. */
screamer 0:c5e2f793b59a 4460
screamer 0:c5e2f793b59a 4461 /*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
screamer 0:c5e2f793b59a 4462 #define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
screamer 0:c5e2f793b59a 4463
screamer 0:c5e2f793b59a 4464 /*! @brief Format value for bitfield FTM_CONF_GTBEOUT. */
screamer 0:c5e2f793b59a 4465 #define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT)
screamer 0:c5e2f793b59a 4466
screamer 0:c5e2f793b59a 4467 /*! @brief Set the GTBEOUT field to a new value. */
screamer 0:c5e2f793b59a 4468 #define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
screamer 0:c5e2f793b59a 4469 /*@}*/
screamer 0:c5e2f793b59a 4470
screamer 0:c5e2f793b59a 4471 /*******************************************************************************
screamer 0:c5e2f793b59a 4472 * HW_FTM_FLTPOL - FTM Fault Input Polarity
screamer 0:c5e2f793b59a 4473 ******************************************************************************/
screamer 0:c5e2f793b59a 4474
screamer 0:c5e2f793b59a 4475 /*!
screamer 0:c5e2f793b59a 4476 * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
screamer 0:c5e2f793b59a 4477 *
screamer 0:c5e2f793b59a 4478 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 4479 *
screamer 0:c5e2f793b59a 4480 * This register defines the fault inputs polarity.
screamer 0:c5e2f793b59a 4481 */
screamer 0:c5e2f793b59a 4482 typedef union _hw_ftm_fltpol
screamer 0:c5e2f793b59a 4483 {
screamer 0:c5e2f793b59a 4484 uint32_t U;
screamer 0:c5e2f793b59a 4485 struct _hw_ftm_fltpol_bitfields
screamer 0:c5e2f793b59a 4486 {
screamer 0:c5e2f793b59a 4487 uint32_t FLT0POL : 1; /*!< [0] Fault Input 0 Polarity */
screamer 0:c5e2f793b59a 4488 uint32_t FLT1POL : 1; /*!< [1] Fault Input 1 Polarity */
screamer 0:c5e2f793b59a 4489 uint32_t FLT2POL : 1; /*!< [2] Fault Input 2 Polarity */
screamer 0:c5e2f793b59a 4490 uint32_t FLT3POL : 1; /*!< [3] Fault Input 3 Polarity */
screamer 0:c5e2f793b59a 4491 uint32_t RESERVED0 : 28; /*!< [31:4] */
screamer 0:c5e2f793b59a 4492 } B;
screamer 0:c5e2f793b59a 4493 } hw_ftm_fltpol_t;
screamer 0:c5e2f793b59a 4494
screamer 0:c5e2f793b59a 4495 /*!
screamer 0:c5e2f793b59a 4496 * @name Constants and macros for entire FTM_FLTPOL register
screamer 0:c5e2f793b59a 4497 */
screamer 0:c5e2f793b59a 4498 /*@{*/
screamer 0:c5e2f793b59a 4499 #define HW_FTM_FLTPOL_ADDR(x) ((x) + 0x88U)
screamer 0:c5e2f793b59a 4500
screamer 0:c5e2f793b59a 4501 #define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
screamer 0:c5e2f793b59a 4502 #define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
screamer 0:c5e2f793b59a 4503 #define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
screamer 0:c5e2f793b59a 4504 #define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v)))
screamer 0:c5e2f793b59a 4505 #define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 4506 #define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 4507 /*@}*/
screamer 0:c5e2f793b59a 4508
screamer 0:c5e2f793b59a 4509 /*
screamer 0:c5e2f793b59a 4510 * Constants & macros for individual FTM_FLTPOL bitfields
screamer 0:c5e2f793b59a 4511 */
screamer 0:c5e2f793b59a 4512
screamer 0:c5e2f793b59a 4513 /*!
screamer 0:c5e2f793b59a 4514 * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
screamer 0:c5e2f793b59a 4515 *
screamer 0:c5e2f793b59a 4516 * Defines the polarity of the fault input. This field is write protected. It
screamer 0:c5e2f793b59a 4517 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 4518 *
screamer 0:c5e2f793b59a 4519 * Values:
screamer 0:c5e2f793b59a 4520 * - 0 - The fault input polarity is active high. A 1 at the fault input
screamer 0:c5e2f793b59a 4521 * indicates a fault.
screamer 0:c5e2f793b59a 4522 * - 1 - The fault input polarity is active low. A 0 at the fault input
screamer 0:c5e2f793b59a 4523 * indicates a fault.
screamer 0:c5e2f793b59a 4524 */
screamer 0:c5e2f793b59a 4525 /*@{*/
screamer 0:c5e2f793b59a 4526 #define BP_FTM_FLTPOL_FLT0POL (0U) /*!< Bit position for FTM_FLTPOL_FLT0POL. */
screamer 0:c5e2f793b59a 4527 #define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /*!< Bit mask for FTM_FLTPOL_FLT0POL. */
screamer 0:c5e2f793b59a 4528 #define BS_FTM_FLTPOL_FLT0POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT0POL. */
screamer 0:c5e2f793b59a 4529
screamer 0:c5e2f793b59a 4530 /*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
screamer 0:c5e2f793b59a 4531 #define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
screamer 0:c5e2f793b59a 4532
screamer 0:c5e2f793b59a 4533 /*! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. */
screamer 0:c5e2f793b59a 4534 #define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL)
screamer 0:c5e2f793b59a 4535
screamer 0:c5e2f793b59a 4536 /*! @brief Set the FLT0POL field to a new value. */
screamer 0:c5e2f793b59a 4537 #define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
screamer 0:c5e2f793b59a 4538 /*@}*/
screamer 0:c5e2f793b59a 4539
screamer 0:c5e2f793b59a 4540 /*!
screamer 0:c5e2f793b59a 4541 * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
screamer 0:c5e2f793b59a 4542 *
screamer 0:c5e2f793b59a 4543 * Defines the polarity of the fault input. This field is write protected. It
screamer 0:c5e2f793b59a 4544 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 4545 *
screamer 0:c5e2f793b59a 4546 * Values:
screamer 0:c5e2f793b59a 4547 * - 0 - The fault input polarity is active high. A 1 at the fault input
screamer 0:c5e2f793b59a 4548 * indicates a fault.
screamer 0:c5e2f793b59a 4549 * - 1 - The fault input polarity is active low. A 0 at the fault input
screamer 0:c5e2f793b59a 4550 * indicates a fault.
screamer 0:c5e2f793b59a 4551 */
screamer 0:c5e2f793b59a 4552 /*@{*/
screamer 0:c5e2f793b59a 4553 #define BP_FTM_FLTPOL_FLT1POL (1U) /*!< Bit position for FTM_FLTPOL_FLT1POL. */
screamer 0:c5e2f793b59a 4554 #define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /*!< Bit mask for FTM_FLTPOL_FLT1POL. */
screamer 0:c5e2f793b59a 4555 #define BS_FTM_FLTPOL_FLT1POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT1POL. */
screamer 0:c5e2f793b59a 4556
screamer 0:c5e2f793b59a 4557 /*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
screamer 0:c5e2f793b59a 4558 #define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
screamer 0:c5e2f793b59a 4559
screamer 0:c5e2f793b59a 4560 /*! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. */
screamer 0:c5e2f793b59a 4561 #define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL)
screamer 0:c5e2f793b59a 4562
screamer 0:c5e2f793b59a 4563 /*! @brief Set the FLT1POL field to a new value. */
screamer 0:c5e2f793b59a 4564 #define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
screamer 0:c5e2f793b59a 4565 /*@}*/
screamer 0:c5e2f793b59a 4566
screamer 0:c5e2f793b59a 4567 /*!
screamer 0:c5e2f793b59a 4568 * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
screamer 0:c5e2f793b59a 4569 *
screamer 0:c5e2f793b59a 4570 * Defines the polarity of the fault input. This field is write protected. It
screamer 0:c5e2f793b59a 4571 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 4572 *
screamer 0:c5e2f793b59a 4573 * Values:
screamer 0:c5e2f793b59a 4574 * - 0 - The fault input polarity is active high. A 1 at the fault input
screamer 0:c5e2f793b59a 4575 * indicates a fault.
screamer 0:c5e2f793b59a 4576 * - 1 - The fault input polarity is active low. A 0 at the fault input
screamer 0:c5e2f793b59a 4577 * indicates a fault.
screamer 0:c5e2f793b59a 4578 */
screamer 0:c5e2f793b59a 4579 /*@{*/
screamer 0:c5e2f793b59a 4580 #define BP_FTM_FLTPOL_FLT2POL (2U) /*!< Bit position for FTM_FLTPOL_FLT2POL. */
screamer 0:c5e2f793b59a 4581 #define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /*!< Bit mask for FTM_FLTPOL_FLT2POL. */
screamer 0:c5e2f793b59a 4582 #define BS_FTM_FLTPOL_FLT2POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT2POL. */
screamer 0:c5e2f793b59a 4583
screamer 0:c5e2f793b59a 4584 /*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
screamer 0:c5e2f793b59a 4585 #define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
screamer 0:c5e2f793b59a 4586
screamer 0:c5e2f793b59a 4587 /*! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. */
screamer 0:c5e2f793b59a 4588 #define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL)
screamer 0:c5e2f793b59a 4589
screamer 0:c5e2f793b59a 4590 /*! @brief Set the FLT2POL field to a new value. */
screamer 0:c5e2f793b59a 4591 #define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
screamer 0:c5e2f793b59a 4592 /*@}*/
screamer 0:c5e2f793b59a 4593
screamer 0:c5e2f793b59a 4594 /*!
screamer 0:c5e2f793b59a 4595 * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
screamer 0:c5e2f793b59a 4596 *
screamer 0:c5e2f793b59a 4597 * Defines the polarity of the fault input. This field is write protected. It
screamer 0:c5e2f793b59a 4598 * can be written only when MODE[WPDIS] = 1.
screamer 0:c5e2f793b59a 4599 *
screamer 0:c5e2f793b59a 4600 * Values:
screamer 0:c5e2f793b59a 4601 * - 0 - The fault input polarity is active high. A 1 at the fault input
screamer 0:c5e2f793b59a 4602 * indicates a fault.
screamer 0:c5e2f793b59a 4603 * - 1 - The fault input polarity is active low. A 0 at the fault input
screamer 0:c5e2f793b59a 4604 * indicates a fault.
screamer 0:c5e2f793b59a 4605 */
screamer 0:c5e2f793b59a 4606 /*@{*/
screamer 0:c5e2f793b59a 4607 #define BP_FTM_FLTPOL_FLT3POL (3U) /*!< Bit position for FTM_FLTPOL_FLT3POL. */
screamer 0:c5e2f793b59a 4608 #define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /*!< Bit mask for FTM_FLTPOL_FLT3POL. */
screamer 0:c5e2f793b59a 4609 #define BS_FTM_FLTPOL_FLT3POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT3POL. */
screamer 0:c5e2f793b59a 4610
screamer 0:c5e2f793b59a 4611 /*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
screamer 0:c5e2f793b59a 4612 #define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
screamer 0:c5e2f793b59a 4613
screamer 0:c5e2f793b59a 4614 /*! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. */
screamer 0:c5e2f793b59a 4615 #define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL)
screamer 0:c5e2f793b59a 4616
screamer 0:c5e2f793b59a 4617 /*! @brief Set the FLT3POL field to a new value. */
screamer 0:c5e2f793b59a 4618 #define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
screamer 0:c5e2f793b59a 4619 /*@}*/
screamer 0:c5e2f793b59a 4620
screamer 0:c5e2f793b59a 4621 /*******************************************************************************
screamer 0:c5e2f793b59a 4622 * HW_FTM_SYNCONF - Synchronization Configuration
screamer 0:c5e2f793b59a 4623 ******************************************************************************/
screamer 0:c5e2f793b59a 4624
screamer 0:c5e2f793b59a 4625 /*!
screamer 0:c5e2f793b59a 4626 * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
screamer 0:c5e2f793b59a 4627 *
screamer 0:c5e2f793b59a 4628 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 4629 *
screamer 0:c5e2f793b59a 4630 * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
screamer 0:c5e2f793b59a 4631 * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
screamer 0:c5e2f793b59a 4632 * 0, 1, 2, when the hardware trigger j is detected.
screamer 0:c5e2f793b59a 4633 */
screamer 0:c5e2f793b59a 4634 typedef union _hw_ftm_synconf
screamer 0:c5e2f793b59a 4635 {
screamer 0:c5e2f793b59a 4636 uint32_t U;
screamer 0:c5e2f793b59a 4637 struct _hw_ftm_synconf_bitfields
screamer 0:c5e2f793b59a 4638 {
screamer 0:c5e2f793b59a 4639 uint32_t HWTRIGMODE : 1; /*!< [0] Hardware Trigger Mode */
screamer 0:c5e2f793b59a 4640 uint32_t RESERVED0 : 1; /*!< [1] */
screamer 0:c5e2f793b59a 4641 uint32_t CNTINC : 1; /*!< [2] CNTIN Register Synchronization */
screamer 0:c5e2f793b59a 4642 uint32_t RESERVED1 : 1; /*!< [3] */
screamer 0:c5e2f793b59a 4643 uint32_t INVC : 1; /*!< [4] INVCTRL Register Synchronization */
screamer 0:c5e2f793b59a 4644 uint32_t SWOC : 1; /*!< [5] SWOCTRL Register Synchronization */
screamer 0:c5e2f793b59a 4645 uint32_t RESERVED2 : 1; /*!< [6] */
screamer 0:c5e2f793b59a 4646 uint32_t SYNCMODE : 1; /*!< [7] Synchronization Mode */
screamer 0:c5e2f793b59a 4647 uint32_t SWRSTCNT : 1; /*!< [8] */
screamer 0:c5e2f793b59a 4648 uint32_t SWWRBUF : 1; /*!< [9] */
screamer 0:c5e2f793b59a 4649 uint32_t SWOM : 1; /*!< [10] */
screamer 0:c5e2f793b59a 4650 uint32_t SWINVC : 1; /*!< [11] */
screamer 0:c5e2f793b59a 4651 uint32_t SWSOC : 1; /*!< [12] */
screamer 0:c5e2f793b59a 4652 uint32_t RESERVED3 : 3; /*!< [15:13] */
screamer 0:c5e2f793b59a 4653 uint32_t HWRSTCNT : 1; /*!< [16] */
screamer 0:c5e2f793b59a 4654 uint32_t HWWRBUF : 1; /*!< [17] */
screamer 0:c5e2f793b59a 4655 uint32_t HWOM : 1; /*!< [18] */
screamer 0:c5e2f793b59a 4656 uint32_t HWINVC : 1; /*!< [19] */
screamer 0:c5e2f793b59a 4657 uint32_t HWSOC : 1; /*!< [20] */
screamer 0:c5e2f793b59a 4658 uint32_t RESERVED4 : 11; /*!< [31:21] */
screamer 0:c5e2f793b59a 4659 } B;
screamer 0:c5e2f793b59a 4660 } hw_ftm_synconf_t;
screamer 0:c5e2f793b59a 4661
screamer 0:c5e2f793b59a 4662 /*!
screamer 0:c5e2f793b59a 4663 * @name Constants and macros for entire FTM_SYNCONF register
screamer 0:c5e2f793b59a 4664 */
screamer 0:c5e2f793b59a 4665 /*@{*/
screamer 0:c5e2f793b59a 4666 #define HW_FTM_SYNCONF_ADDR(x) ((x) + 0x8CU)
screamer 0:c5e2f793b59a 4667
screamer 0:c5e2f793b59a 4668 #define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
screamer 0:c5e2f793b59a 4669 #define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
screamer 0:c5e2f793b59a 4670 #define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
screamer 0:c5e2f793b59a 4671 #define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v)))
screamer 0:c5e2f793b59a 4672 #define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 4673 #define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 4674 /*@}*/
screamer 0:c5e2f793b59a 4675
screamer 0:c5e2f793b59a 4676 /*
screamer 0:c5e2f793b59a 4677 * Constants & macros for individual FTM_SYNCONF bitfields
screamer 0:c5e2f793b59a 4678 */
screamer 0:c5e2f793b59a 4679
screamer 0:c5e2f793b59a 4680 /*!
screamer 0:c5e2f793b59a 4681 * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
screamer 0:c5e2f793b59a 4682 *
screamer 0:c5e2f793b59a 4683 * Values:
screamer 0:c5e2f793b59a 4684 * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
screamer 0:c5e2f793b59a 4685 * j = 0, 1,2.
screamer 0:c5e2f793b59a 4686 * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
screamer 0:c5e2f793b59a 4687 * detected, where j = 0, 1,2.
screamer 0:c5e2f793b59a 4688 */
screamer 0:c5e2f793b59a 4689 /*@{*/
screamer 0:c5e2f793b59a 4690 #define BP_FTM_SYNCONF_HWTRIGMODE (0U) /*!< Bit position for FTM_SYNCONF_HWTRIGMODE. */
screamer 0:c5e2f793b59a 4691 #define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /*!< Bit mask for FTM_SYNCONF_HWTRIGMODE. */
screamer 0:c5e2f793b59a 4692 #define BS_FTM_SYNCONF_HWTRIGMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. */
screamer 0:c5e2f793b59a 4693
screamer 0:c5e2f793b59a 4694 /*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
screamer 0:c5e2f793b59a 4695 #define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
screamer 0:c5e2f793b59a 4696
screamer 0:c5e2f793b59a 4697 /*! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. */
screamer 0:c5e2f793b59a 4698 #define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE)
screamer 0:c5e2f793b59a 4699
screamer 0:c5e2f793b59a 4700 /*! @brief Set the HWTRIGMODE field to a new value. */
screamer 0:c5e2f793b59a 4701 #define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
screamer 0:c5e2f793b59a 4702 /*@}*/
screamer 0:c5e2f793b59a 4703
screamer 0:c5e2f793b59a 4704 /*!
screamer 0:c5e2f793b59a 4705 * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
screamer 0:c5e2f793b59a 4706 *
screamer 0:c5e2f793b59a 4707 * Values:
screamer 0:c5e2f793b59a 4708 * - 0 - CNTIN register is updated with its buffer value at all rising edges of
screamer 0:c5e2f793b59a 4709 * system clock.
screamer 0:c5e2f793b59a 4710 * - 1 - CNTIN register is updated with its buffer value by the PWM
screamer 0:c5e2f793b59a 4711 * synchronization.
screamer 0:c5e2f793b59a 4712 */
screamer 0:c5e2f793b59a 4713 /*@{*/
screamer 0:c5e2f793b59a 4714 #define BP_FTM_SYNCONF_CNTINC (2U) /*!< Bit position for FTM_SYNCONF_CNTINC. */
screamer 0:c5e2f793b59a 4715 #define BM_FTM_SYNCONF_CNTINC (0x00000004U) /*!< Bit mask for FTM_SYNCONF_CNTINC. */
screamer 0:c5e2f793b59a 4716 #define BS_FTM_SYNCONF_CNTINC (1U) /*!< Bit field size in bits for FTM_SYNCONF_CNTINC. */
screamer 0:c5e2f793b59a 4717
screamer 0:c5e2f793b59a 4718 /*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
screamer 0:c5e2f793b59a 4719 #define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
screamer 0:c5e2f793b59a 4720
screamer 0:c5e2f793b59a 4721 /*! @brief Format value for bitfield FTM_SYNCONF_CNTINC. */
screamer 0:c5e2f793b59a 4722 #define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC)
screamer 0:c5e2f793b59a 4723
screamer 0:c5e2f793b59a 4724 /*! @brief Set the CNTINC field to a new value. */
screamer 0:c5e2f793b59a 4725 #define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
screamer 0:c5e2f793b59a 4726 /*@}*/
screamer 0:c5e2f793b59a 4727
screamer 0:c5e2f793b59a 4728 /*!
screamer 0:c5e2f793b59a 4729 * @name Register FTM_SYNCONF, field INVC[4] (RW)
screamer 0:c5e2f793b59a 4730 *
screamer 0:c5e2f793b59a 4731 * Values:
screamer 0:c5e2f793b59a 4732 * - 0 - INVCTRL register is updated with its buffer value at all rising edges
screamer 0:c5e2f793b59a 4733 * of system clock.
screamer 0:c5e2f793b59a 4734 * - 1 - INVCTRL register is updated with its buffer value by the PWM
screamer 0:c5e2f793b59a 4735 * synchronization.
screamer 0:c5e2f793b59a 4736 */
screamer 0:c5e2f793b59a 4737 /*@{*/
screamer 0:c5e2f793b59a 4738 #define BP_FTM_SYNCONF_INVC (4U) /*!< Bit position for FTM_SYNCONF_INVC. */
screamer 0:c5e2f793b59a 4739 #define BM_FTM_SYNCONF_INVC (0x00000010U) /*!< Bit mask for FTM_SYNCONF_INVC. */
screamer 0:c5e2f793b59a 4740 #define BS_FTM_SYNCONF_INVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_INVC. */
screamer 0:c5e2f793b59a 4741
screamer 0:c5e2f793b59a 4742 /*! @brief Read current value of the FTM_SYNCONF_INVC field. */
screamer 0:c5e2f793b59a 4743 #define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
screamer 0:c5e2f793b59a 4744
screamer 0:c5e2f793b59a 4745 /*! @brief Format value for bitfield FTM_SYNCONF_INVC. */
screamer 0:c5e2f793b59a 4746 #define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC)
screamer 0:c5e2f793b59a 4747
screamer 0:c5e2f793b59a 4748 /*! @brief Set the INVC field to a new value. */
screamer 0:c5e2f793b59a 4749 #define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
screamer 0:c5e2f793b59a 4750 /*@}*/
screamer 0:c5e2f793b59a 4751
screamer 0:c5e2f793b59a 4752 /*!
screamer 0:c5e2f793b59a 4753 * @name Register FTM_SYNCONF, field SWOC[5] (RW)
screamer 0:c5e2f793b59a 4754 *
screamer 0:c5e2f793b59a 4755 * Values:
screamer 0:c5e2f793b59a 4756 * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
screamer 0:c5e2f793b59a 4757 * of system clock.
screamer 0:c5e2f793b59a 4758 * - 1 - SWOCTRL register is updated with its buffer value by the PWM
screamer 0:c5e2f793b59a 4759 * synchronization.
screamer 0:c5e2f793b59a 4760 */
screamer 0:c5e2f793b59a 4761 /*@{*/
screamer 0:c5e2f793b59a 4762 #define BP_FTM_SYNCONF_SWOC (5U) /*!< Bit position for FTM_SYNCONF_SWOC. */
screamer 0:c5e2f793b59a 4763 #define BM_FTM_SYNCONF_SWOC (0x00000020U) /*!< Bit mask for FTM_SYNCONF_SWOC. */
screamer 0:c5e2f793b59a 4764 #define BS_FTM_SYNCONF_SWOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOC. */
screamer 0:c5e2f793b59a 4765
screamer 0:c5e2f793b59a 4766 /*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
screamer 0:c5e2f793b59a 4767 #define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
screamer 0:c5e2f793b59a 4768
screamer 0:c5e2f793b59a 4769 /*! @brief Format value for bitfield FTM_SYNCONF_SWOC. */
screamer 0:c5e2f793b59a 4770 #define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC)
screamer 0:c5e2f793b59a 4771
screamer 0:c5e2f793b59a 4772 /*! @brief Set the SWOC field to a new value. */
screamer 0:c5e2f793b59a 4773 #define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
screamer 0:c5e2f793b59a 4774 /*@}*/
screamer 0:c5e2f793b59a 4775
screamer 0:c5e2f793b59a 4776 /*!
screamer 0:c5e2f793b59a 4777 * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
screamer 0:c5e2f793b59a 4778 *
screamer 0:c5e2f793b59a 4779 * Selects the PWM Synchronization mode.
screamer 0:c5e2f793b59a 4780 *
screamer 0:c5e2f793b59a 4781 * Values:
screamer 0:c5e2f793b59a 4782 * - 0 - Legacy PWM synchronization is selected.
screamer 0:c5e2f793b59a 4783 * - 1 - Enhanced PWM synchronization is selected.
screamer 0:c5e2f793b59a 4784 */
screamer 0:c5e2f793b59a 4785 /*@{*/
screamer 0:c5e2f793b59a 4786 #define BP_FTM_SYNCONF_SYNCMODE (7U) /*!< Bit position for FTM_SYNCONF_SYNCMODE. */
screamer 0:c5e2f793b59a 4787 #define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /*!< Bit mask for FTM_SYNCONF_SYNCMODE. */
screamer 0:c5e2f793b59a 4788 #define BS_FTM_SYNCONF_SYNCMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. */
screamer 0:c5e2f793b59a 4789
screamer 0:c5e2f793b59a 4790 /*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
screamer 0:c5e2f793b59a 4791 #define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
screamer 0:c5e2f793b59a 4792
screamer 0:c5e2f793b59a 4793 /*! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. */
screamer 0:c5e2f793b59a 4794 #define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE)
screamer 0:c5e2f793b59a 4795
screamer 0:c5e2f793b59a 4796 /*! @brief Set the SYNCMODE field to a new value. */
screamer 0:c5e2f793b59a 4797 #define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
screamer 0:c5e2f793b59a 4798 /*@}*/
screamer 0:c5e2f793b59a 4799
screamer 0:c5e2f793b59a 4800 /*!
screamer 0:c5e2f793b59a 4801 * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
screamer 0:c5e2f793b59a 4802 *
screamer 0:c5e2f793b59a 4803 * FTM counter synchronization is activated by the software trigger.
screamer 0:c5e2f793b59a 4804 *
screamer 0:c5e2f793b59a 4805 * Values:
screamer 0:c5e2f793b59a 4806 * - 0 - The software trigger does not activate the FTM counter synchronization.
screamer 0:c5e2f793b59a 4807 * - 1 - The software trigger activates the FTM counter synchronization.
screamer 0:c5e2f793b59a 4808 */
screamer 0:c5e2f793b59a 4809 /*@{*/
screamer 0:c5e2f793b59a 4810 #define BP_FTM_SYNCONF_SWRSTCNT (8U) /*!< Bit position for FTM_SYNCONF_SWRSTCNT. */
screamer 0:c5e2f793b59a 4811 #define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /*!< Bit mask for FTM_SYNCONF_SWRSTCNT. */
screamer 0:c5e2f793b59a 4812 #define BS_FTM_SYNCONF_SWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. */
screamer 0:c5e2f793b59a 4813
screamer 0:c5e2f793b59a 4814 /*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
screamer 0:c5e2f793b59a 4815 #define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
screamer 0:c5e2f793b59a 4816
screamer 0:c5e2f793b59a 4817 /*! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. */
screamer 0:c5e2f793b59a 4818 #define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT)
screamer 0:c5e2f793b59a 4819
screamer 0:c5e2f793b59a 4820 /*! @brief Set the SWRSTCNT field to a new value. */
screamer 0:c5e2f793b59a 4821 #define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
screamer 0:c5e2f793b59a 4822 /*@}*/
screamer 0:c5e2f793b59a 4823
screamer 0:c5e2f793b59a 4824 /*!
screamer 0:c5e2f793b59a 4825 * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
screamer 0:c5e2f793b59a 4826 *
screamer 0:c5e2f793b59a 4827 * MOD, CNTIN, and CV registers synchronization is activated by the software
screamer 0:c5e2f793b59a 4828 * trigger.
screamer 0:c5e2f793b59a 4829 *
screamer 0:c5e2f793b59a 4830 * Values:
screamer 0:c5e2f793b59a 4831 * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
screamer 0:c5e2f793b59a 4832 * synchronization.
screamer 0:c5e2f793b59a 4833 * - 1 - The software trigger activates MOD, CNTIN, and CV registers
screamer 0:c5e2f793b59a 4834 * synchronization.
screamer 0:c5e2f793b59a 4835 */
screamer 0:c5e2f793b59a 4836 /*@{*/
screamer 0:c5e2f793b59a 4837 #define BP_FTM_SYNCONF_SWWRBUF (9U) /*!< Bit position for FTM_SYNCONF_SWWRBUF. */
screamer 0:c5e2f793b59a 4838 #define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /*!< Bit mask for FTM_SYNCONF_SWWRBUF. */
screamer 0:c5e2f793b59a 4839 #define BS_FTM_SYNCONF_SWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. */
screamer 0:c5e2f793b59a 4840
screamer 0:c5e2f793b59a 4841 /*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
screamer 0:c5e2f793b59a 4842 #define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
screamer 0:c5e2f793b59a 4843
screamer 0:c5e2f793b59a 4844 /*! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. */
screamer 0:c5e2f793b59a 4845 #define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF)
screamer 0:c5e2f793b59a 4846
screamer 0:c5e2f793b59a 4847 /*! @brief Set the SWWRBUF field to a new value. */
screamer 0:c5e2f793b59a 4848 #define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
screamer 0:c5e2f793b59a 4849 /*@}*/
screamer 0:c5e2f793b59a 4850
screamer 0:c5e2f793b59a 4851 /*!
screamer 0:c5e2f793b59a 4852 * @name Register FTM_SYNCONF, field SWOM[10] (RW)
screamer 0:c5e2f793b59a 4853 *
screamer 0:c5e2f793b59a 4854 * Output mask synchronization is activated by the software trigger.
screamer 0:c5e2f793b59a 4855 *
screamer 0:c5e2f793b59a 4856 * Values:
screamer 0:c5e2f793b59a 4857 * - 0 - The software trigger does not activate the OUTMASK register
screamer 0:c5e2f793b59a 4858 * synchronization.
screamer 0:c5e2f793b59a 4859 * - 1 - The software trigger activates the OUTMASK register synchronization.
screamer 0:c5e2f793b59a 4860 */
screamer 0:c5e2f793b59a 4861 /*@{*/
screamer 0:c5e2f793b59a 4862 #define BP_FTM_SYNCONF_SWOM (10U) /*!< Bit position for FTM_SYNCONF_SWOM. */
screamer 0:c5e2f793b59a 4863 #define BM_FTM_SYNCONF_SWOM (0x00000400U) /*!< Bit mask for FTM_SYNCONF_SWOM. */
screamer 0:c5e2f793b59a 4864 #define BS_FTM_SYNCONF_SWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOM. */
screamer 0:c5e2f793b59a 4865
screamer 0:c5e2f793b59a 4866 /*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
screamer 0:c5e2f793b59a 4867 #define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
screamer 0:c5e2f793b59a 4868
screamer 0:c5e2f793b59a 4869 /*! @brief Format value for bitfield FTM_SYNCONF_SWOM. */
screamer 0:c5e2f793b59a 4870 #define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM)
screamer 0:c5e2f793b59a 4871
screamer 0:c5e2f793b59a 4872 /*! @brief Set the SWOM field to a new value. */
screamer 0:c5e2f793b59a 4873 #define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
screamer 0:c5e2f793b59a 4874 /*@}*/
screamer 0:c5e2f793b59a 4875
screamer 0:c5e2f793b59a 4876 /*!
screamer 0:c5e2f793b59a 4877 * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
screamer 0:c5e2f793b59a 4878 *
screamer 0:c5e2f793b59a 4879 * Inverting control synchronization is activated by the software trigger.
screamer 0:c5e2f793b59a 4880 *
screamer 0:c5e2f793b59a 4881 * Values:
screamer 0:c5e2f793b59a 4882 * - 0 - The software trigger does not activate the INVCTRL register
screamer 0:c5e2f793b59a 4883 * synchronization.
screamer 0:c5e2f793b59a 4884 * - 1 - The software trigger activates the INVCTRL register synchronization.
screamer 0:c5e2f793b59a 4885 */
screamer 0:c5e2f793b59a 4886 /*@{*/
screamer 0:c5e2f793b59a 4887 #define BP_FTM_SYNCONF_SWINVC (11U) /*!< Bit position for FTM_SYNCONF_SWINVC. */
screamer 0:c5e2f793b59a 4888 #define BM_FTM_SYNCONF_SWINVC (0x00000800U) /*!< Bit mask for FTM_SYNCONF_SWINVC. */
screamer 0:c5e2f793b59a 4889 #define BS_FTM_SYNCONF_SWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWINVC. */
screamer 0:c5e2f793b59a 4890
screamer 0:c5e2f793b59a 4891 /*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
screamer 0:c5e2f793b59a 4892 #define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
screamer 0:c5e2f793b59a 4893
screamer 0:c5e2f793b59a 4894 /*! @brief Format value for bitfield FTM_SYNCONF_SWINVC. */
screamer 0:c5e2f793b59a 4895 #define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC)
screamer 0:c5e2f793b59a 4896
screamer 0:c5e2f793b59a 4897 /*! @brief Set the SWINVC field to a new value. */
screamer 0:c5e2f793b59a 4898 #define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
screamer 0:c5e2f793b59a 4899 /*@}*/
screamer 0:c5e2f793b59a 4900
screamer 0:c5e2f793b59a 4901 /*!
screamer 0:c5e2f793b59a 4902 * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
screamer 0:c5e2f793b59a 4903 *
screamer 0:c5e2f793b59a 4904 * Software output control synchronization is activated by the software trigger.
screamer 0:c5e2f793b59a 4905 *
screamer 0:c5e2f793b59a 4906 * Values:
screamer 0:c5e2f793b59a 4907 * - 0 - The software trigger does not activate the SWOCTRL register
screamer 0:c5e2f793b59a 4908 * synchronization.
screamer 0:c5e2f793b59a 4909 * - 1 - The software trigger activates the SWOCTRL register synchronization.
screamer 0:c5e2f793b59a 4910 */
screamer 0:c5e2f793b59a 4911 /*@{*/
screamer 0:c5e2f793b59a 4912 #define BP_FTM_SYNCONF_SWSOC (12U) /*!< Bit position for FTM_SYNCONF_SWSOC. */
screamer 0:c5e2f793b59a 4913 #define BM_FTM_SYNCONF_SWSOC (0x00001000U) /*!< Bit mask for FTM_SYNCONF_SWSOC. */
screamer 0:c5e2f793b59a 4914 #define BS_FTM_SYNCONF_SWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWSOC. */
screamer 0:c5e2f793b59a 4915
screamer 0:c5e2f793b59a 4916 /*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
screamer 0:c5e2f793b59a 4917 #define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
screamer 0:c5e2f793b59a 4918
screamer 0:c5e2f793b59a 4919 /*! @brief Format value for bitfield FTM_SYNCONF_SWSOC. */
screamer 0:c5e2f793b59a 4920 #define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC)
screamer 0:c5e2f793b59a 4921
screamer 0:c5e2f793b59a 4922 /*! @brief Set the SWSOC field to a new value. */
screamer 0:c5e2f793b59a 4923 #define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
screamer 0:c5e2f793b59a 4924 /*@}*/
screamer 0:c5e2f793b59a 4925
screamer 0:c5e2f793b59a 4926 /*!
screamer 0:c5e2f793b59a 4927 * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
screamer 0:c5e2f793b59a 4928 *
screamer 0:c5e2f793b59a 4929 * FTM counter synchronization is activated by a hardware trigger.
screamer 0:c5e2f793b59a 4930 *
screamer 0:c5e2f793b59a 4931 * Values:
screamer 0:c5e2f793b59a 4932 * - 0 - A hardware trigger does not activate the FTM counter synchronization.
screamer 0:c5e2f793b59a 4933 * - 1 - A hardware trigger activates the FTM counter synchronization.
screamer 0:c5e2f793b59a 4934 */
screamer 0:c5e2f793b59a 4935 /*@{*/
screamer 0:c5e2f793b59a 4936 #define BP_FTM_SYNCONF_HWRSTCNT (16U) /*!< Bit position for FTM_SYNCONF_HWRSTCNT. */
screamer 0:c5e2f793b59a 4937 #define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /*!< Bit mask for FTM_SYNCONF_HWRSTCNT. */
screamer 0:c5e2f793b59a 4938 #define BS_FTM_SYNCONF_HWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. */
screamer 0:c5e2f793b59a 4939
screamer 0:c5e2f793b59a 4940 /*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
screamer 0:c5e2f793b59a 4941 #define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
screamer 0:c5e2f793b59a 4942
screamer 0:c5e2f793b59a 4943 /*! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. */
screamer 0:c5e2f793b59a 4944 #define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT)
screamer 0:c5e2f793b59a 4945
screamer 0:c5e2f793b59a 4946 /*! @brief Set the HWRSTCNT field to a new value. */
screamer 0:c5e2f793b59a 4947 #define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
screamer 0:c5e2f793b59a 4948 /*@}*/
screamer 0:c5e2f793b59a 4949
screamer 0:c5e2f793b59a 4950 /*!
screamer 0:c5e2f793b59a 4951 * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
screamer 0:c5e2f793b59a 4952 *
screamer 0:c5e2f793b59a 4953 * MOD, CNTIN, and CV registers synchronization is activated by a hardware
screamer 0:c5e2f793b59a 4954 * trigger.
screamer 0:c5e2f793b59a 4955 *
screamer 0:c5e2f793b59a 4956 * Values:
screamer 0:c5e2f793b59a 4957 * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
screamer 0:c5e2f793b59a 4958 * synchronization.
screamer 0:c5e2f793b59a 4959 * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
screamer 0:c5e2f793b59a 4960 * synchronization.
screamer 0:c5e2f793b59a 4961 */
screamer 0:c5e2f793b59a 4962 /*@{*/
screamer 0:c5e2f793b59a 4963 #define BP_FTM_SYNCONF_HWWRBUF (17U) /*!< Bit position for FTM_SYNCONF_HWWRBUF. */
screamer 0:c5e2f793b59a 4964 #define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /*!< Bit mask for FTM_SYNCONF_HWWRBUF. */
screamer 0:c5e2f793b59a 4965 #define BS_FTM_SYNCONF_HWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. */
screamer 0:c5e2f793b59a 4966
screamer 0:c5e2f793b59a 4967 /*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
screamer 0:c5e2f793b59a 4968 #define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
screamer 0:c5e2f793b59a 4969
screamer 0:c5e2f793b59a 4970 /*! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. */
screamer 0:c5e2f793b59a 4971 #define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF)
screamer 0:c5e2f793b59a 4972
screamer 0:c5e2f793b59a 4973 /*! @brief Set the HWWRBUF field to a new value. */
screamer 0:c5e2f793b59a 4974 #define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
screamer 0:c5e2f793b59a 4975 /*@}*/
screamer 0:c5e2f793b59a 4976
screamer 0:c5e2f793b59a 4977 /*!
screamer 0:c5e2f793b59a 4978 * @name Register FTM_SYNCONF, field HWOM[18] (RW)
screamer 0:c5e2f793b59a 4979 *
screamer 0:c5e2f793b59a 4980 * Output mask synchronization is activated by a hardware trigger.
screamer 0:c5e2f793b59a 4981 *
screamer 0:c5e2f793b59a 4982 * Values:
screamer 0:c5e2f793b59a 4983 * - 0 - A hardware trigger does not activate the OUTMASK register
screamer 0:c5e2f793b59a 4984 * synchronization.
screamer 0:c5e2f793b59a 4985 * - 1 - A hardware trigger activates the OUTMASK register synchronization.
screamer 0:c5e2f793b59a 4986 */
screamer 0:c5e2f793b59a 4987 /*@{*/
screamer 0:c5e2f793b59a 4988 #define BP_FTM_SYNCONF_HWOM (18U) /*!< Bit position for FTM_SYNCONF_HWOM. */
screamer 0:c5e2f793b59a 4989 #define BM_FTM_SYNCONF_HWOM (0x00040000U) /*!< Bit mask for FTM_SYNCONF_HWOM. */
screamer 0:c5e2f793b59a 4990 #define BS_FTM_SYNCONF_HWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWOM. */
screamer 0:c5e2f793b59a 4991
screamer 0:c5e2f793b59a 4992 /*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
screamer 0:c5e2f793b59a 4993 #define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
screamer 0:c5e2f793b59a 4994
screamer 0:c5e2f793b59a 4995 /*! @brief Format value for bitfield FTM_SYNCONF_HWOM. */
screamer 0:c5e2f793b59a 4996 #define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM)
screamer 0:c5e2f793b59a 4997
screamer 0:c5e2f793b59a 4998 /*! @brief Set the HWOM field to a new value. */
screamer 0:c5e2f793b59a 4999 #define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
screamer 0:c5e2f793b59a 5000 /*@}*/
screamer 0:c5e2f793b59a 5001
screamer 0:c5e2f793b59a 5002 /*!
screamer 0:c5e2f793b59a 5003 * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
screamer 0:c5e2f793b59a 5004 *
screamer 0:c5e2f793b59a 5005 * Inverting control synchronization is activated by a hardware trigger.
screamer 0:c5e2f793b59a 5006 *
screamer 0:c5e2f793b59a 5007 * Values:
screamer 0:c5e2f793b59a 5008 * - 0 - A hardware trigger does not activate the INVCTRL register
screamer 0:c5e2f793b59a 5009 * synchronization.
screamer 0:c5e2f793b59a 5010 * - 1 - A hardware trigger activates the INVCTRL register synchronization.
screamer 0:c5e2f793b59a 5011 */
screamer 0:c5e2f793b59a 5012 /*@{*/
screamer 0:c5e2f793b59a 5013 #define BP_FTM_SYNCONF_HWINVC (19U) /*!< Bit position for FTM_SYNCONF_HWINVC. */
screamer 0:c5e2f793b59a 5014 #define BM_FTM_SYNCONF_HWINVC (0x00080000U) /*!< Bit mask for FTM_SYNCONF_HWINVC. */
screamer 0:c5e2f793b59a 5015 #define BS_FTM_SYNCONF_HWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWINVC. */
screamer 0:c5e2f793b59a 5016
screamer 0:c5e2f793b59a 5017 /*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
screamer 0:c5e2f793b59a 5018 #define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
screamer 0:c5e2f793b59a 5019
screamer 0:c5e2f793b59a 5020 /*! @brief Format value for bitfield FTM_SYNCONF_HWINVC. */
screamer 0:c5e2f793b59a 5021 #define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC)
screamer 0:c5e2f793b59a 5022
screamer 0:c5e2f793b59a 5023 /*! @brief Set the HWINVC field to a new value. */
screamer 0:c5e2f793b59a 5024 #define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
screamer 0:c5e2f793b59a 5025 /*@}*/
screamer 0:c5e2f793b59a 5026
screamer 0:c5e2f793b59a 5027 /*!
screamer 0:c5e2f793b59a 5028 * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
screamer 0:c5e2f793b59a 5029 *
screamer 0:c5e2f793b59a 5030 * Software output control synchronization is activated by a hardware trigger.
screamer 0:c5e2f793b59a 5031 *
screamer 0:c5e2f793b59a 5032 * Values:
screamer 0:c5e2f793b59a 5033 * - 0 - A hardware trigger does not activate the SWOCTRL register
screamer 0:c5e2f793b59a 5034 * synchronization.
screamer 0:c5e2f793b59a 5035 * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
screamer 0:c5e2f793b59a 5036 */
screamer 0:c5e2f793b59a 5037 /*@{*/
screamer 0:c5e2f793b59a 5038 #define BP_FTM_SYNCONF_HWSOC (20U) /*!< Bit position for FTM_SYNCONF_HWSOC. */
screamer 0:c5e2f793b59a 5039 #define BM_FTM_SYNCONF_HWSOC (0x00100000U) /*!< Bit mask for FTM_SYNCONF_HWSOC. */
screamer 0:c5e2f793b59a 5040 #define BS_FTM_SYNCONF_HWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWSOC. */
screamer 0:c5e2f793b59a 5041
screamer 0:c5e2f793b59a 5042 /*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
screamer 0:c5e2f793b59a 5043 #define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
screamer 0:c5e2f793b59a 5044
screamer 0:c5e2f793b59a 5045 /*! @brief Format value for bitfield FTM_SYNCONF_HWSOC. */
screamer 0:c5e2f793b59a 5046 #define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC)
screamer 0:c5e2f793b59a 5047
screamer 0:c5e2f793b59a 5048 /*! @brief Set the HWSOC field to a new value. */
screamer 0:c5e2f793b59a 5049 #define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
screamer 0:c5e2f793b59a 5050 /*@}*/
screamer 0:c5e2f793b59a 5051
screamer 0:c5e2f793b59a 5052 /*******************************************************************************
screamer 0:c5e2f793b59a 5053 * HW_FTM_INVCTRL - FTM Inverting Control
screamer 0:c5e2f793b59a 5054 ******************************************************************************/
screamer 0:c5e2f793b59a 5055
screamer 0:c5e2f793b59a 5056 /*!
screamer 0:c5e2f793b59a 5057 * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
screamer 0:c5e2f793b59a 5058 *
screamer 0:c5e2f793b59a 5059 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 5060 *
screamer 0:c5e2f793b59a 5061 * This register controls when the channel (n) output becomes the channel (n+1)
screamer 0:c5e2f793b59a 5062 * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
screamer 0:c5e2f793b59a 5063 * bit enables the inverting operation for the corresponding pair channels m. This
screamer 0:c5e2f793b59a 5064 * register has a write buffer. The INVmEN bit is updated by the INVCTRL
screamer 0:c5e2f793b59a 5065 * register synchronization.
screamer 0:c5e2f793b59a 5066 */
screamer 0:c5e2f793b59a 5067 typedef union _hw_ftm_invctrl
screamer 0:c5e2f793b59a 5068 {
screamer 0:c5e2f793b59a 5069 uint32_t U;
screamer 0:c5e2f793b59a 5070 struct _hw_ftm_invctrl_bitfields
screamer 0:c5e2f793b59a 5071 {
screamer 0:c5e2f793b59a 5072 uint32_t INV0EN : 1; /*!< [0] Pair Channels 0 Inverting Enable */
screamer 0:c5e2f793b59a 5073 uint32_t INV1EN : 1; /*!< [1] Pair Channels 1 Inverting Enable */
screamer 0:c5e2f793b59a 5074 uint32_t INV2EN : 1; /*!< [2] Pair Channels 2 Inverting Enable */
screamer 0:c5e2f793b59a 5075 uint32_t INV3EN : 1; /*!< [3] Pair Channels 3 Inverting Enable */
screamer 0:c5e2f793b59a 5076 uint32_t RESERVED0 : 28; /*!< [31:4] */
screamer 0:c5e2f793b59a 5077 } B;
screamer 0:c5e2f793b59a 5078 } hw_ftm_invctrl_t;
screamer 0:c5e2f793b59a 5079
screamer 0:c5e2f793b59a 5080 /*!
screamer 0:c5e2f793b59a 5081 * @name Constants and macros for entire FTM_INVCTRL register
screamer 0:c5e2f793b59a 5082 */
screamer 0:c5e2f793b59a 5083 /*@{*/
screamer 0:c5e2f793b59a 5084 #define HW_FTM_INVCTRL_ADDR(x) ((x) + 0x90U)
screamer 0:c5e2f793b59a 5085
screamer 0:c5e2f793b59a 5086 #define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
screamer 0:c5e2f793b59a 5087 #define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
screamer 0:c5e2f793b59a 5088 #define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
screamer 0:c5e2f793b59a 5089 #define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v)))
screamer 0:c5e2f793b59a 5090 #define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 5091 #define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 5092 /*@}*/
screamer 0:c5e2f793b59a 5093
screamer 0:c5e2f793b59a 5094 /*
screamer 0:c5e2f793b59a 5095 * Constants & macros for individual FTM_INVCTRL bitfields
screamer 0:c5e2f793b59a 5096 */
screamer 0:c5e2f793b59a 5097
screamer 0:c5e2f793b59a 5098 /*!
screamer 0:c5e2f793b59a 5099 * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
screamer 0:c5e2f793b59a 5100 *
screamer 0:c5e2f793b59a 5101 * Values:
screamer 0:c5e2f793b59a 5102 * - 0 - Inverting is disabled.
screamer 0:c5e2f793b59a 5103 * - 1 - Inverting is enabled.
screamer 0:c5e2f793b59a 5104 */
screamer 0:c5e2f793b59a 5105 /*@{*/
screamer 0:c5e2f793b59a 5106 #define BP_FTM_INVCTRL_INV0EN (0U) /*!< Bit position for FTM_INVCTRL_INV0EN. */
screamer 0:c5e2f793b59a 5107 #define BM_FTM_INVCTRL_INV0EN (0x00000001U) /*!< Bit mask for FTM_INVCTRL_INV0EN. */
screamer 0:c5e2f793b59a 5108 #define BS_FTM_INVCTRL_INV0EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV0EN. */
screamer 0:c5e2f793b59a 5109
screamer 0:c5e2f793b59a 5110 /*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
screamer 0:c5e2f793b59a 5111 #define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
screamer 0:c5e2f793b59a 5112
screamer 0:c5e2f793b59a 5113 /*! @brief Format value for bitfield FTM_INVCTRL_INV0EN. */
screamer 0:c5e2f793b59a 5114 #define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN)
screamer 0:c5e2f793b59a 5115
screamer 0:c5e2f793b59a 5116 /*! @brief Set the INV0EN field to a new value. */
screamer 0:c5e2f793b59a 5117 #define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
screamer 0:c5e2f793b59a 5118 /*@}*/
screamer 0:c5e2f793b59a 5119
screamer 0:c5e2f793b59a 5120 /*!
screamer 0:c5e2f793b59a 5121 * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
screamer 0:c5e2f793b59a 5122 *
screamer 0:c5e2f793b59a 5123 * Values:
screamer 0:c5e2f793b59a 5124 * - 0 - Inverting is disabled.
screamer 0:c5e2f793b59a 5125 * - 1 - Inverting is enabled.
screamer 0:c5e2f793b59a 5126 */
screamer 0:c5e2f793b59a 5127 /*@{*/
screamer 0:c5e2f793b59a 5128 #define BP_FTM_INVCTRL_INV1EN (1U) /*!< Bit position for FTM_INVCTRL_INV1EN. */
screamer 0:c5e2f793b59a 5129 #define BM_FTM_INVCTRL_INV1EN (0x00000002U) /*!< Bit mask for FTM_INVCTRL_INV1EN. */
screamer 0:c5e2f793b59a 5130 #define BS_FTM_INVCTRL_INV1EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV1EN. */
screamer 0:c5e2f793b59a 5131
screamer 0:c5e2f793b59a 5132 /*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
screamer 0:c5e2f793b59a 5133 #define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
screamer 0:c5e2f793b59a 5134
screamer 0:c5e2f793b59a 5135 /*! @brief Format value for bitfield FTM_INVCTRL_INV1EN. */
screamer 0:c5e2f793b59a 5136 #define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN)
screamer 0:c5e2f793b59a 5137
screamer 0:c5e2f793b59a 5138 /*! @brief Set the INV1EN field to a new value. */
screamer 0:c5e2f793b59a 5139 #define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
screamer 0:c5e2f793b59a 5140 /*@}*/
screamer 0:c5e2f793b59a 5141
screamer 0:c5e2f793b59a 5142 /*!
screamer 0:c5e2f793b59a 5143 * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
screamer 0:c5e2f793b59a 5144 *
screamer 0:c5e2f793b59a 5145 * Values:
screamer 0:c5e2f793b59a 5146 * - 0 - Inverting is disabled.
screamer 0:c5e2f793b59a 5147 * - 1 - Inverting is enabled.
screamer 0:c5e2f793b59a 5148 */
screamer 0:c5e2f793b59a 5149 /*@{*/
screamer 0:c5e2f793b59a 5150 #define BP_FTM_INVCTRL_INV2EN (2U) /*!< Bit position for FTM_INVCTRL_INV2EN. */
screamer 0:c5e2f793b59a 5151 #define BM_FTM_INVCTRL_INV2EN (0x00000004U) /*!< Bit mask for FTM_INVCTRL_INV2EN. */
screamer 0:c5e2f793b59a 5152 #define BS_FTM_INVCTRL_INV2EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV2EN. */
screamer 0:c5e2f793b59a 5153
screamer 0:c5e2f793b59a 5154 /*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
screamer 0:c5e2f793b59a 5155 #define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
screamer 0:c5e2f793b59a 5156
screamer 0:c5e2f793b59a 5157 /*! @brief Format value for bitfield FTM_INVCTRL_INV2EN. */
screamer 0:c5e2f793b59a 5158 #define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN)
screamer 0:c5e2f793b59a 5159
screamer 0:c5e2f793b59a 5160 /*! @brief Set the INV2EN field to a new value. */
screamer 0:c5e2f793b59a 5161 #define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
screamer 0:c5e2f793b59a 5162 /*@}*/
screamer 0:c5e2f793b59a 5163
screamer 0:c5e2f793b59a 5164 /*!
screamer 0:c5e2f793b59a 5165 * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
screamer 0:c5e2f793b59a 5166 *
screamer 0:c5e2f793b59a 5167 * Values:
screamer 0:c5e2f793b59a 5168 * - 0 - Inverting is disabled.
screamer 0:c5e2f793b59a 5169 * - 1 - Inverting is enabled.
screamer 0:c5e2f793b59a 5170 */
screamer 0:c5e2f793b59a 5171 /*@{*/
screamer 0:c5e2f793b59a 5172 #define BP_FTM_INVCTRL_INV3EN (3U) /*!< Bit position for FTM_INVCTRL_INV3EN. */
screamer 0:c5e2f793b59a 5173 #define BM_FTM_INVCTRL_INV3EN (0x00000008U) /*!< Bit mask for FTM_INVCTRL_INV3EN. */
screamer 0:c5e2f793b59a 5174 #define BS_FTM_INVCTRL_INV3EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV3EN. */
screamer 0:c5e2f793b59a 5175
screamer 0:c5e2f793b59a 5176 /*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
screamer 0:c5e2f793b59a 5177 #define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
screamer 0:c5e2f793b59a 5178
screamer 0:c5e2f793b59a 5179 /*! @brief Format value for bitfield FTM_INVCTRL_INV3EN. */
screamer 0:c5e2f793b59a 5180 #define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN)
screamer 0:c5e2f793b59a 5181
screamer 0:c5e2f793b59a 5182 /*! @brief Set the INV3EN field to a new value. */
screamer 0:c5e2f793b59a 5183 #define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
screamer 0:c5e2f793b59a 5184 /*@}*/
screamer 0:c5e2f793b59a 5185
screamer 0:c5e2f793b59a 5186 /*******************************************************************************
screamer 0:c5e2f793b59a 5187 * HW_FTM_SWOCTRL - FTM Software Output Control
screamer 0:c5e2f793b59a 5188 ******************************************************************************/
screamer 0:c5e2f793b59a 5189
screamer 0:c5e2f793b59a 5190 /*!
screamer 0:c5e2f793b59a 5191 * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
screamer 0:c5e2f793b59a 5192 *
screamer 0:c5e2f793b59a 5193 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 5194 *
screamer 0:c5e2f793b59a 5195 * This register enables software control of channel (n) output and defines the
screamer 0:c5e2f793b59a 5196 * value forced to the channel (n) output: The CHnOC bits enable the control of
screamer 0:c5e2f793b59a 5197 * the corresponding channel (n) output by software. The CHnOCV bits select the
screamer 0:c5e2f793b59a 5198 * value that is forced at the corresponding channel (n) output. This register has
screamer 0:c5e2f793b59a 5199 * a write buffer. The fields are updated by the SWOCTRL register synchronization.
screamer 0:c5e2f793b59a 5200 */
screamer 0:c5e2f793b59a 5201 typedef union _hw_ftm_swoctrl
screamer 0:c5e2f793b59a 5202 {
screamer 0:c5e2f793b59a 5203 uint32_t U;
screamer 0:c5e2f793b59a 5204 struct _hw_ftm_swoctrl_bitfields
screamer 0:c5e2f793b59a 5205 {
screamer 0:c5e2f793b59a 5206 uint32_t CH0OC : 1; /*!< [0] Channel 0 Software Output Control Enable
screamer 0:c5e2f793b59a 5207 * */
screamer 0:c5e2f793b59a 5208 uint32_t CH1OC : 1; /*!< [1] Channel 1 Software Output Control Enable
screamer 0:c5e2f793b59a 5209 * */
screamer 0:c5e2f793b59a 5210 uint32_t CH2OC : 1; /*!< [2] Channel 2 Software Output Control Enable
screamer 0:c5e2f793b59a 5211 * */
screamer 0:c5e2f793b59a 5212 uint32_t CH3OC : 1; /*!< [3] Channel 3 Software Output Control Enable
screamer 0:c5e2f793b59a 5213 * */
screamer 0:c5e2f793b59a 5214 uint32_t CH4OC : 1; /*!< [4] Channel 4 Software Output Control Enable
screamer 0:c5e2f793b59a 5215 * */
screamer 0:c5e2f793b59a 5216 uint32_t CH5OC : 1; /*!< [5] Channel 5 Software Output Control Enable
screamer 0:c5e2f793b59a 5217 * */
screamer 0:c5e2f793b59a 5218 uint32_t CH6OC : 1; /*!< [6] Channel 6 Software Output Control Enable
screamer 0:c5e2f793b59a 5219 * */
screamer 0:c5e2f793b59a 5220 uint32_t CH7OC : 1; /*!< [7] Channel 7 Software Output Control Enable
screamer 0:c5e2f793b59a 5221 * */
screamer 0:c5e2f793b59a 5222 uint32_t CH0OCV : 1; /*!< [8] Channel 0 Software Output Control Value
screamer 0:c5e2f793b59a 5223 * */
screamer 0:c5e2f793b59a 5224 uint32_t CH1OCV : 1; /*!< [9] Channel 1 Software Output Control Value
screamer 0:c5e2f793b59a 5225 * */
screamer 0:c5e2f793b59a 5226 uint32_t CH2OCV : 1; /*!< [10] Channel 2 Software Output Control
screamer 0:c5e2f793b59a 5227 * Value */
screamer 0:c5e2f793b59a 5228 uint32_t CH3OCV : 1; /*!< [11] Channel 3 Software Output Control
screamer 0:c5e2f793b59a 5229 * Value */
screamer 0:c5e2f793b59a 5230 uint32_t CH4OCV : 1; /*!< [12] Channel 4 Software Output Control
screamer 0:c5e2f793b59a 5231 * Value */
screamer 0:c5e2f793b59a 5232 uint32_t CH5OCV : 1; /*!< [13] Channel 5 Software Output Control
screamer 0:c5e2f793b59a 5233 * Value */
screamer 0:c5e2f793b59a 5234 uint32_t CH6OCV : 1; /*!< [14] Channel 6 Software Output Control
screamer 0:c5e2f793b59a 5235 * Value */
screamer 0:c5e2f793b59a 5236 uint32_t CH7OCV : 1; /*!< [15] Channel 7 Software Output Control
screamer 0:c5e2f793b59a 5237 * Value */
screamer 0:c5e2f793b59a 5238 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 5239 } B;
screamer 0:c5e2f793b59a 5240 } hw_ftm_swoctrl_t;
screamer 0:c5e2f793b59a 5241
screamer 0:c5e2f793b59a 5242 /*!
screamer 0:c5e2f793b59a 5243 * @name Constants and macros for entire FTM_SWOCTRL register
screamer 0:c5e2f793b59a 5244 */
screamer 0:c5e2f793b59a 5245 /*@{*/
screamer 0:c5e2f793b59a 5246 #define HW_FTM_SWOCTRL_ADDR(x) ((x) + 0x94U)
screamer 0:c5e2f793b59a 5247
screamer 0:c5e2f793b59a 5248 #define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
screamer 0:c5e2f793b59a 5249 #define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
screamer 0:c5e2f793b59a 5250 #define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
screamer 0:c5e2f793b59a 5251 #define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v)))
screamer 0:c5e2f793b59a 5252 #define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 5253 #define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 5254 /*@}*/
screamer 0:c5e2f793b59a 5255
screamer 0:c5e2f793b59a 5256 /*
screamer 0:c5e2f793b59a 5257 * Constants & macros for individual FTM_SWOCTRL bitfields
screamer 0:c5e2f793b59a 5258 */
screamer 0:c5e2f793b59a 5259
screamer 0:c5e2f793b59a 5260 /*!
screamer 0:c5e2f793b59a 5261 * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
screamer 0:c5e2f793b59a 5262 *
screamer 0:c5e2f793b59a 5263 * Values:
screamer 0:c5e2f793b59a 5264 * - 0 - The channel output is not affected by software output control.
screamer 0:c5e2f793b59a 5265 * - 1 - The channel output is affected by software output control.
screamer 0:c5e2f793b59a 5266 */
screamer 0:c5e2f793b59a 5267 /*@{*/
screamer 0:c5e2f793b59a 5268 #define BP_FTM_SWOCTRL_CH0OC (0U) /*!< Bit position for FTM_SWOCTRL_CH0OC. */
screamer 0:c5e2f793b59a 5269 #define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /*!< Bit mask for FTM_SWOCTRL_CH0OC. */
screamer 0:c5e2f793b59a 5270 #define BS_FTM_SWOCTRL_CH0OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OC. */
screamer 0:c5e2f793b59a 5271
screamer 0:c5e2f793b59a 5272 /*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
screamer 0:c5e2f793b59a 5273 #define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
screamer 0:c5e2f793b59a 5274
screamer 0:c5e2f793b59a 5275 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. */
screamer 0:c5e2f793b59a 5276 #define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC)
screamer 0:c5e2f793b59a 5277
screamer 0:c5e2f793b59a 5278 /*! @brief Set the CH0OC field to a new value. */
screamer 0:c5e2f793b59a 5279 #define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
screamer 0:c5e2f793b59a 5280 /*@}*/
screamer 0:c5e2f793b59a 5281
screamer 0:c5e2f793b59a 5282 /*!
screamer 0:c5e2f793b59a 5283 * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
screamer 0:c5e2f793b59a 5284 *
screamer 0:c5e2f793b59a 5285 * Values:
screamer 0:c5e2f793b59a 5286 * - 0 - The channel output is not affected by software output control.
screamer 0:c5e2f793b59a 5287 * - 1 - The channel output is affected by software output control.
screamer 0:c5e2f793b59a 5288 */
screamer 0:c5e2f793b59a 5289 /*@{*/
screamer 0:c5e2f793b59a 5290 #define BP_FTM_SWOCTRL_CH1OC (1U) /*!< Bit position for FTM_SWOCTRL_CH1OC. */
screamer 0:c5e2f793b59a 5291 #define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /*!< Bit mask for FTM_SWOCTRL_CH1OC. */
screamer 0:c5e2f793b59a 5292 #define BS_FTM_SWOCTRL_CH1OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OC. */
screamer 0:c5e2f793b59a 5293
screamer 0:c5e2f793b59a 5294 /*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
screamer 0:c5e2f793b59a 5295 #define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
screamer 0:c5e2f793b59a 5296
screamer 0:c5e2f793b59a 5297 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. */
screamer 0:c5e2f793b59a 5298 #define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC)
screamer 0:c5e2f793b59a 5299
screamer 0:c5e2f793b59a 5300 /*! @brief Set the CH1OC field to a new value. */
screamer 0:c5e2f793b59a 5301 #define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
screamer 0:c5e2f793b59a 5302 /*@}*/
screamer 0:c5e2f793b59a 5303
screamer 0:c5e2f793b59a 5304 /*!
screamer 0:c5e2f793b59a 5305 * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
screamer 0:c5e2f793b59a 5306 *
screamer 0:c5e2f793b59a 5307 * Values:
screamer 0:c5e2f793b59a 5308 * - 0 - The channel output is not affected by software output control.
screamer 0:c5e2f793b59a 5309 * - 1 - The channel output is affected by software output control.
screamer 0:c5e2f793b59a 5310 */
screamer 0:c5e2f793b59a 5311 /*@{*/
screamer 0:c5e2f793b59a 5312 #define BP_FTM_SWOCTRL_CH2OC (2U) /*!< Bit position for FTM_SWOCTRL_CH2OC. */
screamer 0:c5e2f793b59a 5313 #define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /*!< Bit mask for FTM_SWOCTRL_CH2OC. */
screamer 0:c5e2f793b59a 5314 #define BS_FTM_SWOCTRL_CH2OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OC. */
screamer 0:c5e2f793b59a 5315
screamer 0:c5e2f793b59a 5316 /*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
screamer 0:c5e2f793b59a 5317 #define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
screamer 0:c5e2f793b59a 5318
screamer 0:c5e2f793b59a 5319 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. */
screamer 0:c5e2f793b59a 5320 #define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC)
screamer 0:c5e2f793b59a 5321
screamer 0:c5e2f793b59a 5322 /*! @brief Set the CH2OC field to a new value. */
screamer 0:c5e2f793b59a 5323 #define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
screamer 0:c5e2f793b59a 5324 /*@}*/
screamer 0:c5e2f793b59a 5325
screamer 0:c5e2f793b59a 5326 /*!
screamer 0:c5e2f793b59a 5327 * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
screamer 0:c5e2f793b59a 5328 *
screamer 0:c5e2f793b59a 5329 * Values:
screamer 0:c5e2f793b59a 5330 * - 0 - The channel output is not affected by software output control.
screamer 0:c5e2f793b59a 5331 * - 1 - The channel output is affected by software output control.
screamer 0:c5e2f793b59a 5332 */
screamer 0:c5e2f793b59a 5333 /*@{*/
screamer 0:c5e2f793b59a 5334 #define BP_FTM_SWOCTRL_CH3OC (3U) /*!< Bit position for FTM_SWOCTRL_CH3OC. */
screamer 0:c5e2f793b59a 5335 #define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /*!< Bit mask for FTM_SWOCTRL_CH3OC. */
screamer 0:c5e2f793b59a 5336 #define BS_FTM_SWOCTRL_CH3OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OC. */
screamer 0:c5e2f793b59a 5337
screamer 0:c5e2f793b59a 5338 /*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
screamer 0:c5e2f793b59a 5339 #define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
screamer 0:c5e2f793b59a 5340
screamer 0:c5e2f793b59a 5341 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. */
screamer 0:c5e2f793b59a 5342 #define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC)
screamer 0:c5e2f793b59a 5343
screamer 0:c5e2f793b59a 5344 /*! @brief Set the CH3OC field to a new value. */
screamer 0:c5e2f793b59a 5345 #define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
screamer 0:c5e2f793b59a 5346 /*@}*/
screamer 0:c5e2f793b59a 5347
screamer 0:c5e2f793b59a 5348 /*!
screamer 0:c5e2f793b59a 5349 * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
screamer 0:c5e2f793b59a 5350 *
screamer 0:c5e2f793b59a 5351 * Values:
screamer 0:c5e2f793b59a 5352 * - 0 - The channel output is not affected by software output control.
screamer 0:c5e2f793b59a 5353 * - 1 - The channel output is affected by software output control.
screamer 0:c5e2f793b59a 5354 */
screamer 0:c5e2f793b59a 5355 /*@{*/
screamer 0:c5e2f793b59a 5356 #define BP_FTM_SWOCTRL_CH4OC (4U) /*!< Bit position for FTM_SWOCTRL_CH4OC. */
screamer 0:c5e2f793b59a 5357 #define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /*!< Bit mask for FTM_SWOCTRL_CH4OC. */
screamer 0:c5e2f793b59a 5358 #define BS_FTM_SWOCTRL_CH4OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OC. */
screamer 0:c5e2f793b59a 5359
screamer 0:c5e2f793b59a 5360 /*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
screamer 0:c5e2f793b59a 5361 #define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
screamer 0:c5e2f793b59a 5362
screamer 0:c5e2f793b59a 5363 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. */
screamer 0:c5e2f793b59a 5364 #define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC)
screamer 0:c5e2f793b59a 5365
screamer 0:c5e2f793b59a 5366 /*! @brief Set the CH4OC field to a new value. */
screamer 0:c5e2f793b59a 5367 #define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
screamer 0:c5e2f793b59a 5368 /*@}*/
screamer 0:c5e2f793b59a 5369
screamer 0:c5e2f793b59a 5370 /*!
screamer 0:c5e2f793b59a 5371 * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
screamer 0:c5e2f793b59a 5372 *
screamer 0:c5e2f793b59a 5373 * Values:
screamer 0:c5e2f793b59a 5374 * - 0 - The channel output is not affected by software output control.
screamer 0:c5e2f793b59a 5375 * - 1 - The channel output is affected by software output control.
screamer 0:c5e2f793b59a 5376 */
screamer 0:c5e2f793b59a 5377 /*@{*/
screamer 0:c5e2f793b59a 5378 #define BP_FTM_SWOCTRL_CH5OC (5U) /*!< Bit position for FTM_SWOCTRL_CH5OC. */
screamer 0:c5e2f793b59a 5379 #define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /*!< Bit mask for FTM_SWOCTRL_CH5OC. */
screamer 0:c5e2f793b59a 5380 #define BS_FTM_SWOCTRL_CH5OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OC. */
screamer 0:c5e2f793b59a 5381
screamer 0:c5e2f793b59a 5382 /*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
screamer 0:c5e2f793b59a 5383 #define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
screamer 0:c5e2f793b59a 5384
screamer 0:c5e2f793b59a 5385 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. */
screamer 0:c5e2f793b59a 5386 #define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC)
screamer 0:c5e2f793b59a 5387
screamer 0:c5e2f793b59a 5388 /*! @brief Set the CH5OC field to a new value. */
screamer 0:c5e2f793b59a 5389 #define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
screamer 0:c5e2f793b59a 5390 /*@}*/
screamer 0:c5e2f793b59a 5391
screamer 0:c5e2f793b59a 5392 /*!
screamer 0:c5e2f793b59a 5393 * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
screamer 0:c5e2f793b59a 5394 *
screamer 0:c5e2f793b59a 5395 * Values:
screamer 0:c5e2f793b59a 5396 * - 0 - The channel output is not affected by software output control.
screamer 0:c5e2f793b59a 5397 * - 1 - The channel output is affected by software output control.
screamer 0:c5e2f793b59a 5398 */
screamer 0:c5e2f793b59a 5399 /*@{*/
screamer 0:c5e2f793b59a 5400 #define BP_FTM_SWOCTRL_CH6OC (6U) /*!< Bit position for FTM_SWOCTRL_CH6OC. */
screamer 0:c5e2f793b59a 5401 #define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /*!< Bit mask for FTM_SWOCTRL_CH6OC. */
screamer 0:c5e2f793b59a 5402 #define BS_FTM_SWOCTRL_CH6OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OC. */
screamer 0:c5e2f793b59a 5403
screamer 0:c5e2f793b59a 5404 /*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
screamer 0:c5e2f793b59a 5405 #define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
screamer 0:c5e2f793b59a 5406
screamer 0:c5e2f793b59a 5407 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. */
screamer 0:c5e2f793b59a 5408 #define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC)
screamer 0:c5e2f793b59a 5409
screamer 0:c5e2f793b59a 5410 /*! @brief Set the CH6OC field to a new value. */
screamer 0:c5e2f793b59a 5411 #define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
screamer 0:c5e2f793b59a 5412 /*@}*/
screamer 0:c5e2f793b59a 5413
screamer 0:c5e2f793b59a 5414 /*!
screamer 0:c5e2f793b59a 5415 * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
screamer 0:c5e2f793b59a 5416 *
screamer 0:c5e2f793b59a 5417 * Values:
screamer 0:c5e2f793b59a 5418 * - 0 - The channel output is not affected by software output control.
screamer 0:c5e2f793b59a 5419 * - 1 - The channel output is affected by software output control.
screamer 0:c5e2f793b59a 5420 */
screamer 0:c5e2f793b59a 5421 /*@{*/
screamer 0:c5e2f793b59a 5422 #define BP_FTM_SWOCTRL_CH7OC (7U) /*!< Bit position for FTM_SWOCTRL_CH7OC. */
screamer 0:c5e2f793b59a 5423 #define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /*!< Bit mask for FTM_SWOCTRL_CH7OC. */
screamer 0:c5e2f793b59a 5424 #define BS_FTM_SWOCTRL_CH7OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OC. */
screamer 0:c5e2f793b59a 5425
screamer 0:c5e2f793b59a 5426 /*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
screamer 0:c5e2f793b59a 5427 #define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
screamer 0:c5e2f793b59a 5428
screamer 0:c5e2f793b59a 5429 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. */
screamer 0:c5e2f793b59a 5430 #define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC)
screamer 0:c5e2f793b59a 5431
screamer 0:c5e2f793b59a 5432 /*! @brief Set the CH7OC field to a new value. */
screamer 0:c5e2f793b59a 5433 #define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
screamer 0:c5e2f793b59a 5434 /*@}*/
screamer 0:c5e2f793b59a 5435
screamer 0:c5e2f793b59a 5436 /*!
screamer 0:c5e2f793b59a 5437 * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
screamer 0:c5e2f793b59a 5438 *
screamer 0:c5e2f793b59a 5439 * Values:
screamer 0:c5e2f793b59a 5440 * - 0 - The software output control forces 0 to the channel output.
screamer 0:c5e2f793b59a 5441 * - 1 - The software output control forces 1 to the channel output.
screamer 0:c5e2f793b59a 5442 */
screamer 0:c5e2f793b59a 5443 /*@{*/
screamer 0:c5e2f793b59a 5444 #define BP_FTM_SWOCTRL_CH0OCV (8U) /*!< Bit position for FTM_SWOCTRL_CH0OCV. */
screamer 0:c5e2f793b59a 5445 #define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /*!< Bit mask for FTM_SWOCTRL_CH0OCV. */
screamer 0:c5e2f793b59a 5446 #define BS_FTM_SWOCTRL_CH0OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. */
screamer 0:c5e2f793b59a 5447
screamer 0:c5e2f793b59a 5448 /*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
screamer 0:c5e2f793b59a 5449 #define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
screamer 0:c5e2f793b59a 5450
screamer 0:c5e2f793b59a 5451 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. */
screamer 0:c5e2f793b59a 5452 #define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV)
screamer 0:c5e2f793b59a 5453
screamer 0:c5e2f793b59a 5454 /*! @brief Set the CH0OCV field to a new value. */
screamer 0:c5e2f793b59a 5455 #define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
screamer 0:c5e2f793b59a 5456 /*@}*/
screamer 0:c5e2f793b59a 5457
screamer 0:c5e2f793b59a 5458 /*!
screamer 0:c5e2f793b59a 5459 * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
screamer 0:c5e2f793b59a 5460 *
screamer 0:c5e2f793b59a 5461 * Values:
screamer 0:c5e2f793b59a 5462 * - 0 - The software output control forces 0 to the channel output.
screamer 0:c5e2f793b59a 5463 * - 1 - The software output control forces 1 to the channel output.
screamer 0:c5e2f793b59a 5464 */
screamer 0:c5e2f793b59a 5465 /*@{*/
screamer 0:c5e2f793b59a 5466 #define BP_FTM_SWOCTRL_CH1OCV (9U) /*!< Bit position for FTM_SWOCTRL_CH1OCV. */
screamer 0:c5e2f793b59a 5467 #define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /*!< Bit mask for FTM_SWOCTRL_CH1OCV. */
screamer 0:c5e2f793b59a 5468 #define BS_FTM_SWOCTRL_CH1OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. */
screamer 0:c5e2f793b59a 5469
screamer 0:c5e2f793b59a 5470 /*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
screamer 0:c5e2f793b59a 5471 #define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
screamer 0:c5e2f793b59a 5472
screamer 0:c5e2f793b59a 5473 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. */
screamer 0:c5e2f793b59a 5474 #define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV)
screamer 0:c5e2f793b59a 5475
screamer 0:c5e2f793b59a 5476 /*! @brief Set the CH1OCV field to a new value. */
screamer 0:c5e2f793b59a 5477 #define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
screamer 0:c5e2f793b59a 5478 /*@}*/
screamer 0:c5e2f793b59a 5479
screamer 0:c5e2f793b59a 5480 /*!
screamer 0:c5e2f793b59a 5481 * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
screamer 0:c5e2f793b59a 5482 *
screamer 0:c5e2f793b59a 5483 * Values:
screamer 0:c5e2f793b59a 5484 * - 0 - The software output control forces 0 to the channel output.
screamer 0:c5e2f793b59a 5485 * - 1 - The software output control forces 1 to the channel output.
screamer 0:c5e2f793b59a 5486 */
screamer 0:c5e2f793b59a 5487 /*@{*/
screamer 0:c5e2f793b59a 5488 #define BP_FTM_SWOCTRL_CH2OCV (10U) /*!< Bit position for FTM_SWOCTRL_CH2OCV. */
screamer 0:c5e2f793b59a 5489 #define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /*!< Bit mask for FTM_SWOCTRL_CH2OCV. */
screamer 0:c5e2f793b59a 5490 #define BS_FTM_SWOCTRL_CH2OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. */
screamer 0:c5e2f793b59a 5491
screamer 0:c5e2f793b59a 5492 /*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
screamer 0:c5e2f793b59a 5493 #define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
screamer 0:c5e2f793b59a 5494
screamer 0:c5e2f793b59a 5495 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. */
screamer 0:c5e2f793b59a 5496 #define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV)
screamer 0:c5e2f793b59a 5497
screamer 0:c5e2f793b59a 5498 /*! @brief Set the CH2OCV field to a new value. */
screamer 0:c5e2f793b59a 5499 #define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
screamer 0:c5e2f793b59a 5500 /*@}*/
screamer 0:c5e2f793b59a 5501
screamer 0:c5e2f793b59a 5502 /*!
screamer 0:c5e2f793b59a 5503 * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
screamer 0:c5e2f793b59a 5504 *
screamer 0:c5e2f793b59a 5505 * Values:
screamer 0:c5e2f793b59a 5506 * - 0 - The software output control forces 0 to the channel output.
screamer 0:c5e2f793b59a 5507 * - 1 - The software output control forces 1 to the channel output.
screamer 0:c5e2f793b59a 5508 */
screamer 0:c5e2f793b59a 5509 /*@{*/
screamer 0:c5e2f793b59a 5510 #define BP_FTM_SWOCTRL_CH3OCV (11U) /*!< Bit position for FTM_SWOCTRL_CH3OCV. */
screamer 0:c5e2f793b59a 5511 #define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /*!< Bit mask for FTM_SWOCTRL_CH3OCV. */
screamer 0:c5e2f793b59a 5512 #define BS_FTM_SWOCTRL_CH3OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. */
screamer 0:c5e2f793b59a 5513
screamer 0:c5e2f793b59a 5514 /*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
screamer 0:c5e2f793b59a 5515 #define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
screamer 0:c5e2f793b59a 5516
screamer 0:c5e2f793b59a 5517 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. */
screamer 0:c5e2f793b59a 5518 #define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV)
screamer 0:c5e2f793b59a 5519
screamer 0:c5e2f793b59a 5520 /*! @brief Set the CH3OCV field to a new value. */
screamer 0:c5e2f793b59a 5521 #define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
screamer 0:c5e2f793b59a 5522 /*@}*/
screamer 0:c5e2f793b59a 5523
screamer 0:c5e2f793b59a 5524 /*!
screamer 0:c5e2f793b59a 5525 * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
screamer 0:c5e2f793b59a 5526 *
screamer 0:c5e2f793b59a 5527 * Values:
screamer 0:c5e2f793b59a 5528 * - 0 - The software output control forces 0 to the channel output.
screamer 0:c5e2f793b59a 5529 * - 1 - The software output control forces 1 to the channel output.
screamer 0:c5e2f793b59a 5530 */
screamer 0:c5e2f793b59a 5531 /*@{*/
screamer 0:c5e2f793b59a 5532 #define BP_FTM_SWOCTRL_CH4OCV (12U) /*!< Bit position for FTM_SWOCTRL_CH4OCV. */
screamer 0:c5e2f793b59a 5533 #define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /*!< Bit mask for FTM_SWOCTRL_CH4OCV. */
screamer 0:c5e2f793b59a 5534 #define BS_FTM_SWOCTRL_CH4OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. */
screamer 0:c5e2f793b59a 5535
screamer 0:c5e2f793b59a 5536 /*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
screamer 0:c5e2f793b59a 5537 #define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
screamer 0:c5e2f793b59a 5538
screamer 0:c5e2f793b59a 5539 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. */
screamer 0:c5e2f793b59a 5540 #define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV)
screamer 0:c5e2f793b59a 5541
screamer 0:c5e2f793b59a 5542 /*! @brief Set the CH4OCV field to a new value. */
screamer 0:c5e2f793b59a 5543 #define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
screamer 0:c5e2f793b59a 5544 /*@}*/
screamer 0:c5e2f793b59a 5545
screamer 0:c5e2f793b59a 5546 /*!
screamer 0:c5e2f793b59a 5547 * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
screamer 0:c5e2f793b59a 5548 *
screamer 0:c5e2f793b59a 5549 * Values:
screamer 0:c5e2f793b59a 5550 * - 0 - The software output control forces 0 to the channel output.
screamer 0:c5e2f793b59a 5551 * - 1 - The software output control forces 1 to the channel output.
screamer 0:c5e2f793b59a 5552 */
screamer 0:c5e2f793b59a 5553 /*@{*/
screamer 0:c5e2f793b59a 5554 #define BP_FTM_SWOCTRL_CH5OCV (13U) /*!< Bit position for FTM_SWOCTRL_CH5OCV. */
screamer 0:c5e2f793b59a 5555 #define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /*!< Bit mask for FTM_SWOCTRL_CH5OCV. */
screamer 0:c5e2f793b59a 5556 #define BS_FTM_SWOCTRL_CH5OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. */
screamer 0:c5e2f793b59a 5557
screamer 0:c5e2f793b59a 5558 /*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
screamer 0:c5e2f793b59a 5559 #define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
screamer 0:c5e2f793b59a 5560
screamer 0:c5e2f793b59a 5561 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. */
screamer 0:c5e2f793b59a 5562 #define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV)
screamer 0:c5e2f793b59a 5563
screamer 0:c5e2f793b59a 5564 /*! @brief Set the CH5OCV field to a new value. */
screamer 0:c5e2f793b59a 5565 #define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
screamer 0:c5e2f793b59a 5566 /*@}*/
screamer 0:c5e2f793b59a 5567
screamer 0:c5e2f793b59a 5568 /*!
screamer 0:c5e2f793b59a 5569 * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
screamer 0:c5e2f793b59a 5570 *
screamer 0:c5e2f793b59a 5571 * Values:
screamer 0:c5e2f793b59a 5572 * - 0 - The software output control forces 0 to the channel output.
screamer 0:c5e2f793b59a 5573 * - 1 - The software output control forces 1 to the channel output.
screamer 0:c5e2f793b59a 5574 */
screamer 0:c5e2f793b59a 5575 /*@{*/
screamer 0:c5e2f793b59a 5576 #define BP_FTM_SWOCTRL_CH6OCV (14U) /*!< Bit position for FTM_SWOCTRL_CH6OCV. */
screamer 0:c5e2f793b59a 5577 #define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /*!< Bit mask for FTM_SWOCTRL_CH6OCV. */
screamer 0:c5e2f793b59a 5578 #define BS_FTM_SWOCTRL_CH6OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. */
screamer 0:c5e2f793b59a 5579
screamer 0:c5e2f793b59a 5580 /*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
screamer 0:c5e2f793b59a 5581 #define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
screamer 0:c5e2f793b59a 5582
screamer 0:c5e2f793b59a 5583 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. */
screamer 0:c5e2f793b59a 5584 #define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV)
screamer 0:c5e2f793b59a 5585
screamer 0:c5e2f793b59a 5586 /*! @brief Set the CH6OCV field to a new value. */
screamer 0:c5e2f793b59a 5587 #define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
screamer 0:c5e2f793b59a 5588 /*@}*/
screamer 0:c5e2f793b59a 5589
screamer 0:c5e2f793b59a 5590 /*!
screamer 0:c5e2f793b59a 5591 * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
screamer 0:c5e2f793b59a 5592 *
screamer 0:c5e2f793b59a 5593 * Values:
screamer 0:c5e2f793b59a 5594 * - 0 - The software output control forces 0 to the channel output.
screamer 0:c5e2f793b59a 5595 * - 1 - The software output control forces 1 to the channel output.
screamer 0:c5e2f793b59a 5596 */
screamer 0:c5e2f793b59a 5597 /*@{*/
screamer 0:c5e2f793b59a 5598 #define BP_FTM_SWOCTRL_CH7OCV (15U) /*!< Bit position for FTM_SWOCTRL_CH7OCV. */
screamer 0:c5e2f793b59a 5599 #define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /*!< Bit mask for FTM_SWOCTRL_CH7OCV. */
screamer 0:c5e2f793b59a 5600 #define BS_FTM_SWOCTRL_CH7OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. */
screamer 0:c5e2f793b59a 5601
screamer 0:c5e2f793b59a 5602 /*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
screamer 0:c5e2f793b59a 5603 #define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
screamer 0:c5e2f793b59a 5604
screamer 0:c5e2f793b59a 5605 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. */
screamer 0:c5e2f793b59a 5606 #define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV)
screamer 0:c5e2f793b59a 5607
screamer 0:c5e2f793b59a 5608 /*! @brief Set the CH7OCV field to a new value. */
screamer 0:c5e2f793b59a 5609 #define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
screamer 0:c5e2f793b59a 5610 /*@}*/
screamer 0:c5e2f793b59a 5611
screamer 0:c5e2f793b59a 5612 /*******************************************************************************
screamer 0:c5e2f793b59a 5613 * HW_FTM_PWMLOAD - FTM PWM Load
screamer 0:c5e2f793b59a 5614 ******************************************************************************/
screamer 0:c5e2f793b59a 5615
screamer 0:c5e2f793b59a 5616 /*!
screamer 0:c5e2f793b59a 5617 * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
screamer 0:c5e2f793b59a 5618 *
screamer 0:c5e2f793b59a 5619 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 5620 *
screamer 0:c5e2f793b59a 5621 * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
screamer 0:c5e2f793b59a 5622 * values of their write buffers when the FTM counter changes from the MOD
screamer 0:c5e2f793b59a 5623 * register value to its next value or when a channel (j) match occurs. A match occurs
screamer 0:c5e2f793b59a 5624 * for the channel (j) when FTM counter = C(j)V.
screamer 0:c5e2f793b59a 5625 */
screamer 0:c5e2f793b59a 5626 typedef union _hw_ftm_pwmload
screamer 0:c5e2f793b59a 5627 {
screamer 0:c5e2f793b59a 5628 uint32_t U;
screamer 0:c5e2f793b59a 5629 struct _hw_ftm_pwmload_bitfields
screamer 0:c5e2f793b59a 5630 {
screamer 0:c5e2f793b59a 5631 uint32_t CH0SEL : 1; /*!< [0] Channel 0 Select */
screamer 0:c5e2f793b59a 5632 uint32_t CH1SEL : 1; /*!< [1] Channel 1 Select */
screamer 0:c5e2f793b59a 5633 uint32_t CH2SEL : 1; /*!< [2] Channel 2 Select */
screamer 0:c5e2f793b59a 5634 uint32_t CH3SEL : 1; /*!< [3] Channel 3 Select */
screamer 0:c5e2f793b59a 5635 uint32_t CH4SEL : 1; /*!< [4] Channel 4 Select */
screamer 0:c5e2f793b59a 5636 uint32_t CH5SEL : 1; /*!< [5] Channel 5 Select */
screamer 0:c5e2f793b59a 5637 uint32_t CH6SEL : 1; /*!< [6] Channel 6 Select */
screamer 0:c5e2f793b59a 5638 uint32_t CH7SEL : 1; /*!< [7] Channel 7 Select */
screamer 0:c5e2f793b59a 5639 uint32_t RESERVED0 : 1; /*!< [8] */
screamer 0:c5e2f793b59a 5640 uint32_t LDOK : 1; /*!< [9] Load Enable */
screamer 0:c5e2f793b59a 5641 uint32_t RESERVED1 : 22; /*!< [31:10] */
screamer 0:c5e2f793b59a 5642 } B;
screamer 0:c5e2f793b59a 5643 } hw_ftm_pwmload_t;
screamer 0:c5e2f793b59a 5644
screamer 0:c5e2f793b59a 5645 /*!
screamer 0:c5e2f793b59a 5646 * @name Constants and macros for entire FTM_PWMLOAD register
screamer 0:c5e2f793b59a 5647 */
screamer 0:c5e2f793b59a 5648 /*@{*/
screamer 0:c5e2f793b59a 5649 #define HW_FTM_PWMLOAD_ADDR(x) ((x) + 0x98U)
screamer 0:c5e2f793b59a 5650
screamer 0:c5e2f793b59a 5651 #define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
screamer 0:c5e2f793b59a 5652 #define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
screamer 0:c5e2f793b59a 5653 #define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
screamer 0:c5e2f793b59a 5654 #define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v)))
screamer 0:c5e2f793b59a 5655 #define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 5656 #define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 5657 /*@}*/
screamer 0:c5e2f793b59a 5658
screamer 0:c5e2f793b59a 5659 /*
screamer 0:c5e2f793b59a 5660 * Constants & macros for individual FTM_PWMLOAD bitfields
screamer 0:c5e2f793b59a 5661 */
screamer 0:c5e2f793b59a 5662
screamer 0:c5e2f793b59a 5663 /*!
screamer 0:c5e2f793b59a 5664 * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
screamer 0:c5e2f793b59a 5665 *
screamer 0:c5e2f793b59a 5666 * Values:
screamer 0:c5e2f793b59a 5667 * - 0 - Do not include the channel in the matching process.
screamer 0:c5e2f793b59a 5668 * - 1 - Include the channel in the matching process.
screamer 0:c5e2f793b59a 5669 */
screamer 0:c5e2f793b59a 5670 /*@{*/
screamer 0:c5e2f793b59a 5671 #define BP_FTM_PWMLOAD_CH0SEL (0U) /*!< Bit position for FTM_PWMLOAD_CH0SEL. */
screamer 0:c5e2f793b59a 5672 #define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /*!< Bit mask for FTM_PWMLOAD_CH0SEL. */
screamer 0:c5e2f793b59a 5673 #define BS_FTM_PWMLOAD_CH0SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. */
screamer 0:c5e2f793b59a 5674
screamer 0:c5e2f793b59a 5675 /*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
screamer 0:c5e2f793b59a 5676 #define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
screamer 0:c5e2f793b59a 5677
screamer 0:c5e2f793b59a 5678 /*! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. */
screamer 0:c5e2f793b59a 5679 #define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL)
screamer 0:c5e2f793b59a 5680
screamer 0:c5e2f793b59a 5681 /*! @brief Set the CH0SEL field to a new value. */
screamer 0:c5e2f793b59a 5682 #define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
screamer 0:c5e2f793b59a 5683 /*@}*/
screamer 0:c5e2f793b59a 5684
screamer 0:c5e2f793b59a 5685 /*!
screamer 0:c5e2f793b59a 5686 * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
screamer 0:c5e2f793b59a 5687 *
screamer 0:c5e2f793b59a 5688 * Values:
screamer 0:c5e2f793b59a 5689 * - 0 - Do not include the channel in the matching process.
screamer 0:c5e2f793b59a 5690 * - 1 - Include the channel in the matching process.
screamer 0:c5e2f793b59a 5691 */
screamer 0:c5e2f793b59a 5692 /*@{*/
screamer 0:c5e2f793b59a 5693 #define BP_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit position for FTM_PWMLOAD_CH1SEL. */
screamer 0:c5e2f793b59a 5694 #define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /*!< Bit mask for FTM_PWMLOAD_CH1SEL. */
screamer 0:c5e2f793b59a 5695 #define BS_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. */
screamer 0:c5e2f793b59a 5696
screamer 0:c5e2f793b59a 5697 /*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
screamer 0:c5e2f793b59a 5698 #define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
screamer 0:c5e2f793b59a 5699
screamer 0:c5e2f793b59a 5700 /*! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. */
screamer 0:c5e2f793b59a 5701 #define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL)
screamer 0:c5e2f793b59a 5702
screamer 0:c5e2f793b59a 5703 /*! @brief Set the CH1SEL field to a new value. */
screamer 0:c5e2f793b59a 5704 #define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
screamer 0:c5e2f793b59a 5705 /*@}*/
screamer 0:c5e2f793b59a 5706
screamer 0:c5e2f793b59a 5707 /*!
screamer 0:c5e2f793b59a 5708 * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
screamer 0:c5e2f793b59a 5709 *
screamer 0:c5e2f793b59a 5710 * Values:
screamer 0:c5e2f793b59a 5711 * - 0 - Do not include the channel in the matching process.
screamer 0:c5e2f793b59a 5712 * - 1 - Include the channel in the matching process.
screamer 0:c5e2f793b59a 5713 */
screamer 0:c5e2f793b59a 5714 /*@{*/
screamer 0:c5e2f793b59a 5715 #define BP_FTM_PWMLOAD_CH2SEL (2U) /*!< Bit position for FTM_PWMLOAD_CH2SEL. */
screamer 0:c5e2f793b59a 5716 #define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /*!< Bit mask for FTM_PWMLOAD_CH2SEL. */
screamer 0:c5e2f793b59a 5717 #define BS_FTM_PWMLOAD_CH2SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. */
screamer 0:c5e2f793b59a 5718
screamer 0:c5e2f793b59a 5719 /*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
screamer 0:c5e2f793b59a 5720 #define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
screamer 0:c5e2f793b59a 5721
screamer 0:c5e2f793b59a 5722 /*! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. */
screamer 0:c5e2f793b59a 5723 #define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL)
screamer 0:c5e2f793b59a 5724
screamer 0:c5e2f793b59a 5725 /*! @brief Set the CH2SEL field to a new value. */
screamer 0:c5e2f793b59a 5726 #define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
screamer 0:c5e2f793b59a 5727 /*@}*/
screamer 0:c5e2f793b59a 5728
screamer 0:c5e2f793b59a 5729 /*!
screamer 0:c5e2f793b59a 5730 * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
screamer 0:c5e2f793b59a 5731 *
screamer 0:c5e2f793b59a 5732 * Values:
screamer 0:c5e2f793b59a 5733 * - 0 - Do not include the channel in the matching process.
screamer 0:c5e2f793b59a 5734 * - 1 - Include the channel in the matching process.
screamer 0:c5e2f793b59a 5735 */
screamer 0:c5e2f793b59a 5736 /*@{*/
screamer 0:c5e2f793b59a 5737 #define BP_FTM_PWMLOAD_CH3SEL (3U) /*!< Bit position for FTM_PWMLOAD_CH3SEL. */
screamer 0:c5e2f793b59a 5738 #define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /*!< Bit mask for FTM_PWMLOAD_CH3SEL. */
screamer 0:c5e2f793b59a 5739 #define BS_FTM_PWMLOAD_CH3SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. */
screamer 0:c5e2f793b59a 5740
screamer 0:c5e2f793b59a 5741 /*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
screamer 0:c5e2f793b59a 5742 #define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
screamer 0:c5e2f793b59a 5743
screamer 0:c5e2f793b59a 5744 /*! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. */
screamer 0:c5e2f793b59a 5745 #define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL)
screamer 0:c5e2f793b59a 5746
screamer 0:c5e2f793b59a 5747 /*! @brief Set the CH3SEL field to a new value. */
screamer 0:c5e2f793b59a 5748 #define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
screamer 0:c5e2f793b59a 5749 /*@}*/
screamer 0:c5e2f793b59a 5750
screamer 0:c5e2f793b59a 5751 /*!
screamer 0:c5e2f793b59a 5752 * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
screamer 0:c5e2f793b59a 5753 *
screamer 0:c5e2f793b59a 5754 * Values:
screamer 0:c5e2f793b59a 5755 * - 0 - Do not include the channel in the matching process.
screamer 0:c5e2f793b59a 5756 * - 1 - Include the channel in the matching process.
screamer 0:c5e2f793b59a 5757 */
screamer 0:c5e2f793b59a 5758 /*@{*/
screamer 0:c5e2f793b59a 5759 #define BP_FTM_PWMLOAD_CH4SEL (4U) /*!< Bit position for FTM_PWMLOAD_CH4SEL. */
screamer 0:c5e2f793b59a 5760 #define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /*!< Bit mask for FTM_PWMLOAD_CH4SEL. */
screamer 0:c5e2f793b59a 5761 #define BS_FTM_PWMLOAD_CH4SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. */
screamer 0:c5e2f793b59a 5762
screamer 0:c5e2f793b59a 5763 /*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
screamer 0:c5e2f793b59a 5764 #define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
screamer 0:c5e2f793b59a 5765
screamer 0:c5e2f793b59a 5766 /*! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. */
screamer 0:c5e2f793b59a 5767 #define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL)
screamer 0:c5e2f793b59a 5768
screamer 0:c5e2f793b59a 5769 /*! @brief Set the CH4SEL field to a new value. */
screamer 0:c5e2f793b59a 5770 #define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
screamer 0:c5e2f793b59a 5771 /*@}*/
screamer 0:c5e2f793b59a 5772
screamer 0:c5e2f793b59a 5773 /*!
screamer 0:c5e2f793b59a 5774 * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
screamer 0:c5e2f793b59a 5775 *
screamer 0:c5e2f793b59a 5776 * Values:
screamer 0:c5e2f793b59a 5777 * - 0 - Do not include the channel in the matching process.
screamer 0:c5e2f793b59a 5778 * - 1 - Include the channel in the matching process.
screamer 0:c5e2f793b59a 5779 */
screamer 0:c5e2f793b59a 5780 /*@{*/
screamer 0:c5e2f793b59a 5781 #define BP_FTM_PWMLOAD_CH5SEL (5U) /*!< Bit position for FTM_PWMLOAD_CH5SEL. */
screamer 0:c5e2f793b59a 5782 #define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /*!< Bit mask for FTM_PWMLOAD_CH5SEL. */
screamer 0:c5e2f793b59a 5783 #define BS_FTM_PWMLOAD_CH5SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. */
screamer 0:c5e2f793b59a 5784
screamer 0:c5e2f793b59a 5785 /*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
screamer 0:c5e2f793b59a 5786 #define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
screamer 0:c5e2f793b59a 5787
screamer 0:c5e2f793b59a 5788 /*! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. */
screamer 0:c5e2f793b59a 5789 #define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL)
screamer 0:c5e2f793b59a 5790
screamer 0:c5e2f793b59a 5791 /*! @brief Set the CH5SEL field to a new value. */
screamer 0:c5e2f793b59a 5792 #define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
screamer 0:c5e2f793b59a 5793 /*@}*/
screamer 0:c5e2f793b59a 5794
screamer 0:c5e2f793b59a 5795 /*!
screamer 0:c5e2f793b59a 5796 * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
screamer 0:c5e2f793b59a 5797 *
screamer 0:c5e2f793b59a 5798 * Values:
screamer 0:c5e2f793b59a 5799 * - 0 - Do not include the channel in the matching process.
screamer 0:c5e2f793b59a 5800 * - 1 - Include the channel in the matching process.
screamer 0:c5e2f793b59a 5801 */
screamer 0:c5e2f793b59a 5802 /*@{*/
screamer 0:c5e2f793b59a 5803 #define BP_FTM_PWMLOAD_CH6SEL (6U) /*!< Bit position for FTM_PWMLOAD_CH6SEL. */
screamer 0:c5e2f793b59a 5804 #define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /*!< Bit mask for FTM_PWMLOAD_CH6SEL. */
screamer 0:c5e2f793b59a 5805 #define BS_FTM_PWMLOAD_CH6SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. */
screamer 0:c5e2f793b59a 5806
screamer 0:c5e2f793b59a 5807 /*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
screamer 0:c5e2f793b59a 5808 #define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
screamer 0:c5e2f793b59a 5809
screamer 0:c5e2f793b59a 5810 /*! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. */
screamer 0:c5e2f793b59a 5811 #define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL)
screamer 0:c5e2f793b59a 5812
screamer 0:c5e2f793b59a 5813 /*! @brief Set the CH6SEL field to a new value. */
screamer 0:c5e2f793b59a 5814 #define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
screamer 0:c5e2f793b59a 5815 /*@}*/
screamer 0:c5e2f793b59a 5816
screamer 0:c5e2f793b59a 5817 /*!
screamer 0:c5e2f793b59a 5818 * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
screamer 0:c5e2f793b59a 5819 *
screamer 0:c5e2f793b59a 5820 * Values:
screamer 0:c5e2f793b59a 5821 * - 0 - Do not include the channel in the matching process.
screamer 0:c5e2f793b59a 5822 * - 1 - Include the channel in the matching process.
screamer 0:c5e2f793b59a 5823 */
screamer 0:c5e2f793b59a 5824 /*@{*/
screamer 0:c5e2f793b59a 5825 #define BP_FTM_PWMLOAD_CH7SEL (7U) /*!< Bit position for FTM_PWMLOAD_CH7SEL. */
screamer 0:c5e2f793b59a 5826 #define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /*!< Bit mask for FTM_PWMLOAD_CH7SEL. */
screamer 0:c5e2f793b59a 5827 #define BS_FTM_PWMLOAD_CH7SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. */
screamer 0:c5e2f793b59a 5828
screamer 0:c5e2f793b59a 5829 /*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
screamer 0:c5e2f793b59a 5830 #define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
screamer 0:c5e2f793b59a 5831
screamer 0:c5e2f793b59a 5832 /*! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. */
screamer 0:c5e2f793b59a 5833 #define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL)
screamer 0:c5e2f793b59a 5834
screamer 0:c5e2f793b59a 5835 /*! @brief Set the CH7SEL field to a new value. */
screamer 0:c5e2f793b59a 5836 #define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
screamer 0:c5e2f793b59a 5837 /*@}*/
screamer 0:c5e2f793b59a 5838
screamer 0:c5e2f793b59a 5839 /*!
screamer 0:c5e2f793b59a 5840 * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
screamer 0:c5e2f793b59a 5841 *
screamer 0:c5e2f793b59a 5842 * Enables the loading of the MOD, CNTIN, and CV registers with the values of
screamer 0:c5e2f793b59a 5843 * their write buffers.
screamer 0:c5e2f793b59a 5844 *
screamer 0:c5e2f793b59a 5845 * Values:
screamer 0:c5e2f793b59a 5846 * - 0 - Loading updated values is disabled.
screamer 0:c5e2f793b59a 5847 * - 1 - Loading updated values is enabled.
screamer 0:c5e2f793b59a 5848 */
screamer 0:c5e2f793b59a 5849 /*@{*/
screamer 0:c5e2f793b59a 5850 #define BP_FTM_PWMLOAD_LDOK (9U) /*!< Bit position for FTM_PWMLOAD_LDOK. */
screamer 0:c5e2f793b59a 5851 #define BM_FTM_PWMLOAD_LDOK (0x00000200U) /*!< Bit mask for FTM_PWMLOAD_LDOK. */
screamer 0:c5e2f793b59a 5852 #define BS_FTM_PWMLOAD_LDOK (1U) /*!< Bit field size in bits for FTM_PWMLOAD_LDOK. */
screamer 0:c5e2f793b59a 5853
screamer 0:c5e2f793b59a 5854 /*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
screamer 0:c5e2f793b59a 5855 #define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
screamer 0:c5e2f793b59a 5856
screamer 0:c5e2f793b59a 5857 /*! @brief Format value for bitfield FTM_PWMLOAD_LDOK. */
screamer 0:c5e2f793b59a 5858 #define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK)
screamer 0:c5e2f793b59a 5859
screamer 0:c5e2f793b59a 5860 /*! @brief Set the LDOK field to a new value. */
screamer 0:c5e2f793b59a 5861 #define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
screamer 0:c5e2f793b59a 5862 /*@}*/
screamer 0:c5e2f793b59a 5863
screamer 0:c5e2f793b59a 5864 /*******************************************************************************
screamer 0:c5e2f793b59a 5865 * hw_ftm_t - module struct
screamer 0:c5e2f793b59a 5866 ******************************************************************************/
screamer 0:c5e2f793b59a 5867 /*!
screamer 0:c5e2f793b59a 5868 * @brief All FTM module registers.
screamer 0:c5e2f793b59a 5869 */
screamer 0:c5e2f793b59a 5870 #pragma pack(1)
screamer 0:c5e2f793b59a 5871 typedef struct _hw_ftm
screamer 0:c5e2f793b59a 5872 {
screamer 0:c5e2f793b59a 5873 __IO hw_ftm_sc_t SC; /*!< [0x0] Status And Control */
screamer 0:c5e2f793b59a 5874 __IO hw_ftm_cnt_t CNT; /*!< [0x4] Counter */
screamer 0:c5e2f793b59a 5875 __IO hw_ftm_mod_t MOD; /*!< [0x8] Modulo */
screamer 0:c5e2f793b59a 5876 struct {
screamer 0:c5e2f793b59a 5877 __IO hw_ftm_cnsc_t CnSC; /*!< [0xC] Channel (n) Status And Control */
screamer 0:c5e2f793b59a 5878 __IO hw_ftm_cnv_t CnV; /*!< [0x10] Channel (n) Value */
screamer 0:c5e2f793b59a 5879 } CONTROLS[8];
screamer 0:c5e2f793b59a 5880 __IO hw_ftm_cntin_t CNTIN; /*!< [0x4C] Counter Initial Value */
screamer 0:c5e2f793b59a 5881 __IO hw_ftm_status_t STATUS; /*!< [0x50] Capture And Compare Status */
screamer 0:c5e2f793b59a 5882 __IO hw_ftm_mode_t MODE; /*!< [0x54] Features Mode Selection */
screamer 0:c5e2f793b59a 5883 __IO hw_ftm_sync_t SYNC; /*!< [0x58] Synchronization */
screamer 0:c5e2f793b59a 5884 __IO hw_ftm_outinit_t OUTINIT; /*!< [0x5C] Initial State For Channels Output */
screamer 0:c5e2f793b59a 5885 __IO hw_ftm_outmask_t OUTMASK; /*!< [0x60] Output Mask */
screamer 0:c5e2f793b59a 5886 __IO hw_ftm_combine_t COMBINE; /*!< [0x64] Function For Linked Channels */
screamer 0:c5e2f793b59a 5887 __IO hw_ftm_deadtime_t DEADTIME; /*!< [0x68] Deadtime Insertion Control */
screamer 0:c5e2f793b59a 5888 __IO hw_ftm_exttrig_t EXTTRIG; /*!< [0x6C] FTM External Trigger */
screamer 0:c5e2f793b59a 5889 __IO hw_ftm_pol_t POL; /*!< [0x70] Channels Polarity */
screamer 0:c5e2f793b59a 5890 __IO hw_ftm_fms_t FMS; /*!< [0x74] Fault Mode Status */
screamer 0:c5e2f793b59a 5891 __IO hw_ftm_filter_t FILTER; /*!< [0x78] Input Capture Filter Control */
screamer 0:c5e2f793b59a 5892 __IO hw_ftm_fltctrl_t FLTCTRL; /*!< [0x7C] Fault Control */
screamer 0:c5e2f793b59a 5893 __IO hw_ftm_qdctrl_t QDCTRL; /*!< [0x80] Quadrature Decoder Control And Status */
screamer 0:c5e2f793b59a 5894 __IO hw_ftm_conf_t CONF; /*!< [0x84] Configuration */
screamer 0:c5e2f793b59a 5895 __IO hw_ftm_fltpol_t FLTPOL; /*!< [0x88] FTM Fault Input Polarity */
screamer 0:c5e2f793b59a 5896 __IO hw_ftm_synconf_t SYNCONF; /*!< [0x8C] Synchronization Configuration */
screamer 0:c5e2f793b59a 5897 __IO hw_ftm_invctrl_t INVCTRL; /*!< [0x90] FTM Inverting Control */
screamer 0:c5e2f793b59a 5898 __IO hw_ftm_swoctrl_t SWOCTRL; /*!< [0x94] FTM Software Output Control */
screamer 0:c5e2f793b59a 5899 __IO hw_ftm_pwmload_t PWMLOAD; /*!< [0x98] FTM PWM Load */
screamer 0:c5e2f793b59a 5900 } hw_ftm_t;
screamer 0:c5e2f793b59a 5901 #pragma pack()
screamer 0:c5e2f793b59a 5902
screamer 0:c5e2f793b59a 5903 /*! @brief Macro to access all FTM registers. */
screamer 0:c5e2f793b59a 5904 /*! @param x FTM module instance base address. */
screamer 0:c5e2f793b59a 5905 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
screamer 0:c5e2f793b59a 5906 * use the '&' operator, like <code>&HW_FTM(FTM0_BASE)</code>. */
screamer 0:c5e2f793b59a 5907 #define HW_FTM(x) (*(hw_ftm_t *)(x))
screamer 0:c5e2f793b59a 5908
screamer 0:c5e2f793b59a 5909 #endif /* __HW_FTM_REGISTERS_H__ */
screamer 0:c5e2f793b59a 5910 /* EOF */