Morpheus / target-mcu-k64f

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hal/device/device/MK64F12/MK64F12_cmt.h@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 4 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 5 ** GNU C Compiler
screamer 0:c5e2f793b59a 6 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 9 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 10 ** Build: b140604
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Abstract:
screamer 0:c5e2f793b59a 13 ** Extension to the CMSIS register access layer header.
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 16 ** All rights reserved.
screamer 0:c5e2f793b59a 17 **
screamer 0:c5e2f793b59a 18 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 19 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 20 **
screamer 0:c5e2f793b59a 21 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 22 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 25 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 26 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 27 **
screamer 0:c5e2f793b59a 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 29 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 30 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 31 **
screamer 0:c5e2f793b59a 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 42 **
screamer 0:c5e2f793b59a 43 ** http: www.freescale.com
screamer 0:c5e2f793b59a 44 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 45 **
screamer 0:c5e2f793b59a 46 ** Revisions:
screamer 0:c5e2f793b59a 47 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 48 ** Initial version.
screamer 0:c5e2f793b59a 49 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 50 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 53 ** System initialization updated.
screamer 0:c5e2f793b59a 54 ** MCG - registers updated.
screamer 0:c5e2f793b59a 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 56 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 58 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 59 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 60 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 61 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 62 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 63 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 64 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 67 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 71 **
screamer 0:c5e2f793b59a 72 ** ###################################################################
screamer 0:c5e2f793b59a 73 */
screamer 0:c5e2f793b59a 74
screamer 0:c5e2f793b59a 75 /*
screamer 0:c5e2f793b59a 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
screamer 0:c5e2f793b59a 77 *
screamer 0:c5e2f793b59a 78 * This file was generated automatically and any changes may be lost.
screamer 0:c5e2f793b59a 79 */
screamer 0:c5e2f793b59a 80 #ifndef __HW_CMT_REGISTERS_H__
screamer 0:c5e2f793b59a 81 #define __HW_CMT_REGISTERS_H__
screamer 0:c5e2f793b59a 82
screamer 0:c5e2f793b59a 83 #include "MK64F12.h"
screamer 0:c5e2f793b59a 84 #include "fsl_bitaccess.h"
screamer 0:c5e2f793b59a 85
screamer 0:c5e2f793b59a 86 /*
screamer 0:c5e2f793b59a 87 * MK64F12 CMT
screamer 0:c5e2f793b59a 88 *
screamer 0:c5e2f793b59a 89 * Carrier Modulator Transmitter
screamer 0:c5e2f793b59a 90 *
screamer 0:c5e2f793b59a 91 * Registers defined in this header file:
screamer 0:c5e2f793b59a 92 * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
screamer 0:c5e2f793b59a 93 * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
screamer 0:c5e2f793b59a 94 * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
screamer 0:c5e2f793b59a 95 * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
screamer 0:c5e2f793b59a 96 * - HW_CMT_OC - CMT Output Control Register
screamer 0:c5e2f793b59a 97 * - HW_CMT_MSC - CMT Modulator Status and Control Register
screamer 0:c5e2f793b59a 98 * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
screamer 0:c5e2f793b59a 99 * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
screamer 0:c5e2f793b59a 100 * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
screamer 0:c5e2f793b59a 101 * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
screamer 0:c5e2f793b59a 102 * - HW_CMT_PPS - CMT Primary Prescaler Register
screamer 0:c5e2f793b59a 103 * - HW_CMT_DMA - CMT Direct Memory Access Register
screamer 0:c5e2f793b59a 104 *
screamer 0:c5e2f793b59a 105 * - hw_cmt_t - Struct containing all module registers.
screamer 0:c5e2f793b59a 106 */
screamer 0:c5e2f793b59a 107
screamer 0:c5e2f793b59a 108 #define HW_CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
screamer 0:c5e2f793b59a 109
screamer 0:c5e2f793b59a 110 /*******************************************************************************
screamer 0:c5e2f793b59a 111 * HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
screamer 0:c5e2f793b59a 112 ******************************************************************************/
screamer 0:c5e2f793b59a 113
screamer 0:c5e2f793b59a 114 /*!
screamer 0:c5e2f793b59a 115 * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
screamer 0:c5e2f793b59a 116 *
screamer 0:c5e2f793b59a 117 * Reset value: 0x00U
screamer 0:c5e2f793b59a 118 *
screamer 0:c5e2f793b59a 119 * This data register contains the primary high value for generating the carrier
screamer 0:c5e2f793b59a 120 * output.
screamer 0:c5e2f793b59a 121 */
screamer 0:c5e2f793b59a 122 typedef union _hw_cmt_cgh1
screamer 0:c5e2f793b59a 123 {
screamer 0:c5e2f793b59a 124 uint8_t U;
screamer 0:c5e2f793b59a 125 struct _hw_cmt_cgh1_bitfields
screamer 0:c5e2f793b59a 126 {
screamer 0:c5e2f793b59a 127 uint8_t PH : 8; /*!< [7:0] Primary Carrier High Time Data Value */
screamer 0:c5e2f793b59a 128 } B;
screamer 0:c5e2f793b59a 129 } hw_cmt_cgh1_t;
screamer 0:c5e2f793b59a 130
screamer 0:c5e2f793b59a 131 /*!
screamer 0:c5e2f793b59a 132 * @name Constants and macros for entire CMT_CGH1 register
screamer 0:c5e2f793b59a 133 */
screamer 0:c5e2f793b59a 134 /*@{*/
screamer 0:c5e2f793b59a 135 #define HW_CMT_CGH1_ADDR(x) ((x) + 0x0U)
screamer 0:c5e2f793b59a 136
screamer 0:c5e2f793b59a 137 #define HW_CMT_CGH1(x) (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR(x))
screamer 0:c5e2f793b59a 138 #define HW_CMT_CGH1_RD(x) (HW_CMT_CGH1(x).U)
screamer 0:c5e2f793b59a 139 #define HW_CMT_CGH1_WR(x, v) (HW_CMT_CGH1(x).U = (v))
screamer 0:c5e2f793b59a 140 #define HW_CMT_CGH1_SET(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) | (v)))
screamer 0:c5e2f793b59a 141 #define HW_CMT_CGH1_CLR(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 142 #define HW_CMT_CGH1_TOG(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 143 /*@}*/
screamer 0:c5e2f793b59a 144
screamer 0:c5e2f793b59a 145 /*
screamer 0:c5e2f793b59a 146 * Constants & macros for individual CMT_CGH1 bitfields
screamer 0:c5e2f793b59a 147 */
screamer 0:c5e2f793b59a 148
screamer 0:c5e2f793b59a 149 /*!
screamer 0:c5e2f793b59a 150 * @name Register CMT_CGH1, field PH[7:0] (RW)
screamer 0:c5e2f793b59a 151 *
screamer 0:c5e2f793b59a 152 * Contains the number of input clocks required to generate the carrier high
screamer 0:c5e2f793b59a 153 * time period. When operating in Time mode, this register is always selected. When
screamer 0:c5e2f793b59a 154 * operating in FSK mode, this register and the secondary register pair are
screamer 0:c5e2f793b59a 155 * alternately selected under the control of the modulator. The primary carrier high
screamer 0:c5e2f793b59a 156 * time value is undefined out of reset. This register must be written to nonzero
screamer 0:c5e2f793b59a 157 * values before the carrier generator is enabled to avoid spurious results.
screamer 0:c5e2f793b59a 158 */
screamer 0:c5e2f793b59a 159 /*@{*/
screamer 0:c5e2f793b59a 160 #define BP_CMT_CGH1_PH (0U) /*!< Bit position for CMT_CGH1_PH. */
screamer 0:c5e2f793b59a 161 #define BM_CMT_CGH1_PH (0xFFU) /*!< Bit mask for CMT_CGH1_PH. */
screamer 0:c5e2f793b59a 162 #define BS_CMT_CGH1_PH (8U) /*!< Bit field size in bits for CMT_CGH1_PH. */
screamer 0:c5e2f793b59a 163
screamer 0:c5e2f793b59a 164 /*! @brief Read current value of the CMT_CGH1_PH field. */
screamer 0:c5e2f793b59a 165 #define BR_CMT_CGH1_PH(x) (HW_CMT_CGH1(x).U)
screamer 0:c5e2f793b59a 166
screamer 0:c5e2f793b59a 167 /*! @brief Format value for bitfield CMT_CGH1_PH. */
screamer 0:c5e2f793b59a 168 #define BF_CMT_CGH1_PH(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGH1_PH) & BM_CMT_CGH1_PH)
screamer 0:c5e2f793b59a 169
screamer 0:c5e2f793b59a 170 /*! @brief Set the PH field to a new value. */
screamer 0:c5e2f793b59a 171 #define BW_CMT_CGH1_PH(x, v) (HW_CMT_CGH1_WR(x, v))
screamer 0:c5e2f793b59a 172 /*@}*/
screamer 0:c5e2f793b59a 173
screamer 0:c5e2f793b59a 174 /*******************************************************************************
screamer 0:c5e2f793b59a 175 * HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
screamer 0:c5e2f793b59a 176 ******************************************************************************/
screamer 0:c5e2f793b59a 177
screamer 0:c5e2f793b59a 178 /*!
screamer 0:c5e2f793b59a 179 * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
screamer 0:c5e2f793b59a 180 *
screamer 0:c5e2f793b59a 181 * Reset value: 0x00U
screamer 0:c5e2f793b59a 182 *
screamer 0:c5e2f793b59a 183 * This data register contains the primary low value for generating the carrier
screamer 0:c5e2f793b59a 184 * output.
screamer 0:c5e2f793b59a 185 */
screamer 0:c5e2f793b59a 186 typedef union _hw_cmt_cgl1
screamer 0:c5e2f793b59a 187 {
screamer 0:c5e2f793b59a 188 uint8_t U;
screamer 0:c5e2f793b59a 189 struct _hw_cmt_cgl1_bitfields
screamer 0:c5e2f793b59a 190 {
screamer 0:c5e2f793b59a 191 uint8_t PL : 8; /*!< [7:0] Primary Carrier Low Time Data Value */
screamer 0:c5e2f793b59a 192 } B;
screamer 0:c5e2f793b59a 193 } hw_cmt_cgl1_t;
screamer 0:c5e2f793b59a 194
screamer 0:c5e2f793b59a 195 /*!
screamer 0:c5e2f793b59a 196 * @name Constants and macros for entire CMT_CGL1 register
screamer 0:c5e2f793b59a 197 */
screamer 0:c5e2f793b59a 198 /*@{*/
screamer 0:c5e2f793b59a 199 #define HW_CMT_CGL1_ADDR(x) ((x) + 0x1U)
screamer 0:c5e2f793b59a 200
screamer 0:c5e2f793b59a 201 #define HW_CMT_CGL1(x) (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR(x))
screamer 0:c5e2f793b59a 202 #define HW_CMT_CGL1_RD(x) (HW_CMT_CGL1(x).U)
screamer 0:c5e2f793b59a 203 #define HW_CMT_CGL1_WR(x, v) (HW_CMT_CGL1(x).U = (v))
screamer 0:c5e2f793b59a 204 #define HW_CMT_CGL1_SET(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) | (v)))
screamer 0:c5e2f793b59a 205 #define HW_CMT_CGL1_CLR(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 206 #define HW_CMT_CGL1_TOG(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 207 /*@}*/
screamer 0:c5e2f793b59a 208
screamer 0:c5e2f793b59a 209 /*
screamer 0:c5e2f793b59a 210 * Constants & macros for individual CMT_CGL1 bitfields
screamer 0:c5e2f793b59a 211 */
screamer 0:c5e2f793b59a 212
screamer 0:c5e2f793b59a 213 /*!
screamer 0:c5e2f793b59a 214 * @name Register CMT_CGL1, field PL[7:0] (RW)
screamer 0:c5e2f793b59a 215 *
screamer 0:c5e2f793b59a 216 * Contains the number of input clocks required to generate the carrier low time
screamer 0:c5e2f793b59a 217 * period. When operating in Time mode, this register is always selected. When
screamer 0:c5e2f793b59a 218 * operating in FSK mode, this register and the secondary register pair are
screamer 0:c5e2f793b59a 219 * alternately selected under the control of the modulator. The primary carrier low
screamer 0:c5e2f793b59a 220 * time value is undefined out of reset. This register must be written to nonzero
screamer 0:c5e2f793b59a 221 * values before the carrier generator is enabled to avoid spurious results.
screamer 0:c5e2f793b59a 222 */
screamer 0:c5e2f793b59a 223 /*@{*/
screamer 0:c5e2f793b59a 224 #define BP_CMT_CGL1_PL (0U) /*!< Bit position for CMT_CGL1_PL. */
screamer 0:c5e2f793b59a 225 #define BM_CMT_CGL1_PL (0xFFU) /*!< Bit mask for CMT_CGL1_PL. */
screamer 0:c5e2f793b59a 226 #define BS_CMT_CGL1_PL (8U) /*!< Bit field size in bits for CMT_CGL1_PL. */
screamer 0:c5e2f793b59a 227
screamer 0:c5e2f793b59a 228 /*! @brief Read current value of the CMT_CGL1_PL field. */
screamer 0:c5e2f793b59a 229 #define BR_CMT_CGL1_PL(x) (HW_CMT_CGL1(x).U)
screamer 0:c5e2f793b59a 230
screamer 0:c5e2f793b59a 231 /*! @brief Format value for bitfield CMT_CGL1_PL. */
screamer 0:c5e2f793b59a 232 #define BF_CMT_CGL1_PL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGL1_PL) & BM_CMT_CGL1_PL)
screamer 0:c5e2f793b59a 233
screamer 0:c5e2f793b59a 234 /*! @brief Set the PL field to a new value. */
screamer 0:c5e2f793b59a 235 #define BW_CMT_CGL1_PL(x, v) (HW_CMT_CGL1_WR(x, v))
screamer 0:c5e2f793b59a 236 /*@}*/
screamer 0:c5e2f793b59a 237
screamer 0:c5e2f793b59a 238 /*******************************************************************************
screamer 0:c5e2f793b59a 239 * HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
screamer 0:c5e2f793b59a 240 ******************************************************************************/
screamer 0:c5e2f793b59a 241
screamer 0:c5e2f793b59a 242 /*!
screamer 0:c5e2f793b59a 243 * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
screamer 0:c5e2f793b59a 244 *
screamer 0:c5e2f793b59a 245 * Reset value: 0x00U
screamer 0:c5e2f793b59a 246 *
screamer 0:c5e2f793b59a 247 * This data register contains the secondary high value for generating the
screamer 0:c5e2f793b59a 248 * carrier output.
screamer 0:c5e2f793b59a 249 */
screamer 0:c5e2f793b59a 250 typedef union _hw_cmt_cgh2
screamer 0:c5e2f793b59a 251 {
screamer 0:c5e2f793b59a 252 uint8_t U;
screamer 0:c5e2f793b59a 253 struct _hw_cmt_cgh2_bitfields
screamer 0:c5e2f793b59a 254 {
screamer 0:c5e2f793b59a 255 uint8_t SH : 8; /*!< [7:0] Secondary Carrier High Time Data Value */
screamer 0:c5e2f793b59a 256 } B;
screamer 0:c5e2f793b59a 257 } hw_cmt_cgh2_t;
screamer 0:c5e2f793b59a 258
screamer 0:c5e2f793b59a 259 /*!
screamer 0:c5e2f793b59a 260 * @name Constants and macros for entire CMT_CGH2 register
screamer 0:c5e2f793b59a 261 */
screamer 0:c5e2f793b59a 262 /*@{*/
screamer 0:c5e2f793b59a 263 #define HW_CMT_CGH2_ADDR(x) ((x) + 0x2U)
screamer 0:c5e2f793b59a 264
screamer 0:c5e2f793b59a 265 #define HW_CMT_CGH2(x) (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR(x))
screamer 0:c5e2f793b59a 266 #define HW_CMT_CGH2_RD(x) (HW_CMT_CGH2(x).U)
screamer 0:c5e2f793b59a 267 #define HW_CMT_CGH2_WR(x, v) (HW_CMT_CGH2(x).U = (v))
screamer 0:c5e2f793b59a 268 #define HW_CMT_CGH2_SET(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) | (v)))
screamer 0:c5e2f793b59a 269 #define HW_CMT_CGH2_CLR(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 270 #define HW_CMT_CGH2_TOG(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 271 /*@}*/
screamer 0:c5e2f793b59a 272
screamer 0:c5e2f793b59a 273 /*
screamer 0:c5e2f793b59a 274 * Constants & macros for individual CMT_CGH2 bitfields
screamer 0:c5e2f793b59a 275 */
screamer 0:c5e2f793b59a 276
screamer 0:c5e2f793b59a 277 /*!
screamer 0:c5e2f793b59a 278 * @name Register CMT_CGH2, field SH[7:0] (RW)
screamer 0:c5e2f793b59a 279 *
screamer 0:c5e2f793b59a 280 * Contains the number of input clocks required to generate the carrier high
screamer 0:c5e2f793b59a 281 * time period. When operating in Time mode, this register is never selected. When
screamer 0:c5e2f793b59a 282 * operating in FSK mode, this register and the primary register pair are
screamer 0:c5e2f793b59a 283 * alternately selected under control of the modulator. The secondary carrier high time
screamer 0:c5e2f793b59a 284 * value is undefined out of reset. This register must be written to nonzero
screamer 0:c5e2f793b59a 285 * values before the carrier generator is enabled when operating in FSK mode.
screamer 0:c5e2f793b59a 286 */
screamer 0:c5e2f793b59a 287 /*@{*/
screamer 0:c5e2f793b59a 288 #define BP_CMT_CGH2_SH (0U) /*!< Bit position for CMT_CGH2_SH. */
screamer 0:c5e2f793b59a 289 #define BM_CMT_CGH2_SH (0xFFU) /*!< Bit mask for CMT_CGH2_SH. */
screamer 0:c5e2f793b59a 290 #define BS_CMT_CGH2_SH (8U) /*!< Bit field size in bits for CMT_CGH2_SH. */
screamer 0:c5e2f793b59a 291
screamer 0:c5e2f793b59a 292 /*! @brief Read current value of the CMT_CGH2_SH field. */
screamer 0:c5e2f793b59a 293 #define BR_CMT_CGH2_SH(x) (HW_CMT_CGH2(x).U)
screamer 0:c5e2f793b59a 294
screamer 0:c5e2f793b59a 295 /*! @brief Format value for bitfield CMT_CGH2_SH. */
screamer 0:c5e2f793b59a 296 #define BF_CMT_CGH2_SH(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGH2_SH) & BM_CMT_CGH2_SH)
screamer 0:c5e2f793b59a 297
screamer 0:c5e2f793b59a 298 /*! @brief Set the SH field to a new value. */
screamer 0:c5e2f793b59a 299 #define BW_CMT_CGH2_SH(x, v) (HW_CMT_CGH2_WR(x, v))
screamer 0:c5e2f793b59a 300 /*@}*/
screamer 0:c5e2f793b59a 301
screamer 0:c5e2f793b59a 302 /*******************************************************************************
screamer 0:c5e2f793b59a 303 * HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
screamer 0:c5e2f793b59a 304 ******************************************************************************/
screamer 0:c5e2f793b59a 305
screamer 0:c5e2f793b59a 306 /*!
screamer 0:c5e2f793b59a 307 * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
screamer 0:c5e2f793b59a 308 *
screamer 0:c5e2f793b59a 309 * Reset value: 0x00U
screamer 0:c5e2f793b59a 310 *
screamer 0:c5e2f793b59a 311 * This data register contains the secondary low value for generating the
screamer 0:c5e2f793b59a 312 * carrier output.
screamer 0:c5e2f793b59a 313 */
screamer 0:c5e2f793b59a 314 typedef union _hw_cmt_cgl2
screamer 0:c5e2f793b59a 315 {
screamer 0:c5e2f793b59a 316 uint8_t U;
screamer 0:c5e2f793b59a 317 struct _hw_cmt_cgl2_bitfields
screamer 0:c5e2f793b59a 318 {
screamer 0:c5e2f793b59a 319 uint8_t SL : 8; /*!< [7:0] Secondary Carrier Low Time Data Value */
screamer 0:c5e2f793b59a 320 } B;
screamer 0:c5e2f793b59a 321 } hw_cmt_cgl2_t;
screamer 0:c5e2f793b59a 322
screamer 0:c5e2f793b59a 323 /*!
screamer 0:c5e2f793b59a 324 * @name Constants and macros for entire CMT_CGL2 register
screamer 0:c5e2f793b59a 325 */
screamer 0:c5e2f793b59a 326 /*@{*/
screamer 0:c5e2f793b59a 327 #define HW_CMT_CGL2_ADDR(x) ((x) + 0x3U)
screamer 0:c5e2f793b59a 328
screamer 0:c5e2f793b59a 329 #define HW_CMT_CGL2(x) (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR(x))
screamer 0:c5e2f793b59a 330 #define HW_CMT_CGL2_RD(x) (HW_CMT_CGL2(x).U)
screamer 0:c5e2f793b59a 331 #define HW_CMT_CGL2_WR(x, v) (HW_CMT_CGL2(x).U = (v))
screamer 0:c5e2f793b59a 332 #define HW_CMT_CGL2_SET(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) | (v)))
screamer 0:c5e2f793b59a 333 #define HW_CMT_CGL2_CLR(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 334 #define HW_CMT_CGL2_TOG(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 335 /*@}*/
screamer 0:c5e2f793b59a 336
screamer 0:c5e2f793b59a 337 /*
screamer 0:c5e2f793b59a 338 * Constants & macros for individual CMT_CGL2 bitfields
screamer 0:c5e2f793b59a 339 */
screamer 0:c5e2f793b59a 340
screamer 0:c5e2f793b59a 341 /*!
screamer 0:c5e2f793b59a 342 * @name Register CMT_CGL2, field SL[7:0] (RW)
screamer 0:c5e2f793b59a 343 *
screamer 0:c5e2f793b59a 344 * Contains the number of input clocks required to generate the carrier low time
screamer 0:c5e2f793b59a 345 * period. When operating in Time mode, this register is never selected. When
screamer 0:c5e2f793b59a 346 * operating in FSK mode, this register and the primary register pair are
screamer 0:c5e2f793b59a 347 * alternately selected under the control of the modulator. The secondary carrier low time
screamer 0:c5e2f793b59a 348 * value is undefined out of reset. This register must be written to nonzero
screamer 0:c5e2f793b59a 349 * values before the carrier generator is enabled when operating in FSK mode.
screamer 0:c5e2f793b59a 350 */
screamer 0:c5e2f793b59a 351 /*@{*/
screamer 0:c5e2f793b59a 352 #define BP_CMT_CGL2_SL (0U) /*!< Bit position for CMT_CGL2_SL. */
screamer 0:c5e2f793b59a 353 #define BM_CMT_CGL2_SL (0xFFU) /*!< Bit mask for CMT_CGL2_SL. */
screamer 0:c5e2f793b59a 354 #define BS_CMT_CGL2_SL (8U) /*!< Bit field size in bits for CMT_CGL2_SL. */
screamer 0:c5e2f793b59a 355
screamer 0:c5e2f793b59a 356 /*! @brief Read current value of the CMT_CGL2_SL field. */
screamer 0:c5e2f793b59a 357 #define BR_CMT_CGL2_SL(x) (HW_CMT_CGL2(x).U)
screamer 0:c5e2f793b59a 358
screamer 0:c5e2f793b59a 359 /*! @brief Format value for bitfield CMT_CGL2_SL. */
screamer 0:c5e2f793b59a 360 #define BF_CMT_CGL2_SL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGL2_SL) & BM_CMT_CGL2_SL)
screamer 0:c5e2f793b59a 361
screamer 0:c5e2f793b59a 362 /*! @brief Set the SL field to a new value. */
screamer 0:c5e2f793b59a 363 #define BW_CMT_CGL2_SL(x, v) (HW_CMT_CGL2_WR(x, v))
screamer 0:c5e2f793b59a 364 /*@}*/
screamer 0:c5e2f793b59a 365
screamer 0:c5e2f793b59a 366 /*******************************************************************************
screamer 0:c5e2f793b59a 367 * HW_CMT_OC - CMT Output Control Register
screamer 0:c5e2f793b59a 368 ******************************************************************************/
screamer 0:c5e2f793b59a 369
screamer 0:c5e2f793b59a 370 /*!
screamer 0:c5e2f793b59a 371 * @brief HW_CMT_OC - CMT Output Control Register (RW)
screamer 0:c5e2f793b59a 372 *
screamer 0:c5e2f793b59a 373 * Reset value: 0x00U
screamer 0:c5e2f793b59a 374 *
screamer 0:c5e2f793b59a 375 * This register is used to control the IRO signal of the CMT module.
screamer 0:c5e2f793b59a 376 */
screamer 0:c5e2f793b59a 377 typedef union _hw_cmt_oc
screamer 0:c5e2f793b59a 378 {
screamer 0:c5e2f793b59a 379 uint8_t U;
screamer 0:c5e2f793b59a 380 struct _hw_cmt_oc_bitfields
screamer 0:c5e2f793b59a 381 {
screamer 0:c5e2f793b59a 382 uint8_t RESERVED0 : 5; /*!< [4:0] */
screamer 0:c5e2f793b59a 383 uint8_t IROPEN : 1; /*!< [5] IRO Pin Enable */
screamer 0:c5e2f793b59a 384 uint8_t CMTPOL : 1; /*!< [6] CMT Output Polarity */
screamer 0:c5e2f793b59a 385 uint8_t IROL : 1; /*!< [7] IRO Latch Control */
screamer 0:c5e2f793b59a 386 } B;
screamer 0:c5e2f793b59a 387 } hw_cmt_oc_t;
screamer 0:c5e2f793b59a 388
screamer 0:c5e2f793b59a 389 /*!
screamer 0:c5e2f793b59a 390 * @name Constants and macros for entire CMT_OC register
screamer 0:c5e2f793b59a 391 */
screamer 0:c5e2f793b59a 392 /*@{*/
screamer 0:c5e2f793b59a 393 #define HW_CMT_OC_ADDR(x) ((x) + 0x4U)
screamer 0:c5e2f793b59a 394
screamer 0:c5e2f793b59a 395 #define HW_CMT_OC(x) (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR(x))
screamer 0:c5e2f793b59a 396 #define HW_CMT_OC_RD(x) (HW_CMT_OC(x).U)
screamer 0:c5e2f793b59a 397 #define HW_CMT_OC_WR(x, v) (HW_CMT_OC(x).U = (v))
screamer 0:c5e2f793b59a 398 #define HW_CMT_OC_SET(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) | (v)))
screamer 0:c5e2f793b59a 399 #define HW_CMT_OC_CLR(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 400 #define HW_CMT_OC_TOG(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 401 /*@}*/
screamer 0:c5e2f793b59a 402
screamer 0:c5e2f793b59a 403 /*
screamer 0:c5e2f793b59a 404 * Constants & macros for individual CMT_OC bitfields
screamer 0:c5e2f793b59a 405 */
screamer 0:c5e2f793b59a 406
screamer 0:c5e2f793b59a 407 /*!
screamer 0:c5e2f793b59a 408 * @name Register CMT_OC, field IROPEN[5] (RW)
screamer 0:c5e2f793b59a 409 *
screamer 0:c5e2f793b59a 410 * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
screamer 0:c5e2f793b59a 411 * output that drives out either the CMT transmitter output or the state of IROL
screamer 0:c5e2f793b59a 412 * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
screamer 0:c5e2f793b59a 413 * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
screamer 0:c5e2f793b59a 414 * signal is disabled, it is in a high-impedance state and is unable to draw any
screamer 0:c5e2f793b59a 415 * current. This signal is disabled during reset.
screamer 0:c5e2f793b59a 416 *
screamer 0:c5e2f793b59a 417 * Values:
screamer 0:c5e2f793b59a 418 * - 0 - The IRO signal is disabled.
screamer 0:c5e2f793b59a 419 * - 1 - The IRO signal is enabled as output.
screamer 0:c5e2f793b59a 420 */
screamer 0:c5e2f793b59a 421 /*@{*/
screamer 0:c5e2f793b59a 422 #define BP_CMT_OC_IROPEN (5U) /*!< Bit position for CMT_OC_IROPEN. */
screamer 0:c5e2f793b59a 423 #define BM_CMT_OC_IROPEN (0x20U) /*!< Bit mask for CMT_OC_IROPEN. */
screamer 0:c5e2f793b59a 424 #define BS_CMT_OC_IROPEN (1U) /*!< Bit field size in bits for CMT_OC_IROPEN. */
screamer 0:c5e2f793b59a 425
screamer 0:c5e2f793b59a 426 /*! @brief Read current value of the CMT_OC_IROPEN field. */
screamer 0:c5e2f793b59a 427 #define BR_CMT_OC_IROPEN(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN))
screamer 0:c5e2f793b59a 428
screamer 0:c5e2f793b59a 429 /*! @brief Format value for bitfield CMT_OC_IROPEN. */
screamer 0:c5e2f793b59a 430 #define BF_CMT_OC_IROPEN(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROPEN) & BM_CMT_OC_IROPEN)
screamer 0:c5e2f793b59a 431
screamer 0:c5e2f793b59a 432 /*! @brief Set the IROPEN field to a new value. */
screamer 0:c5e2f793b59a 433 #define BW_CMT_OC_IROPEN(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN) = (v))
screamer 0:c5e2f793b59a 434 /*@}*/
screamer 0:c5e2f793b59a 435
screamer 0:c5e2f793b59a 436 /*!
screamer 0:c5e2f793b59a 437 * @name Register CMT_OC, field CMTPOL[6] (RW)
screamer 0:c5e2f793b59a 438 *
screamer 0:c5e2f793b59a 439 * Controls the polarity of the IRO signal.
screamer 0:c5e2f793b59a 440 *
screamer 0:c5e2f793b59a 441 * Values:
screamer 0:c5e2f793b59a 442 * - 0 - The IRO signal is active-low.
screamer 0:c5e2f793b59a 443 * - 1 - The IRO signal is active-high.
screamer 0:c5e2f793b59a 444 */
screamer 0:c5e2f793b59a 445 /*@{*/
screamer 0:c5e2f793b59a 446 #define BP_CMT_OC_CMTPOL (6U) /*!< Bit position for CMT_OC_CMTPOL. */
screamer 0:c5e2f793b59a 447 #define BM_CMT_OC_CMTPOL (0x40U) /*!< Bit mask for CMT_OC_CMTPOL. */
screamer 0:c5e2f793b59a 448 #define BS_CMT_OC_CMTPOL (1U) /*!< Bit field size in bits for CMT_OC_CMTPOL. */
screamer 0:c5e2f793b59a 449
screamer 0:c5e2f793b59a 450 /*! @brief Read current value of the CMT_OC_CMTPOL field. */
screamer 0:c5e2f793b59a 451 #define BR_CMT_OC_CMTPOL(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL))
screamer 0:c5e2f793b59a 452
screamer 0:c5e2f793b59a 453 /*! @brief Format value for bitfield CMT_OC_CMTPOL. */
screamer 0:c5e2f793b59a 454 #define BF_CMT_OC_CMTPOL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_CMTPOL) & BM_CMT_OC_CMTPOL)
screamer 0:c5e2f793b59a 455
screamer 0:c5e2f793b59a 456 /*! @brief Set the CMTPOL field to a new value. */
screamer 0:c5e2f793b59a 457 #define BW_CMT_OC_CMTPOL(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL) = (v))
screamer 0:c5e2f793b59a 458 /*@}*/
screamer 0:c5e2f793b59a 459
screamer 0:c5e2f793b59a 460 /*!
screamer 0:c5e2f793b59a 461 * @name Register CMT_OC, field IROL[7] (RW)
screamer 0:c5e2f793b59a 462 *
screamer 0:c5e2f793b59a 463 * Reads the state of the IRO latch. Writing to IROL changes the state of the
screamer 0:c5e2f793b59a 464 * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
screamer 0:c5e2f793b59a 465 */
screamer 0:c5e2f793b59a 466 /*@{*/
screamer 0:c5e2f793b59a 467 #define BP_CMT_OC_IROL (7U) /*!< Bit position for CMT_OC_IROL. */
screamer 0:c5e2f793b59a 468 #define BM_CMT_OC_IROL (0x80U) /*!< Bit mask for CMT_OC_IROL. */
screamer 0:c5e2f793b59a 469 #define BS_CMT_OC_IROL (1U) /*!< Bit field size in bits for CMT_OC_IROL. */
screamer 0:c5e2f793b59a 470
screamer 0:c5e2f793b59a 471 /*! @brief Read current value of the CMT_OC_IROL field. */
screamer 0:c5e2f793b59a 472 #define BR_CMT_OC_IROL(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL))
screamer 0:c5e2f793b59a 473
screamer 0:c5e2f793b59a 474 /*! @brief Format value for bitfield CMT_OC_IROL. */
screamer 0:c5e2f793b59a 475 #define BF_CMT_OC_IROL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROL) & BM_CMT_OC_IROL)
screamer 0:c5e2f793b59a 476
screamer 0:c5e2f793b59a 477 /*! @brief Set the IROL field to a new value. */
screamer 0:c5e2f793b59a 478 #define BW_CMT_OC_IROL(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL) = (v))
screamer 0:c5e2f793b59a 479 /*@}*/
screamer 0:c5e2f793b59a 480
screamer 0:c5e2f793b59a 481 /*******************************************************************************
screamer 0:c5e2f793b59a 482 * HW_CMT_MSC - CMT Modulator Status and Control Register
screamer 0:c5e2f793b59a 483 ******************************************************************************/
screamer 0:c5e2f793b59a 484
screamer 0:c5e2f793b59a 485 /*!
screamer 0:c5e2f793b59a 486 * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
screamer 0:c5e2f793b59a 487 *
screamer 0:c5e2f793b59a 488 * Reset value: 0x00U
screamer 0:c5e2f793b59a 489 *
screamer 0:c5e2f793b59a 490 * This register contains the modulator and carrier generator enable (MCGEN),
screamer 0:c5e2f793b59a 491 * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
screamer 0:c5e2f793b59a 492 * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
screamer 0:c5e2f793b59a 493 * (EOCF) status bit.
screamer 0:c5e2f793b59a 494 */
screamer 0:c5e2f793b59a 495 typedef union _hw_cmt_msc
screamer 0:c5e2f793b59a 496 {
screamer 0:c5e2f793b59a 497 uint8_t U;
screamer 0:c5e2f793b59a 498 struct _hw_cmt_msc_bitfields
screamer 0:c5e2f793b59a 499 {
screamer 0:c5e2f793b59a 500 uint8_t MCGEN : 1; /*!< [0] Modulator and Carrier Generator Enable */
screamer 0:c5e2f793b59a 501 uint8_t EOCIE : 1; /*!< [1] End of Cycle Interrupt Enable */
screamer 0:c5e2f793b59a 502 uint8_t FSK : 1; /*!< [2] FSK Mode Select */
screamer 0:c5e2f793b59a 503 uint8_t BASE : 1; /*!< [3] Baseband Enable */
screamer 0:c5e2f793b59a 504 uint8_t EXSPC : 1; /*!< [4] Extended Space Enable */
screamer 0:c5e2f793b59a 505 uint8_t CMTDIV : 2; /*!< [6:5] CMT Clock Divide Prescaler */
screamer 0:c5e2f793b59a 506 uint8_t EOCF : 1; /*!< [7] End Of Cycle Status Flag */
screamer 0:c5e2f793b59a 507 } B;
screamer 0:c5e2f793b59a 508 } hw_cmt_msc_t;
screamer 0:c5e2f793b59a 509
screamer 0:c5e2f793b59a 510 /*!
screamer 0:c5e2f793b59a 511 * @name Constants and macros for entire CMT_MSC register
screamer 0:c5e2f793b59a 512 */
screamer 0:c5e2f793b59a 513 /*@{*/
screamer 0:c5e2f793b59a 514 #define HW_CMT_MSC_ADDR(x) ((x) + 0x5U)
screamer 0:c5e2f793b59a 515
screamer 0:c5e2f793b59a 516 #define HW_CMT_MSC(x) (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR(x))
screamer 0:c5e2f793b59a 517 #define HW_CMT_MSC_RD(x) (HW_CMT_MSC(x).U)
screamer 0:c5e2f793b59a 518 #define HW_CMT_MSC_WR(x, v) (HW_CMT_MSC(x).U = (v))
screamer 0:c5e2f793b59a 519 #define HW_CMT_MSC_SET(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) | (v)))
screamer 0:c5e2f793b59a 520 #define HW_CMT_MSC_CLR(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 521 #define HW_CMT_MSC_TOG(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 522 /*@}*/
screamer 0:c5e2f793b59a 523
screamer 0:c5e2f793b59a 524 /*
screamer 0:c5e2f793b59a 525 * Constants & macros for individual CMT_MSC bitfields
screamer 0:c5e2f793b59a 526 */
screamer 0:c5e2f793b59a 527
screamer 0:c5e2f793b59a 528 /*!
screamer 0:c5e2f793b59a 529 * @name Register CMT_MSC, field MCGEN[0] (RW)
screamer 0:c5e2f793b59a 530 *
screamer 0:c5e2f793b59a 531 * Setting MCGEN will initialize the carrier generator and modulator and will
screamer 0:c5e2f793b59a 532 * enable all clocks. When enabled, the carrier generator and modulator will
screamer 0:c5e2f793b59a 533 * function continuously. When MCGEN is cleared, the current modulator cycle will be
screamer 0:c5e2f793b59a 534 * allowed to expire before all carrier and modulator clocks are disabled to save
screamer 0:c5e2f793b59a 535 * power and the modulator output is forced low. To prevent spurious operation,
screamer 0:c5e2f793b59a 536 * the user should initialize all data and control registers before enabling the
screamer 0:c5e2f793b59a 537 * system.
screamer 0:c5e2f793b59a 538 *
screamer 0:c5e2f793b59a 539 * Values:
screamer 0:c5e2f793b59a 540 * - 0 - Modulator and carrier generator disabled
screamer 0:c5e2f793b59a 541 * - 1 - Modulator and carrier generator enabled
screamer 0:c5e2f793b59a 542 */
screamer 0:c5e2f793b59a 543 /*@{*/
screamer 0:c5e2f793b59a 544 #define BP_CMT_MSC_MCGEN (0U) /*!< Bit position for CMT_MSC_MCGEN. */
screamer 0:c5e2f793b59a 545 #define BM_CMT_MSC_MCGEN (0x01U) /*!< Bit mask for CMT_MSC_MCGEN. */
screamer 0:c5e2f793b59a 546 #define BS_CMT_MSC_MCGEN (1U) /*!< Bit field size in bits for CMT_MSC_MCGEN. */
screamer 0:c5e2f793b59a 547
screamer 0:c5e2f793b59a 548 /*! @brief Read current value of the CMT_MSC_MCGEN field. */
screamer 0:c5e2f793b59a 549 #define BR_CMT_MSC_MCGEN(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN))
screamer 0:c5e2f793b59a 550
screamer 0:c5e2f793b59a 551 /*! @brief Format value for bitfield CMT_MSC_MCGEN. */
screamer 0:c5e2f793b59a 552 #define BF_CMT_MSC_MCGEN(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_MCGEN) & BM_CMT_MSC_MCGEN)
screamer 0:c5e2f793b59a 553
screamer 0:c5e2f793b59a 554 /*! @brief Set the MCGEN field to a new value. */
screamer 0:c5e2f793b59a 555 #define BW_CMT_MSC_MCGEN(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN) = (v))
screamer 0:c5e2f793b59a 556 /*@}*/
screamer 0:c5e2f793b59a 557
screamer 0:c5e2f793b59a 558 /*!
screamer 0:c5e2f793b59a 559 * @name Register CMT_MSC, field EOCIE[1] (RW)
screamer 0:c5e2f793b59a 560 *
screamer 0:c5e2f793b59a 561 * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
screamer 0:c5e2f793b59a 562 *
screamer 0:c5e2f793b59a 563 * Values:
screamer 0:c5e2f793b59a 564 * - 0 - CPU interrupt is disabled.
screamer 0:c5e2f793b59a 565 * - 1 - CPU interrupt is enabled.
screamer 0:c5e2f793b59a 566 */
screamer 0:c5e2f793b59a 567 /*@{*/
screamer 0:c5e2f793b59a 568 #define BP_CMT_MSC_EOCIE (1U) /*!< Bit position for CMT_MSC_EOCIE. */
screamer 0:c5e2f793b59a 569 #define BM_CMT_MSC_EOCIE (0x02U) /*!< Bit mask for CMT_MSC_EOCIE. */
screamer 0:c5e2f793b59a 570 #define BS_CMT_MSC_EOCIE (1U) /*!< Bit field size in bits for CMT_MSC_EOCIE. */
screamer 0:c5e2f793b59a 571
screamer 0:c5e2f793b59a 572 /*! @brief Read current value of the CMT_MSC_EOCIE field. */
screamer 0:c5e2f793b59a 573 #define BR_CMT_MSC_EOCIE(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE))
screamer 0:c5e2f793b59a 574
screamer 0:c5e2f793b59a 575 /*! @brief Format value for bitfield CMT_MSC_EOCIE. */
screamer 0:c5e2f793b59a 576 #define BF_CMT_MSC_EOCIE(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EOCIE) & BM_CMT_MSC_EOCIE)
screamer 0:c5e2f793b59a 577
screamer 0:c5e2f793b59a 578 /*! @brief Set the EOCIE field to a new value. */
screamer 0:c5e2f793b59a 579 #define BW_CMT_MSC_EOCIE(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE) = (v))
screamer 0:c5e2f793b59a 580 /*@}*/
screamer 0:c5e2f793b59a 581
screamer 0:c5e2f793b59a 582 /*!
screamer 0:c5e2f793b59a 583 * @name Register CMT_MSC, field FSK[2] (RW)
screamer 0:c5e2f793b59a 584 *
screamer 0:c5e2f793b59a 585 * Enables FSK operation.
screamer 0:c5e2f793b59a 586 *
screamer 0:c5e2f793b59a 587 * Values:
screamer 0:c5e2f793b59a 588 * - 0 - The CMT operates in Time or Baseband mode.
screamer 0:c5e2f793b59a 589 * - 1 - The CMT operates in FSK mode.
screamer 0:c5e2f793b59a 590 */
screamer 0:c5e2f793b59a 591 /*@{*/
screamer 0:c5e2f793b59a 592 #define BP_CMT_MSC_FSK (2U) /*!< Bit position for CMT_MSC_FSK. */
screamer 0:c5e2f793b59a 593 #define BM_CMT_MSC_FSK (0x04U) /*!< Bit mask for CMT_MSC_FSK. */
screamer 0:c5e2f793b59a 594 #define BS_CMT_MSC_FSK (1U) /*!< Bit field size in bits for CMT_MSC_FSK. */
screamer 0:c5e2f793b59a 595
screamer 0:c5e2f793b59a 596 /*! @brief Read current value of the CMT_MSC_FSK field. */
screamer 0:c5e2f793b59a 597 #define BR_CMT_MSC_FSK(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK))
screamer 0:c5e2f793b59a 598
screamer 0:c5e2f793b59a 599 /*! @brief Format value for bitfield CMT_MSC_FSK. */
screamer 0:c5e2f793b59a 600 #define BF_CMT_MSC_FSK(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_FSK) & BM_CMT_MSC_FSK)
screamer 0:c5e2f793b59a 601
screamer 0:c5e2f793b59a 602 /*! @brief Set the FSK field to a new value. */
screamer 0:c5e2f793b59a 603 #define BW_CMT_MSC_FSK(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK) = (v))
screamer 0:c5e2f793b59a 604 /*@}*/
screamer 0:c5e2f793b59a 605
screamer 0:c5e2f793b59a 606 /*!
screamer 0:c5e2f793b59a 607 * @name Register CMT_MSC, field BASE[3] (RW)
screamer 0:c5e2f793b59a 608 *
screamer 0:c5e2f793b59a 609 * When set, BASE disables the carrier generator and forces the carrier output
screamer 0:c5e2f793b59a 610 * high for generation of baseband protocols. When BASE is cleared, the carrier
screamer 0:c5e2f793b59a 611 * generator is enabled and the carrier output toggles at the frequency determined
screamer 0:c5e2f793b59a 612 * by values stored in the carrier data registers. This field is cleared by
screamer 0:c5e2f793b59a 613 * reset. This field is not double-buffered and must not be written to during a
screamer 0:c5e2f793b59a 614 * transmission.
screamer 0:c5e2f793b59a 615 *
screamer 0:c5e2f793b59a 616 * Values:
screamer 0:c5e2f793b59a 617 * - 0 - Baseband mode is disabled.
screamer 0:c5e2f793b59a 618 * - 1 - Baseband mode is enabled.
screamer 0:c5e2f793b59a 619 */
screamer 0:c5e2f793b59a 620 /*@{*/
screamer 0:c5e2f793b59a 621 #define BP_CMT_MSC_BASE (3U) /*!< Bit position for CMT_MSC_BASE. */
screamer 0:c5e2f793b59a 622 #define BM_CMT_MSC_BASE (0x08U) /*!< Bit mask for CMT_MSC_BASE. */
screamer 0:c5e2f793b59a 623 #define BS_CMT_MSC_BASE (1U) /*!< Bit field size in bits for CMT_MSC_BASE. */
screamer 0:c5e2f793b59a 624
screamer 0:c5e2f793b59a 625 /*! @brief Read current value of the CMT_MSC_BASE field. */
screamer 0:c5e2f793b59a 626 #define BR_CMT_MSC_BASE(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE))
screamer 0:c5e2f793b59a 627
screamer 0:c5e2f793b59a 628 /*! @brief Format value for bitfield CMT_MSC_BASE. */
screamer 0:c5e2f793b59a 629 #define BF_CMT_MSC_BASE(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_BASE) & BM_CMT_MSC_BASE)
screamer 0:c5e2f793b59a 630
screamer 0:c5e2f793b59a 631 /*! @brief Set the BASE field to a new value. */
screamer 0:c5e2f793b59a 632 #define BW_CMT_MSC_BASE(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE) = (v))
screamer 0:c5e2f793b59a 633 /*@}*/
screamer 0:c5e2f793b59a 634
screamer 0:c5e2f793b59a 635 /*!
screamer 0:c5e2f793b59a 636 * @name Register CMT_MSC, field EXSPC[4] (RW)
screamer 0:c5e2f793b59a 637 *
screamer 0:c5e2f793b59a 638 * Enables the extended space operation.
screamer 0:c5e2f793b59a 639 *
screamer 0:c5e2f793b59a 640 * Values:
screamer 0:c5e2f793b59a 641 * - 0 - Extended space is disabled.
screamer 0:c5e2f793b59a 642 * - 1 - Extended space is enabled.
screamer 0:c5e2f793b59a 643 */
screamer 0:c5e2f793b59a 644 /*@{*/
screamer 0:c5e2f793b59a 645 #define BP_CMT_MSC_EXSPC (4U) /*!< Bit position for CMT_MSC_EXSPC. */
screamer 0:c5e2f793b59a 646 #define BM_CMT_MSC_EXSPC (0x10U) /*!< Bit mask for CMT_MSC_EXSPC. */
screamer 0:c5e2f793b59a 647 #define BS_CMT_MSC_EXSPC (1U) /*!< Bit field size in bits for CMT_MSC_EXSPC. */
screamer 0:c5e2f793b59a 648
screamer 0:c5e2f793b59a 649 /*! @brief Read current value of the CMT_MSC_EXSPC field. */
screamer 0:c5e2f793b59a 650 #define BR_CMT_MSC_EXSPC(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC))
screamer 0:c5e2f793b59a 651
screamer 0:c5e2f793b59a 652 /*! @brief Format value for bitfield CMT_MSC_EXSPC. */
screamer 0:c5e2f793b59a 653 #define BF_CMT_MSC_EXSPC(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EXSPC) & BM_CMT_MSC_EXSPC)
screamer 0:c5e2f793b59a 654
screamer 0:c5e2f793b59a 655 /*! @brief Set the EXSPC field to a new value. */
screamer 0:c5e2f793b59a 656 #define BW_CMT_MSC_EXSPC(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC) = (v))
screamer 0:c5e2f793b59a 657 /*@}*/
screamer 0:c5e2f793b59a 658
screamer 0:c5e2f793b59a 659 /*!
screamer 0:c5e2f793b59a 660 * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
screamer 0:c5e2f793b59a 661 *
screamer 0:c5e2f793b59a 662 * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
screamer 0:c5e2f793b59a 663 * divided by 2 ,4, or 8 . This field must not be changed during a transmission
screamer 0:c5e2f793b59a 664 * because it is not double-buffered.
screamer 0:c5e2f793b59a 665 *
screamer 0:c5e2f793b59a 666 * Values:
screamer 0:c5e2f793b59a 667 * - 00 - IF * 1
screamer 0:c5e2f793b59a 668 * - 01 - IF * 2
screamer 0:c5e2f793b59a 669 * - 10 - IF * 4
screamer 0:c5e2f793b59a 670 * - 11 - IF * 8
screamer 0:c5e2f793b59a 671 */
screamer 0:c5e2f793b59a 672 /*@{*/
screamer 0:c5e2f793b59a 673 #define BP_CMT_MSC_CMTDIV (5U) /*!< Bit position for CMT_MSC_CMTDIV. */
screamer 0:c5e2f793b59a 674 #define BM_CMT_MSC_CMTDIV (0x60U) /*!< Bit mask for CMT_MSC_CMTDIV. */
screamer 0:c5e2f793b59a 675 #define BS_CMT_MSC_CMTDIV (2U) /*!< Bit field size in bits for CMT_MSC_CMTDIV. */
screamer 0:c5e2f793b59a 676
screamer 0:c5e2f793b59a 677 /*! @brief Read current value of the CMT_MSC_CMTDIV field. */
screamer 0:c5e2f793b59a 678 #define BR_CMT_MSC_CMTDIV(x) (HW_CMT_MSC(x).B.CMTDIV)
screamer 0:c5e2f793b59a 679
screamer 0:c5e2f793b59a 680 /*! @brief Format value for bitfield CMT_MSC_CMTDIV. */
screamer 0:c5e2f793b59a 681 #define BF_CMT_MSC_CMTDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_CMTDIV) & BM_CMT_MSC_CMTDIV)
screamer 0:c5e2f793b59a 682
screamer 0:c5e2f793b59a 683 /*! @brief Set the CMTDIV field to a new value. */
screamer 0:c5e2f793b59a 684 #define BW_CMT_MSC_CMTDIV(x, v) (HW_CMT_MSC_WR(x, (HW_CMT_MSC_RD(x) & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
screamer 0:c5e2f793b59a 685 /*@}*/
screamer 0:c5e2f793b59a 686
screamer 0:c5e2f793b59a 687 /*!
screamer 0:c5e2f793b59a 688 * @name Register CMT_MSC, field EOCF[7] (RO)
screamer 0:c5e2f793b59a 689 *
screamer 0:c5e2f793b59a 690 * Sets when: The modulator is not currently active and MCGEN is set to begin
screamer 0:c5e2f793b59a 691 * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
screamer 0:c5e2f793b59a 692 * set. This is recognized when a match occurs between the contents of the space
screamer 0:c5e2f793b59a 693 * period register and the down counter. At this time, the counter is
screamer 0:c5e2f793b59a 694 * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
screamer 0:c5e2f793b59a 695 * the space period register is loaded with, possibly new contents of the space
screamer 0:c5e2f793b59a 696 * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
screamer 0:c5e2f793b59a 697 * access of CMD2 or CMD4, or by the DMA transfer.
screamer 0:c5e2f793b59a 698 *
screamer 0:c5e2f793b59a 699 * Values:
screamer 0:c5e2f793b59a 700 * - 0 - End of modulation cycle has not occured since the flag last cleared.
screamer 0:c5e2f793b59a 701 * - 1 - End of modulator cycle has occurred.
screamer 0:c5e2f793b59a 702 */
screamer 0:c5e2f793b59a 703 /*@{*/
screamer 0:c5e2f793b59a 704 #define BP_CMT_MSC_EOCF (7U) /*!< Bit position for CMT_MSC_EOCF. */
screamer 0:c5e2f793b59a 705 #define BM_CMT_MSC_EOCF (0x80U) /*!< Bit mask for CMT_MSC_EOCF. */
screamer 0:c5e2f793b59a 706 #define BS_CMT_MSC_EOCF (1U) /*!< Bit field size in bits for CMT_MSC_EOCF. */
screamer 0:c5e2f793b59a 707
screamer 0:c5e2f793b59a 708 /*! @brief Read current value of the CMT_MSC_EOCF field. */
screamer 0:c5e2f793b59a 709 #define BR_CMT_MSC_EOCF(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCF))
screamer 0:c5e2f793b59a 710 /*@}*/
screamer 0:c5e2f793b59a 711
screamer 0:c5e2f793b59a 712 /*******************************************************************************
screamer 0:c5e2f793b59a 713 * HW_CMT_CMD1 - CMT Modulator Data Register Mark High
screamer 0:c5e2f793b59a 714 ******************************************************************************/
screamer 0:c5e2f793b59a 715
screamer 0:c5e2f793b59a 716 /*!
screamer 0:c5e2f793b59a 717 * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
screamer 0:c5e2f793b59a 718 *
screamer 0:c5e2f793b59a 719 * Reset value: 0x00U
screamer 0:c5e2f793b59a 720 *
screamer 0:c5e2f793b59a 721 * The contents of this register are transferred to the modulator down counter
screamer 0:c5e2f793b59a 722 * upon the completion of a modulation period.
screamer 0:c5e2f793b59a 723 */
screamer 0:c5e2f793b59a 724 typedef union _hw_cmt_cmd1
screamer 0:c5e2f793b59a 725 {
screamer 0:c5e2f793b59a 726 uint8_t U;
screamer 0:c5e2f793b59a 727 struct _hw_cmt_cmd1_bitfields
screamer 0:c5e2f793b59a 728 {
screamer 0:c5e2f793b59a 729 uint8_t MB : 8; /*!< [7:0] */
screamer 0:c5e2f793b59a 730 } B;
screamer 0:c5e2f793b59a 731 } hw_cmt_cmd1_t;
screamer 0:c5e2f793b59a 732
screamer 0:c5e2f793b59a 733 /*!
screamer 0:c5e2f793b59a 734 * @name Constants and macros for entire CMT_CMD1 register
screamer 0:c5e2f793b59a 735 */
screamer 0:c5e2f793b59a 736 /*@{*/
screamer 0:c5e2f793b59a 737 #define HW_CMT_CMD1_ADDR(x) ((x) + 0x6U)
screamer 0:c5e2f793b59a 738
screamer 0:c5e2f793b59a 739 #define HW_CMT_CMD1(x) (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR(x))
screamer 0:c5e2f793b59a 740 #define HW_CMT_CMD1_RD(x) (HW_CMT_CMD1(x).U)
screamer 0:c5e2f793b59a 741 #define HW_CMT_CMD1_WR(x, v) (HW_CMT_CMD1(x).U = (v))
screamer 0:c5e2f793b59a 742 #define HW_CMT_CMD1_SET(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) | (v)))
screamer 0:c5e2f793b59a 743 #define HW_CMT_CMD1_CLR(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 744 #define HW_CMT_CMD1_TOG(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 745 /*@}*/
screamer 0:c5e2f793b59a 746
screamer 0:c5e2f793b59a 747 /*
screamer 0:c5e2f793b59a 748 * Constants & macros for individual CMT_CMD1 bitfields
screamer 0:c5e2f793b59a 749 */
screamer 0:c5e2f793b59a 750
screamer 0:c5e2f793b59a 751 /*!
screamer 0:c5e2f793b59a 752 * @name Register CMT_CMD1, field MB[7:0] (RW)
screamer 0:c5e2f793b59a 753 *
screamer 0:c5e2f793b59a 754 * Controls the upper mark periods of the modulator for all modes.
screamer 0:c5e2f793b59a 755 */
screamer 0:c5e2f793b59a 756 /*@{*/
screamer 0:c5e2f793b59a 757 #define BP_CMT_CMD1_MB (0U) /*!< Bit position for CMT_CMD1_MB. */
screamer 0:c5e2f793b59a 758 #define BM_CMT_CMD1_MB (0xFFU) /*!< Bit mask for CMT_CMD1_MB. */
screamer 0:c5e2f793b59a 759 #define BS_CMT_CMD1_MB (8U) /*!< Bit field size in bits for CMT_CMD1_MB. */
screamer 0:c5e2f793b59a 760
screamer 0:c5e2f793b59a 761 /*! @brief Read current value of the CMT_CMD1_MB field. */
screamer 0:c5e2f793b59a 762 #define BR_CMT_CMD1_MB(x) (HW_CMT_CMD1(x).U)
screamer 0:c5e2f793b59a 763
screamer 0:c5e2f793b59a 764 /*! @brief Format value for bitfield CMT_CMD1_MB. */
screamer 0:c5e2f793b59a 765 #define BF_CMT_CMD1_MB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD1_MB) & BM_CMT_CMD1_MB)
screamer 0:c5e2f793b59a 766
screamer 0:c5e2f793b59a 767 /*! @brief Set the MB field to a new value. */
screamer 0:c5e2f793b59a 768 #define BW_CMT_CMD1_MB(x, v) (HW_CMT_CMD1_WR(x, v))
screamer 0:c5e2f793b59a 769 /*@}*/
screamer 0:c5e2f793b59a 770
screamer 0:c5e2f793b59a 771 /*******************************************************************************
screamer 0:c5e2f793b59a 772 * HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
screamer 0:c5e2f793b59a 773 ******************************************************************************/
screamer 0:c5e2f793b59a 774
screamer 0:c5e2f793b59a 775 /*!
screamer 0:c5e2f793b59a 776 * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
screamer 0:c5e2f793b59a 777 *
screamer 0:c5e2f793b59a 778 * Reset value: 0x00U
screamer 0:c5e2f793b59a 779 *
screamer 0:c5e2f793b59a 780 * The contents of this register are transferred to the modulator down counter
screamer 0:c5e2f793b59a 781 * upon the completion of a modulation period.
screamer 0:c5e2f793b59a 782 */
screamer 0:c5e2f793b59a 783 typedef union _hw_cmt_cmd2
screamer 0:c5e2f793b59a 784 {
screamer 0:c5e2f793b59a 785 uint8_t U;
screamer 0:c5e2f793b59a 786 struct _hw_cmt_cmd2_bitfields
screamer 0:c5e2f793b59a 787 {
screamer 0:c5e2f793b59a 788 uint8_t MB : 8; /*!< [7:0] */
screamer 0:c5e2f793b59a 789 } B;
screamer 0:c5e2f793b59a 790 } hw_cmt_cmd2_t;
screamer 0:c5e2f793b59a 791
screamer 0:c5e2f793b59a 792 /*!
screamer 0:c5e2f793b59a 793 * @name Constants and macros for entire CMT_CMD2 register
screamer 0:c5e2f793b59a 794 */
screamer 0:c5e2f793b59a 795 /*@{*/
screamer 0:c5e2f793b59a 796 #define HW_CMT_CMD2_ADDR(x) ((x) + 0x7U)
screamer 0:c5e2f793b59a 797
screamer 0:c5e2f793b59a 798 #define HW_CMT_CMD2(x) (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR(x))
screamer 0:c5e2f793b59a 799 #define HW_CMT_CMD2_RD(x) (HW_CMT_CMD2(x).U)
screamer 0:c5e2f793b59a 800 #define HW_CMT_CMD2_WR(x, v) (HW_CMT_CMD2(x).U = (v))
screamer 0:c5e2f793b59a 801 #define HW_CMT_CMD2_SET(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) | (v)))
screamer 0:c5e2f793b59a 802 #define HW_CMT_CMD2_CLR(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 803 #define HW_CMT_CMD2_TOG(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 804 /*@}*/
screamer 0:c5e2f793b59a 805
screamer 0:c5e2f793b59a 806 /*
screamer 0:c5e2f793b59a 807 * Constants & macros for individual CMT_CMD2 bitfields
screamer 0:c5e2f793b59a 808 */
screamer 0:c5e2f793b59a 809
screamer 0:c5e2f793b59a 810 /*!
screamer 0:c5e2f793b59a 811 * @name Register CMT_CMD2, field MB[7:0] (RW)
screamer 0:c5e2f793b59a 812 *
screamer 0:c5e2f793b59a 813 * Controls the lower mark periods of the modulator for all modes.
screamer 0:c5e2f793b59a 814 */
screamer 0:c5e2f793b59a 815 /*@{*/
screamer 0:c5e2f793b59a 816 #define BP_CMT_CMD2_MB (0U) /*!< Bit position for CMT_CMD2_MB. */
screamer 0:c5e2f793b59a 817 #define BM_CMT_CMD2_MB (0xFFU) /*!< Bit mask for CMT_CMD2_MB. */
screamer 0:c5e2f793b59a 818 #define BS_CMT_CMD2_MB (8U) /*!< Bit field size in bits for CMT_CMD2_MB. */
screamer 0:c5e2f793b59a 819
screamer 0:c5e2f793b59a 820 /*! @brief Read current value of the CMT_CMD2_MB field. */
screamer 0:c5e2f793b59a 821 #define BR_CMT_CMD2_MB(x) (HW_CMT_CMD2(x).U)
screamer 0:c5e2f793b59a 822
screamer 0:c5e2f793b59a 823 /*! @brief Format value for bitfield CMT_CMD2_MB. */
screamer 0:c5e2f793b59a 824 #define BF_CMT_CMD2_MB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD2_MB) & BM_CMT_CMD2_MB)
screamer 0:c5e2f793b59a 825
screamer 0:c5e2f793b59a 826 /*! @brief Set the MB field to a new value. */
screamer 0:c5e2f793b59a 827 #define BW_CMT_CMD2_MB(x, v) (HW_CMT_CMD2_WR(x, v))
screamer 0:c5e2f793b59a 828 /*@}*/
screamer 0:c5e2f793b59a 829
screamer 0:c5e2f793b59a 830 /*******************************************************************************
screamer 0:c5e2f793b59a 831 * HW_CMT_CMD3 - CMT Modulator Data Register Space High
screamer 0:c5e2f793b59a 832 ******************************************************************************/
screamer 0:c5e2f793b59a 833
screamer 0:c5e2f793b59a 834 /*!
screamer 0:c5e2f793b59a 835 * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
screamer 0:c5e2f793b59a 836 *
screamer 0:c5e2f793b59a 837 * Reset value: 0x00U
screamer 0:c5e2f793b59a 838 *
screamer 0:c5e2f793b59a 839 * The contents of this register are transferred to the space period register
screamer 0:c5e2f793b59a 840 * upon the completion of a modulation period.
screamer 0:c5e2f793b59a 841 */
screamer 0:c5e2f793b59a 842 typedef union _hw_cmt_cmd3
screamer 0:c5e2f793b59a 843 {
screamer 0:c5e2f793b59a 844 uint8_t U;
screamer 0:c5e2f793b59a 845 struct _hw_cmt_cmd3_bitfields
screamer 0:c5e2f793b59a 846 {
screamer 0:c5e2f793b59a 847 uint8_t SB : 8; /*!< [7:0] */
screamer 0:c5e2f793b59a 848 } B;
screamer 0:c5e2f793b59a 849 } hw_cmt_cmd3_t;
screamer 0:c5e2f793b59a 850
screamer 0:c5e2f793b59a 851 /*!
screamer 0:c5e2f793b59a 852 * @name Constants and macros for entire CMT_CMD3 register
screamer 0:c5e2f793b59a 853 */
screamer 0:c5e2f793b59a 854 /*@{*/
screamer 0:c5e2f793b59a 855 #define HW_CMT_CMD3_ADDR(x) ((x) + 0x8U)
screamer 0:c5e2f793b59a 856
screamer 0:c5e2f793b59a 857 #define HW_CMT_CMD3(x) (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR(x))
screamer 0:c5e2f793b59a 858 #define HW_CMT_CMD3_RD(x) (HW_CMT_CMD3(x).U)
screamer 0:c5e2f793b59a 859 #define HW_CMT_CMD3_WR(x, v) (HW_CMT_CMD3(x).U = (v))
screamer 0:c5e2f793b59a 860 #define HW_CMT_CMD3_SET(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) | (v)))
screamer 0:c5e2f793b59a 861 #define HW_CMT_CMD3_CLR(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 862 #define HW_CMT_CMD3_TOG(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 863 /*@}*/
screamer 0:c5e2f793b59a 864
screamer 0:c5e2f793b59a 865 /*
screamer 0:c5e2f793b59a 866 * Constants & macros for individual CMT_CMD3 bitfields
screamer 0:c5e2f793b59a 867 */
screamer 0:c5e2f793b59a 868
screamer 0:c5e2f793b59a 869 /*!
screamer 0:c5e2f793b59a 870 * @name Register CMT_CMD3, field SB[7:0] (RW)
screamer 0:c5e2f793b59a 871 *
screamer 0:c5e2f793b59a 872 * Controls the upper space periods of the modulator for all modes.
screamer 0:c5e2f793b59a 873 */
screamer 0:c5e2f793b59a 874 /*@{*/
screamer 0:c5e2f793b59a 875 #define BP_CMT_CMD3_SB (0U) /*!< Bit position for CMT_CMD3_SB. */
screamer 0:c5e2f793b59a 876 #define BM_CMT_CMD3_SB (0xFFU) /*!< Bit mask for CMT_CMD3_SB. */
screamer 0:c5e2f793b59a 877 #define BS_CMT_CMD3_SB (8U) /*!< Bit field size in bits for CMT_CMD3_SB. */
screamer 0:c5e2f793b59a 878
screamer 0:c5e2f793b59a 879 /*! @brief Read current value of the CMT_CMD3_SB field. */
screamer 0:c5e2f793b59a 880 #define BR_CMT_CMD3_SB(x) (HW_CMT_CMD3(x).U)
screamer 0:c5e2f793b59a 881
screamer 0:c5e2f793b59a 882 /*! @brief Format value for bitfield CMT_CMD3_SB. */
screamer 0:c5e2f793b59a 883 #define BF_CMT_CMD3_SB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD3_SB) & BM_CMT_CMD3_SB)
screamer 0:c5e2f793b59a 884
screamer 0:c5e2f793b59a 885 /*! @brief Set the SB field to a new value. */
screamer 0:c5e2f793b59a 886 #define BW_CMT_CMD3_SB(x, v) (HW_CMT_CMD3_WR(x, v))
screamer 0:c5e2f793b59a 887 /*@}*/
screamer 0:c5e2f793b59a 888
screamer 0:c5e2f793b59a 889 /*******************************************************************************
screamer 0:c5e2f793b59a 890 * HW_CMT_CMD4 - CMT Modulator Data Register Space Low
screamer 0:c5e2f793b59a 891 ******************************************************************************/
screamer 0:c5e2f793b59a 892
screamer 0:c5e2f793b59a 893 /*!
screamer 0:c5e2f793b59a 894 * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
screamer 0:c5e2f793b59a 895 *
screamer 0:c5e2f793b59a 896 * Reset value: 0x00U
screamer 0:c5e2f793b59a 897 *
screamer 0:c5e2f793b59a 898 * The contents of this register are transferred to the space period register
screamer 0:c5e2f793b59a 899 * upon the completion of a modulation period.
screamer 0:c5e2f793b59a 900 */
screamer 0:c5e2f793b59a 901 typedef union _hw_cmt_cmd4
screamer 0:c5e2f793b59a 902 {
screamer 0:c5e2f793b59a 903 uint8_t U;
screamer 0:c5e2f793b59a 904 struct _hw_cmt_cmd4_bitfields
screamer 0:c5e2f793b59a 905 {
screamer 0:c5e2f793b59a 906 uint8_t SB : 8; /*!< [7:0] */
screamer 0:c5e2f793b59a 907 } B;
screamer 0:c5e2f793b59a 908 } hw_cmt_cmd4_t;
screamer 0:c5e2f793b59a 909
screamer 0:c5e2f793b59a 910 /*!
screamer 0:c5e2f793b59a 911 * @name Constants and macros for entire CMT_CMD4 register
screamer 0:c5e2f793b59a 912 */
screamer 0:c5e2f793b59a 913 /*@{*/
screamer 0:c5e2f793b59a 914 #define HW_CMT_CMD4_ADDR(x) ((x) + 0x9U)
screamer 0:c5e2f793b59a 915
screamer 0:c5e2f793b59a 916 #define HW_CMT_CMD4(x) (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR(x))
screamer 0:c5e2f793b59a 917 #define HW_CMT_CMD4_RD(x) (HW_CMT_CMD4(x).U)
screamer 0:c5e2f793b59a 918 #define HW_CMT_CMD4_WR(x, v) (HW_CMT_CMD4(x).U = (v))
screamer 0:c5e2f793b59a 919 #define HW_CMT_CMD4_SET(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) | (v)))
screamer 0:c5e2f793b59a 920 #define HW_CMT_CMD4_CLR(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 921 #define HW_CMT_CMD4_TOG(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 922 /*@}*/
screamer 0:c5e2f793b59a 923
screamer 0:c5e2f793b59a 924 /*
screamer 0:c5e2f793b59a 925 * Constants & macros for individual CMT_CMD4 bitfields
screamer 0:c5e2f793b59a 926 */
screamer 0:c5e2f793b59a 927
screamer 0:c5e2f793b59a 928 /*!
screamer 0:c5e2f793b59a 929 * @name Register CMT_CMD4, field SB[7:0] (RW)
screamer 0:c5e2f793b59a 930 *
screamer 0:c5e2f793b59a 931 * Controls the lower space periods of the modulator for all modes.
screamer 0:c5e2f793b59a 932 */
screamer 0:c5e2f793b59a 933 /*@{*/
screamer 0:c5e2f793b59a 934 #define BP_CMT_CMD4_SB (0U) /*!< Bit position for CMT_CMD4_SB. */
screamer 0:c5e2f793b59a 935 #define BM_CMT_CMD4_SB (0xFFU) /*!< Bit mask for CMT_CMD4_SB. */
screamer 0:c5e2f793b59a 936 #define BS_CMT_CMD4_SB (8U) /*!< Bit field size in bits for CMT_CMD4_SB. */
screamer 0:c5e2f793b59a 937
screamer 0:c5e2f793b59a 938 /*! @brief Read current value of the CMT_CMD4_SB field. */
screamer 0:c5e2f793b59a 939 #define BR_CMT_CMD4_SB(x) (HW_CMT_CMD4(x).U)
screamer 0:c5e2f793b59a 940
screamer 0:c5e2f793b59a 941 /*! @brief Format value for bitfield CMT_CMD4_SB. */
screamer 0:c5e2f793b59a 942 #define BF_CMT_CMD4_SB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD4_SB) & BM_CMT_CMD4_SB)
screamer 0:c5e2f793b59a 943
screamer 0:c5e2f793b59a 944 /*! @brief Set the SB field to a new value. */
screamer 0:c5e2f793b59a 945 #define BW_CMT_CMD4_SB(x, v) (HW_CMT_CMD4_WR(x, v))
screamer 0:c5e2f793b59a 946 /*@}*/
screamer 0:c5e2f793b59a 947
screamer 0:c5e2f793b59a 948 /*******************************************************************************
screamer 0:c5e2f793b59a 949 * HW_CMT_PPS - CMT Primary Prescaler Register
screamer 0:c5e2f793b59a 950 ******************************************************************************/
screamer 0:c5e2f793b59a 951
screamer 0:c5e2f793b59a 952 /*!
screamer 0:c5e2f793b59a 953 * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
screamer 0:c5e2f793b59a 954 *
screamer 0:c5e2f793b59a 955 * Reset value: 0x00U
screamer 0:c5e2f793b59a 956 *
screamer 0:c5e2f793b59a 957 * This register is used to set the Primary Prescaler Divider field (PPSDIV).
screamer 0:c5e2f793b59a 958 */
screamer 0:c5e2f793b59a 959 typedef union _hw_cmt_pps
screamer 0:c5e2f793b59a 960 {
screamer 0:c5e2f793b59a 961 uint8_t U;
screamer 0:c5e2f793b59a 962 struct _hw_cmt_pps_bitfields
screamer 0:c5e2f793b59a 963 {
screamer 0:c5e2f793b59a 964 uint8_t PPSDIV : 4; /*!< [3:0] Primary Prescaler Divider */
screamer 0:c5e2f793b59a 965 uint8_t RESERVED0 : 4; /*!< [7:4] */
screamer 0:c5e2f793b59a 966 } B;
screamer 0:c5e2f793b59a 967 } hw_cmt_pps_t;
screamer 0:c5e2f793b59a 968
screamer 0:c5e2f793b59a 969 /*!
screamer 0:c5e2f793b59a 970 * @name Constants and macros for entire CMT_PPS register
screamer 0:c5e2f793b59a 971 */
screamer 0:c5e2f793b59a 972 /*@{*/
screamer 0:c5e2f793b59a 973 #define HW_CMT_PPS_ADDR(x) ((x) + 0xAU)
screamer 0:c5e2f793b59a 974
screamer 0:c5e2f793b59a 975 #define HW_CMT_PPS(x) (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR(x))
screamer 0:c5e2f793b59a 976 #define HW_CMT_PPS_RD(x) (HW_CMT_PPS(x).U)
screamer 0:c5e2f793b59a 977 #define HW_CMT_PPS_WR(x, v) (HW_CMT_PPS(x).U = (v))
screamer 0:c5e2f793b59a 978 #define HW_CMT_PPS_SET(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) | (v)))
screamer 0:c5e2f793b59a 979 #define HW_CMT_PPS_CLR(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 980 #define HW_CMT_PPS_TOG(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 981 /*@}*/
screamer 0:c5e2f793b59a 982
screamer 0:c5e2f793b59a 983 /*
screamer 0:c5e2f793b59a 984 * Constants & macros for individual CMT_PPS bitfields
screamer 0:c5e2f793b59a 985 */
screamer 0:c5e2f793b59a 986
screamer 0:c5e2f793b59a 987 /*!
screamer 0:c5e2f793b59a 988 * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
screamer 0:c5e2f793b59a 989 *
screamer 0:c5e2f793b59a 990 * Divides the CMT clock to generate the Intermediate Frequency clock enable to
screamer 0:c5e2f793b59a 991 * the secondary prescaler.
screamer 0:c5e2f793b59a 992 *
screamer 0:c5e2f793b59a 993 * Values:
screamer 0:c5e2f793b59a 994 * - 0000 - Bus clock * 1
screamer 0:c5e2f793b59a 995 * - 0001 - Bus clock * 2
screamer 0:c5e2f793b59a 996 * - 0010 - Bus clock * 3
screamer 0:c5e2f793b59a 997 * - 0011 - Bus clock * 4
screamer 0:c5e2f793b59a 998 * - 0100 - Bus clock * 5
screamer 0:c5e2f793b59a 999 * - 0101 - Bus clock * 6
screamer 0:c5e2f793b59a 1000 * - 0110 - Bus clock * 7
screamer 0:c5e2f793b59a 1001 * - 0111 - Bus clock * 8
screamer 0:c5e2f793b59a 1002 * - 1000 - Bus clock * 9
screamer 0:c5e2f793b59a 1003 * - 1001 - Bus clock * 10
screamer 0:c5e2f793b59a 1004 * - 1010 - Bus clock * 11
screamer 0:c5e2f793b59a 1005 * - 1011 - Bus clock * 12
screamer 0:c5e2f793b59a 1006 * - 1100 - Bus clock * 13
screamer 0:c5e2f793b59a 1007 * - 1101 - Bus clock * 14
screamer 0:c5e2f793b59a 1008 * - 1110 - Bus clock * 15
screamer 0:c5e2f793b59a 1009 * - 1111 - Bus clock * 16
screamer 0:c5e2f793b59a 1010 */
screamer 0:c5e2f793b59a 1011 /*@{*/
screamer 0:c5e2f793b59a 1012 #define BP_CMT_PPS_PPSDIV (0U) /*!< Bit position for CMT_PPS_PPSDIV. */
screamer 0:c5e2f793b59a 1013 #define BM_CMT_PPS_PPSDIV (0x0FU) /*!< Bit mask for CMT_PPS_PPSDIV. */
screamer 0:c5e2f793b59a 1014 #define BS_CMT_PPS_PPSDIV (4U) /*!< Bit field size in bits for CMT_PPS_PPSDIV. */
screamer 0:c5e2f793b59a 1015
screamer 0:c5e2f793b59a 1016 /*! @brief Read current value of the CMT_PPS_PPSDIV field. */
screamer 0:c5e2f793b59a 1017 #define BR_CMT_PPS_PPSDIV(x) (HW_CMT_PPS(x).B.PPSDIV)
screamer 0:c5e2f793b59a 1018
screamer 0:c5e2f793b59a 1019 /*! @brief Format value for bitfield CMT_PPS_PPSDIV. */
screamer 0:c5e2f793b59a 1020 #define BF_CMT_PPS_PPSDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_PPS_PPSDIV) & BM_CMT_PPS_PPSDIV)
screamer 0:c5e2f793b59a 1021
screamer 0:c5e2f793b59a 1022 /*! @brief Set the PPSDIV field to a new value. */
screamer 0:c5e2f793b59a 1023 #define BW_CMT_PPS_PPSDIV(x, v) (HW_CMT_PPS_WR(x, (HW_CMT_PPS_RD(x) & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
screamer 0:c5e2f793b59a 1024 /*@}*/
screamer 0:c5e2f793b59a 1025
screamer 0:c5e2f793b59a 1026 /*******************************************************************************
screamer 0:c5e2f793b59a 1027 * HW_CMT_DMA - CMT Direct Memory Access Register
screamer 0:c5e2f793b59a 1028 ******************************************************************************/
screamer 0:c5e2f793b59a 1029
screamer 0:c5e2f793b59a 1030 /*!
screamer 0:c5e2f793b59a 1031 * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
screamer 0:c5e2f793b59a 1032 *
screamer 0:c5e2f793b59a 1033 * Reset value: 0x00U
screamer 0:c5e2f793b59a 1034 *
screamer 0:c5e2f793b59a 1035 * This register is used to enable/disable direct memory access (DMA).
screamer 0:c5e2f793b59a 1036 */
screamer 0:c5e2f793b59a 1037 typedef union _hw_cmt_dma
screamer 0:c5e2f793b59a 1038 {
screamer 0:c5e2f793b59a 1039 uint8_t U;
screamer 0:c5e2f793b59a 1040 struct _hw_cmt_dma_bitfields
screamer 0:c5e2f793b59a 1041 {
screamer 0:c5e2f793b59a 1042 uint8_t DMA : 1; /*!< [0] DMA Enable */
screamer 0:c5e2f793b59a 1043 uint8_t RESERVED0 : 7; /*!< [7:1] */
screamer 0:c5e2f793b59a 1044 } B;
screamer 0:c5e2f793b59a 1045 } hw_cmt_dma_t;
screamer 0:c5e2f793b59a 1046
screamer 0:c5e2f793b59a 1047 /*!
screamer 0:c5e2f793b59a 1048 * @name Constants and macros for entire CMT_DMA register
screamer 0:c5e2f793b59a 1049 */
screamer 0:c5e2f793b59a 1050 /*@{*/
screamer 0:c5e2f793b59a 1051 #define HW_CMT_DMA_ADDR(x) ((x) + 0xBU)
screamer 0:c5e2f793b59a 1052
screamer 0:c5e2f793b59a 1053 #define HW_CMT_DMA(x) (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR(x))
screamer 0:c5e2f793b59a 1054 #define HW_CMT_DMA_RD(x) (HW_CMT_DMA(x).U)
screamer 0:c5e2f793b59a 1055 #define HW_CMT_DMA_WR(x, v) (HW_CMT_DMA(x).U = (v))
screamer 0:c5e2f793b59a 1056 #define HW_CMT_DMA_SET(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) | (v)))
screamer 0:c5e2f793b59a 1057 #define HW_CMT_DMA_CLR(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1058 #define HW_CMT_DMA_TOG(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1059 /*@}*/
screamer 0:c5e2f793b59a 1060
screamer 0:c5e2f793b59a 1061 /*
screamer 0:c5e2f793b59a 1062 * Constants & macros for individual CMT_DMA bitfields
screamer 0:c5e2f793b59a 1063 */
screamer 0:c5e2f793b59a 1064
screamer 0:c5e2f793b59a 1065 /*!
screamer 0:c5e2f793b59a 1066 * @name Register CMT_DMA, field DMA[0] (RW)
screamer 0:c5e2f793b59a 1067 *
screamer 0:c5e2f793b59a 1068 * Enables the DMA protocol.
screamer 0:c5e2f793b59a 1069 *
screamer 0:c5e2f793b59a 1070 * Values:
screamer 0:c5e2f793b59a 1071 * - 0 - DMA transfer request and done are disabled.
screamer 0:c5e2f793b59a 1072 * - 1 - DMA transfer request and done are enabled.
screamer 0:c5e2f793b59a 1073 */
screamer 0:c5e2f793b59a 1074 /*@{*/
screamer 0:c5e2f793b59a 1075 #define BP_CMT_DMA_DMA (0U) /*!< Bit position for CMT_DMA_DMA. */
screamer 0:c5e2f793b59a 1076 #define BM_CMT_DMA_DMA (0x01U) /*!< Bit mask for CMT_DMA_DMA. */
screamer 0:c5e2f793b59a 1077 #define BS_CMT_DMA_DMA (1U) /*!< Bit field size in bits for CMT_DMA_DMA. */
screamer 0:c5e2f793b59a 1078
screamer 0:c5e2f793b59a 1079 /*! @brief Read current value of the CMT_DMA_DMA field. */
screamer 0:c5e2f793b59a 1080 #define BR_CMT_DMA_DMA(x) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA))
screamer 0:c5e2f793b59a 1081
screamer 0:c5e2f793b59a 1082 /*! @brief Format value for bitfield CMT_DMA_DMA. */
screamer 0:c5e2f793b59a 1083 #define BF_CMT_DMA_DMA(v) ((uint8_t)((uint8_t)(v) << BP_CMT_DMA_DMA) & BM_CMT_DMA_DMA)
screamer 0:c5e2f793b59a 1084
screamer 0:c5e2f793b59a 1085 /*! @brief Set the DMA field to a new value. */
screamer 0:c5e2f793b59a 1086 #define BW_CMT_DMA_DMA(x, v) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA) = (v))
screamer 0:c5e2f793b59a 1087 /*@}*/
screamer 0:c5e2f793b59a 1088
screamer 0:c5e2f793b59a 1089 /*******************************************************************************
screamer 0:c5e2f793b59a 1090 * hw_cmt_t - module struct
screamer 0:c5e2f793b59a 1091 ******************************************************************************/
screamer 0:c5e2f793b59a 1092 /*!
screamer 0:c5e2f793b59a 1093 * @brief All CMT module registers.
screamer 0:c5e2f793b59a 1094 */
screamer 0:c5e2f793b59a 1095 #pragma pack(1)
screamer 0:c5e2f793b59a 1096 typedef struct _hw_cmt
screamer 0:c5e2f793b59a 1097 {
screamer 0:c5e2f793b59a 1098 __IO hw_cmt_cgh1_t CGH1; /*!< [0x0] CMT Carrier Generator High Data Register 1 */
screamer 0:c5e2f793b59a 1099 __IO hw_cmt_cgl1_t CGL1; /*!< [0x1] CMT Carrier Generator Low Data Register 1 */
screamer 0:c5e2f793b59a 1100 __IO hw_cmt_cgh2_t CGH2; /*!< [0x2] CMT Carrier Generator High Data Register 2 */
screamer 0:c5e2f793b59a 1101 __IO hw_cmt_cgl2_t CGL2; /*!< [0x3] CMT Carrier Generator Low Data Register 2 */
screamer 0:c5e2f793b59a 1102 __IO hw_cmt_oc_t OC; /*!< [0x4] CMT Output Control Register */
screamer 0:c5e2f793b59a 1103 __IO hw_cmt_msc_t MSC; /*!< [0x5] CMT Modulator Status and Control Register */
screamer 0:c5e2f793b59a 1104 __IO hw_cmt_cmd1_t CMD1; /*!< [0x6] CMT Modulator Data Register Mark High */
screamer 0:c5e2f793b59a 1105 __IO hw_cmt_cmd2_t CMD2; /*!< [0x7] CMT Modulator Data Register Mark Low */
screamer 0:c5e2f793b59a 1106 __IO hw_cmt_cmd3_t CMD3; /*!< [0x8] CMT Modulator Data Register Space High */
screamer 0:c5e2f793b59a 1107 __IO hw_cmt_cmd4_t CMD4; /*!< [0x9] CMT Modulator Data Register Space Low */
screamer 0:c5e2f793b59a 1108 __IO hw_cmt_pps_t PPS; /*!< [0xA] CMT Primary Prescaler Register */
screamer 0:c5e2f793b59a 1109 __IO hw_cmt_dma_t DMA; /*!< [0xB] CMT Direct Memory Access Register */
screamer 0:c5e2f793b59a 1110 } hw_cmt_t;
screamer 0:c5e2f793b59a 1111 #pragma pack()
screamer 0:c5e2f793b59a 1112
screamer 0:c5e2f793b59a 1113 /*! @brief Macro to access all CMT registers. */
screamer 0:c5e2f793b59a 1114 /*! @param x CMT module instance base address. */
screamer 0:c5e2f793b59a 1115 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
screamer 0:c5e2f793b59a 1116 * use the '&' operator, like <code>&HW_CMT(CMT_BASE)</code>. */
screamer 0:c5e2f793b59a 1117 #define HW_CMT(x) (*(hw_cmt_t *)(x))
screamer 0:c5e2f793b59a 1118
screamer 0:c5e2f793b59a 1119 #endif /* __HW_CMT_REGISTERS_H__ */
screamer 0:c5e2f793b59a 1120 /* EOF */