Morpheus / target-mcu-k64f

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of target-mcu-k64f by -deleted-

hal/device/MK64F12/fsl_bitaccess.h@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 4 ** Build: b140604
screamer 0:c5e2f793b59a 5 **
screamer 0:c5e2f793b59a 6 ** Abstract:
screamer 0:c5e2f793b59a 7 ** Register bit field access macros.
screamer 0:c5e2f793b59a 8 **
screamer 0:c5e2f793b59a 9 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 10 ** All rights reserved.
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 13 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 16 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 17 **
screamer 0:c5e2f793b59a 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 19 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 20 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 21 **
screamer 0:c5e2f793b59a 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 23 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 24 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 25 **
screamer 0:c5e2f793b59a 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 36 **
screamer 0:c5e2f793b59a 37 ** http: www.freescale.com
screamer 0:c5e2f793b59a 38 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 39 **
screamer 0:c5e2f793b59a 40 ** Revisions:
screamer 0:c5e2f793b59a 41 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 42 ** Initial version.
screamer 0:c5e2f793b59a 43 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 44 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 45 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 46 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 47 ** System initialization updated.
screamer 0:c5e2f793b59a 48 ** MCG - registers updated.
screamer 0:c5e2f793b59a 49 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 50 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 51 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 52 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 53 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 54 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 55 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 56 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 57 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 58 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 59 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 60 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 61 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 62 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 63 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 64 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 65 **
screamer 0:c5e2f793b59a 66 ** ###################################################################
screamer 0:c5e2f793b59a 67 */
screamer 0:c5e2f793b59a 68
screamer 0:c5e2f793b59a 69
screamer 0:c5e2f793b59a 70 #ifndef _FSL_BITACCESS_H
screamer 0:c5e2f793b59a 71 #define _FSL_BITACCESS_H 1
screamer 0:c5e2f793b59a 72
screamer 0:c5e2f793b59a 73 #include <stdint.h>
screamer 0:c5e2f793b59a 74 #include <stdlib.h>
screamer 0:c5e2f793b59a 75
screamer 0:c5e2f793b59a 76 /**
screamer 0:c5e2f793b59a 77 * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
screamer 0:c5e2f793b59a 78 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
screamer 0:c5e2f793b59a 79 * @param Reg Register to access.
screamer 0:c5e2f793b59a 80 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 81 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 82 */
screamer 0:c5e2f793b59a 83 #define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
screamer 0:c5e2f793b59a 84
screamer 0:c5e2f793b59a 85 /**
screamer 0:c5e2f793b59a 86 * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
screamer 0:c5e2f793b59a 87 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
screamer 0:c5e2f793b59a 88 * @param Reg Register to access.
screamer 0:c5e2f793b59a 89 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 90 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 91 */
screamer 0:c5e2f793b59a 92 #define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
screamer 0:c5e2f793b59a 93
screamer 0:c5e2f793b59a 94 /**
screamer 0:c5e2f793b59a 95 * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
screamer 0:c5e2f793b59a 96 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
screamer 0:c5e2f793b59a 97 * @param Reg Register to access.
screamer 0:c5e2f793b59a 98 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 99 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 100 */
screamer 0:c5e2f793b59a 101 #define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
screamer 0:c5e2f793b59a 102
screamer 0:c5e2f793b59a 103 /*
screamer 0:c5e2f793b59a 104 * Macros for single instance registers
screamer 0:c5e2f793b59a 105 */
screamer 0:c5e2f793b59a 106
screamer 0:c5e2f793b59a 107 #define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
screamer 0:c5e2f793b59a 108 #define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
screamer 0:c5e2f793b59a 109 #define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
screamer 0:c5e2f793b59a 110
screamer 0:c5e2f793b59a 111 #define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 112 #define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 113 #define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 114
screamer 0:c5e2f793b59a 115 #define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
screamer 0:c5e2f793b59a 116 #define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
screamer 0:c5e2f793b59a 117
screamer 0:c5e2f793b59a 118 #define BF_RD(reg, field) HW_##reg.B.field
screamer 0:c5e2f793b59a 119 #define BF_WR(reg, field, v) BW_##reg##_##field(v)
screamer 0:c5e2f793b59a 120
screamer 0:c5e2f793b59a 121 #define BF_CS1(reg, f1, v1) \
screamer 0:c5e2f793b59a 122 (HW_##reg##_CLR(BM_##reg##_##f1), \
screamer 0:c5e2f793b59a 123 HW_##reg##_SET(BF_##reg##_##f1(v1)))
screamer 0:c5e2f793b59a 124
screamer 0:c5e2f793b59a 125 #define BF_CS2(reg, f1, v1, f2, v2) \
screamer 0:c5e2f793b59a 126 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 127 BM_##reg##_##f2), \
screamer 0:c5e2f793b59a 128 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 129 BF_##reg##_##f2(v2)))
screamer 0:c5e2f793b59a 130
screamer 0:c5e2f793b59a 131 #define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
screamer 0:c5e2f793b59a 132 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 133 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 134 BM_##reg##_##f3), \
screamer 0:c5e2f793b59a 135 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 136 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 137 BF_##reg##_##f3(v3)))
screamer 0:c5e2f793b59a 138
screamer 0:c5e2f793b59a 139 #define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
screamer 0:c5e2f793b59a 140 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 141 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 142 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 143 BM_##reg##_##f4), \
screamer 0:c5e2f793b59a 144 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 145 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 146 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 147 BF_##reg##_##f4(v4)))
screamer 0:c5e2f793b59a 148
screamer 0:c5e2f793b59a 149 #define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
screamer 0:c5e2f793b59a 150 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 151 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 152 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 153 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 154 BM_##reg##_##f5), \
screamer 0:c5e2f793b59a 155 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 156 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 157 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 158 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 159 BF_##reg##_##f5(v5)))
screamer 0:c5e2f793b59a 160
screamer 0:c5e2f793b59a 161 #define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
screamer 0:c5e2f793b59a 162 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 163 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 164 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 165 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 166 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 167 BM_##reg##_##f6), \
screamer 0:c5e2f793b59a 168 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 169 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 170 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 171 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 172 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 173 BF_##reg##_##f6(v6)))
screamer 0:c5e2f793b59a 174
screamer 0:c5e2f793b59a 175 #define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
screamer 0:c5e2f793b59a 176 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 177 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 178 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 179 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 180 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 181 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 182 BM_##reg##_##f7), \
screamer 0:c5e2f793b59a 183 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 184 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 185 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 186 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 187 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 188 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 189 BF_##reg##_##f7(v7)))
screamer 0:c5e2f793b59a 190
screamer 0:c5e2f793b59a 191 #define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
screamer 0:c5e2f793b59a 192 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 193 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 194 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 195 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 196 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 197 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 198 BM_##reg##_##f7 | \
screamer 0:c5e2f793b59a 199 BM_##reg##_##f8), \
screamer 0:c5e2f793b59a 200 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 201 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 202 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 203 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 204 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 205 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 206 BF_##reg##_##f7(v7) | \
screamer 0:c5e2f793b59a 207 BF_##reg##_##f8(v8)))
screamer 0:c5e2f793b59a 208
screamer 0:c5e2f793b59a 209 /*
screamer 0:c5e2f793b59a 210 * Macros for multiple instance registers
screamer 0:c5e2f793b59a 211 */
screamer 0:c5e2f793b59a 212
screamer 0:c5e2f793b59a 213 #define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 214 #define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 215 #define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 216
screamer 0:c5e2f793b59a 217 #define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 218 #define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 219 #define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 220
screamer 0:c5e2f793b59a 221 #define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
screamer 0:c5e2f793b59a 222 #define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
screamer 0:c5e2f793b59a 223
screamer 0:c5e2f793b59a 224 #define BF_RDn(reg, n, field) HW_##reg(n).B.field
screamer 0:c5e2f793b59a 225 #define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
screamer 0:c5e2f793b59a 226
screamer 0:c5e2f793b59a 227 #define BF_CS1n(reg, n, f1, v1) \
screamer 0:c5e2f793b59a 228 (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
screamer 0:c5e2f793b59a 229 HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
screamer 0:c5e2f793b59a 230
screamer 0:c5e2f793b59a 231 #define BF_CS2n(reg, n, f1, v1, f2, v2) \
screamer 0:c5e2f793b59a 232 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 233 BM_##reg##_##f2)), \
screamer 0:c5e2f793b59a 234 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 235 BF_##reg##_##f2(v2))))
screamer 0:c5e2f793b59a 236
screamer 0:c5e2f793b59a 237 #define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
screamer 0:c5e2f793b59a 238 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 239 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 240 BM_##reg##_##f3)), \
screamer 0:c5e2f793b59a 241 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 242 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 243 BF_##reg##_##f3(v3))))
screamer 0:c5e2f793b59a 244
screamer 0:c5e2f793b59a 245 #define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
screamer 0:c5e2f793b59a 246 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 247 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 248 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 249 BM_##reg##_##f4)), \
screamer 0:c5e2f793b59a 250 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 251 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 252 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 253 BF_##reg##_##f4(v4))))
screamer 0:c5e2f793b59a 254
screamer 0:c5e2f793b59a 255 #define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
screamer 0:c5e2f793b59a 256 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 257 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 258 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 259 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 260 BM_##reg##_##f5)), \
screamer 0:c5e2f793b59a 261 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 262 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 263 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 264 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 265 BF_##reg##_##f5(v5))))
screamer 0:c5e2f793b59a 266
screamer 0:c5e2f793b59a 267 #define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
screamer 0:c5e2f793b59a 268 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 269 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 270 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 271 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 272 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 273 BM_##reg##_##f6)), \
screamer 0:c5e2f793b59a 274 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 275 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 276 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 277 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 278 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 279 BF_##reg##_##f6(v6))))
screamer 0:c5e2f793b59a 280
screamer 0:c5e2f793b59a 281 #define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
screamer 0:c5e2f793b59a 282 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 283 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 284 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 285 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 286 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 287 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 288 BM_##reg##_##f7)), \
screamer 0:c5e2f793b59a 289 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 290 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 291 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 292 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 293 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 294 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 295 BF_##reg##_##f7(v7))))
screamer 0:c5e2f793b59a 296
screamer 0:c5e2f793b59a 297 #define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
screamer 0:c5e2f793b59a 298 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 299 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 300 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 301 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 302 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 303 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 304 BM_##reg##_##f7 | \
screamer 0:c5e2f793b59a 305 BM_##reg##_##f8)), \
screamer 0:c5e2f793b59a 306 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 307 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 308 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 309 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 310 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 311 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 312 BF_##reg##_##f7(v7) | \
screamer 0:c5e2f793b59a 313 BF_##reg##_##f8(v8))))
screamer 0:c5e2f793b59a 314
screamer 0:c5e2f793b59a 315 /*
screamer 0:c5e2f793b59a 316 * Macros for single instance MULTI-BLOCK registers
screamer 0:c5e2f793b59a 317 */
screamer 0:c5e2f793b59a 318
screamer 0:c5e2f793b59a 319 #define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
screamer 0:c5e2f793b59a 320 #define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
screamer 0:c5e2f793b59a 321 #define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
screamer 0:c5e2f793b59a 322
screamer 0:c5e2f793b59a 323 #define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 324 #define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 325 #define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 326
screamer 0:c5e2f793b59a 327 #define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
screamer 0:c5e2f793b59a 328 #define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
screamer 0:c5e2f793b59a 329
screamer 0:c5e2f793b59a 330 #define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
screamer 0:c5e2f793b59a 331 #define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
screamer 0:c5e2f793b59a 332
screamer 0:c5e2f793b59a 333 #define BFn_CS1(reg, blk, f1, v1) \
screamer 0:c5e2f793b59a 334 (HW_##reg##_CLR(blk, BM_##reg##_##f1), \
screamer 0:c5e2f793b59a 335 HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
screamer 0:c5e2f793b59a 336
screamer 0:c5e2f793b59a 337 #define BFn_CS2(reg, blk, f1, v1, f2, v2) \
screamer 0:c5e2f793b59a 338 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 339 BM_##reg##_##f2), \
screamer 0:c5e2f793b59a 340 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 341 BF_##reg##_##f2(v2)))
screamer 0:c5e2f793b59a 342
screamer 0:c5e2f793b59a 343 #define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
screamer 0:c5e2f793b59a 344 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 345 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 346 BM_##reg##_##f3), \
screamer 0:c5e2f793b59a 347 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 348 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 349 BF_##reg##_##f3(v3)))
screamer 0:c5e2f793b59a 350
screamer 0:c5e2f793b59a 351 #define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
screamer 0:c5e2f793b59a 352 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 353 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 354 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 355 BM_##reg##_##f4), \
screamer 0:c5e2f793b59a 356 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 357 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 358 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 359 BF_##reg##_##f4(v4)))
screamer 0:c5e2f793b59a 360
screamer 0:c5e2f793b59a 361 #define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
screamer 0:c5e2f793b59a 362 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 363 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 364 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 365 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 366 BM_##reg##_##f5), \
screamer 0:c5e2f793b59a 367 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 368 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 369 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 370 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 371 BF_##reg##_##f5(v5)))
screamer 0:c5e2f793b59a 372
screamer 0:c5e2f793b59a 373 #define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
screamer 0:c5e2f793b59a 374 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 375 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 376 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 377 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 378 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 379 BM_##reg##_##f6), \
screamer 0:c5e2f793b59a 380 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 381 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 382 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 383 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 384 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 385 BF_##reg##_##f6(v6)))
screamer 0:c5e2f793b59a 386
screamer 0:c5e2f793b59a 387 #define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
screamer 0:c5e2f793b59a 388 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 389 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 390 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 391 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 392 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 393 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 394 BM_##reg##_##f7), \
screamer 0:c5e2f793b59a 395 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 396 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 397 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 398 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 399 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 400 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 401 BF_##reg##_##f7(v7)))
screamer 0:c5e2f793b59a 402
screamer 0:c5e2f793b59a 403 #define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
screamer 0:c5e2f793b59a 404 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 405 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 406 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 407 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 408 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 409 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 410 BM_##reg##_##f7 | \
screamer 0:c5e2f793b59a 411 BM_##reg##_##f8), \
screamer 0:c5e2f793b59a 412 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 413 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 414 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 415 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 416 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 417 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 418 BF_##reg##_##f7(v7) | \
screamer 0:c5e2f793b59a 419 BF_##reg##_##f8(v8)))
screamer 0:c5e2f793b59a 420
screamer 0:c5e2f793b59a 421 /*
screamer 0:c5e2f793b59a 422 * Macros for MULTI-BLOCK multiple instance registers
screamer 0:c5e2f793b59a 423 */
screamer 0:c5e2f793b59a 424
screamer 0:c5e2f793b59a 425 #define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 426 #define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 427 #define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 428
screamer 0:c5e2f793b59a 429 #define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 430 #define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 431 #define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 432
screamer 0:c5e2f793b59a 433 #define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
screamer 0:c5e2f793b59a 434 #define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
screamer 0:c5e2f793b59a 435
screamer 0:c5e2f793b59a 436 #define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
screamer 0:c5e2f793b59a 437 #define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
screamer 0:c5e2f793b59a 438
screamer 0:c5e2f793b59a 439 #define BFn_CS1n(reg, blk, n, f1, v1) \
screamer 0:c5e2f793b59a 440 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
screamer 0:c5e2f793b59a 441 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
screamer 0:c5e2f793b59a 442
screamer 0:c5e2f793b59a 443 #define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
screamer 0:c5e2f793b59a 444 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 445 BM_##reg##_##f2)), \
screamer 0:c5e2f793b59a 446 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 447 BF_##reg##_##f2(v2))))
screamer 0:c5e2f793b59a 448
screamer 0:c5e2f793b59a 449 #define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
screamer 0:c5e2f793b59a 450 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 451 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 452 BM_##reg##_##f3)), \
screamer 0:c5e2f793b59a 453 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 454 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 455 BF_##reg##_##f3(v3))))
screamer 0:c5e2f793b59a 456
screamer 0:c5e2f793b59a 457 #define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
screamer 0:c5e2f793b59a 458 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 459 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 460 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 461 BM_##reg##_##f4)), \
screamer 0:c5e2f793b59a 462 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 463 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 464 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 465 BF_##reg##_##f4(v4))))
screamer 0:c5e2f793b59a 466
screamer 0:c5e2f793b59a 467 #define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
screamer 0:c5e2f793b59a 468 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 469 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 470 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 471 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 472 BM_##reg##_##f5)), \
screamer 0:c5e2f793b59a 473 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 474 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 475 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 476 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 477 BF_##reg##_##f5(v5))))
screamer 0:c5e2f793b59a 478
screamer 0:c5e2f793b59a 479 #define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
screamer 0:c5e2f793b59a 480 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 481 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 482 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 483 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 484 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 485 BM_##reg##_##f6)), \
screamer 0:c5e2f793b59a 486 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 487 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 488 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 489 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 490 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 491 BF_##reg##_##f6(v6))))
screamer 0:c5e2f793b59a 492
screamer 0:c5e2f793b59a 493 #define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
screamer 0:c5e2f793b59a 494 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 495 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 496 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 497 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 498 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 499 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 500 BM_##reg##_##f7)), \
screamer 0:c5e2f793b59a 501 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 502 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 503 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 504 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 505 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 506 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 507 BF_##reg##_##f7(v7))))
screamer 0:c5e2f793b59a 508
screamer 0:c5e2f793b59a 509 #define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
screamer 0:c5e2f793b59a 510 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 511 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 512 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 513 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 514 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 515 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 516 BM_##reg##_##f7 | \
screamer 0:c5e2f793b59a 517 BM_##reg##_##f8)), \
screamer 0:c5e2f793b59a 518 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 519 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 520 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 521 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 522 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 523 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 524 BF_##reg##_##f7(v7) | \
screamer 0:c5e2f793b59a 525 BF_##reg##_##f8(v8))))
screamer 0:c5e2f793b59a 526
screamer 0:c5e2f793b59a 527 #endif /* _FSL_BITACCESS_H */
screamer 0:c5e2f793b59a 528
screamer 0:c5e2f793b59a 529 /******************************************************************************/