Morpheus / target-mcu-k64f

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cmsis/system_MK64F12.h@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Processor: MK64FN1M0VMD12
screamer 0:c5e2f793b59a 4 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 5 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 6 ** GNU C Compiler
screamer 0:c5e2f793b59a 7 ** GNU C Compiler - CodeSourcery Sourcery G++
screamer 0:c5e2f793b59a 8 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 9 **
screamer 0:c5e2f793b59a 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 11 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 12 ** Build: b140611
screamer 0:c5e2f793b59a 13 **
screamer 0:c5e2f793b59a 14 ** Abstract:
screamer 0:c5e2f793b59a 15 ** Provides a system configuration function and a global variable that
screamer 0:c5e2f793b59a 16 ** contains the system frequency. It configures the device and initializes
screamer 0:c5e2f793b59a 17 ** the oscillator (PLL) that is part of the microcontroller device.
screamer 0:c5e2f793b59a 18 **
screamer 0:c5e2f793b59a 19 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 20 ** All rights reserved.
screamer 0:c5e2f793b59a 21 **
screamer 0:c5e2f793b59a 22 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 23 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 24 **
screamer 0:c5e2f793b59a 25 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 26 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 27 **
screamer 0:c5e2f793b59a 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 29 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 30 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 31 **
screamer 0:c5e2f793b59a 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 33 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 34 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 35 **
screamer 0:c5e2f793b59a 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 46 **
screamer 0:c5e2f793b59a 47 ** http: www.freescale.com
screamer 0:c5e2f793b59a 48 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 49 **
screamer 0:c5e2f793b59a 50 ** Revisions:
screamer 0:c5e2f793b59a 51 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 52 ** Initial version.
screamer 0:c5e2f793b59a 53 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 54 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 55 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 56 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 57 ** System initialization updated.
screamer 0:c5e2f793b59a 58 ** MCG - registers updated.
screamer 0:c5e2f793b59a 59 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 60 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 61 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 62 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 63 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 64 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 65 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 66 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 67 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 68 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 69 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 70 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 71 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 72 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 73 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 75 **
screamer 0:c5e2f793b59a 76 ** ###################################################################
screamer 0:c5e2f793b59a 77 */
screamer 0:c5e2f793b59a 78
screamer 0:c5e2f793b59a 79 /*!
screamer 0:c5e2f793b59a 80 * @file MK64F12
screamer 0:c5e2f793b59a 81 * @version 2.5
screamer 0:c5e2f793b59a 82 * @date 2014-02-10
screamer 0:c5e2f793b59a 83 * @brief Device specific configuration file for MK64F12 (header file)
screamer 0:c5e2f793b59a 84 *
screamer 0:c5e2f793b59a 85 * Provides a system configuration function and a global variable that contains
screamer 0:c5e2f793b59a 86 * the system frequency. It configures the device and initializes the oscillator
screamer 0:c5e2f793b59a 87 * (PLL) that is part of the microcontroller device.
screamer 0:c5e2f793b59a 88 */
screamer 0:c5e2f793b59a 89
screamer 0:c5e2f793b59a 90 #ifndef SYSTEM_MK64F12_H_
screamer 0:c5e2f793b59a 91 #define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
screamer 0:c5e2f793b59a 92
screamer 0:c5e2f793b59a 93 #ifdef __cplusplus
screamer 0:c5e2f793b59a 94 extern "C" {
screamer 0:c5e2f793b59a 95 #endif
screamer 0:c5e2f793b59a 96
screamer 0:c5e2f793b59a 97 #include <stdint.h>
screamer 0:c5e2f793b59a 98
screamer 0:c5e2f793b59a 99
screamer 0:c5e2f793b59a 100 #define DISABLE_WDOG 1
screamer 0:c5e2f793b59a 101
screamer 0:c5e2f793b59a 102 #ifndef CLOCK_SETUP
screamer 0:c5e2f793b59a 103 #define CLOCK_SETUP 4
screamer 0:c5e2f793b59a 104 #endif
screamer 0:c5e2f793b59a 105
screamer 0:c5e2f793b59a 106 /* MCG mode constants */
screamer 0:c5e2f793b59a 107
screamer 0:c5e2f793b59a 108 #define MCG_MODE_FEI 0U
screamer 0:c5e2f793b59a 109 #define MCG_MODE_FBI 1U
screamer 0:c5e2f793b59a 110 #define MCG_MODE_BLPI 2U
screamer 0:c5e2f793b59a 111 #define MCG_MODE_FEE 3U
screamer 0:c5e2f793b59a 112 #define MCG_MODE_FBE 4U
screamer 0:c5e2f793b59a 113 #define MCG_MODE_BLPE 5U
screamer 0:c5e2f793b59a 114 #define MCG_MODE_PBE 6U
screamer 0:c5e2f793b59a 115 #define MCG_MODE_PEE 7U
screamer 0:c5e2f793b59a 116
screamer 0:c5e2f793b59a 117 /* Predefined clock setups
screamer 0:c5e2f793b59a 118 0 ... Default part configuration
screamer 0:c5e2f793b59a 119 Multipurpose Clock Generator (MCG) in FEI mode.
screamer 0:c5e2f793b59a 120 Reference clock source for MCG module: Slow internal reference clock
screamer 0:c5e2f793b59a 121 Core clock = 20.97152MHz
screamer 0:c5e2f793b59a 122 Bus clock = 20.97152MHz
screamer 0:c5e2f793b59a 123 1 ... Maximum achievable clock frequency configuration
screamer 0:c5e2f793b59a 124 Multipurpose Clock Generator (MCG) in PEE mode.
screamer 0:c5e2f793b59a 125 Reference clock source for MCG module: System oscillator 0 reference clock
screamer 0:c5e2f793b59a 126 Core clock = 120MHz
screamer 0:c5e2f793b59a 127 Bus clock = 60MHz
screamer 0:c5e2f793b59a 128 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
screamer 0:c5e2f793b59a 129 Multipurpose Clock Generator (MCG) in BLPI mode.
screamer 0:c5e2f793b59a 130 Reference clock source for MCG module: Fast internal reference clock
screamer 0:c5e2f793b59a 131 Core clock = 4MHz
screamer 0:c5e2f793b59a 132 Bus clock = 4MHz
screamer 0:c5e2f793b59a 133 3 ... Chip externally clocked, ready for Very Low Power Run mode.
screamer 0:c5e2f793b59a 134 Multipurpose Clock Generator (MCG) in BLPE mode.
screamer 0:c5e2f793b59a 135 Reference clock source for MCG module: RTC oscillator reference clock
screamer 0:c5e2f793b59a 136 Core clock = 0.032768MHz
screamer 0:c5e2f793b59a 137 Bus clock = 0.032768MHz
screamer 0:c5e2f793b59a 138 4 ... USB clock setup
screamer 0:c5e2f793b59a 139 Multipurpose Clock Generator (MCG) in PEE mode.
screamer 0:c5e2f793b59a 140 Reference clock source for MCG module: System oscillator 0 reference clock
screamer 0:c5e2f793b59a 141 Core clock = 120MHz
screamer 0:c5e2f793b59a 142 Bus clock = 60MHz
screamer 0:c5e2f793b59a 143 */
screamer 0:c5e2f793b59a 144
screamer 0:c5e2f793b59a 145 /* Define clock source values */
screamer 0:c5e2f793b59a 146
screamer 0:c5e2f793b59a 147 #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
screamer 0:c5e2f793b59a 148 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
screamer 0:c5e2f793b59a 149 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
screamer 0:c5e2f793b59a 150 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
screamer 0:c5e2f793b59a 151 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
screamer 0:c5e2f793b59a 152
screamer 0:c5e2f793b59a 153 /* RTC oscillator setting */
screamer 0:c5e2f793b59a 154 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
screamer 0:c5e2f793b59a 155 #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
screamer 0:c5e2f793b59a 156
screamer 0:c5e2f793b59a 157 /* Low power mode enable */
screamer 0:c5e2f793b59a 158 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
screamer 0:c5e2f793b59a 159 #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
screamer 0:c5e2f793b59a 160
screamer 0:c5e2f793b59a 161 /* Internal reference clock trim */
screamer 0:c5e2f793b59a 162 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
screamer 0:c5e2f793b59a 163 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
screamer 0:c5e2f793b59a 164 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
screamer 0:c5e2f793b59a 165 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
screamer 0:c5e2f793b59a 166
screamer 0:c5e2f793b59a 167 #if (CLOCK_SETUP == 0)
screamer 0:c5e2f793b59a 168 #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
screamer 0:c5e2f793b59a 169 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
screamer 0:c5e2f793b59a 170 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
screamer 0:c5e2f793b59a 171 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
screamer 0:c5e2f793b59a 172 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
screamer 0:c5e2f793b59a 173 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
screamer 0:c5e2f793b59a 174 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
screamer 0:c5e2f793b59a 175 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
screamer 0:c5e2f793b59a 176 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
screamer 0:c5e2f793b59a 177 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
screamer 0:c5e2f793b59a 178 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
screamer 0:c5e2f793b59a 179 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
screamer 0:c5e2f793b59a 180 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
screamer 0:c5e2f793b59a 181 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
screamer 0:c5e2f793b59a 182 /* MCG_C7: OSCSEL=0 */
screamer 0:c5e2f793b59a 183 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
screamer 0:c5e2f793b59a 184 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
screamer 0:c5e2f793b59a 185 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
screamer 0:c5e2f793b59a 186 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
screamer 0:c5e2f793b59a 187 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
screamer 0:c5e2f793b59a 188 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
screamer 0:c5e2f793b59a 189 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
screamer 0:c5e2f793b59a 190 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
screamer 0:c5e2f793b59a 191 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
screamer 0:c5e2f793b59a 192 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
screamer 0:c5e2f793b59a 193 #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
screamer 0:c5e2f793b59a 194 #elif (CLOCK_SETUP == 1)
screamer 0:c5e2f793b59a 195 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
screamer 0:c5e2f793b59a 196 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
screamer 0:c5e2f793b59a 197 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
screamer 0:c5e2f793b59a 198 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
screamer 0:c5e2f793b59a 199 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
screamer 0:c5e2f793b59a 200 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
screamer 0:c5e2f793b59a 201 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
screamer 0:c5e2f793b59a 202 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
screamer 0:c5e2f793b59a 203 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
screamer 0:c5e2f793b59a 204 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
screamer 0:c5e2f793b59a 205 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
screamer 0:c5e2f793b59a 206 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
screamer 0:c5e2f793b59a 207 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
screamer 0:c5e2f793b59a 208 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
screamer 0:c5e2f793b59a 209 /* MCG_C7: OSCSEL=0 */
screamer 0:c5e2f793b59a 210 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
screamer 0:c5e2f793b59a 211 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
screamer 0:c5e2f793b59a 212 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
screamer 0:c5e2f793b59a 213 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
screamer 0:c5e2f793b59a 214 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
screamer 0:c5e2f793b59a 215 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
screamer 0:c5e2f793b59a 216 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
screamer 0:c5e2f793b59a 217 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
screamer 0:c5e2f793b59a 218 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
screamer 0:c5e2f793b59a 219 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
screamer 0:c5e2f793b59a 220 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
screamer 0:c5e2f793b59a 221 #elif (CLOCK_SETUP == 2)
screamer 0:c5e2f793b59a 222 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
screamer 0:c5e2f793b59a 223 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
screamer 0:c5e2f793b59a 224 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
screamer 0:c5e2f793b59a 225 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
screamer 0:c5e2f793b59a 226 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
screamer 0:c5e2f793b59a 227 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
screamer 0:c5e2f793b59a 228 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
screamer 0:c5e2f793b59a 229 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
screamer 0:c5e2f793b59a 230 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
screamer 0:c5e2f793b59a 231 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
screamer 0:c5e2f793b59a 232 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
screamer 0:c5e2f793b59a 233 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
screamer 0:c5e2f793b59a 234 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
screamer 0:c5e2f793b59a 235 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
screamer 0:c5e2f793b59a 236 /* MCG_C7: OSCSEL=0 */
screamer 0:c5e2f793b59a 237 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
screamer 0:c5e2f793b59a 238 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
screamer 0:c5e2f793b59a 239 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
screamer 0:c5e2f793b59a 240 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
screamer 0:c5e2f793b59a 241 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
screamer 0:c5e2f793b59a 242 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
screamer 0:c5e2f793b59a 243 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
screamer 0:c5e2f793b59a 244 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
screamer 0:c5e2f793b59a 245 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
screamer 0:c5e2f793b59a 246 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
screamer 0:c5e2f793b59a 247 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
screamer 0:c5e2f793b59a 248 #elif (CLOCK_SETUP == 3)
screamer 0:c5e2f793b59a 249 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
screamer 0:c5e2f793b59a 250 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
screamer 0:c5e2f793b59a 251 /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
screamer 0:c5e2f793b59a 252 #define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */
screamer 0:c5e2f793b59a 253 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
screamer 0:c5e2f793b59a 254 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
screamer 0:c5e2f793b59a 255 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
screamer 0:c5e2f793b59a 256 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
screamer 0:c5e2f793b59a 257 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
screamer 0:c5e2f793b59a 258 #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
screamer 0:c5e2f793b59a 259 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
screamer 0:c5e2f793b59a 260 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
screamer 0:c5e2f793b59a 261 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
screamer 0:c5e2f793b59a 262 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
screamer 0:c5e2f793b59a 263 /* MCG_C7: OSCSEL=1 */
screamer 0:c5e2f793b59a 264 #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
screamer 0:c5e2f793b59a 265 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
screamer 0:c5e2f793b59a 266 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
screamer 0:c5e2f793b59a 267 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
screamer 0:c5e2f793b59a 268 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
screamer 0:c5e2f793b59a 269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
screamer 0:c5e2f793b59a 270 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
screamer 0:c5e2f793b59a 271 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
screamer 0:c5e2f793b59a 272 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
screamer 0:c5e2f793b59a 273 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
screamer 0:c5e2f793b59a 274 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
screamer 0:c5e2f793b59a 275 #elif (CLOCK_SETUP == 4)
screamer 0:c5e2f793b59a 276 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
screamer 0:c5e2f793b59a 277 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
screamer 0:c5e2f793b59a 278 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
screamer 0:c5e2f793b59a 279 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
screamer 0:c5e2f793b59a 280 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
screamer 0:c5e2f793b59a 281 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
screamer 0:c5e2f793b59a 282 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
screamer 0:c5e2f793b59a 283 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
screamer 0:c5e2f793b59a 284 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
screamer 0:c5e2f793b59a 285 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
screamer 0:c5e2f793b59a 286 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
screamer 0:c5e2f793b59a 287 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
screamer 0:c5e2f793b59a 288 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
screamer 0:c5e2f793b59a 289 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
screamer 0:c5e2f793b59a 290 /* MCG_C7: OSCSEL=0 */
screamer 0:c5e2f793b59a 291 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
screamer 0:c5e2f793b59a 292 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
screamer 0:c5e2f793b59a 293 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
screamer 0:c5e2f793b59a 294 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
screamer 0:c5e2f793b59a 295 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
screamer 0:c5e2f793b59a 296 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
screamer 0:c5e2f793b59a 297 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
screamer 0:c5e2f793b59a 298 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
screamer 0:c5e2f793b59a 299 #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
screamer 0:c5e2f793b59a 300 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
screamer 0:c5e2f793b59a 301 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
screamer 0:c5e2f793b59a 302 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
screamer 0:c5e2f793b59a 303 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
screamer 0:c5e2f793b59a 304 #endif
screamer 0:c5e2f793b59a 305
screamer 0:c5e2f793b59a 306 /**
screamer 0:c5e2f793b59a 307 * @brief System clock frequency (core clock)
screamer 0:c5e2f793b59a 308 *
screamer 0:c5e2f793b59a 309 * The system clock frequency supplied to the SysTick timer and the processor
screamer 0:c5e2f793b59a 310 * core clock. This variable can be used by the user application to setup the
screamer 0:c5e2f793b59a 311 * SysTick timer or configure other parameters. It may also be used by debugger to
screamer 0:c5e2f793b59a 312 * query the frequency of the debug timer or configure the trace clock speed
screamer 0:c5e2f793b59a 313 * SystemCoreClock is initialized with a correct predefined value.
screamer 0:c5e2f793b59a 314 */
screamer 0:c5e2f793b59a 315 extern uint32_t SystemCoreClock;
screamer 0:c5e2f793b59a 316
screamer 0:c5e2f793b59a 317 /**
screamer 0:c5e2f793b59a 318 * @brief Setup the microcontroller system.
screamer 0:c5e2f793b59a 319 *
screamer 0:c5e2f793b59a 320 * Typically this function configures the oscillator (PLL) that is part of the
screamer 0:c5e2f793b59a 321 * microcontroller device. For systems with variable clock speed it also updates
screamer 0:c5e2f793b59a 322 * the variable SystemCoreClock. SystemInit is called from startup_device file.
screamer 0:c5e2f793b59a 323 */
screamer 0:c5e2f793b59a 324 void SystemInit (void);
screamer 0:c5e2f793b59a 325
screamer 0:c5e2f793b59a 326 /**
screamer 0:c5e2f793b59a 327 * @brief Updates the SystemCoreClock variable.
screamer 0:c5e2f793b59a 328 *
screamer 0:c5e2f793b59a 329 * It must be called whenever the core clock is changed during program
screamer 0:c5e2f793b59a 330 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
screamer 0:c5e2f793b59a 331 * the current core clock.
screamer 0:c5e2f793b59a 332 */
screamer 0:c5e2f793b59a 333 void SystemCoreClockUpdate (void);
screamer 0:c5e2f793b59a 334
screamer 0:c5e2f793b59a 335 #ifdef __cplusplus
screamer 0:c5e2f793b59a 336 }
screamer 0:c5e2f793b59a 337 #endif
screamer 0:c5e2f793b59a 338
screamer 0:c5e2f793b59a 339 #endif /* #if !defined(SYSTEM_MK64F12_H_) */