Morpheus / target-mcu-k64f

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cmsis/system_MK64F12.c@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Processor: MK64FN1M0VMD12
screamer 0:c5e2f793b59a 4 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 5 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 6 ** GNU C Compiler
screamer 0:c5e2f793b59a 7 ** GNU C Compiler - CodeSourcery Sourcery G++
screamer 0:c5e2f793b59a 8 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 9 **
screamer 0:c5e2f793b59a 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 11 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 12 ** Build: b140611
screamer 0:c5e2f793b59a 13 **
screamer 0:c5e2f793b59a 14 ** Abstract:
screamer 0:c5e2f793b59a 15 ** Provides a system configuration function and a global variable that
screamer 0:c5e2f793b59a 16 ** contains the system frequency. It configures the device and initializes
screamer 0:c5e2f793b59a 17 ** the oscillator (PLL) that is part of the microcontroller device.
screamer 0:c5e2f793b59a 18 **
screamer 0:c5e2f793b59a 19 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 20 ** All rights reserved.
screamer 0:c5e2f793b59a 21 **
screamer 0:c5e2f793b59a 22 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 23 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 24 **
screamer 0:c5e2f793b59a 25 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 26 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 27 **
screamer 0:c5e2f793b59a 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 29 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 30 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 31 **
screamer 0:c5e2f793b59a 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 33 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 34 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 35 **
screamer 0:c5e2f793b59a 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 46 **
screamer 0:c5e2f793b59a 47 ** http: www.freescale.com
screamer 0:c5e2f793b59a 48 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 49 **
screamer 0:c5e2f793b59a 50 ** Revisions:
screamer 0:c5e2f793b59a 51 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 52 ** Initial version.
screamer 0:c5e2f793b59a 53 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 54 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 55 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 56 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 57 ** System initialization updated.
screamer 0:c5e2f793b59a 58 ** MCG - registers updated.
screamer 0:c5e2f793b59a 59 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 60 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 61 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 62 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 63 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 64 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 65 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 66 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 67 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 68 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 69 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 70 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 71 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 72 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 73 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
screamer 0:c5e2f793b59a 75 **
screamer 0:c5e2f793b59a 76 ** ###################################################################
screamer 0:c5e2f793b59a 77 */
screamer 0:c5e2f793b59a 78
screamer 0:c5e2f793b59a 79 /*!
screamer 0:c5e2f793b59a 80 * @file MK64F12
screamer 0:c5e2f793b59a 81 * @version 2.5
screamer 0:c5e2f793b59a 82 * @date 2014-02-10
screamer 0:c5e2f793b59a 83 * @brief Device specific configuration file for MK64F12 (implementation file)
screamer 0:c5e2f793b59a 84 *
screamer 0:c5e2f793b59a 85 * Provides a system configuration function and a global variable that contains
screamer 0:c5e2f793b59a 86 * the system frequency. It configures the device and initializes the oscillator
screamer 0:c5e2f793b59a 87 * (PLL) that is part of the microcontroller device.
screamer 0:c5e2f793b59a 88 */
screamer 0:c5e2f793b59a 89
screamer 0:c5e2f793b59a 90 #include <stdint.h>
screamer 0:c5e2f793b59a 91 #include "cmsis.h"
screamer 0:c5e2f793b59a 92
screamer 0:c5e2f793b59a 93
screamer 0:c5e2f793b59a 94
screamer 0:c5e2f793b59a 95 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 96 -- Core clock
screamer 0:c5e2f793b59a 97 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 98
screamer 0:c5e2f793b59a 99 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
screamer 0:c5e2f793b59a 100
screamer 0:c5e2f793b59a 101 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 102 -- SystemInit()
screamer 0:c5e2f793b59a 103 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 104
screamer 0:c5e2f793b59a 105 void SystemInit (void) {
screamer 0:c5e2f793b59a 106 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
screamer 0:c5e2f793b59a 107 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
screamer 0:c5e2f793b59a 108 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
screamer 0:c5e2f793b59a 109 #if (DISABLE_WDOG)
screamer 0:c5e2f793b59a 110 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
screamer 0:c5e2f793b59a 111 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
screamer 0:c5e2f793b59a 112 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
screamer 0:c5e2f793b59a 113 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
screamer 0:c5e2f793b59a 114 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
screamer 0:c5e2f793b59a 115 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
screamer 0:c5e2f793b59a 116 WDOG_STCTRLH_WAITEN_MASK |
screamer 0:c5e2f793b59a 117 WDOG_STCTRLH_STOPEN_MASK |
screamer 0:c5e2f793b59a 118 WDOG_STCTRLH_ALLOWUPDATE_MASK |
screamer 0:c5e2f793b59a 119 WDOG_STCTRLH_CLKSRC_MASK |
screamer 0:c5e2f793b59a 120 0x0100U;
screamer 0:c5e2f793b59a 121 #endif /* (DISABLE_WDOG) */
screamer 0:c5e2f793b59a 122 if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
screamer 0:c5e2f793b59a 123 {
screamer 0:c5e2f793b59a 124 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
screamer 0:c5e2f793b59a 125 {
screamer 0:c5e2f793b59a 126 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
screamer 0:c5e2f793b59a 127 }
screamer 0:c5e2f793b59a 128 } else {
screamer 0:c5e2f793b59a 129 #ifdef SYSTEM_RTC_CR_VALUE
screamer 0:c5e2f793b59a 130 SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
screamer 0:c5e2f793b59a 131 if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
screamer 0:c5e2f793b59a 132 RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
screamer 0:c5e2f793b59a 133 RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
screamer 0:c5e2f793b59a 134 RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
screamer 0:c5e2f793b59a 135 }
screamer 0:c5e2f793b59a 136 #endif
screamer 0:c5e2f793b59a 137 }
screamer 0:c5e2f793b59a 138
screamer 0:c5e2f793b59a 139 /* Power mode protection initialization */
screamer 0:c5e2f793b59a 140 #ifdef SYSTEM_SMC_PMPROT_VALUE
screamer 0:c5e2f793b59a 141 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
screamer 0:c5e2f793b59a 142 #endif
screamer 0:c5e2f793b59a 143
screamer 0:c5e2f793b59a 144 /* System clock initialization */
screamer 0:c5e2f793b59a 145 /* Internal reference clock trim initialization */
screamer 0:c5e2f793b59a 146 #if defined(SLOW_TRIM_ADDRESS)
screamer 0:c5e2f793b59a 147 if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
screamer 0:c5e2f793b59a 148 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
screamer 0:c5e2f793b59a 149 #endif /* defined(SLOW_TRIM_ADDRESS) */
screamer 0:c5e2f793b59a 150 #if defined(SLOW_FINE_TRIM_ADDRESS)
screamer 0:c5e2f793b59a 151 MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
screamer 0:c5e2f793b59a 152 #endif
screamer 0:c5e2f793b59a 153 #if defined(FAST_TRIM_ADDRESS)
screamer 0:c5e2f793b59a 154 MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
screamer 0:c5e2f793b59a 155 #endif
screamer 0:c5e2f793b59a 156 #if defined(FAST_FINE_TRIM_ADDRESS)
screamer 0:c5e2f793b59a 157 MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
screamer 0:c5e2f793b59a 158 #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
screamer 0:c5e2f793b59a 159 #if defined(SLOW_TRIM_ADDRESS)
screamer 0:c5e2f793b59a 160 }
screamer 0:c5e2f793b59a 161 #endif /* defined(SLOW_TRIM_ADDRESS) */
screamer 0:c5e2f793b59a 162
screamer 0:c5e2f793b59a 163 /* Set system prescalers and clock sources */
screamer 0:c5e2f793b59a 164 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
screamer 0:c5e2f793b59a 165 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
screamer 0:c5e2f793b59a 166 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
screamer 0:c5e2f793b59a 167 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
screamer 0:c5e2f793b59a 168 /* Set MCG and OSC */
screamer 0:c5e2f793b59a 169 #if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
screamer 0:c5e2f793b59a 170 /* SIM_SCGC5: PORTA=1 */
screamer 0:c5e2f793b59a 171 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
screamer 0:c5e2f793b59a 172 /* PORTA_PCR18: ISF=0,MUX=0 */
screamer 0:c5e2f793b59a 173 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
screamer 0:c5e2f793b59a 174 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
screamer 0:c5e2f793b59a 175 /* PORTA_PCR19: ISF=0,MUX=0 */
screamer 0:c5e2f793b59a 176 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
screamer 0:c5e2f793b59a 177 }
screamer 0:c5e2f793b59a 178 #endif
screamer 0:c5e2f793b59a 179 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
screamer 0:c5e2f793b59a 180 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
screamer 0:c5e2f793b59a 181 /* Check that the source of the FLL reference clock is the requested one. */
screamer 0:c5e2f793b59a 182 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
screamer 0:c5e2f793b59a 183 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
screamer 0:c5e2f793b59a 184 }
screamer 0:c5e2f793b59a 185 } else {
screamer 0:c5e2f793b59a 186 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
screamer 0:c5e2f793b59a 187 }
screamer 0:c5e2f793b59a 188 }
screamer 0:c5e2f793b59a 189 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
screamer 0:c5e2f793b59a 190 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
screamer 0:c5e2f793b59a 191 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
screamer 0:c5e2f793b59a 192 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
screamer 0:c5e2f793b59a 193 #if (MCG_MODE == MCG_MODE_BLPI)
screamer 0:c5e2f793b59a 194 /* BLPI specific */
screamer 0:c5e2f793b59a 195 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
screamer 0:c5e2f793b59a 196 #endif
screamer 0:c5e2f793b59a 197
screamer 0:c5e2f793b59a 198 #else /* MCG_MODE */
screamer 0:c5e2f793b59a 199 /* Set MCG and OSC */
screamer 0:c5e2f793b59a 200 #if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
screamer 0:c5e2f793b59a 201 /* SIM_SCGC5: PORTA=1 */
screamer 0:c5e2f793b59a 202 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
screamer 0:c5e2f793b59a 203 /* PORTA_PCR18: ISF=0,MUX=0 */
screamer 0:c5e2f793b59a 204 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
screamer 0:c5e2f793b59a 205 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
screamer 0:c5e2f793b59a 206 /* PORTA_PCR19: ISF=0,MUX=0 */
screamer 0:c5e2f793b59a 207 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
screamer 0:c5e2f793b59a 208 }
screamer 0:c5e2f793b59a 209 #endif
screamer 0:c5e2f793b59a 210 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
screamer 0:c5e2f793b59a 211 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
screamer 0:c5e2f793b59a 212 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
screamer 0:c5e2f793b59a 213 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
screamer 0:c5e2f793b59a 214 #if (MCG_MODE == MCG_MODE_PEE)
screamer 0:c5e2f793b59a 215 MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
screamer 0:c5e2f793b59a 216 #else
screamer 0:c5e2f793b59a 217 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
screamer 0:c5e2f793b59a 218 #endif
screamer 0:c5e2f793b59a 219 if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
screamer 0:c5e2f793b59a 220 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
screamer 0:c5e2f793b59a 221 }
screamer 0:c5e2f793b59a 222 }
screamer 0:c5e2f793b59a 223 /* Check that the source of the FLL reference clock is the requested one. */
screamer 0:c5e2f793b59a 224 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
screamer 0:c5e2f793b59a 225 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
screamer 0:c5e2f793b59a 226 }
screamer 0:c5e2f793b59a 227 } else {
screamer 0:c5e2f793b59a 228 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
screamer 0:c5e2f793b59a 229 }
screamer 0:c5e2f793b59a 230 }
screamer 0:c5e2f793b59a 231 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
screamer 0:c5e2f793b59a 232 #endif /* MCG_MODE */
screamer 0:c5e2f793b59a 233
screamer 0:c5e2f793b59a 234 /* Common for all MCG modes */
screamer 0:c5e2f793b59a 235
screamer 0:c5e2f793b59a 236 /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
screamer 0:c5e2f793b59a 237 MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
screamer 0:c5e2f793b59a 238 MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
screamer 0:c5e2f793b59a 239 if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
screamer 0:c5e2f793b59a 240 MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
screamer 0:c5e2f793b59a 241 }
screamer 0:c5e2f793b59a 242 /* BLPE, PEE and PBE MCG mode specific */
screamer 0:c5e2f793b59a 243
screamer 0:c5e2f793b59a 244 #if (MCG_MODE == MCG_MODE_BLPE)
screamer 0:c5e2f793b59a 245 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
screamer 0:c5e2f793b59a 246 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
screamer 0:c5e2f793b59a 247 MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
screamer 0:c5e2f793b59a 248 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
screamer 0:c5e2f793b59a 249 }
screamer 0:c5e2f793b59a 250 #if (MCG_MODE == MCG_MODE_PEE)
screamer 0:c5e2f793b59a 251 MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
screamer 0:c5e2f793b59a 252 #endif
screamer 0:c5e2f793b59a 253 #endif
screamer 0:c5e2f793b59a 254 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
screamer 0:c5e2f793b59a 255 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
screamer 0:c5e2f793b59a 256 }
screamer 0:c5e2f793b59a 257 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
screamer 0:c5e2f793b59a 258 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
screamer 0:c5e2f793b59a 259 }
screamer 0:c5e2f793b59a 260 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
screamer 0:c5e2f793b59a 261 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
screamer 0:c5e2f793b59a 262 }
screamer 0:c5e2f793b59a 263 #elif (MCG_MODE == MCG_MODE_PEE)
screamer 0:c5e2f793b59a 264 while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
screamer 0:c5e2f793b59a 265 }
screamer 0:c5e2f793b59a 266 #endif
screamer 0:c5e2f793b59a 267 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
screamer 0:c5e2f793b59a 268 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
screamer 0:c5e2f793b59a 269 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
screamer 0:c5e2f793b59a 270 }
screamer 0:c5e2f793b59a 271 #endif
screamer 0:c5e2f793b59a 272
screamer 0:c5e2f793b59a 273 #if defined(SYSTEM_SIM_CLKDIV2_VALUE)
screamer 0:c5e2f793b59a 274 SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
screamer 0:c5e2f793b59a 275 #endif
screamer 0:c5e2f793b59a 276
screamer 0:c5e2f793b59a 277 /* PLL loss of lock interrupt request initialization */
screamer 0:c5e2f793b59a 278 if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
screamer 0:c5e2f793b59a 279 NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
screamer 0:c5e2f793b59a 280 }
screamer 0:c5e2f793b59a 281 }
screamer 0:c5e2f793b59a 282
screamer 0:c5e2f793b59a 283 /* ----------------------------------------------------------------------------
screamer 0:c5e2f793b59a 284 -- SystemCoreClockUpdate()
screamer 0:c5e2f793b59a 285 ---------------------------------------------------------------------------- */
screamer 0:c5e2f793b59a 286
screamer 0:c5e2f793b59a 287 void SystemCoreClockUpdate (void) {
screamer 0:c5e2f793b59a 288 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
screamer 0:c5e2f793b59a 289 uint16_t Divider;
screamer 0:c5e2f793b59a 290
screamer 0:c5e2f793b59a 291 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
screamer 0:c5e2f793b59a 292 /* Output of FLL or PLL is selected */
screamer 0:c5e2f793b59a 293 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
screamer 0:c5e2f793b59a 294 /* FLL is selected */
screamer 0:c5e2f793b59a 295 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
screamer 0:c5e2f793b59a 296 /* External reference clock is selected */
screamer 0:c5e2f793b59a 297 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
screamer 0:c5e2f793b59a 298 case 0x00U:
screamer 0:c5e2f793b59a 299 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
screamer 0:c5e2f793b59a 300 break;
screamer 0:c5e2f793b59a 301 case 0x01U:
screamer 0:c5e2f793b59a 302 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
screamer 0:c5e2f793b59a 303 break;
screamer 0:c5e2f793b59a 304 case 0x02U:
screamer 0:c5e2f793b59a 305 default:
screamer 0:c5e2f793b59a 306 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
screamer 0:c5e2f793b59a 307 break;
screamer 0:c5e2f793b59a 308 }
screamer 0:c5e2f793b59a 309 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
screamer 0:c5e2f793b59a 310 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
screamer 0:c5e2f793b59a 311 case 0x38U:
screamer 0:c5e2f793b59a 312 Divider = 1536U;
screamer 0:c5e2f793b59a 313 break;
screamer 0:c5e2f793b59a 314 case 0x30U:
screamer 0:c5e2f793b59a 315 Divider = 1280U;
screamer 0:c5e2f793b59a 316 break;
screamer 0:c5e2f793b59a 317 default:
screamer 0:c5e2f793b59a 318 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
screamer 0:c5e2f793b59a 319 break;
screamer 0:c5e2f793b59a 320 }
screamer 0:c5e2f793b59a 321 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
screamer 0:c5e2f793b59a 322 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
screamer 0:c5e2f793b59a 323 }
screamer 0:c5e2f793b59a 324 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
screamer 0:c5e2f793b59a 325 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
screamer 0:c5e2f793b59a 326 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
screamer 0:c5e2f793b59a 327 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
screamer 0:c5e2f793b59a 328 /* Select correct multiplier to calculate the MCG output clock */
screamer 0:c5e2f793b59a 329 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
screamer 0:c5e2f793b59a 330 case 0x00U:
screamer 0:c5e2f793b59a 331 MCGOUTClock *= 640U;
screamer 0:c5e2f793b59a 332 break;
screamer 0:c5e2f793b59a 333 case 0x20U:
screamer 0:c5e2f793b59a 334 MCGOUTClock *= 1280U;
screamer 0:c5e2f793b59a 335 break;
screamer 0:c5e2f793b59a 336 case 0x40U:
screamer 0:c5e2f793b59a 337 MCGOUTClock *= 1920U;
screamer 0:c5e2f793b59a 338 break;
screamer 0:c5e2f793b59a 339 case 0x60U:
screamer 0:c5e2f793b59a 340 MCGOUTClock *= 2560U;
screamer 0:c5e2f793b59a 341 break;
screamer 0:c5e2f793b59a 342 case 0x80U:
screamer 0:c5e2f793b59a 343 MCGOUTClock *= 732U;
screamer 0:c5e2f793b59a 344 break;
screamer 0:c5e2f793b59a 345 case 0xA0U:
screamer 0:c5e2f793b59a 346 MCGOUTClock *= 1464U;
screamer 0:c5e2f793b59a 347 break;
screamer 0:c5e2f793b59a 348 case 0xC0U:
screamer 0:c5e2f793b59a 349 MCGOUTClock *= 2197U;
screamer 0:c5e2f793b59a 350 break;
screamer 0:c5e2f793b59a 351 case 0xE0U:
screamer 0:c5e2f793b59a 352 MCGOUTClock *= 2929U;
screamer 0:c5e2f793b59a 353 break;
screamer 0:c5e2f793b59a 354 default:
screamer 0:c5e2f793b59a 355 break;
screamer 0:c5e2f793b59a 356 }
screamer 0:c5e2f793b59a 357 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
screamer 0:c5e2f793b59a 358 /* PLL is selected */
screamer 0:c5e2f793b59a 359 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
screamer 0:c5e2f793b59a 360 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
screamer 0:c5e2f793b59a 361 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
screamer 0:c5e2f793b59a 362 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
screamer 0:c5e2f793b59a 363 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
screamer 0:c5e2f793b59a 364 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
screamer 0:c5e2f793b59a 365 /* Internal reference clock is selected */
screamer 0:c5e2f793b59a 366 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
screamer 0:c5e2f793b59a 367 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
screamer 0:c5e2f793b59a 368 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
screamer 0:c5e2f793b59a 369 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
screamer 0:c5e2f793b59a 370 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
screamer 0:c5e2f793b59a 371 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
screamer 0:c5e2f793b59a 372 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
screamer 0:c5e2f793b59a 373 /* External reference clock is selected */
screamer 0:c5e2f793b59a 374 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
screamer 0:c5e2f793b59a 375 case 0x00U:
screamer 0:c5e2f793b59a 376 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
screamer 0:c5e2f793b59a 377 break;
screamer 0:c5e2f793b59a 378 case 0x01U:
screamer 0:c5e2f793b59a 379 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
screamer 0:c5e2f793b59a 380 break;
screamer 0:c5e2f793b59a 381 case 0x02U:
screamer 0:c5e2f793b59a 382 default:
screamer 0:c5e2f793b59a 383 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
screamer 0:c5e2f793b59a 384 break;
screamer 0:c5e2f793b59a 385 }
screamer 0:c5e2f793b59a 386 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
screamer 0:c5e2f793b59a 387 /* Reserved value */
screamer 0:c5e2f793b59a 388 return;
screamer 0:c5e2f793b59a 389 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
screamer 0:c5e2f793b59a 390 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
screamer 0:c5e2f793b59a 391 }