Morpheus / target-mcu-k64f

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cmsis/TOOLCHAIN_GCC_ARM/startup_MK64F12.S@0:c5e2f793b59a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:24:48 2016 +0000
Revision:
0:c5e2f793b59a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /* K64F startup ARM GCC
screamer 0:c5e2f793b59a 2 * Purpose: startup file for Cortex-M4 devices. Should use with
screamer 0:c5e2f793b59a 3 * GCC for ARM Embedded Processors
screamer 0:c5e2f793b59a 4 * Version: V1.2
screamer 0:c5e2f793b59a 5 * Date: 15 Nov 2011
screamer 0:c5e2f793b59a 6 *
screamer 0:c5e2f793b59a 7 * Copyright (c) 2011, ARM Limited
screamer 0:c5e2f793b59a 8 * All rights reserved.
screamer 0:c5e2f793b59a 9 *
screamer 0:c5e2f793b59a 10 * Redistribution and use in source and binary forms, with or without
screamer 0:c5e2f793b59a 11 * modification, are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 12 * Redistributions of source code must retain the above copyright
screamer 0:c5e2f793b59a 13 notice, this list of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 14 * Redistributions in binary form must reproduce the above copyright
screamer 0:c5e2f793b59a 15 notice, this list of conditions and the following disclaimer in the
screamer 0:c5e2f793b59a 16 documentation and/or other materials provided with the distribution.
screamer 0:c5e2f793b59a 17 * Neither the name of the ARM Limited nor the
screamer 0:c5e2f793b59a 18 names of its contributors may be used to endorse or promote products
screamer 0:c5e2f793b59a 19 derived from this software without specific prior written permission.
screamer 0:c5e2f793b59a 20 *
screamer 0:c5e2f793b59a 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
screamer 0:c5e2f793b59a 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
screamer 0:c5e2f793b59a 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 31 */
screamer 0:c5e2f793b59a 32 .syntax unified
screamer 0:c5e2f793b59a 33 .arch armv7-m
screamer 0:c5e2f793b59a 34
screamer 0:c5e2f793b59a 35 /* Memory Model
screamer 0:c5e2f793b59a 36 The HEAP starts at the end of the DATA section and grows upward.
screamer 0:c5e2f793b59a 37
screamer 0:c5e2f793b59a 38 The STACK starts at the end of the RAM and grows downward.
screamer 0:c5e2f793b59a 39
screamer 0:c5e2f793b59a 40 The HEAP and stack STACK are only checked at compile time:
screamer 0:c5e2f793b59a 41 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
screamer 0:c5e2f793b59a 42
screamer 0:c5e2f793b59a 43 This is just a check for the bare minimum for the Heap+Stack area before
screamer 0:c5e2f793b59a 44 aborting compilation, it is not the run time limit:
screamer 0:c5e2f793b59a 45 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
screamer 0:c5e2f793b59a 46 */
screamer 0:c5e2f793b59a 47 .section .stack
screamer 0:c5e2f793b59a 48 .align 3
screamer 0:c5e2f793b59a 49 #ifdef __STACK_SIZE
screamer 0:c5e2f793b59a 50 .equ Stack_Size, __STACK_SIZE
screamer 0:c5e2f793b59a 51 #else
screamer 0:c5e2f793b59a 52 .equ Stack_Size, 0xC00
screamer 0:c5e2f793b59a 53 #endif
screamer 0:c5e2f793b59a 54 .globl __StackTop
screamer 0:c5e2f793b59a 55 .globl __StackLimit
screamer 0:c5e2f793b59a 56 __StackLimit:
screamer 0:c5e2f793b59a 57 .space Stack_Size
screamer 0:c5e2f793b59a 58 .size __StackLimit, . - __StackLimit
screamer 0:c5e2f793b59a 59 __StackTop:
screamer 0:c5e2f793b59a 60 .size __StackTop, . - __StackTop
screamer 0:c5e2f793b59a 61
screamer 0:c5e2f793b59a 62 .section .heap
screamer 0:c5e2f793b59a 63 .align 3
screamer 0:c5e2f793b59a 64 #ifdef __HEAP_SIZE
screamer 0:c5e2f793b59a 65 .equ Heap_Size, __HEAP_SIZE
screamer 0:c5e2f793b59a 66 #else
screamer 0:c5e2f793b59a 67 .equ Heap_Size, 0x400
screamer 0:c5e2f793b59a 68 #endif
screamer 0:c5e2f793b59a 69 .globl __HeapBase
screamer 0:c5e2f793b59a 70 .globl __HeapLimit
screamer 0:c5e2f793b59a 71 __HeapBase:
screamer 0:c5e2f793b59a 72 .space Heap_Size
screamer 0:c5e2f793b59a 73 .size __HeapBase, . - __HeapBase
screamer 0:c5e2f793b59a 74 __HeapLimit:
screamer 0:c5e2f793b59a 75 .size __HeapLimit, . - __HeapLimit
screamer 0:c5e2f793b59a 76
screamer 0:c5e2f793b59a 77 .section .vector_table,"a",%progbits
screamer 0:c5e2f793b59a 78 .align 2
screamer 0:c5e2f793b59a 79 .globl __isr_vector
screamer 0:c5e2f793b59a 80 __isr_vector:
screamer 0:c5e2f793b59a 81 .long __StackTop /* Top of Stack */
screamer 0:c5e2f793b59a 82 .long Reset_Handler /* Reset Handler */
screamer 0:c5e2f793b59a 83 .long NMI_Handler /* NMI Handler */
screamer 0:c5e2f793b59a 84 .long HardFault_Handler /* Hard Fault Handler */
screamer 0:c5e2f793b59a 85 .long MemManage_Handler /* MPU Fault Handler */
screamer 0:c5e2f793b59a 86 .long BusFault_Handler /* Bus Fault Handler */
screamer 0:c5e2f793b59a 87 .long UsageFault_Handler /* Usage Fault Handler */
screamer 0:c5e2f793b59a 88 .long 0 /* Reserved */
screamer 0:c5e2f793b59a 89 .long 0 /* Reserved */
screamer 0:c5e2f793b59a 90 .long 0 /* Reserved */
screamer 0:c5e2f793b59a 91 .long 0 /* Reserved */
screamer 0:c5e2f793b59a 92 .long SVC_Handler /* SVCall Handler */
screamer 0:c5e2f793b59a 93 .long DebugMon_Handler /* Debug Monitor Handler */
screamer 0:c5e2f793b59a 94 .long 0 /* Reserved */
screamer 0:c5e2f793b59a 95 .long PendSV_Handler /* PendSV Handler */
screamer 0:c5e2f793b59a 96 .long SysTick_Handler /* SysTick Handler */
screamer 0:c5e2f793b59a 97
screamer 0:c5e2f793b59a 98 /* External Interrupts */
screamer 0:c5e2f793b59a 99 .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete */
screamer 0:c5e2f793b59a 100 .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete */
screamer 0:c5e2f793b59a 101 .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete */
screamer 0:c5e2f793b59a 102 .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete */
screamer 0:c5e2f793b59a 103 .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete */
screamer 0:c5e2f793b59a 104 .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete */
screamer 0:c5e2f793b59a 105 .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete */
screamer 0:c5e2f793b59a 106 .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete */
screamer 0:c5e2f793b59a 107 .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete */
screamer 0:c5e2f793b59a 108 .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete */
screamer 0:c5e2f793b59a 109 .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete */
screamer 0:c5e2f793b59a 110 .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete */
screamer 0:c5e2f793b59a 111 .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete */
screamer 0:c5e2f793b59a 112 .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete */
screamer 0:c5e2f793b59a 113 .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete */
screamer 0:c5e2f793b59a 114 .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete */
screamer 0:c5e2f793b59a 115 .long DMA_Error_IRQHandler /* DMA Error Interrupt */
screamer 0:c5e2f793b59a 116 .long MCM_IRQHandler /* Normal Interrupt */
screamer 0:c5e2f793b59a 117 .long FTFE_IRQHandler /* FTFE Command complete interrupt */
screamer 0:c5e2f793b59a 118 .long Read_Collision_IRQHandler /* Read Collision Interrupt */
screamer 0:c5e2f793b59a 119 .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
screamer 0:c5e2f793b59a 120 .long LLW_IRQHandler /* Low Leakage Wakeup */
screamer 0:c5e2f793b59a 121 .long Watchdog_IRQHandler /* WDOG Interrupt */
screamer 0:c5e2f793b59a 122 .long RNG_IRQHandler /* RNG Interrupt */
screamer 0:c5e2f793b59a 123 .long I2C0_IRQHandler /* I2C0 interrupt */
screamer 0:c5e2f793b59a 124 .long I2C1_IRQHandler /* I2C1 interrupt */
screamer 0:c5e2f793b59a 125 .long SPI0_IRQHandler /* SPI0 Interrupt */
screamer 0:c5e2f793b59a 126 .long SPI1_IRQHandler /* SPI1 Interrupt */
screamer 0:c5e2f793b59a 127 .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt */
screamer 0:c5e2f793b59a 128 .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt */
screamer 0:c5e2f793b59a 129 .long UART0_LON_IRQHandler /* UART0 LON interrupt */
screamer 0:c5e2f793b59a 130 .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 131 .long UART0_ERR_IRQHandler /* UART0 Error interrupt */
screamer 0:c5e2f793b59a 132 .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 133 .long UART1_ERR_IRQHandler /* UART1 Error interrupt */
screamer 0:c5e2f793b59a 134 .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 135 .long UART2_ERR_IRQHandler /* UART2 Error interrupt */
screamer 0:c5e2f793b59a 136 .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 137 .long UART3_ERR_IRQHandler /* UART3 Error interrupt */
screamer 0:c5e2f793b59a 138 .long ADC0_IRQHandler /* ADC0 interrupt */
screamer 0:c5e2f793b59a 139 .long CMP0_IRQHandler /* CMP0 interrupt */
screamer 0:c5e2f793b59a 140 .long CMP1_IRQHandler /* CMP1 interrupt */
screamer 0:c5e2f793b59a 141 .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt */
screamer 0:c5e2f793b59a 142 .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt */
screamer 0:c5e2f793b59a 143 .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt */
screamer 0:c5e2f793b59a 144 .long CMT_IRQHandler /* CMT interrupt */
screamer 0:c5e2f793b59a 145 .long RTC_IRQHandler /* RTC interrupt */
screamer 0:c5e2f793b59a 146 .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
screamer 0:c5e2f793b59a 147 .long PIT0_IRQHandler /* PIT timer channel 0 interrupt */
screamer 0:c5e2f793b59a 148 .long PIT1_IRQHandler /* PIT timer channel 1 interrupt */
screamer 0:c5e2f793b59a 149 .long PIT2_IRQHandler /* PIT timer channel 2 interrupt */
screamer 0:c5e2f793b59a 150 .long PIT3_IRQHandler /* PIT timer channel 3 interrupt */
screamer 0:c5e2f793b59a 151 .long PDB0_IRQHandler /* PDB0 Interrupt */
screamer 0:c5e2f793b59a 152 .long USB0_IRQHandler /* USB0 interrupt */
screamer 0:c5e2f793b59a 153 .long USBDCD_IRQHandler /* USBDCD Interrupt */
screamer 0:c5e2f793b59a 154 .long Reserved71_IRQHandler /* Reserved interrupt 71 */
screamer 0:c5e2f793b59a 155 .long DAC0_IRQHandler /* DAC0 interrupt */
screamer 0:c5e2f793b59a 156 .long MCG_IRQHandler /* MCG Interrupt */
screamer 0:c5e2f793b59a 157 .long LPTimer_IRQHandler /* LPTimer interrupt */
screamer 0:c5e2f793b59a 158 .long PORTA_IRQHandler /* Port A interrupt */
screamer 0:c5e2f793b59a 159 .long PORTB_IRQHandler /* Port B interrupt */
screamer 0:c5e2f793b59a 160 .long PORTC_IRQHandler /* Port C interrupt */
screamer 0:c5e2f793b59a 161 .long PORTD_IRQHandler /* Port D interrupt */
screamer 0:c5e2f793b59a 162 .long PORTE_IRQHandler /* Port E interrupt */
screamer 0:c5e2f793b59a 163 .long SWI_IRQHandler /* Software interrupt */
screamer 0:c5e2f793b59a 164 .long SPI2_IRQHandler /* SPI2 Interrupt */
screamer 0:c5e2f793b59a 165 .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 166 .long UART4_ERR_IRQHandler /* UART4 Error interrupt */
screamer 0:c5e2f793b59a 167 .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt */
screamer 0:c5e2f793b59a 168 .long UART5_ERR_IRQHandler /* UART5 Error interrupt */
screamer 0:c5e2f793b59a 169 .long CMP2_IRQHandler /* CMP2 interrupt */
screamer 0:c5e2f793b59a 170 .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt */
screamer 0:c5e2f793b59a 171 .long DAC1_IRQHandler /* DAC1 interrupt */
screamer 0:c5e2f793b59a 172 .long ADC1_IRQHandler /* ADC1 interrupt */
screamer 0:c5e2f793b59a 173 .long I2C2_IRQHandler /* I2C2 interrupt */
screamer 0:c5e2f793b59a 174 .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt */
screamer 0:c5e2f793b59a 175 .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt */
screamer 0:c5e2f793b59a 176 .long CAN0_Error_IRQHandler /* CAN0 error interrupt */
screamer 0:c5e2f793b59a 177 .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt */
screamer 0:c5e2f793b59a 178 .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt */
screamer 0:c5e2f793b59a 179 .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt */
screamer 0:c5e2f793b59a 180 .long SDHC_IRQHandler /* SDHC interrupt */
screamer 0:c5e2f793b59a 181 .long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt */
screamer 0:c5e2f793b59a 182 .long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt */
screamer 0:c5e2f793b59a 183 .long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt */
screamer 0:c5e2f793b59a 184 .long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt */
screamer 0:c5e2f793b59a 185
screamer 0:c5e2f793b59a 186 .size __isr_vector, . - __isr_vector
screamer 0:c5e2f793b59a 187
screamer 0:c5e2f793b59a 188 .section .text.Reset_Handler
screamer 0:c5e2f793b59a 189 .thumb
screamer 0:c5e2f793b59a 190 .thumb_func
screamer 0:c5e2f793b59a 191 .align 2
screamer 0:c5e2f793b59a 192 .globl Reset_Handler
screamer 0:c5e2f793b59a 193 .type Reset_Handler, %function
screamer 0:c5e2f793b59a 194 Reset_Handler:
screamer 0:c5e2f793b59a 195 /* Loop to copy data from read only memory to RAM. The ranges
screamer 0:c5e2f793b59a 196 * of copy from/to are specified by following symbols evaluated in
screamer 0:c5e2f793b59a 197 * linker script.
screamer 0:c5e2f793b59a 198 * __etext: End of code section, i.e., begin of data sections to copy from.
screamer 0:c5e2f793b59a 199 * __data_start__/__data_end__: RAM address range that data should be
screamer 0:c5e2f793b59a 200 * copied to. Both must be aligned to 4 bytes boundary. */
screamer 0:c5e2f793b59a 201
screamer 0:c5e2f793b59a 202 disable_watchdog:
screamer 0:c5e2f793b59a 203 /* unlock */
screamer 0:c5e2f793b59a 204 ldr r1, =0x4005200e
screamer 0:c5e2f793b59a 205 ldr r0, =0xc520
screamer 0:c5e2f793b59a 206 strh r0, [r1]
screamer 0:c5e2f793b59a 207 ldr r0, =0xd928
screamer 0:c5e2f793b59a 208 strh r0, [r1]
screamer 0:c5e2f793b59a 209 /* disable */
screamer 0:c5e2f793b59a 210 ldr r1, =0x40052000
screamer 0:c5e2f793b59a 211 ldr r0, =0x01d2
screamer 0:c5e2f793b59a 212 strh r0, [r1]
screamer 0:c5e2f793b59a 213
screamer 0:c5e2f793b59a 214 ldr r1, =__etext
screamer 0:c5e2f793b59a 215 ldr r2, =__data_start__
screamer 0:c5e2f793b59a 216 ldr r3, =__data_end__
screamer 0:c5e2f793b59a 217
screamer 0:c5e2f793b59a 218 subs r3, r2
screamer 0:c5e2f793b59a 219 ble .Lflash_to_ram_loop_end
screamer 0:c5e2f793b59a 220
screamer 0:c5e2f793b59a 221 movs r4, 0
screamer 0:c5e2f793b59a 222 .Lflash_to_ram_loop:
screamer 0:c5e2f793b59a 223 ldr r0, [r1,r4]
screamer 0:c5e2f793b59a 224 str r0, [r2,r4]
screamer 0:c5e2f793b59a 225 adds r4, 4
screamer 0:c5e2f793b59a 226 cmp r4, r3
screamer 0:c5e2f793b59a 227 blt .Lflash_to_ram_loop
screamer 0:c5e2f793b59a 228 .Lflash_to_ram_loop_end:
screamer 0:c5e2f793b59a 229
screamer 0:c5e2f793b59a 230 ldr r0, =SystemInit
screamer 0:c5e2f793b59a 231 blx r0
screamer 0:c5e2f793b59a 232 ldr r0, =_start
screamer 0:c5e2f793b59a 233 bx r0
screamer 0:c5e2f793b59a 234 .pool
screamer 0:c5e2f793b59a 235 .size Reset_Handler, . - Reset_Handler
screamer 0:c5e2f793b59a 236
screamer 0:c5e2f793b59a 237 .text
screamer 0:c5e2f793b59a 238 /* Macro to define default handlers. Default handler
screamer 0:c5e2f793b59a 239 * will be weak symbol and just dead loops. They can be
screamer 0:c5e2f793b59a 240 * overwritten by other handlers */
screamer 0:c5e2f793b59a 241 .macro def_default_handler handler_name
screamer 0:c5e2f793b59a 242 .align 1
screamer 0:c5e2f793b59a 243 .thumb_func
screamer 0:c5e2f793b59a 244 .weak \handler_name
screamer 0:c5e2f793b59a 245 .type \handler_name, %function
screamer 0:c5e2f793b59a 246 \handler_name :
screamer 0:c5e2f793b59a 247 b .
screamer 0:c5e2f793b59a 248 .size \handler_name, . - \handler_name
screamer 0:c5e2f793b59a 249 .endm
screamer 0:c5e2f793b59a 250
screamer 0:c5e2f793b59a 251 /* Exception Handlers */
screamer 0:c5e2f793b59a 252
screamer 0:c5e2f793b59a 253 def_default_handler NMI_Handler
screamer 0:c5e2f793b59a 254 def_default_handler HardFault_Handler
screamer 0:c5e2f793b59a 255 def_default_handler MemManage_Handler
screamer 0:c5e2f793b59a 256 def_default_handler BusFault_Handler
screamer 0:c5e2f793b59a 257 def_default_handler UsageFault_Handler
screamer 0:c5e2f793b59a 258 def_default_handler SVC_Handler
screamer 0:c5e2f793b59a 259 def_default_handler DebugMon_Handler
screamer 0:c5e2f793b59a 260 def_default_handler PendSV_Handler
screamer 0:c5e2f793b59a 261 def_default_handler SysTick_Handler
screamer 0:c5e2f793b59a 262 def_default_handler Default_Handler
screamer 0:c5e2f793b59a 263
screamer 0:c5e2f793b59a 264 .macro def_irq_default_handler handler_name
screamer 0:c5e2f793b59a 265 .weak \handler_name
screamer 0:c5e2f793b59a 266 .set \handler_name, Default_Handler
screamer 0:c5e2f793b59a 267 .endm
screamer 0:c5e2f793b59a 268
screamer 0:c5e2f793b59a 269 /* IRQ Handlers */
screamer 0:c5e2f793b59a 270 def_irq_default_handler DMA0_IRQHandler
screamer 0:c5e2f793b59a 271 def_irq_default_handler DMA1_IRQHandler
screamer 0:c5e2f793b59a 272 def_irq_default_handler DMA2_IRQHandler
screamer 0:c5e2f793b59a 273 def_irq_default_handler DMA3_IRQHandler
screamer 0:c5e2f793b59a 274 def_irq_default_handler DMA4_IRQHandler
screamer 0:c5e2f793b59a 275 def_irq_default_handler DMA5_IRQHandler
screamer 0:c5e2f793b59a 276 def_irq_default_handler DMA6_IRQHandler
screamer 0:c5e2f793b59a 277 def_irq_default_handler DMA7_IRQHandler
screamer 0:c5e2f793b59a 278 def_irq_default_handler DMA8_IRQHandler
screamer 0:c5e2f793b59a 279 def_irq_default_handler DMA9_IRQHandler
screamer 0:c5e2f793b59a 280 def_irq_default_handler DMA10_IRQHandler
screamer 0:c5e2f793b59a 281 def_irq_default_handler DMA11_IRQHandler
screamer 0:c5e2f793b59a 282 def_irq_default_handler DMA12_IRQHandler
screamer 0:c5e2f793b59a 283 def_irq_default_handler DMA13_IRQHandler
screamer 0:c5e2f793b59a 284 def_irq_default_handler DMA14_IRQHandler
screamer 0:c5e2f793b59a 285 def_irq_default_handler DMA15_IRQHandler
screamer 0:c5e2f793b59a 286 def_irq_default_handler DMA_Error_IRQHandler
screamer 0:c5e2f793b59a 287 def_irq_default_handler MCM_IRQHandler
screamer 0:c5e2f793b59a 288 def_irq_default_handler FTFE_IRQHandler
screamer 0:c5e2f793b59a 289 def_irq_default_handler Read_Collision_IRQHandler
screamer 0:c5e2f793b59a 290 def_irq_default_handler LVD_LVW_IRQHandler
screamer 0:c5e2f793b59a 291 def_irq_default_handler LLW_IRQHandler
screamer 0:c5e2f793b59a 292 def_irq_default_handler Watchdog_IRQHandler
screamer 0:c5e2f793b59a 293 def_irq_default_handler RNG_IRQHandler
screamer 0:c5e2f793b59a 294 def_irq_default_handler I2C0_IRQHandler
screamer 0:c5e2f793b59a 295 def_irq_default_handler I2C1_IRQHandler
screamer 0:c5e2f793b59a 296 def_irq_default_handler SPI0_IRQHandler
screamer 0:c5e2f793b59a 297 def_irq_default_handler SPI1_IRQHandler
screamer 0:c5e2f793b59a 298 def_irq_default_handler I2S0_Tx_IRQHandler
screamer 0:c5e2f793b59a 299 def_irq_default_handler I2S0_Rx_IRQHandler
screamer 0:c5e2f793b59a 300 def_irq_default_handler UART0_LON_IRQHandler
screamer 0:c5e2f793b59a 301 def_irq_default_handler UART0_RX_TX_IRQHandler
screamer 0:c5e2f793b59a 302 def_irq_default_handler UART0_ERR_IRQHandler
screamer 0:c5e2f793b59a 303 def_irq_default_handler UART1_RX_TX_IRQHandler
screamer 0:c5e2f793b59a 304 def_irq_default_handler UART1_ERR_IRQHandler
screamer 0:c5e2f793b59a 305 def_irq_default_handler UART2_RX_TX_IRQHandler
screamer 0:c5e2f793b59a 306 def_irq_default_handler UART2_ERR_IRQHandler
screamer 0:c5e2f793b59a 307 def_irq_default_handler UART3_RX_TX_IRQHandler
screamer 0:c5e2f793b59a 308 def_irq_default_handler UART3_ERR_IRQHandler
screamer 0:c5e2f793b59a 309 def_irq_default_handler ADC0_IRQHandler
screamer 0:c5e2f793b59a 310 def_irq_default_handler CMP0_IRQHandler
screamer 0:c5e2f793b59a 311 def_irq_default_handler CMP1_IRQHandler
screamer 0:c5e2f793b59a 312 def_irq_default_handler FTM0_IRQHandler
screamer 0:c5e2f793b59a 313 def_irq_default_handler FTM1_IRQHandler
screamer 0:c5e2f793b59a 314 def_irq_default_handler FTM2_IRQHandler
screamer 0:c5e2f793b59a 315 def_irq_default_handler CMT_IRQHandler
screamer 0:c5e2f793b59a 316 def_irq_default_handler RTC_IRQHandler
screamer 0:c5e2f793b59a 317 def_irq_default_handler RTC_Seconds_IRQHandler
screamer 0:c5e2f793b59a 318 def_irq_default_handler PIT0_IRQHandler
screamer 0:c5e2f793b59a 319 def_irq_default_handler PIT1_IRQHandler
screamer 0:c5e2f793b59a 320 def_irq_default_handler PIT2_IRQHandler
screamer 0:c5e2f793b59a 321 def_irq_default_handler PIT3_IRQHandler
screamer 0:c5e2f793b59a 322 def_irq_default_handler PDB0_IRQHandler
screamer 0:c5e2f793b59a 323 def_irq_default_handler USB0_IRQHandler
screamer 0:c5e2f793b59a 324 def_irq_default_handler USBDCD_IRQHandler
screamer 0:c5e2f793b59a 325 def_irq_default_handler Reserved71_IRQHandler
screamer 0:c5e2f793b59a 326 def_irq_default_handler DAC0_IRQHandler
screamer 0:c5e2f793b59a 327 def_irq_default_handler MCG_IRQHandler
screamer 0:c5e2f793b59a 328 def_irq_default_handler LPTimer_IRQHandler
screamer 0:c5e2f793b59a 329 def_irq_default_handler PORTA_IRQHandler
screamer 0:c5e2f793b59a 330 def_irq_default_handler PORTB_IRQHandler
screamer 0:c5e2f793b59a 331 def_irq_default_handler PORTC_IRQHandler
screamer 0:c5e2f793b59a 332 def_irq_default_handler PORTD_IRQHandler
screamer 0:c5e2f793b59a 333 def_irq_default_handler PORTE_IRQHandler
screamer 0:c5e2f793b59a 334 def_irq_default_handler SWI_IRQHandler
screamer 0:c5e2f793b59a 335 def_irq_default_handler SPI2_IRQHandler
screamer 0:c5e2f793b59a 336 def_irq_default_handler UART4_RX_TX_IRQHandler
screamer 0:c5e2f793b59a 337 def_irq_default_handler UART4_ERR_IRQHandler
screamer 0:c5e2f793b59a 338 def_irq_default_handler UART5_RX_TX_IRQHandler
screamer 0:c5e2f793b59a 339 def_irq_default_handler UART5_ERR_IRQHandler
screamer 0:c5e2f793b59a 340 def_irq_default_handler CMP2_IRQHandler
screamer 0:c5e2f793b59a 341 def_irq_default_handler FTM3_IRQHandler
screamer 0:c5e2f793b59a 342 def_irq_default_handler DAC1_IRQHandler
screamer 0:c5e2f793b59a 343 def_irq_default_handler ADC1_IRQHandler
screamer 0:c5e2f793b59a 344 def_irq_default_handler I2C2_IRQHandler
screamer 0:c5e2f793b59a 345 def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler
screamer 0:c5e2f793b59a 346 def_irq_default_handler CAN0_Bus_Off_IRQHandler
screamer 0:c5e2f793b59a 347 def_irq_default_handler CAN0_Error_IRQHandler
screamer 0:c5e2f793b59a 348 def_irq_default_handler CAN0_Tx_Warning_IRQHandler
screamer 0:c5e2f793b59a 349 def_irq_default_handler CAN0_Rx_Warning_IRQHandler
screamer 0:c5e2f793b59a 350 def_irq_default_handler CAN0_Wake_Up_IRQHandler
screamer 0:c5e2f793b59a 351 def_irq_default_handler SDHC_IRQHandler
screamer 0:c5e2f793b59a 352 def_irq_default_handler ENET_1588_Timer_IRQHandler
screamer 0:c5e2f793b59a 353 def_irq_default_handler ENET_Transmit_IRQHandler
screamer 0:c5e2f793b59a 354 def_irq_default_handler ENET_Receive_IRQHandler
screamer 0:c5e2f793b59a 355 def_irq_default_handler ENET_Error_IRQHandler
screamer 0:c5e2f793b59a 356 def_irq_default_handler DefaultISR
screamer 0:c5e2f793b59a 357
screamer 0:c5e2f793b59a 358 /* Flash protection region, placed at 0x400 */
screamer 0:c5e2f793b59a 359 .text
screamer 0:c5e2f793b59a 360 .thumb
screamer 0:c5e2f793b59a 361 .align 2
screamer 0:c5e2f793b59a 362 .section .kinetis_flash_config_field,"a",%progbits
screamer 0:c5e2f793b59a 363 kinetis_flash_config:
screamer 0:c5e2f793b59a 364 .long 0xffffffff
screamer 0:c5e2f793b59a 365 .long 0xffffffff
screamer 0:c5e2f793b59a 366 .long 0xffffffff
screamer 0:c5e2f793b59a 367 .long 0xfffffdfe
screamer 0:c5e2f793b59a 368
screamer 0:c5e2f793b59a 369 .end