MorphGI / Mbed OS MGI_Rebuild_MidLevel_9_0-Basic_PWM

Basic Mid-Level control for the rebuilt MorphGI control unit, using PWM to communicate with the low level controllers.

Dependencies:   ros_lib_kinetic

LLComms.h@42:5a5ad23a4bb1, 2021-06-24 (annotated)

Committer:
dofydoink
Date:
Thu Jun 24 20:34:47 2021 +0000
Revision:
42:5a5ad23a4bb1
Parent:
37:37da606f4466 
first

Who changed what in which revision?

UserRevisionLine numberNew contents of line
WD40andTape 8:d6657767a182 1 // LLComms.h
WD40andTape 8:d6657767a182 2
WD40andTape 8:d6657767a182 3 #ifndef LLCOMMS_H
WD40andTape 8:d6657767a182 4 #define LLCOMMS_H
WD40andTape 8:d6657767a182 5
WD40andTape 8:d6657767a182 6 // STANDARD IMPORTS
WD40andTape 26:7c59002c9cd7 7 #include "math.h"
WD40andTape 26:7c59002c9cd7 8 #include <algorithm>
WD40andTape 8:d6657767a182 9 // MBED IMPORTS
WD40andTape 8:d6657767a182 10 #include "mbed.h"
WD40andTape 8:d6657767a182 11 #include "mbed_events.h"
dofydoink 11:7029367a1840 12 // CUSTOM IMPORTS
dofydoink 12:595ed862e52f 13 #include "MLSettings.h"
WD40andTape 8:d6657767a182 14
WD40andTape 8:d6657767a182 15 // ADC SPI DEFINES
WD40andTape 8:d6657767a182 16 #define PREAMBLE 0x06
WD40andTape 8:d6657767a182 17 #define CHAN_1 0x30
WD40andTape 8:d6657767a182 18 #define CHAN_2 0x70
WD40andTape 8:d6657767a182 19 #define CHAN_3 0xB0
WD40andTape 8:d6657767a182 20 #define CHAN_4 0xF0
WD40andTape 8:d6657767a182 21 #define DATA_MASK 0x0F
WD40andTape 8:d6657767a182 22
WD40andTape 8:d6657767a182 23 class LLComms
WD40andTape 8:d6657767a182 24 {
dofydoink 11:7029367a1840 25
WD40andTape 8:d6657767a182 26 public:
dofydoink 12:595ed862e52f 27
dofydoink 12:595ed862e52f 28 EventQueue queue;
dofydoink 12:595ed862e52f 29 Mutex mutChannel[N_CHANNELS];
dofydoink 12:595ed862e52f 30 bool isDataReady[N_CHANNELS]; // Flag to indicate path data is ready for transmission to low level.
WD40andTape 26:7c59002c9cd7 31 double demandPosition_mm[N_CHANNELS];
WD40andTape 26:7c59002c9cd7 32 double demandSpeed_mmps[N_CHANNELS];
dofydoink 12:595ed862e52f 33 char chrErrorFlag[N_CHANNELS]; // 3 error bits from LL
WD40andTape 29:10a5cf37a875 34 unsigned int positionSensor_uint[N_CHANNELS];
WD40andTape 26:7c59002c9cd7 35 double positionSensor_mm[N_CHANNELS]; // The actual chamber lengths in meters given as the change in length relative to neutral (should always be >=0)
WD40andTape 29:10a5cf37a875 36 unsigned int pressureSensor_uint[N_CHANNELS];
WD40andTape 22:82871f00f89d 37 double pressureSensor_bar[N_CHANNELS]; // The pressure in a given chamber in bar (1 bar = 100,000 Pa)
dofydoink 42:5a5ad23a4bb1 38 unsigned int formatMessage(short int type, double dblValue, double dblMaxValue);
dofydoink 42:5a5ad23a4bb1 39 //bool CheckMessage(int msg, short int trueType);
dofydoink 42:5a5ad23a4bb1 40 bool CheckMessage(int msg);
dofydoink 42:5a5ad23a4bb1 41 bool PerformMasterSPI(SPI *spi, unsigned int outboundMsgs[], unsigned int inboundMsgsData[]);
dofydoink 42:5a5ad23a4bb1 42 void SendReceiveData(int channel);
dofydoink 42:5a5ad23a4bb1 43 int countervar;
dofydoink 12:595ed862e52f 44
dofydoink 12:595ed862e52f 45 LLComms(); // Constructor
dofydoink 12:595ed862e52f 46 //~LLComms(); // Destructor
dofydoink 12:595ed862e52f 47
dofydoink 12:595ed862e52f 48 private:
WD40andTape 8:d6657767a182 49
WD40andTape 8:d6657767a182 50 // PIN DECLARATIONS
WD40andTape 14:54c3759e76ed 51 SPI spi_0; // mosi, miso, sclk
dofydoink 42:5a5ad23a4bb1 52 //SPI spi_1; // mosi, miso, sclk
dofydoink 11:7029367a1840 53 DigitalOut* cs_LL[N_CHANNELS]; // Chip select for low level controller
WD40andTape 34:54e9ebe9e87f 54 //DigitalOut* cs_ADC[N_CHANNELS]; // Chip select for ADC
WD40andTape 8:d6657767a182 55 // These interrupt pins have to be declared AFTER SPI declaration. No Clue Why.
WD40andTape 8:d6657767a182 56 InterruptIn pinGate0;
WD40andTape 8:d6657767a182 57 InterruptIn pinGate1;
WD40andTape 8:d6657767a182 58 InterruptIn pinGate2;
dofydoink 42:5a5ad23a4bb1 59 //InterruptIn pinGate3;
dofydoink 42:5a5ad23a4bb1 60 DigitalInOut pinReset; // Reset pin for all controllers.
WD40andTape 8:d6657767a182 61
dofydoink 11:7029367a1840 62 int ThreadID[N_CHANNELS];
WD40andTape 8:d6657767a182 63
dofydoink 42:5a5ad23a4bb1 64
WD40andTape 10:1b6daba32452 65 void common_rise_handler(int channel);
WD40andTape 10:1b6daba32452 66 void common_fall_handler(int channel);
WD40andTape 10:1b6daba32452 67 void rise0(void);
WD40andTape 10:1b6daba32452 68 void rise1(void);
WD40andTape 10:1b6daba32452 69 void rise2(void);
dofydoink 42:5a5ad23a4bb1 70 //void rise3(void);
WD40andTape 10:1b6daba32452 71 void fall0(void);
WD40andTape 10:1b6daba32452 72 void fall1(void);
WD40andTape 10:1b6daba32452 73 void fall2(void);
dofydoink 42:5a5ad23a4bb1 74 //void fall3(void);
WD40andTape 8:d6657767a182 75
WD40andTape 8:d6657767a182 76 };
WD40andTape 8:d6657767a182 77
WD40andTape 8:d6657767a182 78 #endif