Patched version of nrf51822 FOTA compatible driver, with GPTIO disabled, as it clashed with the mbed definitions...

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nrf51_deprecated.h

00001 /* Copyright (c) 2013, Nordic Semiconductor ASA
00002  * All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions are met:
00006  *
00007  *   * Redistributions of source code must retain the above copyright notice, this
00008  *     list of conditions and the following disclaimer.
00009  *
00010  *   * Redistributions in binary form must reproduce the above copyright notice,
00011  *     this list of conditions and the following disclaimer in the documentation
00012  *     and/or other materials provided with the distribution.
00013  *
00014  *   * Neither the name of Nordic Semiconductor ASA nor the names of its
00015  *     contributors may be used to endorse or promote products derived from
00016  *     this software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00019  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00020  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00021  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00022  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00023  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00024  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00025  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00027  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00028  *
00029  */
00030 #ifndef NRF51_DEPRECATED_H
00031 #define NRF51_DEPRECATED_H
00032 
00033 /*lint ++flb "Enter library region */
00034 
00035 /* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 
00036  * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
00037  * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
00038  */
00039 
00040 /* NVMC */
00041 /* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
00042 #define ERASEPCR0   ERASEPROTECTEDPAGE
00043 /* The register ERASEPAGE is also called ERASEPCR1 in the documentation. */
00044 #define ERASEPCR1   ERASEPAGE
00045  
00046 /* LPCOMP */
00047 /* The interrupt ISR was renamed. Adding old name to the macros. */
00048 #define LPCOMP_COMP_IRQHandler      LPCOMP_IRQHandler
00049  
00050  
00051 /* MPU */
00052 /* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
00053 #define MPU_PERR0_LPCOMP_COMP_Pos           MPU_PERR0_LPCOMP_Pos
00054 #define MPU_PERR0_LPCOMP_COMP_Msk           MPU_PERR0_LPCOMP_Msk
00055 #define MPU_PERR0_LPCOMP_COMP_InRegion1     MPU_PERR0_LPCOMP_InRegion1
00056 #define MPU_PERR0_LPCOMP_COMP_InRegion0     MPU_PERR0_LPCOMP_InRegion0
00057  
00058  
00059 /* POWER */
00060 /* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
00061 #define POWER_RAMON_OFFRAM3_Pos         (19UL)                                  
00062 #define POWER_RAMON_OFFRAM3_Msk         (0x1UL << POWER_RAMON_OFFRAM3_Pos)      
00063 #define POWER_RAMON_OFFRAM3_RAM3Off     (0UL)                                   
00064 #define POWER_RAMON_OFFRAM3_RAM3On      (1UL)                                   
00065 /* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
00066 #define POWER_RAMON_OFFRAM2_Pos         (18UL)                                  
00067 #define POWER_RAMON_OFFRAM2_Msk         (0x1UL << POWER_RAMON_OFFRAM2_Pos)      
00068 #define POWER_RAMON_OFFRAM2_RAM2Off     (0UL)                                   
00069 #define POWER_RAMON_OFFRAM2_RAM2On      (1UL)                                  
00070 /* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
00071 #define POWER_RAMON_ONRAM3_Pos          (3UL)                                  
00072 #define POWER_RAMON_ONRAM3_Msk          (0x1UL << POWER_RAMON_ONRAM3_Pos)      
00073 #define POWER_RAMON_ONRAM3_RAM3Off      (0UL)                                  
00074 #define POWER_RAMON_ONRAM3_RAM3On       (1UL)                                  
00075 /* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
00076 #define POWER_RAMON_ONRAM2_Pos          (2UL)                                  
00077 #define POWER_RAMON_ONRAM2_Msk          (0x1UL << POWER_RAMON_ONRAM2_Pos)       
00078 #define POWER_RAMON_ONRAM2_RAM2Off      (0UL)                                  
00079 #define POWER_RAMON_ONRAM2_RAM2On       (1UL)                                 
00080 
00081  
00082 /* RADIO */
00083 /* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
00084 #define RADIO_TXPOWER_TXPOWER_Neg40dBm  RADIO_TXPOWER_TXPOWER_Neg30dBm      
00085 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
00086 #define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos 
00087 #define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk 
00088 #define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include 
00089 #define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip 
00090 /* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
00091 #define RADIO_TEST_PLL_LOCK_Pos         RADIO_TEST_PLLLOCK_Pos 
00092 #define RADIO_TEST_PLL_LOCK_Msk         RADIO_TEST_PLLLOCK_Msk 
00093 #define RADIO_TEST_PLL_LOCK_Disabled    RADIO_TEST_PLLLOCK_Disabled 
00094 #define RADIO_TEST_PLL_LOCK_Enabled     RADIO_TEST_PLLLOCK_Enabled 
00095 /* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
00096 #define RADIO_TEST_CONST_CARRIER_Pos        RADIO_TEST_CONSTCARRIER_Pos 
00097 #define RADIO_TEST_CONST_CARRIER_Msk        RADIO_TEST_CONSTCARRIER_Msk 
00098 #define RADIO_TEST_CONST_CARRIER_Disabled   RADIO_TEST_CONSTCARRIER_Disabled 
00099 #define RADIO_TEST_CONST_CARRIER_Enabled    RADIO_TEST_CONSTCARRIER_Enabled 
00100 
00101 
00102 /* FICR */
00103 /* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
00104 #define SIZERAMBLOCK0   SIZERAMBLOCKS                   
00105 #define SIZERAMBLOCK1   SIZERAMBLOCKS                   
00106 #define SIZERAMBLOCK2   SIZERAMBLOCK[2]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
00107 #define SIZERAMBLOCK3   SIZERAMBLOCK[3]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
00108 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
00109 #define DEVICEID0       DEVICEID[0]                     
00110 #define DEVICEID1       DEVICEID[1]                     
00111 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
00112 #define ER0             ER[0]                           
00113 #define ER1             ER[1]                          
00114 #define ER2             ER[2]                       
00115 #define ER3             ER[3]                      
00116 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
00117 #define IR0             IR[0]                         
00118 #define IR1             IR[1]                         
00119 #define IR2             IR[2]                         
00120 #define IR3             IR[3]                          
00121 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
00122 #define DEVICEADDR0     DEVICEADDR[0]                  
00123 #define DEVICEADDR1     DEVICEADDR[1]                  
00124 
00125 
00126 /* PPI */
00127 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
00128 #define TASKS_CHG0EN     TASKS_CHG[0].EN                    
00129 #define TASKS_CHG0DIS    TASKS_CHG[0].DIS                  
00130 #define TASKS_CHG1EN     TASKS_CHG[1].EN                    
00131 #define TASKS_CHG1DIS    TASKS_CHG[1].DIS                  
00132 #define TASKS_CHG2EN     TASKS_CHG[2].EN                   
00133 #define TASKS_CHG2DIS    TASKS_CHG[2].DIS                  
00134 #define TASKS_CHG3EN     TASKS_CHG[3].EN                    
00135 #define TASKS_CHG3DIS    TASKS_CHG[3].DIS                  
00136 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
00137 #define CH0_EEP          CH[0].EEP                          
00138 #define CH0_TEP          CH[0].TEP                          
00139 #define CH1_EEP          CH[1].EEP                         
00140 #define CH1_TEP          CH[1].TEP                         
00141 #define CH2_EEP          CH[2].EEP                          
00142 #define CH2_TEP          CH[2].TEP                         
00143 #define CH3_EEP          CH[3].EEP                          
00144 #define CH3_TEP          CH[3].TEP                         
00145 #define CH4_EEP          CH[4].EEP                         
00146 #define CH4_TEP          CH[4].TEP                         
00147 #define CH5_EEP          CH[5].EEP                          
00148 #define CH5_TEP          CH[5].TEP                          
00149 #define CH6_EEP          CH[6].EEP                          
00150 #define CH6_TEP          CH[6].TEP                         
00151 #define CH7_EEP          CH[7].EEP                          
00152 #define CH7_TEP          CH[7].TEP                          
00153 #define CH8_EEP          CH[8].EEP                         
00154 #define CH8_TEP          CH[8].TEP                          
00155 #define CH9_EEP          CH[9].EEP                          
00156 #define CH9_TEP          CH[9].TEP                          
00157 #define CH10_EEP         CH[10].EEP                         
00158 #define CH10_TEP         CH[10].TEP                         
00159 #define CH11_EEP         CH[11].EEP                         
00160 #define CH11_TEP         CH[11].TEP                         
00161 #define CH12_EEP         CH[12].EEP                         
00162 #define CH12_TEP         CH[12].TEP                         
00163 #define CH13_EEP         CH[13].EEP                         
00164 #define CH13_TEP         CH[13].TEP                         
00165 #define CH14_EEP         CH[14].EEP                         
00166 #define CH14_TEP         CH[14].TEP                         
00167 #define CH15_EEP         CH[15].EEP                         
00168 #define CH15_TEP         CH[15].TEP                        
00169 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
00170 #define CHG0             CHG[0]                            
00171 #define CHG1             CHG[1]                            
00172 #define CHG2             CHG[2]                             
00173 #define CHG3             CHG[3]                           
00174 /* All bitfield macros for the CHGx registers therefore changed name. */
00175 #define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos            
00176 #define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk            
00177 #define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded       
00178 #define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included       
00179 #define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos            
00180 #define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk           
00181 #define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded       
00182 #define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included       
00183 #define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos            
00184 #define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk            
00185 #define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded      
00186 #define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included       
00187 #define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos            
00188 #define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk            
00189 #define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded       
00190 #define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included       
00191 #define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos            
00192 #define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk            
00193 #define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded       
00194 #define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included       
00195 #define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos            
00196 #define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk            
00197 #define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded       
00198 #define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included       
00199 #define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos             
00200 #define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk             
00201 #define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded        
00202 #define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included        
00203 #define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos             
00204 #define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk             
00205 #define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded        
00206 #define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included        
00207 #define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos             
00208 #define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk             
00209 #define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded        
00210 #define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included        
00211 #define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos             
00212 #define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk             
00213 #define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded        
00214 #define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included        
00215 #define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos             
00216 #define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk             
00217 #define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded       
00218 #define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included        
00219 #define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos             
00220 #define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk             
00221 #define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded       
00222 #define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included       
00223 #define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos             
00224 #define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk            
00225 #define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded        
00226 #define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included       
00227 #define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos            
00228 #define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk             
00229 #define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded       
00230 #define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included       
00231 #define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos            
00232 #define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk            
00233 #define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded        
00234 #define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included       
00235 #define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos            
00236 #define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk            
00237 #define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded        
00238 #define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included       
00239 #define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos           
00240 #define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk           
00241 #define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded       
00242 #define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included      
00243 #define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos           
00244 #define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk            
00245 #define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded      
00246 #define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included       
00247 #define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos           
00248 #define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk            
00249 #define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded      
00250 #define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included      
00251 #define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos            
00252 #define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk           
00253 #define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded      
00254 #define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included      
00255 #define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos            
00256 #define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk           
00257 #define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded      
00258 #define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included      
00259 #define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos           
00260 #define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk            
00261 #define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded      
00262 #define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included      
00263 #define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos            
00264 #define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk            
00265 #define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded       
00266 #define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included       
00267 #define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos            
00268 #define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk            
00269 #define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded       
00270 #define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included       
00271 #define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos             
00272 #define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk            
00273 #define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded        
00274 #define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included       
00275 #define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos             
00276 #define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk            
00277 #define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded       
00278 #define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included       
00279 #define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos             
00280 #define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk             
00281 #define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded       
00282 #define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included        
00283 #define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos             
00284 #define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk             
00285 #define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded        
00286 #define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included        
00287 #define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos            
00288 #define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk             
00289 #define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded        
00290 #define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included       
00291 #define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos            
00292 #define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk             
00293 #define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded        
00294 #define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included        
00295 #define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos             
00296 #define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk            
00297 #define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded        
00298 #define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included       
00299 #define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos             
00300 #define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk            
00301 #define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded       
00302 #define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included       
00303 #define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos           
00304 #define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk            
00305 #define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded      
00306 #define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included      
00307 #define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos           
00308 #define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk           
00309 #define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded       
00310 #define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included      
00311 #define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos           
00312 #define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk            
00313 #define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded       
00314 #define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included      
00315 #define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos            
00316 #define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk            
00317 #define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded      
00318 #define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included       
00319 #define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos           
00320 #define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk           
00321 #define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded       
00322 #define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included       
00323 #define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos            
00324 #define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk            
00325 #define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded      
00326 #define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included      
00327 #define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos            
00328 #define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk            
00329 #define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded        
00330 #define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included       
00331 #define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos            
00332 #define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk            
00333 #define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded       
00334 #define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included        
00335 #define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos            
00336 #define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk            
00337 #define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded       
00338 #define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included       
00339 #define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos            
00340 #define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk            
00341 #define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded       
00342 #define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included       
00343 #define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos            
00344 #define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk            
00345 #define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded       
00346 #define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included        
00347 #define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos             
00348 #define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk             
00349 #define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded        
00350 #define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included       
00351 #define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos            
00352 #define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk            
00353 #define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded       
00354 #define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included       
00355 #define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos            
00356 #define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk           
00357 #define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded       
00358 #define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included       
00359 #define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos             
00360 #define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk             
00361 #define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded       
00362 #define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included       
00363 #define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos            
00364 #define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk            
00365 #define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded       
00366 #define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included        
00367 #define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos           
00368 #define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk           
00369 #define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded     
00370 #define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included      
00371 #define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos          
00372 #define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk           
00373 #define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded      
00374 #define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included       
00375 #define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos           
00376 #define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk            
00377 #define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded      
00378 #define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included      
00379 #define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos            
00380 #define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk            
00381 #define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded       
00382 #define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included       
00383 #define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos            
00384 #define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk            
00385 #define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded      
00386 #define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included       
00387 #define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos            
00388 #define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk            
00389 #define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded      
00390 #define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included      
00391 #define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos            
00392 #define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk            
00393 #define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded       
00394 #define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included       
00395 #define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos            
00396 #define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk             
00397 #define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded       
00398 #define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included       
00399 #define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos             
00400 #define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk            
00401 #define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded        
00402 #define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included       
00403 #define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos             
00404 #define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk             
00405 #define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded       
00406 #define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included        
00407 #define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos             
00408 #define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk             
00409 #define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded        
00410 #define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included       
00411 #define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos             
00412 #define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk            
00413 #define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded        
00414 #define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included        
00415 #define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos             
00416 #define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk            
00417 #define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded        
00418 #define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included        
00419 #define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos             
00420 #define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk             
00421 #define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded        
00422 #define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included       
00423 #define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos             
00424 #define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk             
00425 #define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded        
00426 #define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included        
00427 #define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos             
00428 #define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk             
00429 #define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded        
00430 #define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included        
00431 
00432 
00433 
00434 /*lint --flb "Leave library region" */
00435 
00436 #endif /* NRF51_DEPRECATED_H */
00437