Metropolia Embedded Project Beibes / Mbed 2 deprecated Simple_Touch_Sens

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Dependencies:   mbed

Fork of Simple_Touch_Sens by Veikko Kero

USBDevice/USBHAL_KL25Z.cpp@1:7ed7d128d225, 2014-01-30 (annotated)

Committer:
Vekotin
Date:
Thu Jan 30 06:13:55 2014 +0000
Revision:
1:7ed7d128d225
egw

Who changed what in which revision?

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Vekotin 1:7ed7d128d225 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
Vekotin 1:7ed7d128d225 2 *
Vekotin 1:7ed7d128d225 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
Vekotin 1:7ed7d128d225 4 * and associated documentation files (the "Software"), to deal in the Software without
Vekotin 1:7ed7d128d225 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
Vekotin 1:7ed7d128d225 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
Vekotin 1:7ed7d128d225 7 * Software is furnished to do so, subject to the following conditions:
Vekotin 1:7ed7d128d225 8 *
Vekotin 1:7ed7d128d225 9 * The above copyright notice and this permission notice shall be included in all copies or
Vekotin 1:7ed7d128d225 10 * substantial portions of the Software.
Vekotin 1:7ed7d128d225 11 *
Vekotin 1:7ed7d128d225 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Vekotin 1:7ed7d128d225 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Vekotin 1:7ed7d128d225 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Vekotin 1:7ed7d128d225 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Vekotin 1:7ed7d128d225 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Vekotin 1:7ed7d128d225 17 */
Vekotin 1:7ed7d128d225 18
Vekotin 1:7ed7d128d225 19 #if defined(TARGET_KL25Z)
Vekotin 1:7ed7d128d225 20
Vekotin 1:7ed7d128d225 21 #include "USBHAL.h"
Vekotin 1:7ed7d128d225 22
Vekotin 1:7ed7d128d225 23 USBHAL * USBHAL::instance;
Vekotin 1:7ed7d128d225 24
Vekotin 1:7ed7d128d225 25 static volatile int epComplete = 0;
Vekotin 1:7ed7d128d225 26
Vekotin 1:7ed7d128d225 27 // Convert physical endpoint number to register bit
Vekotin 1:7ed7d128d225 28 #define EP(endpoint) (1<<(endpoint))
Vekotin 1:7ed7d128d225 29
Vekotin 1:7ed7d128d225 30 // Convert physical to logical
Vekotin 1:7ed7d128d225 31 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
Vekotin 1:7ed7d128d225 32
Vekotin 1:7ed7d128d225 33 // Get endpoint direction
Vekotin 1:7ed7d128d225 34 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
Vekotin 1:7ed7d128d225 35 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
Vekotin 1:7ed7d128d225 36
Vekotin 1:7ed7d128d225 37 #define BD_OWN_MASK (1<<7)
Vekotin 1:7ed7d128d225 38 #define BD_DATA01_MASK (1<<6)
Vekotin 1:7ed7d128d225 39 #define BD_KEEP_MASK (1<<5)
Vekotin 1:7ed7d128d225 40 #define BD_NINC_MASK (1<<4)
Vekotin 1:7ed7d128d225 41 #define BD_DTS_MASK (1<<3)
Vekotin 1:7ed7d128d225 42 #define BD_STALL_MASK (1<<2)
Vekotin 1:7ed7d128d225 43
Vekotin 1:7ed7d128d225 44 #define TX 1
Vekotin 1:7ed7d128d225 45 #define RX 0
Vekotin 1:7ed7d128d225 46 #define ODD 0
Vekotin 1:7ed7d128d225 47 #define EVEN 1
Vekotin 1:7ed7d128d225 48 // this macro waits a physical endpoint number
Vekotin 1:7ed7d128d225 49 #define EP_BDT_IDX(ep, dir, odd) (((ep * 4) + (2 * dir) + (1 * odd)))
Vekotin 1:7ed7d128d225 50
Vekotin 1:7ed7d128d225 51 #define SETUP_TOKEN 0x0D
Vekotin 1:7ed7d128d225 52 #define IN_TOKEN 0x09
Vekotin 1:7ed7d128d225 53 #define OUT_TOKEN 0x01
Vekotin 1:7ed7d128d225 54 #define TOK_PID(idx) ((bdt[idx].info >> 2) & 0x0F)
Vekotin 1:7ed7d128d225 55
Vekotin 1:7ed7d128d225 56 // for each endpt: 8 bytes
Vekotin 1:7ed7d128d225 57 typedef struct BDT {
Vekotin 1:7ed7d128d225 58 uint8_t info; // BD[0:7]
Vekotin 1:7ed7d128d225 59 uint8_t dummy; // RSVD: BD[8:15]
Vekotin 1:7ed7d128d225 60 uint16_t byte_count; // BD[16:32]
Vekotin 1:7ed7d128d225 61 uint32_t address; // Addr
Vekotin 1:7ed7d128d225 62 } BDT;
Vekotin 1:7ed7d128d225 63
Vekotin 1:7ed7d128d225 64
Vekotin 1:7ed7d128d225 65 // there are:
Vekotin 1:7ed7d128d225 66 // * 16 bidirectionnal endpt -> 32 physical endpt
Vekotin 1:7ed7d128d225 67 // * as there are ODD and EVEN buffer -> 32*2 bdt
Vekotin 1:7ed7d128d225 68 __attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
Vekotin 1:7ed7d128d225 69 uint8_t endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2][64];
Vekotin 1:7ed7d128d225 70 uint8_t endpoint_buffer_iso[2*2][1023];
Vekotin 1:7ed7d128d225 71
Vekotin 1:7ed7d128d225 72 static uint8_t set_addr = 0;
Vekotin 1:7ed7d128d225 73 static uint8_t addr = 0;
Vekotin 1:7ed7d128d225 74
Vekotin 1:7ed7d128d225 75 static uint32_t Data1 = 0x55555555;
Vekotin 1:7ed7d128d225 76
Vekotin 1:7ed7d128d225 77 static uint32_t frameNumber() {
Vekotin 1:7ed7d128d225 78 return((USB0->FRMNUML | (USB0->FRMNUMH << 8) & 0x07FF));
Vekotin 1:7ed7d128d225 79 }
Vekotin 1:7ed7d128d225 80
Vekotin 1:7ed7d128d225 81 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
Vekotin 1:7ed7d128d225 82 return 0;
Vekotin 1:7ed7d128d225 83 }
Vekotin 1:7ed7d128d225 84
Vekotin 1:7ed7d128d225 85 USBHAL::USBHAL(void) {
Vekotin 1:7ed7d128d225 86 // Disable IRQ
Vekotin 1:7ed7d128d225 87 NVIC_DisableIRQ(USB0_IRQn);
Vekotin 1:7ed7d128d225 88
Vekotin 1:7ed7d128d225 89 // fill in callback array
Vekotin 1:7ed7d128d225 90 epCallback[0] = &USBHAL::EP1_OUT_callback;
Vekotin 1:7ed7d128d225 91 epCallback[1] = &USBHAL::EP1_IN_callback;
Vekotin 1:7ed7d128d225 92 epCallback[2] = &USBHAL::EP2_OUT_callback;
Vekotin 1:7ed7d128d225 93 epCallback[3] = &USBHAL::EP2_IN_callback;
Vekotin 1:7ed7d128d225 94 epCallback[4] = &USBHAL::EP3_OUT_callback;
Vekotin 1:7ed7d128d225 95 epCallback[5] = &USBHAL::EP3_IN_callback;
Vekotin 1:7ed7d128d225 96 epCallback[6] = &USBHAL::EP4_OUT_callback;
Vekotin 1:7ed7d128d225 97 epCallback[7] = &USBHAL::EP4_IN_callback;
Vekotin 1:7ed7d128d225 98 epCallback[8] = &USBHAL::EP5_OUT_callback;
Vekotin 1:7ed7d128d225 99 epCallback[9] = &USBHAL::EP5_IN_callback;
Vekotin 1:7ed7d128d225 100 epCallback[10] = &USBHAL::EP6_OUT_callback;
Vekotin 1:7ed7d128d225 101 epCallback[11] = &USBHAL::EP6_IN_callback;
Vekotin 1:7ed7d128d225 102 epCallback[12] = &USBHAL::EP7_OUT_callback;
Vekotin 1:7ed7d128d225 103 epCallback[13] = &USBHAL::EP7_IN_callback;
Vekotin 1:7ed7d128d225 104 epCallback[14] = &USBHAL::EP8_OUT_callback;
Vekotin 1:7ed7d128d225 105 epCallback[15] = &USBHAL::EP8_IN_callback;
Vekotin 1:7ed7d128d225 106 epCallback[16] = &USBHAL::EP9_OUT_callback;
Vekotin 1:7ed7d128d225 107 epCallback[17] = &USBHAL::EP9_IN_callback;
Vekotin 1:7ed7d128d225 108 epCallback[18] = &USBHAL::EP10_OUT_callback;
Vekotin 1:7ed7d128d225 109 epCallback[19] = &USBHAL::EP10_IN_callback;
Vekotin 1:7ed7d128d225 110 epCallback[20] = &USBHAL::EP11_OUT_callback;
Vekotin 1:7ed7d128d225 111 epCallback[21] = &USBHAL::EP11_IN_callback;
Vekotin 1:7ed7d128d225 112 epCallback[22] = &USBHAL::EP12_OUT_callback;
Vekotin 1:7ed7d128d225 113 epCallback[23] = &USBHAL::EP12_IN_callback;
Vekotin 1:7ed7d128d225 114 epCallback[24] = &USBHAL::EP13_OUT_callback;
Vekotin 1:7ed7d128d225 115 epCallback[25] = &USBHAL::EP13_IN_callback;
Vekotin 1:7ed7d128d225 116 epCallback[26] = &USBHAL::EP14_OUT_callback;
Vekotin 1:7ed7d128d225 117 epCallback[27] = &USBHAL::EP14_IN_callback;
Vekotin 1:7ed7d128d225 118 epCallback[28] = &USBHAL::EP15_OUT_callback;
Vekotin 1:7ed7d128d225 119 epCallback[29] = &USBHAL::EP15_IN_callback;
Vekotin 1:7ed7d128d225 120
Vekotin 1:7ed7d128d225 121
Vekotin 1:7ed7d128d225 122 // choose usb src as PLL
Vekotin 1:7ed7d128d225 123 SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
Vekotin 1:7ed7d128d225 124
Vekotin 1:7ed7d128d225 125 // enable OTG clock
Vekotin 1:7ed7d128d225 126 SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
Vekotin 1:7ed7d128d225 127
Vekotin 1:7ed7d128d225 128 // Attach IRQ
Vekotin 1:7ed7d128d225 129 instance = this;
Vekotin 1:7ed7d128d225 130 NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
Vekotin 1:7ed7d128d225 131 NVIC_EnableIRQ(USB0_IRQn);
Vekotin 1:7ed7d128d225 132
Vekotin 1:7ed7d128d225 133 // USB Module Configuration
Vekotin 1:7ed7d128d225 134 // Reset USB Module
Vekotin 1:7ed7d128d225 135 USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
Vekotin 1:7ed7d128d225 136 while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
Vekotin 1:7ed7d128d225 137
Vekotin 1:7ed7d128d225 138 // Set BDT Base Register
Vekotin 1:7ed7d128d225 139 USB0->BDTPAGE1=(uint8_t)((uint32_t)bdt>>8);
Vekotin 1:7ed7d128d225 140 USB0->BDTPAGE2=(uint8_t)((uint32_t)bdt>>16);
Vekotin 1:7ed7d128d225 141 USB0->BDTPAGE3=(uint8_t)((uint32_t)bdt>>24);
Vekotin 1:7ed7d128d225 142
Vekotin 1:7ed7d128d225 143 // Clear interrupt flag
Vekotin 1:7ed7d128d225 144 USB0->ISTAT = 0xff;
Vekotin 1:7ed7d128d225 145
Vekotin 1:7ed7d128d225 146 // USB Interrupt Enablers
Vekotin 1:7ed7d128d225 147 USB0->INTEN |= USB_INTEN_TOKDNEEN_MASK |
Vekotin 1:7ed7d128d225 148 USB_INTEN_SOFTOKEN_MASK |
Vekotin 1:7ed7d128d225 149 USB_INTEN_ERROREN_MASK |
Vekotin 1:7ed7d128d225 150 USB_INTEN_USBRSTEN_MASK;
Vekotin 1:7ed7d128d225 151
Vekotin 1:7ed7d128d225 152 // Disable weak pull downs
Vekotin 1:7ed7d128d225 153 USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
Vekotin 1:7ed7d128d225 154
Vekotin 1:7ed7d128d225 155 USB0->USBTRC0 |= 0x40;
Vekotin 1:7ed7d128d225 156 }
Vekotin 1:7ed7d128d225 157
Vekotin 1:7ed7d128d225 158 USBHAL::~USBHAL(void) { }
Vekotin 1:7ed7d128d225 159
Vekotin 1:7ed7d128d225 160 void USBHAL::connect(void) {
Vekotin 1:7ed7d128d225 161 // enable USB
Vekotin 1:7ed7d128d225 162 USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
Vekotin 1:7ed7d128d225 163 // Pull up enable
Vekotin 1:7ed7d128d225 164 USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
Vekotin 1:7ed7d128d225 165 }
Vekotin 1:7ed7d128d225 166
Vekotin 1:7ed7d128d225 167 void USBHAL::disconnect(void) {
Vekotin 1:7ed7d128d225 168 // disable USB
Vekotin 1:7ed7d128d225 169 USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;
Vekotin 1:7ed7d128d225 170 // Pull up disable
Vekotin 1:7ed7d128d225 171 USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
Vekotin 1:7ed7d128d225 172 }
Vekotin 1:7ed7d128d225 173
Vekotin 1:7ed7d128d225 174 void USBHAL::configureDevice(void) {
Vekotin 1:7ed7d128d225 175 // not needed
Vekotin 1:7ed7d128d225 176 }
Vekotin 1:7ed7d128d225 177
Vekotin 1:7ed7d128d225 178 void USBHAL::unconfigureDevice(void) {
Vekotin 1:7ed7d128d225 179 // not needed
Vekotin 1:7ed7d128d225 180 }
Vekotin 1:7ed7d128d225 181
Vekotin 1:7ed7d128d225 182 void USBHAL::setAddress(uint8_t address) {
Vekotin 1:7ed7d128d225 183 // we don't set the address now otherwise the usb controller does not ack
Vekotin 1:7ed7d128d225 184 // we set a flag instead
Vekotin 1:7ed7d128d225 185 // see usbisr when an IN token is received
Vekotin 1:7ed7d128d225 186 set_addr = 1;
Vekotin 1:7ed7d128d225 187 addr = address;
Vekotin 1:7ed7d128d225 188 }
Vekotin 1:7ed7d128d225 189
Vekotin 1:7ed7d128d225 190 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
Vekotin 1:7ed7d128d225 191 uint32_t handshake_flag = 0;
Vekotin 1:7ed7d128d225 192 uint8_t * buf;
Vekotin 1:7ed7d128d225 193
Vekotin 1:7ed7d128d225 194 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
Vekotin 1:7ed7d128d225 195 return false;
Vekotin 1:7ed7d128d225 196 }
Vekotin 1:7ed7d128d225 197
Vekotin 1:7ed7d128d225 198 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
Vekotin 1:7ed7d128d225 199
Vekotin 1:7ed7d128d225 200 if ((flags & ISOCHRONOUS) == 0) {
Vekotin 1:7ed7d128d225 201 handshake_flag = USB_ENDPT_EPHSHK_MASK;
Vekotin 1:7ed7d128d225 202 if (IN_EP(endpoint))
Vekotin 1:7ed7d128d225 203 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD )][0];
Vekotin 1:7ed7d128d225 204 else
Vekotin 1:7ed7d128d225 205 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD )][0];
Vekotin 1:7ed7d128d225 206 } else {
Vekotin 1:7ed7d128d225 207 if (IN_EP(endpoint))
Vekotin 1:7ed7d128d225 208 buf = &endpoint_buffer_iso[2][0];
Vekotin 1:7ed7d128d225 209 else
Vekotin 1:7ed7d128d225 210 buf = &endpoint_buffer_iso[0][0];
Vekotin 1:7ed7d128d225 211 }
Vekotin 1:7ed7d128d225 212
Vekotin 1:7ed7d128d225 213 // IN endpt -> device to host (TX)
Vekotin 1:7ed7d128d225 214 if (IN_EP(endpoint)) {
Vekotin 1:7ed7d128d225 215 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
Vekotin 1:7ed7d128d225 216 USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
Vekotin 1:7ed7d128d225 217 bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
Vekotin 1:7ed7d128d225 218 bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
Vekotin 1:7ed7d128d225 219 }
Vekotin 1:7ed7d128d225 220 // OUT endpt -> host to device (RX)
Vekotin 1:7ed7d128d225 221 else {
Vekotin 1:7ed7d128d225 222 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
Vekotin 1:7ed7d128d225 223 USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
Vekotin 1:7ed7d128d225 224 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket;
Vekotin 1:7ed7d128d225 225 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
Vekotin 1:7ed7d128d225 226 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK;
Vekotin 1:7ed7d128d225 227 bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
Vekotin 1:7ed7d128d225 228 }
Vekotin 1:7ed7d128d225 229
Vekotin 1:7ed7d128d225 230 Data1 |= (1 << endpoint);
Vekotin 1:7ed7d128d225 231
Vekotin 1:7ed7d128d225 232 return true;
Vekotin 1:7ed7d128d225 233 }
Vekotin 1:7ed7d128d225 234
Vekotin 1:7ed7d128d225 235 // read setup packet
Vekotin 1:7ed7d128d225 236 void USBHAL::EP0setup(uint8_t *buffer) {
Vekotin 1:7ed7d128d225 237 uint32_t sz;
Vekotin 1:7ed7d128d225 238 endpointReadResult(EP0OUT, buffer, &sz);
Vekotin 1:7ed7d128d225 239 }
Vekotin 1:7ed7d128d225 240
Vekotin 1:7ed7d128d225 241 void USBHAL::EP0readStage(void) {
Vekotin 1:7ed7d128d225 242 Data1 &= ~1UL; // set DATA0
Vekotin 1:7ed7d128d225 243 bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK);
Vekotin 1:7ed7d128d225 244 }
Vekotin 1:7ed7d128d225 245
Vekotin 1:7ed7d128d225 246 void USBHAL::EP0read(void) {
Vekotin 1:7ed7d128d225 247 uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
Vekotin 1:7ed7d128d225 248 bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
Vekotin 1:7ed7d128d225 249 }
Vekotin 1:7ed7d128d225 250
Vekotin 1:7ed7d128d225 251 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
Vekotin 1:7ed7d128d225 252 uint32_t sz;
Vekotin 1:7ed7d128d225 253 endpointReadResult(EP0OUT, buffer, &sz);
Vekotin 1:7ed7d128d225 254 return sz;
Vekotin 1:7ed7d128d225 255 }
Vekotin 1:7ed7d128d225 256
Vekotin 1:7ed7d128d225 257 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
Vekotin 1:7ed7d128d225 258 endpointWrite(EP0IN, buffer, size);
Vekotin 1:7ed7d128d225 259 }
Vekotin 1:7ed7d128d225 260
Vekotin 1:7ed7d128d225 261 void USBHAL::EP0getWriteResult(void) {
Vekotin 1:7ed7d128d225 262 }
Vekotin 1:7ed7d128d225 263
Vekotin 1:7ed7d128d225 264 void USBHAL::EP0stall(void) {
Vekotin 1:7ed7d128d225 265 stallEndpoint(EP0OUT);
Vekotin 1:7ed7d128d225 266 }
Vekotin 1:7ed7d128d225 267
Vekotin 1:7ed7d128d225 268 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
Vekotin 1:7ed7d128d225 269 endpoint = PHY_TO_LOG(endpoint);
Vekotin 1:7ed7d128d225 270 uint32_t idx = EP_BDT_IDX(endpoint, RX, 0);
Vekotin 1:7ed7d128d225 271 bdt[idx].byte_count = maximumSize;
Vekotin 1:7ed7d128d225 272 return EP_PENDING;
Vekotin 1:7ed7d128d225 273 }
Vekotin 1:7ed7d128d225 274
Vekotin 1:7ed7d128d225 275 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
Vekotin 1:7ed7d128d225 276 uint32_t n, sz, idx, setup = 0;
Vekotin 1:7ed7d128d225 277 uint8_t not_iso;
Vekotin 1:7ed7d128d225 278 uint8_t * ep_buf;
Vekotin 1:7ed7d128d225 279
Vekotin 1:7ed7d128d225 280 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
Vekotin 1:7ed7d128d225 281
Vekotin 1:7ed7d128d225 282 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
Vekotin 1:7ed7d128d225 283 return EP_INVALID;
Vekotin 1:7ed7d128d225 284 }
Vekotin 1:7ed7d128d225 285
Vekotin 1:7ed7d128d225 286 // if read on a IN endpoint -> error
Vekotin 1:7ed7d128d225 287 if (IN_EP(endpoint)) {
Vekotin 1:7ed7d128d225 288 return EP_INVALID;
Vekotin 1:7ed7d128d225 289 }
Vekotin 1:7ed7d128d225 290
Vekotin 1:7ed7d128d225 291 idx = EP_BDT_IDX(log_endpoint, RX, 0);
Vekotin 1:7ed7d128d225 292 sz = bdt[idx].byte_count;
Vekotin 1:7ed7d128d225 293 not_iso = USB0->ENDPOINT[log_endpoint].ENDPT & USB_ENDPT_EPHSHK_MASK;
Vekotin 1:7ed7d128d225 294
Vekotin 1:7ed7d128d225 295 //for isochronous endpoint, we don't wait an interrupt
Vekotin 1:7ed7d128d225 296 if ((log_endpoint != 0) && not_iso && !(epComplete & EP(endpoint))) {
Vekotin 1:7ed7d128d225 297 return EP_PENDING;
Vekotin 1:7ed7d128d225 298 }
Vekotin 1:7ed7d128d225 299
Vekotin 1:7ed7d128d225 300 if ((log_endpoint == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
Vekotin 1:7ed7d128d225 301 setup = 1;
Vekotin 1:7ed7d128d225 302 }
Vekotin 1:7ed7d128d225 303
Vekotin 1:7ed7d128d225 304 // non iso endpoint
Vekotin 1:7ed7d128d225 305 if (not_iso) {
Vekotin 1:7ed7d128d225 306 ep_buf = endpoint_buffer[idx];
Vekotin 1:7ed7d128d225 307 } else {
Vekotin 1:7ed7d128d225 308 ep_buf = endpoint_buffer_iso[0];
Vekotin 1:7ed7d128d225 309 }
Vekotin 1:7ed7d128d225 310
Vekotin 1:7ed7d128d225 311 for (n = 0; n < sz; n++) {
Vekotin 1:7ed7d128d225 312 buffer[n] = ep_buf[n];
Vekotin 1:7ed7d128d225 313 }
Vekotin 1:7ed7d128d225 314
Vekotin 1:7ed7d128d225 315 if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
Vekotin 1:7ed7d128d225 316 if (setup && (buffer[6] == 0)) // if no setup data stage,
Vekotin 1:7ed7d128d225 317 Data1 &= ~1UL; // set DATA0
Vekotin 1:7ed7d128d225 318 else
Vekotin 1:7ed7d128d225 319 Data1 ^= (1 << endpoint);
Vekotin 1:7ed7d128d225 320 }
Vekotin 1:7ed7d128d225 321
Vekotin 1:7ed7d128d225 322 if (((Data1 >> endpoint) & 1)) {
Vekotin 1:7ed7d128d225 323 bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK;
Vekotin 1:7ed7d128d225 324 }
Vekotin 1:7ed7d128d225 325 else {
Vekotin 1:7ed7d128d225 326 bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK;
Vekotin 1:7ed7d128d225 327 }
Vekotin 1:7ed7d128d225 328
Vekotin 1:7ed7d128d225 329 USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
Vekotin 1:7ed7d128d225 330 *bytesRead = sz;
Vekotin 1:7ed7d128d225 331
Vekotin 1:7ed7d128d225 332 epComplete &= ~EP(endpoint);
Vekotin 1:7ed7d128d225 333 return EP_COMPLETED;
Vekotin 1:7ed7d128d225 334 }
Vekotin 1:7ed7d128d225 335
Vekotin 1:7ed7d128d225 336 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
Vekotin 1:7ed7d128d225 337 uint32_t idx, n;
Vekotin 1:7ed7d128d225 338 uint8_t * ep_buf;
Vekotin 1:7ed7d128d225 339
Vekotin 1:7ed7d128d225 340 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
Vekotin 1:7ed7d128d225 341 return EP_INVALID;
Vekotin 1:7ed7d128d225 342 }
Vekotin 1:7ed7d128d225 343
Vekotin 1:7ed7d128d225 344 // if write on a OUT endpoint -> error
Vekotin 1:7ed7d128d225 345 if (OUT_EP(endpoint)) {
Vekotin 1:7ed7d128d225 346 return EP_INVALID;
Vekotin 1:7ed7d128d225 347 }
Vekotin 1:7ed7d128d225 348
Vekotin 1:7ed7d128d225 349 idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);
Vekotin 1:7ed7d128d225 350 bdt[idx].byte_count = size;
Vekotin 1:7ed7d128d225 351
Vekotin 1:7ed7d128d225 352
Vekotin 1:7ed7d128d225 353 // non iso endpoint
Vekotin 1:7ed7d128d225 354 if (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPHSHK_MASK) {
Vekotin 1:7ed7d128d225 355 ep_buf = endpoint_buffer[idx];
Vekotin 1:7ed7d128d225 356 } else {
Vekotin 1:7ed7d128d225 357 ep_buf = endpoint_buffer_iso[2];
Vekotin 1:7ed7d128d225 358 }
Vekotin 1:7ed7d128d225 359
Vekotin 1:7ed7d128d225 360 for (n = 0; n < size; n++) {
Vekotin 1:7ed7d128d225 361 ep_buf[n] = data[n];
Vekotin 1:7ed7d128d225 362 }
Vekotin 1:7ed7d128d225 363
Vekotin 1:7ed7d128d225 364 if ((Data1 >> endpoint) & 1) {
Vekotin 1:7ed7d128d225 365 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
Vekotin 1:7ed7d128d225 366 } else {
Vekotin 1:7ed7d128d225 367 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
Vekotin 1:7ed7d128d225 368 }
Vekotin 1:7ed7d128d225 369
Vekotin 1:7ed7d128d225 370 Data1 ^= (1 << endpoint);
Vekotin 1:7ed7d128d225 371
Vekotin 1:7ed7d128d225 372 return EP_PENDING;
Vekotin 1:7ed7d128d225 373 }
Vekotin 1:7ed7d128d225 374
Vekotin 1:7ed7d128d225 375 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
Vekotin 1:7ed7d128d225 376 if (epComplete & EP(endpoint)) {
Vekotin 1:7ed7d128d225 377 epComplete &= ~EP(endpoint);
Vekotin 1:7ed7d128d225 378 return EP_COMPLETED;
Vekotin 1:7ed7d128d225 379 }
Vekotin 1:7ed7d128d225 380
Vekotin 1:7ed7d128d225 381 return EP_PENDING;
Vekotin 1:7ed7d128d225 382 }
Vekotin 1:7ed7d128d225 383
Vekotin 1:7ed7d128d225 384 void USBHAL::stallEndpoint(uint8_t endpoint) {
Vekotin 1:7ed7d128d225 385 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
Vekotin 1:7ed7d128d225 386 }
Vekotin 1:7ed7d128d225 387
Vekotin 1:7ed7d128d225 388 void USBHAL::unstallEndpoint(uint8_t endpoint) {
Vekotin 1:7ed7d128d225 389 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
Vekotin 1:7ed7d128d225 390 }
Vekotin 1:7ed7d128d225 391
Vekotin 1:7ed7d128d225 392 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
Vekotin 1:7ed7d128d225 393 uint8_t stall = (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK);
Vekotin 1:7ed7d128d225 394 return (stall) ? true : false;
Vekotin 1:7ed7d128d225 395 }
Vekotin 1:7ed7d128d225 396
Vekotin 1:7ed7d128d225 397 void USBHAL::remoteWakeup(void) {
Vekotin 1:7ed7d128d225 398 // [TODO]
Vekotin 1:7ed7d128d225 399 }
Vekotin 1:7ed7d128d225 400
Vekotin 1:7ed7d128d225 401
Vekotin 1:7ed7d128d225 402 void USBHAL::_usbisr(void) {
Vekotin 1:7ed7d128d225 403 instance->usbisr();
Vekotin 1:7ed7d128d225 404 }
Vekotin 1:7ed7d128d225 405
Vekotin 1:7ed7d128d225 406
Vekotin 1:7ed7d128d225 407 void USBHAL::usbisr(void) {
Vekotin 1:7ed7d128d225 408 uint8_t i;
Vekotin 1:7ed7d128d225 409 uint8_t istat = USB0->ISTAT;
Vekotin 1:7ed7d128d225 410
Vekotin 1:7ed7d128d225 411 // reset interrupt
Vekotin 1:7ed7d128d225 412 if (istat & USB_ISTAT_USBRST_MASK) {
Vekotin 1:7ed7d128d225 413 // disable all endpt
Vekotin 1:7ed7d128d225 414 for(i = 0; i < 16; i++) {
Vekotin 1:7ed7d128d225 415 USB0->ENDPOINT[i].ENDPT = 0x00;
Vekotin 1:7ed7d128d225 416 }
Vekotin 1:7ed7d128d225 417
Vekotin 1:7ed7d128d225 418 // enable control endpoint
Vekotin 1:7ed7d128d225 419 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
Vekotin 1:7ed7d128d225 420 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
Vekotin 1:7ed7d128d225 421
Vekotin 1:7ed7d128d225 422 Data1 = 0x55555555;
Vekotin 1:7ed7d128d225 423 USB0->CTL |= USB_CTL_ODDRST_MASK;
Vekotin 1:7ed7d128d225 424
Vekotin 1:7ed7d128d225 425 USB0->ISTAT = 0xFF; // clear all interrupt status flags
Vekotin 1:7ed7d128d225 426 USB0->ERRSTAT = 0xFF; // clear all error flags
Vekotin 1:7ed7d128d225 427 USB0->ERREN = 0xFF; // enable error interrupt sources
Vekotin 1:7ed7d128d225 428 USB0->ADDR = 0x00; // set default address
Vekotin 1:7ed7d128d225 429
Vekotin 1:7ed7d128d225 430 return;
Vekotin 1:7ed7d128d225 431 }
Vekotin 1:7ed7d128d225 432
Vekotin 1:7ed7d128d225 433 // resume interrupt
Vekotin 1:7ed7d128d225 434 if (istat & USB_ISTAT_RESUME_MASK) {
Vekotin 1:7ed7d128d225 435 USB0->ISTAT = USB_ISTAT_RESUME_MASK;
Vekotin 1:7ed7d128d225 436 }
Vekotin 1:7ed7d128d225 437
Vekotin 1:7ed7d128d225 438 // SOF interrupt
Vekotin 1:7ed7d128d225 439 if (istat & USB_ISTAT_SOFTOK_MASK) {
Vekotin 1:7ed7d128d225 440 USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
Vekotin 1:7ed7d128d225 441 // SOF event, read frame number
Vekotin 1:7ed7d128d225 442 SOF(frameNumber());
Vekotin 1:7ed7d128d225 443 }
Vekotin 1:7ed7d128d225 444
Vekotin 1:7ed7d128d225 445 // stall interrupt
Vekotin 1:7ed7d128d225 446 if (istat & 1<<7) {
Vekotin 1:7ed7d128d225 447 if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
Vekotin 1:7ed7d128d225 448 USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
Vekotin 1:7ed7d128d225 449 USB0->ISTAT |= USB_ISTAT_STALL_MASK;
Vekotin 1:7ed7d128d225 450 }
Vekotin 1:7ed7d128d225 451
Vekotin 1:7ed7d128d225 452 // token interrupt
Vekotin 1:7ed7d128d225 453 if (istat & 1<<3) {
Vekotin 1:7ed7d128d225 454 uint32_t num = (USB0->STAT >> 4) & 0x0F;
Vekotin 1:7ed7d128d225 455 uint32_t dir = (USB0->STAT >> 3) & 0x01;
Vekotin 1:7ed7d128d225 456 uint32_t ev_odd = (USB0->STAT >> 2) & 0x01;
Vekotin 1:7ed7d128d225 457
Vekotin 1:7ed7d128d225 458 // setup packet
Vekotin 1:7ed7d128d225 459 if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
Vekotin 1:7ed7d128d225 460 Data1 &= ~0x02;
Vekotin 1:7ed7d128d225 461 bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
Vekotin 1:7ed7d128d225 462 bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK;
Vekotin 1:7ed7d128d225 463
Vekotin 1:7ed7d128d225 464 // EP0 SETUP event (SETUP data received)
Vekotin 1:7ed7d128d225 465 EP0setupCallback();
Vekotin 1:7ed7d128d225 466
Vekotin 1:7ed7d128d225 467 } else {
Vekotin 1:7ed7d128d225 468 // OUT packet
Vekotin 1:7ed7d128d225 469 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN) {
Vekotin 1:7ed7d128d225 470 if (num == 0)
Vekotin 1:7ed7d128d225 471 EP0out();
Vekotin 1:7ed7d128d225 472 else {
Vekotin 1:7ed7d128d225 473 epComplete |= (1 << EP(num));
Vekotin 1:7ed7d128d225 474 if ((instance->*(epCallback[EP(num) - 2]))()) {
Vekotin 1:7ed7d128d225 475 epComplete &= ~(1 << EP(num));
Vekotin 1:7ed7d128d225 476 }
Vekotin 1:7ed7d128d225 477 }
Vekotin 1:7ed7d128d225 478 }
Vekotin 1:7ed7d128d225 479
Vekotin 1:7ed7d128d225 480 // IN packet
Vekotin 1:7ed7d128d225 481 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == IN_TOKEN) {
Vekotin 1:7ed7d128d225 482 if (num == 0) {
Vekotin 1:7ed7d128d225 483 EP0in();
Vekotin 1:7ed7d128d225 484 if (set_addr == 1) {
Vekotin 1:7ed7d128d225 485 USB0->ADDR = addr & 0x7F;
Vekotin 1:7ed7d128d225 486 set_addr = 0;
Vekotin 1:7ed7d128d225 487 }
Vekotin 1:7ed7d128d225 488 }
Vekotin 1:7ed7d128d225 489 else {
Vekotin 1:7ed7d128d225 490 epComplete |= (1 << (EP(num) + 1));
Vekotin 1:7ed7d128d225 491 if ((instance->*(epCallback[EP(num) + 1 - 2]))()) {
Vekotin 1:7ed7d128d225 492 epComplete &= ~(1 << (EP(num) + 1));
Vekotin 1:7ed7d128d225 493 }
Vekotin 1:7ed7d128d225 494 }
Vekotin 1:7ed7d128d225 495 }
Vekotin 1:7ed7d128d225 496 }
Vekotin 1:7ed7d128d225 497
Vekotin 1:7ed7d128d225 498 USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
Vekotin 1:7ed7d128d225 499 }
Vekotin 1:7ed7d128d225 500
Vekotin 1:7ed7d128d225 501 // sleep interrupt
Vekotin 1:7ed7d128d225 502 if (istat & 1<<4) {
Vekotin 1:7ed7d128d225 503 USB0->ISTAT |= USB_ISTAT_SLEEP_MASK;
Vekotin 1:7ed7d128d225 504 }
Vekotin 1:7ed7d128d225 505
Vekotin 1:7ed7d128d225 506 // error interrupt
Vekotin 1:7ed7d128d225 507 if (istat & USB_ISTAT_ERROR_MASK) {
Vekotin 1:7ed7d128d225 508 USB0->ERRSTAT = 0xFF;
Vekotin 1:7ed7d128d225 509 USB0->ISTAT |= USB_ISTAT_ERROR_MASK;
Vekotin 1:7ed7d128d225 510 }
Vekotin 1:7ed7d128d225 511 }
Vekotin 1:7ed7d128d225 512
Vekotin 1:7ed7d128d225 513
Vekotin 1:7ed7d128d225 514 #endif