Metropolia Embedded Project Beibes / Mbed 2 deprecated Simple_Touch_Sens

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Dependencies:   mbed

Fork of Simple_Touch_Sens by Veikko Kero

USBDevice/USBHAL_LPC11U.cpp@2:30d2ced09088, 2014-01-30 (annotated)

Committer:
tanssisatu
Date:
Thu Jan 30 06:24:52 2014 +0000
Revision:
2:30d2ced09088
Parent:
1:7ed7d128d225 
plob multitouch

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Vekotin 1:7ed7d128d225 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
Vekotin 1:7ed7d128d225 2 *
Vekotin 1:7ed7d128d225 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
Vekotin 1:7ed7d128d225 4 * and associated documentation files (the "Software"), to deal in the Software without
Vekotin 1:7ed7d128d225 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
Vekotin 1:7ed7d128d225 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
Vekotin 1:7ed7d128d225 7 * Software is furnished to do so, subject to the following conditions:
Vekotin 1:7ed7d128d225 8 *
Vekotin 1:7ed7d128d225 9 * The above copyright notice and this permission notice shall be included in all copies or
Vekotin 1:7ed7d128d225 10 * substantial portions of the Software.
Vekotin 1:7ed7d128d225 11 *
Vekotin 1:7ed7d128d225 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Vekotin 1:7ed7d128d225 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Vekotin 1:7ed7d128d225 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Vekotin 1:7ed7d128d225 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Vekotin 1:7ed7d128d225 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Vekotin 1:7ed7d128d225 17 */
Vekotin 1:7ed7d128d225 18
Vekotin 1:7ed7d128d225 19 #ifdef TARGET_LPC11U24
Vekotin 1:7ed7d128d225 20
Vekotin 1:7ed7d128d225 21 #include "USBHAL.h"
Vekotin 1:7ed7d128d225 22
Vekotin 1:7ed7d128d225 23 USBHAL * USBHAL::instance;
Vekotin 1:7ed7d128d225 24
Vekotin 1:7ed7d128d225 25 // Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
Vekotin 1:7ed7d128d225 26 #define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
Vekotin 1:7ed7d128d225 27
Vekotin 1:7ed7d128d225 28 // Convert physical endpoint number to register bit
Vekotin 1:7ed7d128d225 29 #define EP(endpoint) (1UL<<endpoint)
Vekotin 1:7ed7d128d225 30
Vekotin 1:7ed7d128d225 31 // Convert physical to logical
Vekotin 1:7ed7d128d225 32 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
Vekotin 1:7ed7d128d225 33
Vekotin 1:7ed7d128d225 34 // Get endpoint direction
Vekotin 1:7ed7d128d225 35 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
Vekotin 1:7ed7d128d225 36 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
Vekotin 1:7ed7d128d225 37
Vekotin 1:7ed7d128d225 38 // USB RAM
Vekotin 1:7ed7d128d225 39 #define USB_RAM_START (0x20004000)
Vekotin 1:7ed7d128d225 40 #define USB_RAM_SIZE (0x00000800)
Vekotin 1:7ed7d128d225 41
Vekotin 1:7ed7d128d225 42 // SYSAHBCLKCTRL
Vekotin 1:7ed7d128d225 43 #define CLK_USB (1UL<<14)
Vekotin 1:7ed7d128d225 44 #define CLK_USBRAM (1UL<<27)
Vekotin 1:7ed7d128d225 45
Vekotin 1:7ed7d128d225 46 // USB Information register
Vekotin 1:7ed7d128d225 47 #define FRAME_NR(a) ((a) & 0x7ff) // Frame number
Vekotin 1:7ed7d128d225 48
Vekotin 1:7ed7d128d225 49 // USB Device Command/Status register
Vekotin 1:7ed7d128d225 50 #define DEV_ADDR_MASK (0x7f) // Device address
Vekotin 1:7ed7d128d225 51 #define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
Vekotin 1:7ed7d128d225 52 #define DEV_EN (1UL<<7) // Device enable
Vekotin 1:7ed7d128d225 53 #define SETUP (1UL<<8) // SETUP token received
Vekotin 1:7ed7d128d225 54 #define PLL_ON (1UL<<9) // PLL enabled in suspend
Vekotin 1:7ed7d128d225 55 #define DCON (1UL<<16) // Device status - connect
Vekotin 1:7ed7d128d225 56 #define DSUS (1UL<<17) // Device status - suspend
Vekotin 1:7ed7d128d225 57 #define DCON_C (1UL<<24) // Connect change
Vekotin 1:7ed7d128d225 58 #define DSUS_C (1UL<<25) // Suspend change
Vekotin 1:7ed7d128d225 59 #define DRES_C (1UL<<26) // Reset change
Vekotin 1:7ed7d128d225 60 #define VBUSDEBOUNCED (1UL<<28) // Vbus detected
Vekotin 1:7ed7d128d225 61
Vekotin 1:7ed7d128d225 62 // Endpoint Command/Status list
Vekotin 1:7ed7d128d225 63 #define CMDSTS_A (1UL<<31) // Active
Vekotin 1:7ed7d128d225 64 #define CMDSTS_D (1UL<<30) // Disable
Vekotin 1:7ed7d128d225 65 #define CMDSTS_S (1UL<<29) // Stall
Vekotin 1:7ed7d128d225 66 #define CMDSTS_TR (1UL<<28) // Toggle Reset
Vekotin 1:7ed7d128d225 67 #define CMDSTS_RF (1UL<<27) // Rate Feedback mode
Vekotin 1:7ed7d128d225 68 #define CMDSTS_TV (1UL<<27) // Toggle Value
Vekotin 1:7ed7d128d225 69 #define CMDSTS_T (1UL<<26) // Endpoint Type
Vekotin 1:7ed7d128d225 70 #define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
Vekotin 1:7ed7d128d225 71 #define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
Vekotin 1:7ed7d128d225 72
Vekotin 1:7ed7d128d225 73 #define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
Vekotin 1:7ed7d128d225 74
Vekotin 1:7ed7d128d225 75 // USB Non-endpoint interrupt sources
Vekotin 1:7ed7d128d225 76 #define FRAME_INT (1UL<<30)
Vekotin 1:7ed7d128d225 77 #define DEV_INT (1UL<<31)
Vekotin 1:7ed7d128d225 78
Vekotin 1:7ed7d128d225 79 static volatile int epComplete = 0;
Vekotin 1:7ed7d128d225 80
Vekotin 1:7ed7d128d225 81 // One entry for a double-buffered logical endpoint in the endpoint
Vekotin 1:7ed7d128d225 82 // command/status list. Endpoint 0 is single buffered, out[1] is used
Vekotin 1:7ed7d128d225 83 // for the SETUP packet and in[1] is not used
Vekotin 1:7ed7d128d225 84 typedef __packed struct {
Vekotin 1:7ed7d128d225 85 uint32_t out[2];
Vekotin 1:7ed7d128d225 86 uint32_t in[2];
Vekotin 1:7ed7d128d225 87 } EP_COMMAND_STATUS;
Vekotin 1:7ed7d128d225 88
Vekotin 1:7ed7d128d225 89 typedef __packed struct {
Vekotin 1:7ed7d128d225 90 uint8_t out[MAX_PACKET_SIZE_EP0];
Vekotin 1:7ed7d128d225 91 uint8_t in[MAX_PACKET_SIZE_EP0];
Vekotin 1:7ed7d128d225 92 uint8_t setup[SETUP_PACKET_SIZE];
Vekotin 1:7ed7d128d225 93 } CONTROL_TRANSFER;
Vekotin 1:7ed7d128d225 94
Vekotin 1:7ed7d128d225 95 typedef __packed struct {
Vekotin 1:7ed7d128d225 96 uint32_t maxPacket;
Vekotin 1:7ed7d128d225 97 uint32_t buffer[2];
Vekotin 1:7ed7d128d225 98 uint32_t options;
Vekotin 1:7ed7d128d225 99 } EP_STATE;
Vekotin 1:7ed7d128d225 100
Vekotin 1:7ed7d128d225 101 static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
Vekotin 1:7ed7d128d225 102
Vekotin 1:7ed7d128d225 103 // Pointer to the endpoint command/status list
Vekotin 1:7ed7d128d225 104 static EP_COMMAND_STATUS *ep = NULL;
Vekotin 1:7ed7d128d225 105
Vekotin 1:7ed7d128d225 106 // Pointer to endpoint 0 data (IN/OUT and SETUP)
Vekotin 1:7ed7d128d225 107 static CONTROL_TRANSFER *ct = NULL;
Vekotin 1:7ed7d128d225 108
Vekotin 1:7ed7d128d225 109 // Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
Vekotin 1:7ed7d128d225 110 // initiating a remote wakeup event.
Vekotin 1:7ed7d128d225 111 static volatile uint32_t devCmdStat;
Vekotin 1:7ed7d128d225 112
Vekotin 1:7ed7d128d225 113 // Pointers used to allocate USB RAM
Vekotin 1:7ed7d128d225 114 static uint32_t usbRamPtr = USB_RAM_START;
Vekotin 1:7ed7d128d225 115 static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
Vekotin 1:7ed7d128d225 116
Vekotin 1:7ed7d128d225 117 #define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
Vekotin 1:7ed7d128d225 118
Vekotin 1:7ed7d128d225 119 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
Vekotin 1:7ed7d128d225 120 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
Vekotin 1:7ed7d128d225 121 if (size > 0) {
Vekotin 1:7ed7d128d225 122 do {
Vekotin 1:7ed7d128d225 123 *dst++ = *src++;
Vekotin 1:7ed7d128d225 124 } while (--size > 0);
Vekotin 1:7ed7d128d225 125 }
Vekotin 1:7ed7d128d225 126 }
Vekotin 1:7ed7d128d225 127
Vekotin 1:7ed7d128d225 128
Vekotin 1:7ed7d128d225 129 USBHAL::USBHAL(void) {
Vekotin 1:7ed7d128d225 130 NVIC_DisableIRQ(USB_IRQn);
Vekotin 1:7ed7d128d225 131
Vekotin 1:7ed7d128d225 132 // fill in callback array
Vekotin 1:7ed7d128d225 133 epCallback[0] = &USBHAL::EP1_OUT_callback;
Vekotin 1:7ed7d128d225 134 epCallback[1] = &USBHAL::EP1_IN_callback;
Vekotin 1:7ed7d128d225 135 epCallback[2] = &USBHAL::EP2_OUT_callback;
Vekotin 1:7ed7d128d225 136 epCallback[3] = &USBHAL::EP2_IN_callback;
Vekotin 1:7ed7d128d225 137 epCallback[4] = &USBHAL::EP3_OUT_callback;
Vekotin 1:7ed7d128d225 138 epCallback[5] = &USBHAL::EP3_IN_callback;
Vekotin 1:7ed7d128d225 139 epCallback[6] = &USBHAL::EP4_OUT_callback;
Vekotin 1:7ed7d128d225 140 epCallback[7] = &USBHAL::EP4_IN_callback;
Vekotin 1:7ed7d128d225 141
Vekotin 1:7ed7d128d225 142 // nUSB_CONNECT output
Vekotin 1:7ed7d128d225 143 LPC_IOCON->PIO0_6 = 0x00000001;
Vekotin 1:7ed7d128d225 144
Vekotin 1:7ed7d128d225 145 // Enable clocks (USB registers, USB RAM)
Vekotin 1:7ed7d128d225 146 LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
Vekotin 1:7ed7d128d225 147
Vekotin 1:7ed7d128d225 148 // Ensure device disconnected (DCON not set)
Vekotin 1:7ed7d128d225 149 LPC_USB->DEVCMDSTAT = 0;
Vekotin 1:7ed7d128d225 150
Vekotin 1:7ed7d128d225 151 // to ensure that the USB host sees the device as
Vekotin 1:7ed7d128d225 152 // disconnected if the target CPU is reset.
Vekotin 1:7ed7d128d225 153 wait(0.3);
Vekotin 1:7ed7d128d225 154
Vekotin 1:7ed7d128d225 155 // Reserve space in USB RAM for endpoint command/status list
Vekotin 1:7ed7d128d225 156 // Must be 256 byte aligned
Vekotin 1:7ed7d128d225 157 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
Vekotin 1:7ed7d128d225 158 ep = (EP_COMMAND_STATUS *)usbRamPtr;
Vekotin 1:7ed7d128d225 159 usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
Vekotin 1:7ed7d128d225 160 LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
Vekotin 1:7ed7d128d225 161
Vekotin 1:7ed7d128d225 162 // Reserve space in USB RAM for Endpoint 0
Vekotin 1:7ed7d128d225 163 // Must be 64 byte aligned
Vekotin 1:7ed7d128d225 164 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
Vekotin 1:7ed7d128d225 165 ct = (CONTROL_TRANSFER *)usbRamPtr;
Vekotin 1:7ed7d128d225 166 usbRamPtr += sizeof(CONTROL_TRANSFER);
Vekotin 1:7ed7d128d225 167 LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
Vekotin 1:7ed7d128d225 168
Vekotin 1:7ed7d128d225 169 // Setup command/status list for EP0
Vekotin 1:7ed7d128d225 170 ep[0].out[0] = 0;
Vekotin 1:7ed7d128d225 171 ep[0].in[0] = 0;
Vekotin 1:7ed7d128d225 172 ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
Vekotin 1:7ed7d128d225 173
Vekotin 1:7ed7d128d225 174 // Route all interrupts to IRQ, some can be routed to
Vekotin 1:7ed7d128d225 175 // USB_FIQ if you wish.
Vekotin 1:7ed7d128d225 176 LPC_USB->INTROUTING = 0;
Vekotin 1:7ed7d128d225 177
Vekotin 1:7ed7d128d225 178 // Set device address 0, enable USB device, no remote wakeup
Vekotin 1:7ed7d128d225 179 devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
Vekotin 1:7ed7d128d225 180 LPC_USB->DEVCMDSTAT = devCmdStat;
Vekotin 1:7ed7d128d225 181
Vekotin 1:7ed7d128d225 182 // Enable interrupts for device events and EP0
Vekotin 1:7ed7d128d225 183 LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
Vekotin 1:7ed7d128d225 184 instance = this;
Vekotin 1:7ed7d128d225 185
Vekotin 1:7ed7d128d225 186 //attach IRQ handler and enable interrupts
Vekotin 1:7ed7d128d225 187 NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
Vekotin 1:7ed7d128d225 188 }
Vekotin 1:7ed7d128d225 189
Vekotin 1:7ed7d128d225 190 USBHAL::~USBHAL(void) {
Vekotin 1:7ed7d128d225 191 // Ensure device disconnected (DCON not set)
Vekotin 1:7ed7d128d225 192 LPC_USB->DEVCMDSTAT = 0;
Vekotin 1:7ed7d128d225 193 // Disable USB interrupts
Vekotin 1:7ed7d128d225 194 NVIC_DisableIRQ(USB_IRQn);
Vekotin 1:7ed7d128d225 195 }
Vekotin 1:7ed7d128d225 196
Vekotin 1:7ed7d128d225 197 void USBHAL::connect(void) {
Vekotin 1:7ed7d128d225 198 NVIC_EnableIRQ(USB_IRQn);
Vekotin 1:7ed7d128d225 199 devCmdStat |= DCON;
Vekotin 1:7ed7d128d225 200 LPC_USB->DEVCMDSTAT = devCmdStat;
Vekotin 1:7ed7d128d225 201 }
Vekotin 1:7ed7d128d225 202
Vekotin 1:7ed7d128d225 203 void USBHAL::disconnect(void) {
Vekotin 1:7ed7d128d225 204 NVIC_DisableIRQ(USB_IRQn);
Vekotin 1:7ed7d128d225 205 devCmdStat &= ~DCON;
Vekotin 1:7ed7d128d225 206 LPC_USB->DEVCMDSTAT = devCmdStat;
Vekotin 1:7ed7d128d225 207 }
Vekotin 1:7ed7d128d225 208
Vekotin 1:7ed7d128d225 209 void USBHAL::configureDevice(void) {
Vekotin 1:7ed7d128d225 210 // Not required
Vekotin 1:7ed7d128d225 211 }
Vekotin 1:7ed7d128d225 212
Vekotin 1:7ed7d128d225 213 void USBHAL::unconfigureDevice(void) {
Vekotin 1:7ed7d128d225 214 // Not required
Vekotin 1:7ed7d128d225 215 }
Vekotin 1:7ed7d128d225 216
Vekotin 1:7ed7d128d225 217 void USBHAL::EP0setup(uint8_t *buffer) {
Vekotin 1:7ed7d128d225 218 // Copy setup packet data
Vekotin 1:7ed7d128d225 219 USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
Vekotin 1:7ed7d128d225 220 }
Vekotin 1:7ed7d128d225 221
Vekotin 1:7ed7d128d225 222 void USBHAL::EP0read(void) {
Vekotin 1:7ed7d128d225 223 // Start an endpoint 0 read
Vekotin 1:7ed7d128d225 224
Vekotin 1:7ed7d128d225 225 // The USB ISR will call USBDevice_EP0out() when a packet has been read,
Vekotin 1:7ed7d128d225 226 // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
Vekotin 1:7ed7d128d225 227 // read the data.
Vekotin 1:7ed7d128d225 228
Vekotin 1:7ed7d128d225 229 ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
Vekotin 1:7ed7d128d225 230 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
Vekotin 1:7ed7d128d225 231 }
Vekotin 1:7ed7d128d225 232
Vekotin 1:7ed7d128d225 233 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
Vekotin 1:7ed7d128d225 234 // Complete an endpoint 0 read
Vekotin 1:7ed7d128d225 235 uint32_t bytesRead;
Vekotin 1:7ed7d128d225 236
Vekotin 1:7ed7d128d225 237 // Find how many bytes were read
Vekotin 1:7ed7d128d225 238 bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
Vekotin 1:7ed7d128d225 239
Vekotin 1:7ed7d128d225 240 // Copy data
Vekotin 1:7ed7d128d225 241 USBMemCopy(buffer, ct->out, bytesRead);
Vekotin 1:7ed7d128d225 242 return bytesRead;
Vekotin 1:7ed7d128d225 243 }
Vekotin 1:7ed7d128d225 244
Vekotin 1:7ed7d128d225 245
Vekotin 1:7ed7d128d225 246 void USBHAL::EP0readStage(void) {
Vekotin 1:7ed7d128d225 247 // Not required
Vekotin 1:7ed7d128d225 248 }
Vekotin 1:7ed7d128d225 249
Vekotin 1:7ed7d128d225 250 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
Vekotin 1:7ed7d128d225 251 // Start and endpoint 0 write
Vekotin 1:7ed7d128d225 252
Vekotin 1:7ed7d128d225 253 // The USB ISR will call USBDevice_EP0in() when the data has
Vekotin 1:7ed7d128d225 254 // been written, the USBDevice layer then calls
Vekotin 1:7ed7d128d225 255 // USBBusInterface_EP0getWriteResult() to complete the transaction.
Vekotin 1:7ed7d128d225 256
Vekotin 1:7ed7d128d225 257 // Copy data
Vekotin 1:7ed7d128d225 258 USBMemCopy(ct->in, buffer, size);
Vekotin 1:7ed7d128d225 259
Vekotin 1:7ed7d128d225 260 // Start transfer
Vekotin 1:7ed7d128d225 261 ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
Vekotin 1:7ed7d128d225 262 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
Vekotin 1:7ed7d128d225 263 }
Vekotin 1:7ed7d128d225 264
Vekotin 1:7ed7d128d225 265
Vekotin 1:7ed7d128d225 266 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
Vekotin 1:7ed7d128d225 267 uint8_t bf = 0;
Vekotin 1:7ed7d128d225 268 uint32_t flags = 0;
Vekotin 1:7ed7d128d225 269
Vekotin 1:7ed7d128d225 270 //check which buffer must be filled
Vekotin 1:7ed7d128d225 271 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Vekotin 1:7ed7d128d225 272 // Double buffered
Vekotin 1:7ed7d128d225 273 if (LPC_USB->EPINUSE & EP(endpoint)) {
Vekotin 1:7ed7d128d225 274 bf = 1;
Vekotin 1:7ed7d128d225 275 } else {
Vekotin 1:7ed7d128d225 276 bf = 0;
Vekotin 1:7ed7d128d225 277 }
Vekotin 1:7ed7d128d225 278 }
Vekotin 1:7ed7d128d225 279
Vekotin 1:7ed7d128d225 280 // if isochronous endpoint, T = 1
Vekotin 1:7ed7d128d225 281 if(endpointState[endpoint].options & ISOCHRONOUS)
Vekotin 1:7ed7d128d225 282 {
Vekotin 1:7ed7d128d225 283 flags |= CMDSTS_T;
Vekotin 1:7ed7d128d225 284 }
Vekotin 1:7ed7d128d225 285
Vekotin 1:7ed7d128d225 286 //Active the endpoint for reading
Vekotin 1:7ed7d128d225 287 ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
Vekotin 1:7ed7d128d225 288 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
Vekotin 1:7ed7d128d225 289 return EP_PENDING;
Vekotin 1:7ed7d128d225 290 }
Vekotin 1:7ed7d128d225 291
Vekotin 1:7ed7d128d225 292 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
Vekotin 1:7ed7d128d225 293
Vekotin 1:7ed7d128d225 294 uint8_t bf = 0;
Vekotin 1:7ed7d128d225 295
Vekotin 1:7ed7d128d225 296 if (!(epComplete & EP(endpoint)))
Vekotin 1:7ed7d128d225 297 return EP_PENDING;
Vekotin 1:7ed7d128d225 298 else {
Vekotin 1:7ed7d128d225 299 epComplete &= ~EP(endpoint);
Vekotin 1:7ed7d128d225 300
Vekotin 1:7ed7d128d225 301 //check which buffer has been filled
Vekotin 1:7ed7d128d225 302 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Vekotin 1:7ed7d128d225 303 // Double buffered (here we read the previous buffer which was used)
Vekotin 1:7ed7d128d225 304 if (LPC_USB->EPINUSE & EP(endpoint)) {
Vekotin 1:7ed7d128d225 305 bf = 0;
Vekotin 1:7ed7d128d225 306 } else {
Vekotin 1:7ed7d128d225 307 bf = 1;
Vekotin 1:7ed7d128d225 308 }
Vekotin 1:7ed7d128d225 309 }
Vekotin 1:7ed7d128d225 310
Vekotin 1:7ed7d128d225 311 // Find how many bytes were read
Vekotin 1:7ed7d128d225 312 *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
Vekotin 1:7ed7d128d225 313
Vekotin 1:7ed7d128d225 314 // Copy data
Vekotin 1:7ed7d128d225 315 USBMemCopy(data, ct->out, *bytesRead);
Vekotin 1:7ed7d128d225 316 return EP_COMPLETED;
Vekotin 1:7ed7d128d225 317 }
Vekotin 1:7ed7d128d225 318 }
Vekotin 1:7ed7d128d225 319
Vekotin 1:7ed7d128d225 320 void USBHAL::EP0getWriteResult(void) {
Vekotin 1:7ed7d128d225 321 // Not required
Vekotin 1:7ed7d128d225 322 }
Vekotin 1:7ed7d128d225 323
Vekotin 1:7ed7d128d225 324 void USBHAL::EP0stall(void) {
Vekotin 1:7ed7d128d225 325 ep[0].in[0] = CMDSTS_S;
Vekotin 1:7ed7d128d225 326 ep[0].out[0] = CMDSTS_S;
Vekotin 1:7ed7d128d225 327 }
Vekotin 1:7ed7d128d225 328
Vekotin 1:7ed7d128d225 329 void USBHAL::setAddress(uint8_t address) {
Vekotin 1:7ed7d128d225 330 devCmdStat &= ~DEV_ADDR_MASK;
Vekotin 1:7ed7d128d225 331 devCmdStat |= DEV_ADDR(address);
Vekotin 1:7ed7d128d225 332 LPC_USB->DEVCMDSTAT = devCmdStat;
Vekotin 1:7ed7d128d225 333 }
Vekotin 1:7ed7d128d225 334
Vekotin 1:7ed7d128d225 335 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
Vekotin 1:7ed7d128d225 336 uint32_t flags = 0;
Vekotin 1:7ed7d128d225 337 uint32_t bf;
Vekotin 1:7ed7d128d225 338
Vekotin 1:7ed7d128d225 339 // Validate parameters
Vekotin 1:7ed7d128d225 340 if (data == NULL) {
Vekotin 1:7ed7d128d225 341 return EP_INVALID;
Vekotin 1:7ed7d128d225 342 }
Vekotin 1:7ed7d128d225 343
Vekotin 1:7ed7d128d225 344 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Vekotin 1:7ed7d128d225 345 return EP_INVALID;
Vekotin 1:7ed7d128d225 346 }
Vekotin 1:7ed7d128d225 347
Vekotin 1:7ed7d128d225 348 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
Vekotin 1:7ed7d128d225 349 return EP_INVALID;
Vekotin 1:7ed7d128d225 350 }
Vekotin 1:7ed7d128d225 351
Vekotin 1:7ed7d128d225 352 if (size > endpointState[endpoint].maxPacket) {
Vekotin 1:7ed7d128d225 353 return EP_INVALID;
Vekotin 1:7ed7d128d225 354 }
Vekotin 1:7ed7d128d225 355
Vekotin 1:7ed7d128d225 356 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Vekotin 1:7ed7d128d225 357 // Double buffered
Vekotin 1:7ed7d128d225 358 if (LPC_USB->EPINUSE & EP(endpoint)) {
Vekotin 1:7ed7d128d225 359 bf = 1;
Vekotin 1:7ed7d128d225 360 } else {
Vekotin 1:7ed7d128d225 361 bf = 0;
Vekotin 1:7ed7d128d225 362 }
Vekotin 1:7ed7d128d225 363 } else {
Vekotin 1:7ed7d128d225 364 // Single buffered
Vekotin 1:7ed7d128d225 365 bf = 0;
Vekotin 1:7ed7d128d225 366 }
Vekotin 1:7ed7d128d225 367
Vekotin 1:7ed7d128d225 368 // Check if already active
Vekotin 1:7ed7d128d225 369 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
Vekotin 1:7ed7d128d225 370 return EP_INVALID;
Vekotin 1:7ed7d128d225 371 }
Vekotin 1:7ed7d128d225 372
Vekotin 1:7ed7d128d225 373 // Check if stalled
Vekotin 1:7ed7d128d225 374 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
Vekotin 1:7ed7d128d225 375 return EP_STALLED;
Vekotin 1:7ed7d128d225 376 }
Vekotin 1:7ed7d128d225 377
Vekotin 1:7ed7d128d225 378 // Copy data to USB RAM
Vekotin 1:7ed7d128d225 379 USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
Vekotin 1:7ed7d128d225 380
Vekotin 1:7ed7d128d225 381 // Add options
Vekotin 1:7ed7d128d225 382 if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
Vekotin 1:7ed7d128d225 383 flags |= CMDSTS_RF;
Vekotin 1:7ed7d128d225 384 }
Vekotin 1:7ed7d128d225 385
Vekotin 1:7ed7d128d225 386 if (endpointState[endpoint].options & ISOCHRONOUS) {
Vekotin 1:7ed7d128d225 387 flags |= CMDSTS_T;
Vekotin 1:7ed7d128d225 388 }
Vekotin 1:7ed7d128d225 389
Vekotin 1:7ed7d128d225 390 // Add transfer
Vekotin 1:7ed7d128d225 391 ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
Vekotin 1:7ed7d128d225 392 endpointState[endpoint].buffer[bf]) \
Vekotin 1:7ed7d128d225 393 | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
Vekotin 1:7ed7d128d225 394
Vekotin 1:7ed7d128d225 395 return EP_PENDING;
Vekotin 1:7ed7d128d225 396 }
Vekotin 1:7ed7d128d225 397
Vekotin 1:7ed7d128d225 398 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
Vekotin 1:7ed7d128d225 399 uint32_t bf;
Vekotin 1:7ed7d128d225 400
Vekotin 1:7ed7d128d225 401 // Validate parameters
Vekotin 1:7ed7d128d225 402 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Vekotin 1:7ed7d128d225 403 return EP_INVALID;
Vekotin 1:7ed7d128d225 404 }
Vekotin 1:7ed7d128d225 405
Vekotin 1:7ed7d128d225 406 if (OUT_EP(endpoint)) {
Vekotin 1:7ed7d128d225 407 return EP_INVALID;
Vekotin 1:7ed7d128d225 408 }
Vekotin 1:7ed7d128d225 409
Vekotin 1:7ed7d128d225 410 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Vekotin 1:7ed7d128d225 411 // Double buffered // TODO: FIX THIS
Vekotin 1:7ed7d128d225 412 if (LPC_USB->EPINUSE & EP(endpoint)) {
Vekotin 1:7ed7d128d225 413 bf = 1;
Vekotin 1:7ed7d128d225 414 } else {
Vekotin 1:7ed7d128d225 415 bf = 0;
Vekotin 1:7ed7d128d225 416 }
Vekotin 1:7ed7d128d225 417 } else {
Vekotin 1:7ed7d128d225 418 // Single buffered
Vekotin 1:7ed7d128d225 419 bf = 0;
Vekotin 1:7ed7d128d225 420 }
Vekotin 1:7ed7d128d225 421
Vekotin 1:7ed7d128d225 422 // Check if endpoint still active
Vekotin 1:7ed7d128d225 423 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
Vekotin 1:7ed7d128d225 424 return EP_PENDING;
Vekotin 1:7ed7d128d225 425 }
Vekotin 1:7ed7d128d225 426
Vekotin 1:7ed7d128d225 427 // Check if stalled
Vekotin 1:7ed7d128d225 428 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
Vekotin 1:7ed7d128d225 429 return EP_STALLED;
Vekotin 1:7ed7d128d225 430 }
Vekotin 1:7ed7d128d225 431
Vekotin 1:7ed7d128d225 432 return EP_COMPLETED;
Vekotin 1:7ed7d128d225 433 }
Vekotin 1:7ed7d128d225 434
Vekotin 1:7ed7d128d225 435 void USBHAL::stallEndpoint(uint8_t endpoint) {
Vekotin 1:7ed7d128d225 436
Vekotin 1:7ed7d128d225 437 // FIX: should this clear active bit?
Vekotin 1:7ed7d128d225 438 if (IN_EP(endpoint)) {
Vekotin 1:7ed7d128d225 439 ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
Vekotin 1:7ed7d128d225 440 ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
Vekotin 1:7ed7d128d225 441 } else {
Vekotin 1:7ed7d128d225 442 ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
Vekotin 1:7ed7d128d225 443 ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
Vekotin 1:7ed7d128d225 444 }
Vekotin 1:7ed7d128d225 445 }
Vekotin 1:7ed7d128d225 446
Vekotin 1:7ed7d128d225 447 void USBHAL::unstallEndpoint(uint8_t endpoint) {
Vekotin 1:7ed7d128d225 448 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Vekotin 1:7ed7d128d225 449 // Double buffered
Vekotin 1:7ed7d128d225 450 if (IN_EP(endpoint)) {
Vekotin 1:7ed7d128d225 451 ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
Vekotin 1:7ed7d128d225 452 ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
Vekotin 1:7ed7d128d225 453
Vekotin 1:7ed7d128d225 454 if (LPC_USB->EPINUSE & EP(endpoint)) {
Vekotin 1:7ed7d128d225 455 ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Vekotin 1:7ed7d128d225 456 } else {
Vekotin 1:7ed7d128d225 457 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Vekotin 1:7ed7d128d225 458 }
Vekotin 1:7ed7d128d225 459 } else {
Vekotin 1:7ed7d128d225 460 ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
Vekotin 1:7ed7d128d225 461 ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
Vekotin 1:7ed7d128d225 462
Vekotin 1:7ed7d128d225 463 if (LPC_USB->EPINUSE & EP(endpoint)) {
Vekotin 1:7ed7d128d225 464 ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Vekotin 1:7ed7d128d225 465 } else {
Vekotin 1:7ed7d128d225 466 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Vekotin 1:7ed7d128d225 467 }
Vekotin 1:7ed7d128d225 468 }
Vekotin 1:7ed7d128d225 469 } else {
Vekotin 1:7ed7d128d225 470 // Single buffered
Vekotin 1:7ed7d128d225 471 if (IN_EP(endpoint)) {
Vekotin 1:7ed7d128d225 472 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Vekotin 1:7ed7d128d225 473 } else {
Vekotin 1:7ed7d128d225 474 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Vekotin 1:7ed7d128d225 475 }
Vekotin 1:7ed7d128d225 476 }
Vekotin 1:7ed7d128d225 477 }
Vekotin 1:7ed7d128d225 478
Vekotin 1:7ed7d128d225 479 bool USBHAL::getEndpointStallState(unsigned char endpoint) {
Vekotin 1:7ed7d128d225 480 if (IN_EP(endpoint)) {
Vekotin 1:7ed7d128d225 481 if (LPC_USB->EPINUSE & EP(endpoint)) {
Vekotin 1:7ed7d128d225 482 if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
Vekotin 1:7ed7d128d225 483 return true;
Vekotin 1:7ed7d128d225 484 }
Vekotin 1:7ed7d128d225 485 } else {
Vekotin 1:7ed7d128d225 486 if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
Vekotin 1:7ed7d128d225 487 return true;
Vekotin 1:7ed7d128d225 488 }
Vekotin 1:7ed7d128d225 489 }
Vekotin 1:7ed7d128d225 490 } else {
Vekotin 1:7ed7d128d225 491 if (LPC_USB->EPINUSE & EP(endpoint)) {
Vekotin 1:7ed7d128d225 492 if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
Vekotin 1:7ed7d128d225 493 return true;
Vekotin 1:7ed7d128d225 494 }
Vekotin 1:7ed7d128d225 495 } else {
Vekotin 1:7ed7d128d225 496 if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
Vekotin 1:7ed7d128d225 497 return true;
Vekotin 1:7ed7d128d225 498 }
Vekotin 1:7ed7d128d225 499 }
Vekotin 1:7ed7d128d225 500 }
Vekotin 1:7ed7d128d225 501
Vekotin 1:7ed7d128d225 502 return false;
Vekotin 1:7ed7d128d225 503 }
Vekotin 1:7ed7d128d225 504
Vekotin 1:7ed7d128d225 505 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
Vekotin 1:7ed7d128d225 506 uint32_t tmpEpRamPtr;
Vekotin 1:7ed7d128d225 507
Vekotin 1:7ed7d128d225 508 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Vekotin 1:7ed7d128d225 509 return false;
Vekotin 1:7ed7d128d225 510 }
Vekotin 1:7ed7d128d225 511
Vekotin 1:7ed7d128d225 512 // Not applicable to the control endpoints
Vekotin 1:7ed7d128d225 513 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
Vekotin 1:7ed7d128d225 514 return false;
Vekotin 1:7ed7d128d225 515 }
Vekotin 1:7ed7d128d225 516
Vekotin 1:7ed7d128d225 517 // Allocate buffers in USB RAM
Vekotin 1:7ed7d128d225 518 tmpEpRamPtr = epRamPtr;
Vekotin 1:7ed7d128d225 519
Vekotin 1:7ed7d128d225 520 // Must be 64 byte aligned
Vekotin 1:7ed7d128d225 521 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
Vekotin 1:7ed7d128d225 522
Vekotin 1:7ed7d128d225 523 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
Vekotin 1:7ed7d128d225 524 // Out of memory
Vekotin 1:7ed7d128d225 525 return false;
Vekotin 1:7ed7d128d225 526 }
Vekotin 1:7ed7d128d225 527
Vekotin 1:7ed7d128d225 528 // Allocate first buffer
Vekotin 1:7ed7d128d225 529 endpointState[endpoint].buffer[0] = tmpEpRamPtr;
Vekotin 1:7ed7d128d225 530 tmpEpRamPtr += maxPacket;
Vekotin 1:7ed7d128d225 531
Vekotin 1:7ed7d128d225 532 if (!(options & SINGLE_BUFFERED)) {
Vekotin 1:7ed7d128d225 533 // Must be 64 byte aligned
Vekotin 1:7ed7d128d225 534 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
Vekotin 1:7ed7d128d225 535
Vekotin 1:7ed7d128d225 536 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
Vekotin 1:7ed7d128d225 537 // Out of memory
Vekotin 1:7ed7d128d225 538 return false;
Vekotin 1:7ed7d128d225 539 }
Vekotin 1:7ed7d128d225 540
Vekotin 1:7ed7d128d225 541 // Allocate second buffer
Vekotin 1:7ed7d128d225 542 endpointState[endpoint].buffer[1] = tmpEpRamPtr;
Vekotin 1:7ed7d128d225 543 tmpEpRamPtr += maxPacket;
Vekotin 1:7ed7d128d225 544 }
Vekotin 1:7ed7d128d225 545
Vekotin 1:7ed7d128d225 546 // Commit to this USB RAM allocation
Vekotin 1:7ed7d128d225 547 epRamPtr = tmpEpRamPtr;
Vekotin 1:7ed7d128d225 548
Vekotin 1:7ed7d128d225 549 // Remaining endpoint state values
Vekotin 1:7ed7d128d225 550 endpointState[endpoint].maxPacket = maxPacket;
Vekotin 1:7ed7d128d225 551 endpointState[endpoint].options = options;
Vekotin 1:7ed7d128d225 552
Vekotin 1:7ed7d128d225 553 // Enable double buffering if required
Vekotin 1:7ed7d128d225 554 if (options & SINGLE_BUFFERED) {
Vekotin 1:7ed7d128d225 555 LPC_USB->EPBUFCFG &= ~EP(endpoint);
Vekotin 1:7ed7d128d225 556 } else {
Vekotin 1:7ed7d128d225 557 // Double buffered
Vekotin 1:7ed7d128d225 558 LPC_USB->EPBUFCFG |= EP(endpoint);
Vekotin 1:7ed7d128d225 559 }
Vekotin 1:7ed7d128d225 560
Vekotin 1:7ed7d128d225 561 // Enable interrupt
Vekotin 1:7ed7d128d225 562 LPC_USB->INTEN |= EP(endpoint);
Vekotin 1:7ed7d128d225 563
Vekotin 1:7ed7d128d225 564 // Enable endpoint
Vekotin 1:7ed7d128d225 565 unstallEndpoint(endpoint);
Vekotin 1:7ed7d128d225 566 return true;
Vekotin 1:7ed7d128d225 567 }
Vekotin 1:7ed7d128d225 568
Vekotin 1:7ed7d128d225 569 void USBHAL::remoteWakeup(void) {
Vekotin 1:7ed7d128d225 570 // Clearing DSUS bit initiates a remote wakeup if the
Vekotin 1:7ed7d128d225 571 // device is currently enabled and suspended - otherwise
Vekotin 1:7ed7d128d225 572 // it has no effect.
Vekotin 1:7ed7d128d225 573 LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
Vekotin 1:7ed7d128d225 574 }
Vekotin 1:7ed7d128d225 575
Vekotin 1:7ed7d128d225 576
Vekotin 1:7ed7d128d225 577 static void disableEndpoints(void) {
Vekotin 1:7ed7d128d225 578 uint32_t logEp;
Vekotin 1:7ed7d128d225 579
Vekotin 1:7ed7d128d225 580 // Ref. Table 158 "When a bus reset is received, software
Vekotin 1:7ed7d128d225 581 // must set the disable bit of all endpoints to 1".
Vekotin 1:7ed7d128d225 582
Vekotin 1:7ed7d128d225 583 for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
Vekotin 1:7ed7d128d225 584 ep[logEp].out[0] = CMDSTS_D;
Vekotin 1:7ed7d128d225 585 ep[logEp].out[1] = CMDSTS_D;
Vekotin 1:7ed7d128d225 586 ep[logEp].in[0] = CMDSTS_D;
Vekotin 1:7ed7d128d225 587 ep[logEp].in[1] = CMDSTS_D;
Vekotin 1:7ed7d128d225 588 }
Vekotin 1:7ed7d128d225 589
Vekotin 1:7ed7d128d225 590 // Start of USB RAM for endpoints > 0
Vekotin 1:7ed7d128d225 591 epRamPtr = usbRamPtr;
Vekotin 1:7ed7d128d225 592 }
Vekotin 1:7ed7d128d225 593
Vekotin 1:7ed7d128d225 594
Vekotin 1:7ed7d128d225 595
Vekotin 1:7ed7d128d225 596 void USBHAL::_usbisr(void) {
Vekotin 1:7ed7d128d225 597 instance->usbisr();
Vekotin 1:7ed7d128d225 598 }
Vekotin 1:7ed7d128d225 599
Vekotin 1:7ed7d128d225 600 void USBHAL::usbisr(void) {
Vekotin 1:7ed7d128d225 601 // Start of frame
Vekotin 1:7ed7d128d225 602 if (LPC_USB->INTSTAT & FRAME_INT) {
Vekotin 1:7ed7d128d225 603 // Clear SOF interrupt
Vekotin 1:7ed7d128d225 604 LPC_USB->INTSTAT = FRAME_INT;
Vekotin 1:7ed7d128d225 605
Vekotin 1:7ed7d128d225 606 // SOF event, read frame number
Vekotin 1:7ed7d128d225 607 SOF(FRAME_NR(LPC_USB->INFO));
Vekotin 1:7ed7d128d225 608 }
Vekotin 1:7ed7d128d225 609
Vekotin 1:7ed7d128d225 610 // Device state
Vekotin 1:7ed7d128d225 611 if (LPC_USB->INTSTAT & DEV_INT) {
Vekotin 1:7ed7d128d225 612 LPC_USB->INTSTAT = DEV_INT;
Vekotin 1:7ed7d128d225 613
Vekotin 1:7ed7d128d225 614 if (LPC_USB->DEVCMDSTAT & DSUS_C) {
Vekotin 1:7ed7d128d225 615 // Suspend status changed
Vekotin 1:7ed7d128d225 616 LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
Vekotin 1:7ed7d128d225 617 if((LPC_USB->DEVCMDSTAT & DSUS) != 0) {
Vekotin 1:7ed7d128d225 618 suspendStateChanged(1);
Vekotin 1:7ed7d128d225 619 }
Vekotin 1:7ed7d128d225 620 }
Vekotin 1:7ed7d128d225 621
Vekotin 1:7ed7d128d225 622 if (LPC_USB->DEVCMDSTAT & DRES_C) {
Vekotin 1:7ed7d128d225 623 // Bus reset
Vekotin 1:7ed7d128d225 624 LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
Vekotin 1:7ed7d128d225 625
Vekotin 1:7ed7d128d225 626 suspendStateChanged(0);
Vekotin 1:7ed7d128d225 627
Vekotin 1:7ed7d128d225 628 // Disable endpoints > 0
Vekotin 1:7ed7d128d225 629 disableEndpoints();
Vekotin 1:7ed7d128d225 630
Vekotin 1:7ed7d128d225 631 // Bus reset event
Vekotin 1:7ed7d128d225 632 busReset();
Vekotin 1:7ed7d128d225 633 }
Vekotin 1:7ed7d128d225 634 }
Vekotin 1:7ed7d128d225 635
Vekotin 1:7ed7d128d225 636 // Endpoint 0
Vekotin 1:7ed7d128d225 637 if (LPC_USB->INTSTAT & EP(EP0OUT)) {
Vekotin 1:7ed7d128d225 638 // Clear EP0OUT/SETUP interrupt
Vekotin 1:7ed7d128d225 639 LPC_USB->INTSTAT = EP(EP0OUT);
Vekotin 1:7ed7d128d225 640
Vekotin 1:7ed7d128d225 641 // Check if SETUP
Vekotin 1:7ed7d128d225 642 if (LPC_USB->DEVCMDSTAT & SETUP) {
Vekotin 1:7ed7d128d225 643 // Clear Active and Stall bits for EP0
Vekotin 1:7ed7d128d225 644 // Documentation does not make it clear if we must use the
Vekotin 1:7ed7d128d225 645 // EPSKIP register to achieve this, Fig. 16 and NXP reference
Vekotin 1:7ed7d128d225 646 // code suggests we can just clear the Active bits - check with
Vekotin 1:7ed7d128d225 647 // NXP to be sure.
Vekotin 1:7ed7d128d225 648 ep[0].in[0] = 0;
Vekotin 1:7ed7d128d225 649 ep[0].out[0] = 0;
Vekotin 1:7ed7d128d225 650
Vekotin 1:7ed7d128d225 651 // Clear EP0IN interrupt
Vekotin 1:7ed7d128d225 652 LPC_USB->INTSTAT = EP(EP0IN);
Vekotin 1:7ed7d128d225 653
Vekotin 1:7ed7d128d225 654 // Clear SETUP (and INTONNAK_CI/O) in device status register
Vekotin 1:7ed7d128d225 655 LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
Vekotin 1:7ed7d128d225 656
Vekotin 1:7ed7d128d225 657 // EP0 SETUP event (SETUP data received)
Vekotin 1:7ed7d128d225 658 EP0setupCallback();
Vekotin 1:7ed7d128d225 659 } else {
Vekotin 1:7ed7d128d225 660 // EP0OUT ACK event (OUT data received)
Vekotin 1:7ed7d128d225 661 EP0out();
Vekotin 1:7ed7d128d225 662 }
Vekotin 1:7ed7d128d225 663 }
Vekotin 1:7ed7d128d225 664
Vekotin 1:7ed7d128d225 665 if (LPC_USB->INTSTAT & EP(EP0IN)) {
Vekotin 1:7ed7d128d225 666 // Clear EP0IN interrupt
Vekotin 1:7ed7d128d225 667 LPC_USB->INTSTAT = EP(EP0IN);
Vekotin 1:7ed7d128d225 668
Vekotin 1:7ed7d128d225 669 // EP0IN ACK event (IN data sent)
Vekotin 1:7ed7d128d225 670 EP0in();
Vekotin 1:7ed7d128d225 671 }
Vekotin 1:7ed7d128d225 672
Vekotin 1:7ed7d128d225 673 for (uint8_t num = 2; num < 5*2; num++) {
Vekotin 1:7ed7d128d225 674 if (LPC_USB->INTSTAT & EP(num)) {
Vekotin 1:7ed7d128d225 675 LPC_USB->INTSTAT = EP(num);
Vekotin 1:7ed7d128d225 676 epComplete |= EP(num);
Vekotin 1:7ed7d128d225 677 if ((instance->*(epCallback[num - 2]))()) {
Vekotin 1:7ed7d128d225 678 epComplete &= ~EP(num);
Vekotin 1:7ed7d128d225 679 }
Vekotin 1:7ed7d128d225 680 }
Vekotin 1:7ed7d128d225 681 }
Vekotin 1:7ed7d128d225 682 }
Vekotin 1:7ed7d128d225 683
Vekotin 1:7ed7d128d225 684 #endif